CN114722747A - Chip design method and device, equipment and storage medium - Google Patents

Chip design method and device, equipment and storage medium Download PDF

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Publication number
CN114722747A
CN114722747A CN202210406306.1A CN202210406306A CN114722747A CN 114722747 A CN114722747 A CN 114722747A CN 202210406306 A CN202210406306 A CN 202210406306A CN 114722747 A CN114722747 A CN 114722747A
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chip unit
chip
unit
replacement
dynamic
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崔兴美
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

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Abstract

The application provides a chip design method, a chip design device, equipment and a storage medium; wherein the method comprises the following steps: determining a first chip unit of which the dynamic electrical parameters do not meet the chip design conditions in the designed chip structure; searching a second chip unit meeting the replacement condition from the library; wherein the replacement condition comprises that the layout is the same as the chip unit to be replaced and the inherent electrical characteristics are better than the chip unit to be replaced; replacing the first chip unit to be replaced with the second chip unit.

Description

Chip design method and device, equipment and storage medium
Technical Field
The present application relates to electronic technology, and relates to, but is not limited to, chip design methods and apparatuses, devices, and storage media.
Background
As integrated circuit fabrication processes enter the nanometer scale, chip speed and integration continue to increase, and ultra-large scale high performance computing chips often incorporate billions of transistors, which presents new problems and challenges to chip design.
Disclosure of Invention
In view of this, the chip design method, device, apparatus, and storage medium provided in the present application can achieve the purpose of optimizing the dynamic electrical parameters of the chip unit without adding additional windings or units, thereby improving the overall performance of the chip.
According to an aspect of an embodiment of the present application, there is provided a chip design method, including: determining a first chip unit of which the dynamic electrical parameters do not meet the chip design conditions in the designed chip structure; searching a second chip unit meeting the first replacement condition from the library; wherein the first replacement condition comprises a layout (layout) identical to the first chip cell and having inherent electrical characteristics superior to the first chip cell; replacing the first chip unit with the second chip unit.
According to another aspect of the embodiments of the present application, there is provided a chip design method, including: determining a first chip unit of which the dynamic electrical parameters in the designed chip structure do not meet the chip design conditions; determining a third chip unit which has a connection relation with the first chip unit and has intersection with the working time; searching a fourth chip unit meeting a second replacement condition from the library; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit; replacing the third chip unit with the fourth chip unit, thereby affecting a dynamic electrical parameter of the first chip unit.
According to an aspect of an embodiment of the present application, there is provided a chip design apparatus, including: a first determination module configured to determine a first chip unit in the designed chip structure for which the dynamic electrical parameter does not satisfy the chip design condition; a first search module configured to search the library for a second chip unit satisfying a first replacement condition; wherein the first replacement condition includes a layout identical to the first chip cell and having inherent electrical characteristics superior to the first chip cell; a first replacement module configured to replace the first chip unit with the second chip unit.
According to another aspect of the embodiments of the present application, there is provided a chip design apparatus, including: a second determination module configured to determine a first chip unit in the designed chip structure for which the dynamic electrical parameter does not satisfy the chip design condition; a third determining module configured to determine a third chip unit having a connection relation with the first chip unit and intersection of working times; a second searching module configured to search the library for a fourth chip unit satisfying a second replacement condition; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit; a second replacement module configured to replace the third chip unit with the fourth chip unit, thereby affecting a dynamic electrical parameter of the first chip unit.
According to an aspect of the embodiments of the present application, there is provided an electronic device, including a memory and a processor, the memory storing a computer program executable on the processor, and the processor implementing the method of the embodiments of the present application when executing the program.
According to an aspect of the embodiments of the present application, there is provided a computer-readable storage medium on which a computer program is stored, the computer program, when executed by a processor, implementing the method provided by the embodiments of the present application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
Fig. 1 is a schematic diagram illustrating an implementation flow of a chip design method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an equivalent circuit of the first chip unit for dynamic operation;
fig. 3 is a schematic diagram illustrating an implementation flow of another chip design method according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of an equivalent circuit of the first chip unit in dynamic operation;
fig. 5 is a schematic diagram illustrating an implementation flow of another chip design method according to an embodiment of the present application;
fig. 6 is a schematic flow chart illustrating an implementation of another chip design method according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a chip design apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of another chip design apparatus provided in the embodiment of the present application;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present application will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
The embodiment of the application provides a chip design method, which is applied to electronic equipment, wherein the electronic equipment can be various types of equipment with information processing capability in the implementation process, and for example, the electronic equipment can comprise a personal computer, a notebook computer, a tablet computer, a mobile phone and the like. The functions implemented by the method can be implemented by calling program code by a processor in an electronic device, and the program code can be stored in a computer storage medium.
Fig. 1 is a schematic view of an implementation flow of a chip design method provided in an embodiment of the present application, and as shown in fig. 1, the method may include the following steps 101 to 103:
step 101, determining a first chip unit of which dynamic electrical parameters do not meet chip design conditions in a designed chip structure.
The dynamic electrical parameter is an electrical parameter that changes under the influence of its own operating state or the operating state of a chip unit connected thereto. In the embodiment of the present application, the type of the dynamic electrical parameter is not limited, and in short, the dynamic electrical parameter is a parameter that affects the performance, such as the operating speed of the chip. In some embodiments, the dynamic electrical parameters include at least one of: dynamic voltage drop, Peak Power (Peak Power), fault Power (Glitch Power).
Different types of dynamic electrical parameters correspond to different chip design conditions. In some embodiments, the dynamic electrical parameter includes a dynamic voltage drop, and the corresponding chip design condition is that the dynamic voltage drop is greater than a first threshold value, and the unit of the first threshold value is the unit of the dynamic voltage drop, so as to detect whether the dynamic voltage drop of the chip unit has a problem. Similarly, in other embodiments, the dynamic electrical parameter includes peak power, and the corresponding chip design condition is that the peak power is greater than a second threshold, and the unit of the second threshold is the unit of the peak power, so as to detect whether the peak power of the chip unit is in problem. In still other embodiments, the dynamic electrical parameter includes a fault power, and the corresponding chip design condition is that the fault power is greater than a third threshold, and the unit of the third threshold is the unit of the fault power, so as to detect whether the fault power of the chip unit is in problem.
Step 102, searching a second chip unit meeting a first replacement condition from a library; wherein the first replacement condition includes a layout identical to the first chip cell and having inherent electrical characteristics superior to the first chip cell.
In some embodiments, the layout is the same as the first chip cell, including: the connection relationship of the components and the corresponding components is the same as that of the first chip unit, and the bottom layer doping is different from that of the first chip unit. Namely, the circuit structures and the unit functions of the two chip units are the same, and only the bottom layers are doped differently; therefore, the first chip unit is replaced by the second chip unit which has the same layout and excellent inherent electrical characteristics, so that the purpose of optimizing the dynamic electrical parameters of the first chip unit is achieved, and meanwhile, no winding or unit is additionally arranged, the iteration time of the retest (signoff) in the chip design stage can be greatly saved, and the optimization efficiency of the chip design is improved.
The intrinsic electrical characteristics are characteristic parameters that do not change with changes in the operating state of the chip unit itself or the chip unit connected thereto. The magnitude of the dynamic electrical parameter of the cell is directly affected by the intrinsic electrical properties. In the embodiment of the present application, the inherent electrical characteristics are not limited, and in any case, the dynamic electrical parameters of the chip units connected to the chip units may be affected. In some embodiments, the inherent electrical characteristic comprises a delay and/or a threshold voltage; the inherent electrical characteristics are superior to the first chip unit, including: the delay and/or threshold voltage is greater than the first chip unit.
And 103, replacing the first chip unit to be replaced with the second chip unit, so as to achieve the purpose of optimizing the dynamic electrical parameters of the first chip unit.
It will be appreciated that the magnitude of the dynamic electrical parameter of the cell is directly affected by the intrinsic electrical properties. For example, the larger the delay or the larger the threshold voltage, the smaller the current of the branch in which the cell is located, and the better the corresponding dynamic electrical parameter. For example, FIG. 2 is a schematic diagram of an equivalent circuit of a first chip unit (labeled inst1) operating dynamically, taking the example that the dynamic electrical parameter includes a dynamic voltage drop, as shown in FIG. 2, the dynamic voltage drop at inst1 is represented by ItotalThe resistor network RC1 and the resistor network RC2 jointly determine to reduce I1Can reduce ItotalThereby optimizing the dynamic voltage drop across inst 1. Therefore, inst1 may be replaced with a larger threshold voltage or larger delay but laying out the same second chip cell to reduce I1Thereby reducing ItotalAnd thus reduce the dynamic voltage drop across inst 1. In this way, the dynamic voltage drop across inst1 can be improved without the need for re-placement and routing.
In the embodiment of the application, a first chip unit of which the dynamic electrical parameter does not meet the chip design condition in the designed chip structure is found out; searching a second chip unit with the layout which is the same as that of the first chip unit but has the inherent electrical characteristics superior to those of the first chip unit from the library; replacing the first chip unit to be replaced with a second chip unit; therefore, the purpose of optimizing dynamic electrical parameters is achieved under the condition that no additional winding or unit is added, and the overall performance of the chip is improved.
Fig. 3 is a schematic flow chart of an implementation of another chip design method provided in the embodiment of the present application, and as shown in fig. 3, the method includes the following steps 301 to 312:
step 301, determining a first chip unit of which dynamic electrical parameters do not meet chip design conditions in a designed chip structure;
step 302, searching a second chip unit meeting the first replacement condition from a library; if the second chip unit is found, executing step 303; if the second chip unit is not found, go to step 308.
Wherein the first replacement condition comprises: the layout is the same as the first chip cell and has inherent electrical characteristics superior to the first chip cell.
Further, in some embodiments, the first replacement condition includes that a layout is the same as the first chip cell and inherent electrical characteristics are optimal. Accordingly, the second chip cell found is a chip cell having the same layout as the first chip cell and having the optimum electrical characteristics inherent in the plurality of chip cells superior to those of the first chip cell. For example, the second chip unit is a chip unit with the largest delay or the largest threshold voltage among the plurality of chip units.
Step 303, replacing the first chip unit to be replaced with the second chip unit; then, go to step 304;
step 304, determining whether the dynamic electrical parameters of the second chip unit meet the chip design conditions; if not, go to step 305; if the dynamic electrical parameters of the second chip unit are satisfied, finishing the optimization of the dynamic electrical parameters of the second chip unit, continuously searching the next chip unit of which the dynamic electrical parameters do not satisfy the chip design conditions, and optimizing the chip unit by adopting the same method.
It can be understood that, after the first chip unit is replaced by the second chip unit, whether the dynamic electrical parameters of the second chip unit meet the chip design conditions is continuously judged; if not, it continues to be further optimized by steps 305 and 306 as follows, thereby further improving chip performance without adding additional routing or cells.
And 305, determining a third chip unit which has a connection relation with the second chip unit and has intersection in working time.
It is to be understood that by the intersection of the working times is meant that the working times of the two chip units at least partly coincide. In some embodiments, the connection relationship is a parallel relationship or a series relationship.
Step 306, performing a replacement operation on the third chip unit; the replacement operation includes searching for a fourth chip unit satisfying a second replacement condition from the library, and step 307;
wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
In some embodiments, as shown in fig. 3, if there is no fourth chip unit satisfying the second replacement condition in the library, step 311 is entered, and a fifth chip unit having a connection relationship with the second chip unit and an intersection exists between working times is continuously searched, and then a chip unit that can replace the fifth chip unit is searched from the library, so as to implement optimization of the dynamic electrical parameter of the second chip unit.
307, replacing the third chip unit to be replaced with the fourth chip unit, so as to influence the dynamic electrical parameters of the second chip unit, namely, achieve the purpose of optimizing the dynamic electrical parameters of the second chip unit; then, step 310 is entered.
For example, fig. 4 is a schematic structural diagram of an equivalent circuit of a first chip unit (labeled inst1), taking an example that a dynamic electrical parameter includes a dynamic voltage drop, a third chip unit (labeled inst2) is a chip unit having a connection relationship with the first chip unit or a replaced second chip unit, as shown in fig. 4, a voltage drop across inst1 is represented by ItotalThe resistor network RC1 and the resistor network RC2 jointly determine to reduce I1Or I2Can reduce ItotalThereby optimizing the dynamic voltage drop across inst 1. Therefore, instead of replacing the first chip cell (inst1) with the second chip cell, the third chip cell (inst2) connected thereto may be replaced with a fourth chip cell of larger threshold voltage or larger delay but the same layout to reduce I2Thereby further reducing ItotalAnd thus reduce the dynamic voltage drop across inst 1. In this way, the dynamic voltage drop across the inst1 location can be further improved without the need for re-placement and routing.
And step 308, determining a third chip unit which has a connection relation with the first chip unit and has intersection with the working time.
By working time intersection there is meant that the working times (i.e. time windows) of the two units are at least partially coincident. In some embodiments, the connection relationship is a parallel relationship or a series relationship.
Step 309, performing a replacement operation on the third chip unit; the replacing operation comprises: searching a fourth chip unit meeting a second replacement condition from a library, and replacing the third chip unit to be replaced with the fourth chip unit, so as to influence the dynamic electrical parameters of the first chip unit; then, go to step 310;
wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
In some embodiments, as shown in fig. 3, if no fourth chip unit satisfying the second replacement condition is found in the library, step 311 is also entered, and a fifth chip unit having a connection relationship with the first chip unit and an intersection exists between working times is continuously searched, and then a chip unit that can replace the fifth chip unit is searched from the library, thereby implementing optimization of the dynamic electrical parameter of the second chip unit.
The principle of step 308 and step 309 can be understood with reference to the equivalent circuit diagram shown in fig. 4 described above.
It can be understood that, for a first chip unit whose dynamic electrical parameter does not satisfy the chip design condition, if there is no second chip unit capable of replacing the chip unit in the library, the dynamic electrical parameter of the first chip unit is continuously optimized through steps 308 and 309, that is, a third chip unit having a connection relationship with the first chip unit and having an intersection with the working time is found out, and the replacement operation is performed on the third chip unit; thus, even if the second chip unit which can replace the first chip unit does not exist in the library, the purpose of optimizing the dynamic electrical parameters of the first chip unit can be achieved, and therefore the flexibility of optimizing the dynamic electrical parameters of the first chip unit is enhanced under the condition that no additional routing or unit is added.
Step 310, determining whether the dynamic electrical parameters of the target chip unit (i.e. the first chip unit or the second chip unit) meet the chip design conditions; if yes, ending; otherwise, go to step 311;
step 311, continuously determining a fifth chip unit which has a connection relation with the target chip unit and has an intersection in working time; wherein the target chip unit is the first chip unit or the second chip unit;
step 312, performing a replacement operation on the fifth chip unit until the dynamic electrical parameter of the target chip unit meets the chip design condition; wherein the fifth chip unit is different from the fourth chip unit; the replacing operation in step 312 includes: searching a sixth chip unit meeting a third replacement condition from a library, and replacing the fifth chip unit with the sixth chip unit so as to influence the dynamic electrical parameters of the target chip unit; wherein the third replacement condition comprises: the layout is the same as the fifth chip unit and has inherent electrical characteristics superior to the fifth chip unit.
In the embodiment of the application, for a first chip unit of which the dynamic electrical parameter does not meet the chip design condition, the optimization of the dynamic electrical parameter at the position of the first chip unit is finished through the steps until the dynamic electrical parameter of the first chip unit or a second chip unit replacing the first chip unit meets the chip design condition; in this way, the maximum degree of optimization is realized without adding additional wires or units, thereby maximally improving the chip performance.
An embodiment of the present application further provides a chip design method, and fig. 5 is a schematic implementation flow chart of another chip design method provided in the embodiment of the present application, and as shown in fig. 5, the method may include the following steps 501 to 504:
step 501, determining a first chip unit of which dynamic electrical parameters do not meet chip design conditions in a designed chip structure;
step 502, determining a third chip unit which has a connection relation with the first chip unit and has intersection in working time;
step 503, searching a fourth chip unit satisfying the second replacement condition from the library; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit;
step 504, replacing the third chip unit to be replaced with the fourth chip unit, thereby influencing (i.e. optimizing) the dynamic electrical parameters of the first chip unit.
In some embodiments, if there is no fourth chip unit satisfying the second replacement condition in the library, step 311 and step 312 are executed, so as to achieve the purpose of optimizing the dynamic electrical parameter of the first chip unit.
In some embodiments, after performing step 504, it is determined whether the dynamic electrical parameter of the first chip unit satisfies the chip design condition, and if not, the schemes of steps 311 and 312 are performed so as to maximally optimize the dynamic electrical parameter of the first chip unit.
It should be noted that, for the embodiment shown in fig. 5, the description is similar to the description of the other method embodiments, and for the technical details not disclosed in this embodiment, please refer to the description of the other method embodiments.
In some embodiments, the inherent electrical characteristics are superior to the chip unit to be replaced, including: the delay and/or the threshold voltage is larger than the chip unit to be replaced; the layout is the same as the chip cells to be replaced, including: the same connection relation between the components and the corresponding components is the same as that under the chip unit to be replaced, and the bottom layer doping is different from that of the chip unit to be replaced.
With the reduction of the process size, the integration density of the chip is higher and higher, and the working frequency is higher and higher. This presents new problems and challenges to the dynamic voltage drop of the chip. The dynamic voltage drop affects the operation speed of the chip, and even causes functional errors when the dynamic voltage drop is serious, so that the dynamic voltage drop needs to be considered seriously.
In some embodiments, the main methods of optimizing the dynamic voltage drop are: increasing the density of the power supply network, manually reducing the density of local chip cells (cells), and adding decoupling cells (decap) around cells with a relatively large voltage drop.
However, these methods for optimizing the dynamic voltage drop require changing the layout and routing of the module (block) for the purpose of reducing the dynamic voltage drop, which leads to an increase in the module area; in the engineer manual optimization stage (eco), the iteration time of PPA signoff is greatly lengthened, and thus the overall efficiency is low.
Based on this, an exemplary application of the embodiment of the present application in a practical application scenario will be described below.
Fig. 4 is an equivalent circuit diagram of dynamic operation of a certain cell (labeled inst1) in a chip, wherein inst2 is a cell that is placed relatively close to the physical location of inst1, and during the dynamic operation, TW (time Window) of inst1 and inst2 are overlapped. The voltage drop across inst1 is represented by ItotalDetermined in conjunction with resistor network RC1 and resistor network RC2, thereby reducing I1Or I2All can reduce ItotalAnd thus optimize the dynamic voltage drop across inst 1.
In the embodiment of the present application, a cell is replaced (swap), the current cell is replaced with another cell having a larger threshold voltage or a longer channel length but the same layout (layout), the delay (delay) value of one of the insts is made larger to reduce I1 or I2, thereby reducing ItotalThereby reducing the voltage drop across inst 1. This improves the dynamic voltage drop across inst1 without the need for re-placement and routing.
The specific process of optimizing the dynamic voltage drop in this embodiment, as shown in fig. 6, includes the following steps 601 to 607:
step 601, selecting a cell with a dynamic voltage drop problem, and marking the cell as inst1 (as shown in fig. 4);
step 602, judging whether inst1 can be replaced; if so, go to step 603; otherwise, go to step 606;
wherein, the judgment criteria capable of being replaced are: there is a cell in the library that has the same layout (layout) as inst1, and the delay or threshold voltage of the cell is large compared to inst 1.
At step 603, if there is a cell in the library (referred to for convenience as inst3) with the same layout (layout) as inst1, and the delay or threshold voltage of inst3 is greater than inst1, then inst1 can be replaced with inst3, and the dynamic voltage drop at this location can be mitigated after direct replacement. Step 604 is entered.
For example, as shown in fig. 6, the replacement policy is to replace an ulvt-type cell with an lvt-type cell; as another example, a cell of type Ivt is replaced with a cell of type svt; as another example, a cell replacement of H8 type is replaced with a cell of H11 type. In these examples, the physical parameters of the surfaces of the pre-replacement cell and the post-replacement cell are the same, but the electrical parameters are different.
Step 604, it may be determined whether the dynamic voltage drop of inst3 after replacement meets the requirement; if not, go to step 605; if yes, ending;
step 605, the neighboring cells with at least partially overlapped time windows around can be continuously found to perform the same operation; after completion, the dynamic voltage drop of inst3 is evaluated and ends if the dynamic voltage drop of inst3 meets the requirements.
Step 606, if inst1 cannot be replaced, find other cells (labeled inst2) around and at least partially coinciding with its time window;
step 607, based on the criterion of replacement capability, determining whether inst2 can be replaced; if the space for replacement exists, replacing so as to realize optimization of the dynamic voltage drop, then judging whether the dynamic voltage drop after replacement meets the requirement, and if not, continuing to find the cells with the time windows at least partially overlapped around for the same operation; and ending if the dynamic voltage drop meets the requirement.
The above operations are repeated until the dynamic voltage drop meets the requirements.
In the embodiment of the present application, only the threshold voltage or the channel length of a specific cell group is changed, and the physical layout and wiring is not affected. The purpose of optimizing the dynamic voltage drop can be achieved without adding extra winding wires or units. The main current is changed by increasing the threshold voltage or increasing the channel length, and the layout of the replaced cell is not changed, so that the dynamic voltage drop on the cell can be optimized without re-layout and wiring. The method is simple and feasible, and the signoff iteration time can be greatly saved in the eco stage, so that the optimization efficiency of the dynamic voltage drop is improved. In addition, additional units and wiring are not required to be added, and the overall performance (PPA) of the design can be ensured while voltage drop is optimized.
The technical scheme is applicable to both a placement and routing stage (PnR) and an engineer manual optimization stage (eco). The scheme can be used for improving the dynamic voltage drop and is also suitable for optimizing peak power and fault power.
It should be noted that although the steps of the methods in this application are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order or that all of the depicted steps must be performed to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step execution, and/or one step may be broken down into multiple step executions, etc.; or, the steps in different embodiments are combined into a new technical solution.
Based on the foregoing embodiments, an embodiment of the present application provides a chip design apparatus, where the apparatus includes modules that can be implemented by a processor; in implementation, the processor may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.
Fig. 7 is a schematic structural diagram of a chip design apparatus according to an embodiment of the present application, and as shown in fig. 7, the chip design apparatus 70 includes:
a first determining module 701 configured to determine a first chip unit in the designed chip structure whose dynamic electrical parameter does not satisfy a chip design condition;
a first search module 702 configured to search the library for a second chip unit satisfying the first replacement condition; wherein the first replacement condition includes a layout identical to the first chip cell and having inherent electrical characteristics superior to the first chip cell;
a first replacement module 703 configured to replace the first chip unit to be replaced with the second chip unit.
In some embodiments, the first determining module 701 is further configured to determine, based on determining that no second chip unit satisfying the first replacement condition is found from the library, a third chip unit having a connection relationship with the first chip unit and intersection with the working times; a first replacement module 703, further configured to search a library for a fourth chip unit satisfying a second replacement condition, and replace the third chip unit to be replaced with the fourth chip unit, thereby affecting a dynamic electrical parameter of the first chip unit; wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
In some embodiments, the first determining module 701 is further configured to, after replacing the first chip unit with the second chip unit, determine a third chip unit having a connection relationship with the second chip unit and an intersection of working times based on determining that the dynamic electrical parameter of the second chip unit does not satisfy the chip design condition; a first replacement module 703, further configured to search a library for a fourth chip unit satisfying a second replacement condition, and replace the third chip unit to be replaced with the fourth chip unit, so as to affect a dynamic electrical parameter of the second chip unit; wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
In some embodiments, the first determining module 701 is further configured to, after replacing the third chip unit with the fourth chip unit, based on determining that the dynamic electrical parameter of the target chip unit does not satisfy the chip design condition, continue to determine a fifth chip unit having a connection relationship with the target chip unit and an intersection of the working times; wherein the target chip unit is the first chip unit or the second chip unit; a first replacement module 703, further configured to perform a replacement operation on the fifth chip unit until the dynamic electrical parameter of the target chip unit satisfies the chip design condition; wherein the fifth chip unit is different from the fourth chip unit; the replacing operation comprises: searching a sixth chip unit meeting a third replacement condition from a library, and replacing the fifth chip unit with the sixth chip unit so as to influence the dynamic electrical parameters of the target chip unit; wherein the third replacement condition comprises: the layout is the same as the fifth chip unit and has inherent electrical characteristics superior to the fifth chip unit.
Fig. 8 is a schematic structural diagram of another chip design apparatus provided in an embodiment of the present application, and as shown in fig. 8, a chip design apparatus 80 includes:
a second determining module 801 configured to determine a first chip unit in the designed chip structure for which the dynamic electrical parameter does not satisfy the chip design condition;
a third determining module 802 configured to determine a third chip unit having a connection relation with the first chip unit and intersection of working times;
a second searching module 803 configured to search the library for a fourth chip unit satisfying the second replacement condition; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit; wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit;
a second replacement module 804 configured to replace the third chip unit to be replaced with the fourth chip unit, thereby affecting the dynamic electrical parameter of the first chip unit.
In some embodiments, the third determining module 802 is further configured to, after replacing the third chip unit with the fourth chip unit, based on determining that the dynamic electrical parameter of the first chip unit does not satisfy the chip design condition, continue to determine a fifth chip unit having a connection relationship with the first chip unit and an intersection between working times; a second replacement module 804 further configured to perform the replacement operation on the fifth chip unit until the dynamic electrical parameter of the first chip unit satisfies the chip design condition; wherein the fifth chip unit is different from the fourth chip unit.
In some embodiments, the third determining module 803 is further configured to, from the library, find no fourth chip unit satisfying the replacement condition, continue to determine a fifth chip unit having a connection relationship with the first chip unit and intersection of working times; a second replacement module 804, further configured to perform the replacement operation on the fifth chip unit until the dynamic electrical parameter of the first chip unit satisfies the chip design condition; wherein the fifth chip unit is different from the fourth chip unit.
The above description of the apparatus embodiments, similar to the above description of the method embodiments, has similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the apparatus of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be noted that the division of the chip design apparatus provided in the embodiment of the present application into modules is schematic, and is only a logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, may also exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. Or in a combination of software and hardware.
It should be noted that, in the embodiment of the present application, if the method described above is implemented in the form of a software functional module and sold or used as a standalone product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
An electronic device is provided in an embodiment of the present application, fig. 9 is a schematic diagram of a hardware entity of the electronic device provided in the embodiment of the present application, as shown in fig. 9, the electronic device 90 includes a memory 901 and a processor 902, the memory 901 stores a computer program that can be executed on the processor 902, and the processor 902 executes the computer program to implement the steps in the method provided in the embodiment.
It should be noted that the Memory 901 is configured to store instructions and applications executable by the processor 902, and can also buffer data (for example, image data, audio data, voice communication data, and video communication data) to be processed or processed by each module in the processor 902 and the electronic device 90, and can be implemented by a FLASH Memory (FLASH) or a Random Access Memory (RAM).
Embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps in the methods provided in the above embodiments.
Embodiments of the present application provide a computer program product containing instructions which, when run on a computer, cause the computer to perform the steps of the method provided by the above-described method embodiments.
It is to be noted here that: the above description of the storage medium and device embodiments is similar to the description of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the embodiments of the storage medium, the storage medium and the device of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. The foregoing description of the various embodiments is intended to highlight various differences between the embodiments, and the same or similar parts may be referred to each other, and for brevity, will not be described again herein.
The term "and/or" herein is merely an association relationship describing an associated object, and means that three relationships may exist, for example, object a and/or object B, may mean: the object a exists alone, the object a and the object B exist simultaneously, and the object B exists alone.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments are merely illustrative, and for example, the division of the modules is only one logical functional division, and other divisions may be realized in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules; can be located in one place or distributed on a plurality of network units; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may be separately regarded as one unit, or two or more modules may be integrated into one unit; the integrated module can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media that can store program code, such as removable storage devices, ROMs, magnetic or optical disks, etc.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method of chip design, the method comprising:
determining a first chip unit of which the dynamic electrical parameters do not meet the chip design conditions in the designed chip structure;
searching a second chip unit meeting the first replacement condition from the library; wherein the first replacement condition comprises: the layout is the same as the first chip unit and has inherent electrical characteristics superior to the first chip unit;
replacing the first chip unit with the second chip unit.
2. The method of claim 1, further comprising:
determining a third chip unit which has a connection relation with the first chip unit and has intersection with the working time based on determining that no second chip unit meeting the first replacement condition is found in a library;
searching a fourth chip unit meeting a second replacement condition from a library, and replacing the third chip unit with the fourth chip unit so as to influence the dynamic electrical parameters of the first chip unit;
wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
3. The method of claim 1, further comprising:
after replacing the first chip unit with the second chip unit, determining a third chip unit which has a connection relation with the second chip unit and has intersection in working time based on the fact that the dynamic electrical parameters of the second chip unit do not meet the chip design conditions;
searching a fourth chip unit meeting a second replacement condition from a library, and replacing the third chip unit with the fourth chip unit so as to influence the dynamic electrical parameters of the second chip unit;
wherein the second replacement condition comprises: the layout is the same as the third chip unit and has inherent electrical characteristics superior to the third chip unit.
4. A method according to claim 2 or 3, characterized in that the method further comprises:
after the third chip unit is replaced by the fourth chip unit, based on the fact that the dynamic electrical parameters of the target chip unit do not meet the chip design conditions, continuously determining a fifth chip unit which has a connection relation with the target chip unit and has intersection in working time; wherein the target chip unit is the first chip unit or the second chip unit;
performing a replacement operation on the fifth chip unit until the dynamic electrical parameter of the target chip unit meets the chip design condition; wherein the fifth chip unit is different from the fourth chip unit; the replacing operation comprises: searching a sixth chip unit meeting a third replacement condition from a library, and replacing the fifth chip unit with the sixth chip unit so as to influence the dynamic electrical parameters of the target chip unit;
wherein the third replacement condition comprises: the layout is the same as the fifth chip unit and has inherent electrical characteristics superior to the fifth chip unit.
5. The method of any of claims 1 to 4, wherein the intrinsic electrical characteristics are better than the chip unit to be replaced, comprising: the delay and/or the threshold voltage is larger than the chip unit to be replaced;
the layout is the same as the chip cells to be replaced, including: the same connection relationship between the components and the corresponding components is the same as that under the chip unit to be replaced, and the bottom layer doping is different from that of the chip unit to be replaced.
6. A method of chip design, the method comprising:
determining a first chip unit of which the dynamic electrical parameters do not meet the chip design conditions in the designed chip structure;
determining a third chip unit which has a connection relation with the first chip unit and has intersection in working time;
searching a fourth chip unit meeting a second replacement condition from the library; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit;
replacing the third chip unit with the fourth chip unit, thereby affecting a dynamic electrical parameter of the first chip unit.
7. A chip design apparatus, comprising:
a first determination module configured to determine a first chip unit in the designed chip structure for which the dynamic electrical parameter does not satisfy the chip design condition;
a first search module configured to search the library for a second chip unit satisfying a first replacement condition; wherein the first replacement condition includes a layout identical to the first chip cell and having inherent electrical characteristics superior to the first chip cell;
a first replacement module configured to replace the first chip unit with the second chip unit.
8. A chip design apparatus, comprising:
a second determination module configured to determine a first chip unit in the designed chip structure for which the dynamic electrical parameter does not satisfy the chip design condition;
a third determining module configured to determine a third chip unit having a connection relation with the first chip unit and intersection of working times;
a second searching module configured to search the library for a fourth chip unit satisfying a second replacement condition; wherein the second replacement condition includes a layout identical to the third chip unit and having inherent electrical characteristics superior to the third chip unit;
a second replacement module configured to replace the third chip unit with the fourth chip unit, thereby affecting a dynamic electrical parameter of the first chip unit.
9. An electronic device comprising a memory and a processor, the memory storing a computer program operable on the processor, wherein the processor implements the method of any of claims 1 to 5 when executing the program or implements the method of claim 6 when executing the program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method of any one of claims 1 to 5, or which, when being executed by a processor, carries out the method of claim 6.
CN202210406306.1A 2022-04-18 2022-04-18 Chip design method and device, equipment and storage medium Pending CN114722747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210406306.1A CN114722747A (en) 2022-04-18 2022-04-18 Chip design method and device, equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210406306.1A CN114722747A (en) 2022-04-18 2022-04-18 Chip design method and device, equipment and storage medium

Publications (1)

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