CN114721877A

CN114721877A - Software fault tolerance recovery method, device, equipment and storage medium

Info

Publication number: CN114721877A
Application number: CN202210442347.6A
Authority: CN
Inventors: 黄歆; 林乔捷; 闫雪
Original assignee: Guangzhou Xiaopeng Motors Technology Co Ltd
Current assignee: Guangzhou Xiaopeng Motors Technology Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-07-08

Abstract

The application discloses a software fault-tolerant recovery method, a device, equipment and a storage medium, which are applied to a system-on-chip connected with an EMMC chip, and the method comprises the following steps: when the EMMC chip is in a working state, if a target access request is acquired, whether the execution of the historical access request is finished is judged; if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; if the historical access request access execution is completed, the target access request is executed to access the EMMC chip. Therefore, by adopting the method, when the system-on-chip accesses the EMMC chip in error, the EMMC chip is restarted to perform software fault-tolerant recovery so as to keep the system-on-chip to normally work and improve the working safety of the system-on-chip.

Description

Software fault tolerance recovery method, device, equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method, an apparatus, a device, and a storage medium for recovering software fault tolerance.

Background

With the intellectualization of automobiles, a large-capacity and high-speed storage system is required to support the intellectualization of automobiles in the fields of vehicle control, vehicle-mounted entertainment and automatic driving of vehicles. At present, the memory system of the memory of EMMC chip has been very popular. However, the system to which the EMMC chip is connected has a problem of low security due to inherent defects of the EMMC memory system.

Disclosure of Invention

The application provides a software fault-tolerant recovery method, a device, equipment and a storage medium, so as to improve the problems.

In a first aspect, an embodiment of the present application provides a software fault tolerance recovery method, which is applied to a system-on-chip connected with an EMMC chip, and the method includes: when the EMMC chip is in a working state, if a target access request is acquired, whether the historical access request is executed or not is judged, the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling a system-level chip to access the EMMC chip; if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; if the historical access request access execution is completed, the target access request is executed to access the EMMC chip.

In a second aspect, an embodiment of the present application further provides a software fault-tolerant recovery device, which is applied to a system-on-chip connected with an EMMC chip, and the device includes: the system comprises a target request acquisition unit, an access content storage unit, a fault-tolerant recovery unit and a target request execution unit. The target access request acquisition unit is used for judging whether the historical access request is executed or not if the target access request is acquired under the working state of the EMMC chip, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip; the access content storage unit is used for storing the content of the EMMC chip accessed in the history access request if the history access request is not completely accessed; the fault-tolerant recovery unit is used for restarting the EMMC chip after finishing storing the content of the EMMC chip accessed in the historical access request and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; and the target request execution unit is used for executing the target access request to access the EMMC chip if the historical access request access execution is completed.

In one embodiment, the fault-tolerant recovery unit is further configured to, after storing the content of the EMMC chip accessed in the historical access request, turn off the power supply of the EMMC chip for a preset time period and then start the EMMC chip again; after the EMMC chip is started, the history access request is executed based on the content of the EMMC chip accessed in the saved history access request.

In one embodiment, the access content storage unit is further configured to obtain a type of an error generated when the access of the historical access request is not completed; creating a fault tolerant recovery flag based on the error type; if the execution of the historical access request is completed, judging whether a fault-tolerant recovery mark exists or not; if the fault-tolerant recovery mark exists, a fault-tolerant recovery success mark is established, and the target log is obtained according to the fault-tolerant recovery mark and the fault-tolerant recovery success mark.

In one embodiment, the accessing the content storage unit is further configured to clear the fault-tolerant restoration flag and the fault-tolerant restoration success flag after obtaining the target log.

In one embodiment, the fault-tolerant recovery unit is further configured to control, based on the content of the stored historical access request for accessing the EMMC chip, the controller in the EMMC chip to send an access address and an access data size corresponding to the historical access request to the memory in the EMMC chip, so that the memory writes data sent by the system-on-chip to the memory based on the access address and the access data size, or reads data from the memory and sends the data to the system-on-chip based on the access address and the access data size.

In one embodiment, the target request obtaining unit is further configured to, if a target access request is obtained, analyze the target access request to obtain target analysis data of the target access request, where the target analysis data includes an address and a data size of a target access request read/write EMMC chip; the target request execution unit is further used for controlling the controller of the EMMC chip to send a target command including target analysis data to a memory in the EMMC chip if the historical access request access execution is completed, so that the memory can respond to the target command to obtain data corresponding to the address and the data size of the target access request read EMMC chip and send the data to the system-on-chip, or write the data sent by the system-on-chip into a storage position corresponding to the address and the data size of the target access request write EMMC chip in the memory.

In one embodiment, the target request obtaining unit is further configured to obtain the target access request when it is detected that a target access request enters the access request queue based on a preset access process before the execution of the target access request is completed and whether the execution of the historical access request is completed is determined.

In one embodiment, the target request obtaining unit is further configured to block the preset access process if the historical access request access is not completed, so that the access request queue does not receive a new access request any more.

In a third aspect, an embodiment of the present application further provides an electronic device, including: one or more processors, memory, and one or more applications. Wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to execute to implement the method as described in the first aspect above.

In a fourth aspect, embodiments of the present application further provide a computer-readable storage medium, in which a program code is stored, and the program code can be called by a processor to execute the method according to the first aspect.

The technical scheme provided by the application is applied to a system-level chip connected with an EMMC chip, and whether a historical access request is executed or not is judged if the target access request is acquired when the EMMC chip is in a working state, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip; if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; and if the historical access request access execution is completed, executing the target access request to access the EMMC chip. Therefore, by adopting the method, after the system-level chip reads/writes the EMMC chip and makes an error, the EMMC chip is immediately restarted to perform software fault-tolerant recovery operation, the working safety of the system-level chip is improved, the system-level chip does not need to be restarted, a user cannot sense the error of the system-level chip read/write EMMC chip, and the experience of the user is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 illustrates a flowchart of a software fault tolerance recovery method according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating a software fault tolerance recovery method according to another embodiment of the present application;

FIG. 3 is a flowchart illustrating a software fault tolerance recovery method according to another embodiment of the present application;

FIG. 4 is a flowchart illustrating an operation of a software fault tolerance recovery apparatus according to an embodiment of the present application;

fig. 5 shows a block diagram of an electronic device according to an embodiment of the present application;

fig. 6 shows a block diagram of a computer storage medium according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The EMMC (Embedded multimedia Card) is an Embedded memory standard specification established by the MMC association and mainly used for products such as mobile phones or tablet computers. The EMMC integrates a controller in a package, provides a standard interface and manages a flash memory; the EMMC chip has MMC (multimedia card) interface, flash memory device and controller, and is packaged by a small BGA; the interface speed of the EMMC chip is as high as 400MBytes per second, and the interface voltage of the EMMC chip can be 1.8V or 3.3V; the EMMC chip has fast and scalable performance.

With the automobile intellectualization, the use of an EMMC chip as a memory has generally begun in vehicle memory systems. However, in the related art, in the memory system using the EMMC chip as the memory, the EMMC chip uses 8 data lines for parallel transmission, and once the clock frequency is raised, the interference becomes large, and the integrity of the signal cannot be guaranteed; meanwhile, during the running of the vehicle, due to the influence of temperature and static electricity, the EMMC chip may have read-write overtime or CRC (cyclic redundancy check) errors at any time; moreover, the internal software and hardware systems of the EMMC chip are very complex, and as the EMMC chip is aged as a storage unit, the defects of the controller of the EMMC chip cause the EMMC storage system to have some inherent defects, which easily causes system crash, black screen, file system damage and the like, and further causes the system-level chip connected with the EMMC chip to have low working safety. Therefore, the system-on-chip operation of the EMMC chip has a problem of low security due to inherent defects of the EMMC memory system.

In order to alleviate the above problem, the inventor of the present application provides a software fault-tolerant recovery method, device, apparatus and storage medium provided in an embodiment of the present application, which are applied to a system-on-chip, where the system-on-chip is connected to an EMMC chip. The method comprises the following steps: when the EMMC chip is in a working state, if a target access request is acquired, whether the historical access request is executed or not is judged, the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling a system-level chip to access the EMMC chip; if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; if the historical access request access execution is completed, the target access request is executed to access the EMMC chip. Therefore, by adopting the method, the EMMC chip is restarted immediately to perform software fault-tolerant recovery operation after the system-level chip reads/writes the EMMC chip and has errors, and the working safety of the system-level chip is improved.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a software fault tolerance recovery method according to an embodiment of the present application, where the method may be applied to a system-on-chip, where the system-on-chip is connected to an EMMC chip, and the system-on-chip may be applied to a terminal, such as a vehicle-mounted terminal, a robot, a computer, a smart phone, and the like, to implement the present solution, which is not limited herein. Referring to fig. 1, the method includes at least steps S110 to S140.

Step S110: and when the EMMC chip is in a working state, if a target access request is acquired, judging whether the historical access request is executed completely, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip.

In an embodiment of the present application, a System On Chip (SOC) of an EMMC chip is connected, wherein the SOC may be a product, an integrated circuit with a dedicated target, which contains the complete system and has the entire content of embedded software. The system-level chip comprises a system-level chip control logic module, a microprocessor/microcontroller CPU core module, a digital signal processor DSP module, an embedded memory module, an interface module for communicating with the outside, an analog front-end module containing ADC/DAC, a power supply and power consumption management module and the like; for a wireless SOC that may also include rf front-end modules, user-defined logic (which may be implemented as FPGAs or ASICs), and micro-electromechanical modules, it is more important that a SOC chip has embedded therein a basic software (implementing a disk operating system or other application software) module or loadable user software, etc.

As an implementation manner, when the EMMC chip is in the working state, it may be that when the system-on-chip is started, the system-on-chip powers on the EMMC chip connected to the system-on-chip through a driver of the EMMC chip in the embedded software, initializes the EMMC chip and the initialization block device, and then the EMMC chip is in the powered-on state and the system-on-chip may read data from the EMMC chip or write data into the EMMC chip. The block device is one of i/o devices, and stores information in fixed-size blocks, each block has its own address, and data of a certain length can be read at any position of the device (e.g., a hard disk, a U-disk, an SD card, etc.).

Specifically, the system-on-chip powers on and identifies the EMMC chip connected to the system-on-chip through the EMMC driver, and the system-on-chip may read the value and state of the register of the EMMC chip through the EMMC driver to initialize the EMMC chip, and perform block device initialization through the EMMC driver, that is, create a block device for the system-on-chip to read or write the EMMC chip, and prepare for the system-on-chip to read or write data of the EMMC chip into the EMMC chip.

As another embodiment, the EMMC chip may be in an operating state, where after the EMMC chip is powered on and off for multiple times, the EMMC chip is powered on and the system-on chip may read data from or write data to the EMMC chip.

It should be understood that the EMMC chip is in an operational state, i.e., the EMMC chip is powered up and can be read from or written to, i.e., the EMMC chip can be accessed by the system-on-chip.

In some embodiments, when the EMMC chip is in a working state, and before the execution of the EMMC chip obtains a target access request and whether the execution of a historical access request is completed is judged, the EMMC chip obtains the target access request when detecting that a target access request enters an access request queue based on a preset access process; and if the historical access request access is not completed, blocking the preset access process so that the access request queue does not receive new access requests any more.

In the embodiment of the application, when the system-on-chip detects that a target access request enters an access request queue based on a preset access process, the system-on-chip acquires the target access request. The system-level chip comprises a preset access process for specially accessing the EMMC chip, the preset access process maintains an access request queue and continuously detects whether an access request for accessing the EMMC chip enters the access request queue; and if the preset access process detects that a target access request for enabling the system-level chip to access the EMMC chip enters the access request queue, acquiring the target access request.

Specifically, when the EMMC chip is in a working state and a target access request is detected to enter the access request queue based on a preset access process, the target access request is obtained, whether the historical access request is executed and completed is judged, and if the historical access request is not executed and completed, the preset access process is blocked, so that the access request queue does not receive new access requests any more.

That is, after detecting that the target access request enters the access request queue, the preset access process judges whether the execution of the historical access request is completed, and if the execution of the historical access request is not completed, the preset access process enters a sleep waiting state so that the access request queue does not receive new access requests any more; otherwise, a target access request is executed to cause the system-on-chip to write data to or read data from the EMMC chip.

It should be understood that the system-on-chip detects whether the access to the EMMC chip is in error (the read/write operation is in error) through a proprietary preset access process, and after the error is found, the access request queue does not receive a new access request any more, so that the access (the read/write operation) rate of the system-on-chip to the EMMC chip is improved.

Judging whether the historical access request is executed or not, wherein the judging step comprises the step that the system-on-chip accesses the EMMC chip according to the historical access request, and the historical access request comprises a callback function; if the historical access request is not executed, the system-on-chip calls the callback function to enable the preset access process to be blocked (namely, the preset access process enters a sleep waiting state) so as to execute the target access request and enable the access request queue to receive a new access request after the historical access request is executed; if the historical access request is executed, the system-on-chip calls the callback function, so that the preset access process can continuously detect whether a new target access request enters the access request queue, and the system-on-chip executes the target access request so as to write data into the EMMC chip or read data from the EMMC chip.

It should be understood that, in the embodiment of the present application, the system on chip accesses the EMMC chips one by one, that is, after the last access request causes the system on chip to complete the read/write data operation on the EMMC chip, the next access request for the read/write data operation on the EMMC chip is executed.

Step S120: if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored.

Alternatively, the historical access request access not being completed may be that the system on chip failed to read/write data to the EMMC chip. Specifically, the failure of the system on chip to read/write data to the EMMC chip may be that the system on chip has read/write data to the EMMC chip overtime; CRC (cyclic redundancy check) errors that may occur when the system on chip reads/writes data to/from the EMMC chip during data transmission or saving; the address error of reading the data of the EMMC chip by the system level chip can be generated; address errors that may be data written by the system-on-chip to the EMMC chip; it may be a system-on-chip read EMMC chip data size error; the data size error written into the EMMC chip by the system on chip may be, but is not limited to, the data size error.

In some embodiments, if the history access request access is not completed, the content of the EMMC chip accessed in the history access request may be saved in a data structure initialized by the system chip according to the history access request. The contents of the EMMC chip accessed in the saved execution history access request may include an address at which the history access request causes the system-on-chip to read data of the EMMC chip, an address at which the system-on-chip writes data to the EMMC chip, a data size at which the history access request causes the system-on-chip to read or write data to the EMMC chip, and the like. The data structure initialized by the system-on-chip according to the historical access request can be that when a target access request enters an access request queue based on a preset access process, the target access request is obtained; the preset access process obtains a target access request, analyzes and processes the target access request, and obtains an access purpose of the target access request, namely the target access request enables a system-level chip to read data of the EMMC chip or enables the system-level chip to write the data into the EMMC chip; and initializing a data structure corresponding to the data of the system-on-chip read/write EMMC chip according to the access purpose of the target access request.

The data structure is a way for a computer to store and organize data. A data structure refers to a collection of data elements that have one or more specific relationships to each other. Typically, a carefully selected data structure can lead to greater operational or storage efficiency. Data structures are often associated with efficient retrieval algorithms and indexing techniques; the data structure is a collection of data elements with structural characteristics, which studies the logical structure of data and the physical structure of data and the mutual relationship between them, defines the adaptive operation for the structure, designs the corresponding algorithm, and ensures that the new structure obtained after the operation still maintains the original structure type.

It should be noted that the content of the EMMC chip accessed in the execution history access request is stored, so that the access context of the system-on-chip to the EMMC chip is recovered after the EMMC chip is restarted, that is, before the power of the EMMC chip is turned off, the value and the state of the register when the system-on-chip accesses the EMMC chip and the command including the partition, the sector number, the Buffer address of the read/write data, the length of the read/write data, and the like of the system-on-chip accessing the EMMC chip, which are sent by the controller of the EMMC chip, are recovered, so that the memory of the EMMC chip responds to the command after receiving the command to perform data interaction with the system-on-chip, so that the user has no sense of processing of fault tolerance recovery of the software, and the experience of the user is improved.

Step S130: and after the content of the EMMC chip accessed in the history access request is saved, restarting the EMMC chip, and executing the history access request based on the content of the EMMC chip accessed in the saved history access request.

In some embodiments, after the content of the EMMC chip accessed in the history access request is saved, the EMMC chip is restarted, and the history access request is executed based on the current content may be that, after the content of the EMMC chip accessed in the history access request is saved, the EMMC chip is restarted after the power of the EMMC chip is turned off for a preset time period; after the EMMC chip is started, the history access request is executed based on the content of the EMMC chip accessed in the saved history access request.

The preset time period can be obtained through third-party experimental data or can be set by a user; the preset time period is stored in the driving program of the system-on-chip to the EMMC chip in advance. Illustratively, the specific preset time period is 2s, 1s, 0.5s, and the like.

It should be appreciated that the EMMC chip is completely powered down after a preset period of time after the power to the EMMC chip is turned off.

As an embodiment, if the hardware design of the terminal makes the system-on-chip unable to control the power supply of the EMMC chip, after finishing saving the contents of the EMMC chip accessed in the historical access request, the EMMC chip may be restarted by replacing the operation of restarting the EMMC chip with a hardware reset (such as a low voltage reset, a power-on reset, a power-off reset, and the like).

As another embodiment, if the hardware design of the terminal enables the system-on-chip to control the power supply of the EMMC chip, after the contents of the EMMC chip accessed in the historical access request are saved, the EMMC chip is restarted, where the power supply of the EMMC chip is turned off and then turned on after a preset time period.

After the EMMC chip is powered on or reset again, the EMMC chip is initialized again to enable the EMMC chip to enter a read/write working mode (namely a working state), and since the EMMC chip is not recognized for the first time when the system level chip is started, block equipment for reading/writing the EMMC chip does not need to be created again.

Specifically, initializing the EMMC chip may be based on restoring the context of the history access request accessing the EMMC chip based on the contents of the saved history access request accessing the EMMC chip. For example, initializing the EMMC chip causes the controller of the EMMC chip to issue a command including a partition including data of the memory that reads/writes the EMMC chip before turning off the power of the EMMC chip, a sector number, a Buffer address of the read/write data, and a Buffer size, so that the memory of the EMMC chip performs data interaction with the system-on-chip in response to the command.

It should be understood that after the EMMC chip is restarted, the history access request is executed based on the content of the EMMC chip accessed in the stored history access request, so that the system-level chip accesses the EMMC chip based on the history access request after the EMMC chip is restarted, and the context environment of the system-level chip accessing the EMMC chip based on the history access request before the EMMC chip is restarted is consistent with the context environment of the system-level chip accessing the EMMC chip based on the history access request, so that the system-level chip continues to read/write the EMMC chip based on the history access request, the software fault-tolerant recovery is completed under the condition that a user does not sense, and the experience of the user is improved.

In some embodiments, executing the history access request may be controlling a controller in the EMMC chip to send an access address and an access data size corresponding to the history access request to a memory in the EMMC chip based on contents of the saved history access request for accessing the EMMC chip, so that the memory writes data sent by the system-on-chip to the memory based on the access address and the access data size, or reads data from the memory and sends the data to the system-on-chip based on the access address and the access data size.

In the embodiment of the application, if the system-on-chip accesses the EMMC chip according to the historical access request and makes mistakes, the preset access process controls the access request queue to not receive a new access request, and the system-on-chip performs software fault-tolerant recovery processing in time through the EMMC chip driver, so that the file system of the disk partition of the EMMC chip is prevented from being further damaged.

Step S140: and if the historical access request access execution is completed, executing the target access request to access the EMMC chip.

In some embodiments, if the target access request is acquired, analyzing the target access request to acquire target analysis data of the target access request, where the target analysis data includes an address and a data size of the target access request read/write EMMC chip.

If the access execution of the historical access request is completed, the target access request is executed to access the EMMC chip, and if the access execution of the historical access request is completed, the controller of the EMMC chip is controlled to send a target command including target analysis data to the memory in the EMMC chip, so that the memory responds to the target command to obtain data corresponding to the address and the data size of the target access request read from the EMMC chip and send the data to the system-on-chip, or the data sent by the system-on-chip is written into the memory at a storage location corresponding to the address and the data size of the target access request write from the EMMC chip.

The step of executing the target access request to access the EMMC chip may be that the system-on-chip controls the controller of the EMMC chip to send a target command including an address and a data size of the target access request read/write EMMC chip to the memory of the EMMC chip through a driver of the EMMC chip, and after receiving a response of the memory in the EMMC chip to the target command, writes data sent by the system-on-chip into a storage location in the memory corresponding to the address and the data size of the target access request write EMMC chip, or sends the address and the data size of the target access request read EMMC chip corresponding to the memory in the EMMC chip to the system-on-chip, thereby completing interaction between the system-on-chip and the EMMC chip.

The technical scheme provided by the embodiment of the application is applied to a system-level chip connected with an EMMC chip, and is characterized in that whether a historical access request is executed or not is judged if the target access request is acquired under the working state of the EMMC chip, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip; if the access of the historical access request is not completed, the content of the EMMC chip accessed in the historical access request is stored; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; if the historical access request access execution is completed, the target access request is executed to access the EMMC chip. Therefore, by adopting the method, after the system-level chip accesses the EMMC chip and makes an error, the EMMC chip is restarted to execute the software fault-tolerant recovery processing of the system-level chip to the EMMC chip in time, so that the working safety of the system-level chip is improved, the fault-tolerant recovery is completed in a state that a user does not sense, and the experience of the user is improved.

Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a software fault tolerance recovery method according to an embodiment of the present application, where the method may be applied to a system-on-chip, where the system-on-chip is connected to an EMMC chip, and the system-on-chip may be applied to a terminal, such as a vehicle-mounted terminal, a robot, a computer, a smart phone, and the like, to implement the present solution, which is not limited herein. Referring to fig. 2, the method includes at least steps S210 to S250.

Step S210: and when the EMMC chip is in a working state, if a target access request is acquired, judging whether the historical access request is executed completely, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip.

Step S220: if the access of the historical access request is not completed, the contents of the EMMC chip accessed in the historical access request are stored, the error type generated when the access of the historical access request is not completed is obtained, and a fault-tolerant recovery mark is created based on the error type.

In the embodiment of the application, the historical access request access is not executed completely, namely the historical access request execution fails, and the historical access request execution failure can occur at each stage of reading/writing the EMMC chip by the system on chip according to the historical access request. The reason why the access of the historical access request is not completed can include timeout of a system level chip read/write EMMC chip, CRC (Cyclic Redundancy Check) error and the like. CRC is a channel coding technique for generating a short fixed-bit check code based on data such as network data packets or computer files, and is mainly used to detect or check errors that may occur after data transmission or storage, and uses the principles of division and remainder to detect errors.

In some embodiments, the type of the error generated when the access of the history access request is not completed may be that the system on chip obtains a specific value and a state of a register included in a memory in the EMMC chip through a driver of the EMMC chip, and obtains the type of the error generated when the access of the history access request is not completed according to the specific value and the state of the register.

It should be noted that the purpose of acquiring the error type generated when the historical access request access is not completed is to acquire the reason why the historical access request access fails this time (i.e., the reason why the software fault-tolerant recovery process occurs this time).

In the embodiment of the application, the system-on-chip creates the fault-tolerant recovery mark corresponding to the error type based on the error type.

It should be noted that the system-on-chip creates a fault-tolerant recovery flag corresponding to the error type based on the error type, so that the system-on-chip starts to save the target log based on the fault-tolerant recovery flag.

Step S230: after the preservation of the contents of the EMMC chip accessed in the history access request is completed, the EMMC chip is restarted and the history access request is executed based on the contents of the EMMC chip accessed in the history access request.

Step S240: and if the historical access request access execution is completed, executing the target access request to access the EMMC chip, and judging whether a fault-tolerant recovery mark exists.

In some embodiments, the determining whether the fault-tolerant restoration flag exists may be that the driver of the EMMC chip of the system-on-chip obtains a specific value and a state of a register included in the system-on-chip, and determines whether the fault-tolerant restoration flag exists according to the specific value and the state of the register.

Step S250: if the fault-tolerant recovery mark exists, a fault-tolerant recovery success mark is established, and the target log is obtained according to the fault-tolerant recovery mark and the fault-tolerant recovery success mark.

The target log is a log of an EMMC chip access error in software fault-tolerant recovery processing performed by a system-on-chip, and the target log corresponds to one-time software fault-tolerant recovery processing or multiple times of software fault-tolerant recovery processing; the content of the target log may include the error type of the software fault-tolerant recovery process, the time when the error occurred, the length of time the software fault-tolerant recovery process was performed, and the like.

In some embodiments, after the historical access request access execution is completed, if the system-on-chip detects that the fault-tolerant restoration flag exists in the memory of the system-on-chip through a driver of the EMMC chip in the system-on-chip, the system-on-chip creates a fault-tolerant restoration success flag corresponding to the fault-tolerant restoration flag.

The system-level chip comprises a preset EMMC chip access diagnosis process, and the process monitors the access state of the system-level chip to the EMMC chip in real time in an application layer of the system-level chip. When the preset EMMC chip access diagnosis process detects the fault-tolerant recovery success mark, the preset EMMC chip access diagnosis process stores the corresponding fault-tolerant recovery success mark and the target log corresponding to the fault-tolerant recovery mark in the application layer of the system-on-chip and sends the target log to the memory of the EMMC chip for storage.

For example, the driver of the EMMC chip of the system-on-chip includes an EMMC DIAG process in the application layer of the system-on-chip, which can monitor the access state of the system-on-chip to the EMMC chip in real time; when the EMMC DIAG process detects the fault-tolerant restoration success mark, the EMMC DIAG process saves the corresponding fault-tolerant restoration success mark and the target log corresponding to the fault-tolerant restoration mark in the application layer of the system-level chip and sends the target log to the memory of the EMMC chip for storage.

It should be noted that the purpose of generating the fault-tolerant restoration success flag is to notify the preset access diagnosis process of the EMMC chip that the software fault-tolerant restoration success processing occurs in the system-level chip read/write EMMC chip, so that the system-level chip stores the target log corresponding to the software fault-tolerant restoration processing, and further, the stored target log can be checked to check the error type corresponding to the software fault-tolerant restoration processing, and the root cause of the error occurring in the system-level chip read/write EMMC chip is analyzed. The system-on-chip generates logs all the time, and stores the target logs with fault tolerance when the system-on-chip reads/writes the EMMC chip, so that the logs generated when the system-on-chip works for a long time are prevented from being refreshed continuously, and the target logs which can analyze the specific reasons for the fault tolerance when the system-on-chip reads/writes the EMMC chip are covered.

It should be understood that storing the target log corresponding to the fault-tolerant recovery flag and the fault-tolerant recovery success flag may facilitate analyzing the root cause of the read/write failure of the system-on-chip to the EMMC chip, and may further enhance the reliability of the EMMC chip and the robustness of the software according to the root cause.

Illustratively, the reason for analyzing the read/write failure of the system-on-chip to the EMMC chip according to the target log includes that the clock frequency of the EMMC chip is low, and then the system-on-chip is enabled to read/write overtime to the EMMC chip, so that the read/write performance of the EMMC chip can be faster by increasing the clock frequency of the EMMC chip, and the reliability of the EMMC chip and the robustness of software are enhanced.

In some embodiments, the vehicle uses the EMMC chip as a memory to form a storage system, a large number of operations of reading/writing the EMMC chip are involved in the process of using the OTA (over the air technology), the root cause of the read/write failure of the system-level chip to the EMMC chip can be analyzed according to the stored target log, and then the reliability of the EMMC chip and the robustness of software can be enhanced according to the root cause, so that the working state of the vehicle is more stable in the process of using the OTA (over the air technology), and the risk of the upgrade failure of the vehicle using the OTA (over the air technology) is reduced.

In some embodiments, if the chip connected to the system-on-chip includes other chips (e.g., a SIM card, a flash memory, etc.) besides the EMMC chip, it may be considered to store the target log in the other chips, so that the system-on-chip may immediately store the target log at an application layer of the system-on-chip according to the fault-tolerant recovery flag before the EMMC chip reads/writes errors through a driver of the EMMC chip and the fault-tolerant recovery process is not successful.

In an implementation manner provided in the embodiment of the present application, in consideration of saving a storage space of the system-on-chip and enabling the system-on-chip to normally store a target log generated by the system-on-chip performing fault-tolerant recovery processing on the EMMC chip, after the target log after one-time successful fault-tolerant recovery processing of software is stored, the fault-tolerant recovery flag and the fault-tolerant recovery success flag may be cleared, so as to save resources and purposefully store the log generated by the system-on-chip.

By adopting the technical scheme, the method is applied to the system-level chip connected with the EMMC chip, and whether the historical access request is executed or not is judged if the target access request is acquired when the EMMC chip is in a working state, wherein the historical access request is the access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip; if the access of the historical access request is not completed, the contents of the EMMC chip accessed in the historical access request are stored, the error type generated when the access of the historical access request is not completed is obtained, and a fault-tolerant recovery mark is created based on the error type; after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request; if the historical access request access execution is completed, executing the target access request to access the EMMC chip, and judging whether a fault-tolerant recovery mark exists or not; if the fault-tolerant recovery mark exists, a fault-tolerant recovery success mark is established, and the target log is obtained according to the fault-tolerant recovery mark and the fault-tolerant recovery success mark. Therefore, by adopting the method, the EMMC chip is restarted immediately after the system-on-chip reads/writes the EMMC chip and fault-tolerant recovery operation is carried out, the working safety of the system-on-chip is improved, and meanwhile, when the system-on-chip carries out fault-tolerant recovery on the read/write EMMC chip, a target log of the system-on-chip for carrying out fault-tolerant recovery on the read/write EMMC chip is stored, so that the root cause of the system-on-chip reads/writes the EMMC chip is conveniently analyzed according to the target log, a user can conveniently improve the access process of the system-on-chip to the EMMC chip according to the root cause, and the reliability of the EMMC chip and the robustness of the system-on-chip to the EMMC chip are enhanced.

Referring to fig. 3, a software fault tolerance recovery apparatus according to an embodiment of the present application is shown, which is applied to a system on chip connected with an EMMC chip, where the apparatus 300 includes: a target request acquisition unit 310, an access content storage unit 320, a fault tolerant restoration unit 330, and a target request execution unit 340. Specifically, the target request obtaining unit 310 is configured to, when the EMMC chip is in a working state, determine whether the execution of the historical access request is completed if the target access request is obtained, where the historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-level chip to access the EMMC chip; the access content storage unit 320 is used for storing the content of the EMMC chip accessed in the history access request if the history access request is not completely accessed; the fault-tolerant recovery unit 330 is configured to restart the EMMC chip after finishing storing the content of the EMMC chip accessed in the history access request, and execute the history access request based on the content of the EMMC chip accessed in the stored history access request; and the target request execution unit 340 is configured to execute the target access request to access the EMMC chip if the historical access request access execution is completed.

In one embodiment, the fault-tolerant recovery unit 330 is further configured to, after storing the content of the EMMC chip accessed in the historical access request, turn off the power supply of the EMMC chip for a preset time period and then start the EMMC chip again; after the EMMC chip is started, the history access request is executed based on the content of the EMMC chip accessed in the saved history access request.

In one embodiment, the access content storage unit 320 is further configured to obtain a type of error generated when the access of the historical access request is not completed; creating a fault tolerant recovery flag based on the error type; if the execution of the historical access request is completed, judging whether a fault-tolerant recovery mark exists or not; if the fault-tolerant recovery mark exists, a fault-tolerant recovery success mark is established, and the target log is obtained according to the fault-tolerant recovery mark and the fault-tolerant recovery success mark.

In one embodiment, the access content storage unit 320 is further configured to clear the fault-tolerant restoration flag and the fault-tolerant restoration success flag after obtaining the target log.

In one embodiment, the fault-tolerant recovery unit 330 is further configured to control, based on the content of the stored historical access request for accessing the EMMC chip, the controller in the EMMC chip to send an access address and an access data size corresponding to the historical access request to the memory in the EMMC chip, so that the memory writes data sent by the system-on-chip to the memory based on the access address and the access data size, or reads data from the memory and sends the data to the system-on-chip based on the access address and the access data size.

In one embodiment, the target request obtaining unit 310 is further configured to, if a target access request is obtained, analyze the target access request to obtain target analysis data of the target access request, where the target analysis data includes an address and a data size of a target access request read/write EMMC chip; the target request execution unit is further used for controlling the controller of the EMMC chip to send a target command including target analysis data to a memory in the EMMC chip if the historical access request access execution is completed, so that the memory can respond to the target command to obtain data corresponding to the address and the data size of the target access request read EMMC chip and send the data to the system-on-chip, or write the data sent by the system-on-chip into a storage position corresponding to the address and the data size of the target access request write EMMC chip in the memory.

In one embodiment, the target request obtaining unit 310 is further configured to, before the step of obtaining the target access request and determining whether the historical access request is completely executed, obtain the target access request when it is detected that a target access request enters the access request queue based on a preset access process.

In one embodiment, the target request obtaining unit 310 is further configured to block the preset access process if the historical access request access is not completed, so that the access request queue does not receive a new access request any more.

Referring to fig. 4, as an embodiment, the workflow of the software fault-tolerant recovery apparatus may include the following steps:

step S01: the EMMC chip is powered up and the block devices of the system-on-chip are initialized.

The system-on-chip connected with the EMMC chip can power on the EMMC chip through a driving program of the EMMC chip, set the value and the state of a register of the EMMC chip to initialize the EMMC chip and read/write the EMMC chip initialization block equipment of the system-on-chip.

Step S02: it is determined whether the historical access request is performed.

If a preset access process included in the system-level chip detects that a target access request enters an access request queue, acquiring the target access request; the preset access process processes the target access request, obtains the target access request so as to enable the system-on-chip to access the EMMC chip (read/write data), and initializes a data structure of the system-on-chip for reading/writing data of the EMMC chip according to the target access request; meanwhile, the preset access process detects whether the historical access request is completed.

Step S03: the contents of the EMMC chip accessed in the execution history access request are saved.

If the historical access request is not executed completely, the access request queue is controlled by the preset access process not to receive a new target access request; when the access of the historical access request is unsuccessful, the system-on-chip reads the value and the state of an EMMC chip register through a driving program of the EMMC chip, obtains the error type of the access unsuccessful of the historical access request, creates a fault-tolerant recovery mark corresponding to the error type, and stores an EMMC access context, namely the content of the EMMC chip accessed in the execution historical access request.

Step S04: the EMMC chip is restarted.

Turning off the power supply of the EMMC chip for 2s and then turning on the power supply of the EMMC chip again; and resetting the controller of the EMMC chip based on the content of the accessed EMMC chip in the saved history access request, and setting the value and the state of the register of the EMMC chip through the driving program of the EMMC chip so as to reinitialize the EMMC chip to continuously execute the history access request.

Step S05: the access request is executed.

The system-on-chip controls a controller in the EMMC chip to send an access address and an access data size corresponding to a historical access request to a memory in the EMMC chip through a driving program of the EMMC chip, and simultaneously controls the controller in the EMMC chip to receive interrupt signal processing irq (emergency), namely, the system-on-chip accesses the EMMC chip preferentially, updates an EMMC access context (the address of the system-on-chip accessing the EMMC chip, the size of read/write data and the like) so that the memory writes data sent by the system-on-chip into the memory based on the access address and the access data size, or reads data from the memory based on the access address and the access data size and sends the data to the system-on-chip to complete the request for accessing the EMMC chip in the historical access request.

If the access request corresponds to that the system level chip reads data of the EMMC chip, the system level chip sets a register in a manner of controlling the controller of the EMMC chip to correspondingly read the data through the driving program of the EMMC chip; if the access request corresponds to the fact that the system-on-chip writes data into the EMMC chip, setting a register according to the mode that the system-on-chip controls a controller of the EMMC chip to write data correspondingly; the system level chip controls a controller of the EMMC chip to send different commands corresponding to reading and writing to a memory of the EMMC through a driving program of the EMMC chip. The command further includes the size of the read/write data, the start address of the read/write data, and the like, which are configured by the controller of the EMMC chip through the driver of the EMMC chip.

Step S06: and saving the target log.

After the request for accessing the EMMC chip in the historical access request is completed, the preset access process detects that the historical access request is completed, and the access request queue is controlled to receive the target access request; the system level chip judges whether the fault-tolerant recovery mark exists or not through a driving program of the EMMC chip, if not, the controller of the EMMC chip is controlled to send a target command comprising target analysis data to a memory in the EMMC chip, so that the memory responds to the target command to obtain data corresponding to the address and the data size of the target access request read EMMC chip and sends the data to the system level chip, or the data sent by the system level chip is written into a storage position corresponding to the address and the data size of the target access request write EMMC chip in the memory.

The system level chip judges whether the fault-tolerant recovery mark exists through a driving program of the EMMC chip, if so, the fault-tolerant recovery mark is removed, a fault-tolerant recovery success mark is created, an application layer of the system level chip is informed of fault tolerance and recovery success, and the system level chip stores a target log and removes the fault-tolerant recovery success mark under the control of a preset diagnosis process (EMMC DIAG process) in the application layer of the system level chip through the driving program of the EMMC chip.

It should be noted that, the embodiments of the present disclosure are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment. For any processing manner described in the method embodiment, the processing manner may be implemented by a corresponding processing module in the apparatus embodiment, and details in the apparatus embodiment are not described any more.

Referring to fig. 5, based on the software fault-tolerant restoration method, another electronic device 400 that includes a processor 410, a memory 420, and an application program is provided in the present application. The memory 420 stores programs that can execute the contents of the foregoing embodiments, and the processor 410 can execute the programs stored in the memory 420. The electronic device 400 may be an intelligent control panel, an intelligent wearable device, a vehicle, an intelligent robot, a tablet computer, a personal computer, and the like.

Processor 410 may include, among other things, one or more cores for processing data and a message matrix unit. The processor 410 interfaces with various components throughout the electronic device using various interfaces and circuitry to perform various functions of the electronic device 400 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 420 and invoking data stored in the memory 420. Alternatively, the processor 410 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 410 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the above modem may be implemented by a communication chip without being integrated into the processor.

The Memory 420 may include an EMMC Memory, a Random Access Memory (RAM), and a Read-Only Memory (Read-Only Memory). The memory 420 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 420 may include a program storage area and a data storage area, where the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (for example, when the EMMC chip is in a working state, if a target access request is obtained, whether a historical access request is executed or not is determined to be completed, etc.), instructions for implementing various method embodiments described below, and the like. The storage data area may also store data created by the terminal in use (such as a target log, a fault-tolerant recovery flag, a fault-tolerant recovery success flag), and the like.

Referring to fig. 6, a block diagram of a computer-readable storage medium 500 according to an embodiment of the present application is shown. The computer-readable storage medium 500 has stored therein a program code 510, said program code 510 being invokable by the processor for performing the method described in the above-described method embodiments.

The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 500 includes a non-volatile computer-readable storage medium. The computer readable storage medium 500 has storage space for program code 510 for performing any of the method steps of the method described above. The program code 510 can be read from or written to one or more computer program products. The program code may be compressed, for example, in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A software fault tolerance recovery method is applied to a system-on-chip (SOC) which is connected with an EMMC chip, and comprises the following steps:

when the EMMC chip is in a working state, if a target access request is acquired, judging whether a historical access request is executed completely, wherein the historical access request is an access request acquired before the target access request is acquired, and the target access request is used for enabling the system-level chip to access the EMMC chip;

if the access of the historical access request is not completed, storing the content of the EMMC chip accessed in the historical access request;

after the content of the EMMC chip accessed in the historical access request is stored, restarting the EMMC chip, and executing the historical access request based on the stored content of the EMMC chip accessed in the historical access request;

and if the historical access request access execution is completed, executing the target access request to access the EMMC chip.

2. The method of claim 1, wherein the restarting the EMMC chip after saving the contents of the EMMC chip accessed in the historical access request and performing the historical access request based on the current contents comprises:

after the content of the EMMC chip accessed in the historical access request is stored, the power supply of the EMMC chip is turned off for a preset time period, and then the EMMC chip is started again;

and after the EMMC chip is started, executing the historical access request based on the content of the EMMC chip accessed in the stored historical access request.

3. The method of claim 1, wherein after saving the contents of the EMMC chip accessed in the historical access request if the historical access request access is not performed, the method further comprises:

acquiring an error type generated when the access of the historical access request is not completed;

creating a fault tolerant recovery flag based on the error type;

if the execution of the historical access request is completed, the method further comprises the following steps:

judging whether the fault-tolerant recovery mark exists or not;

if the fault-tolerant recovery mark exists, a fault-tolerant recovery success mark is established, and a target log is obtained according to the fault-tolerant recovery mark and the fault-tolerant recovery success mark.

4. The method of claim 3, further comprising:

and after the target log is obtained, clearing the fault-tolerant recovery mark and the fault-tolerant recovery success mark.

5. The method of claim 1, wherein performing the historical access request based on the saved contents of the historical access request that accessed the EMMC chip comprises:

based on the content of the history access request for accessing the EMMC chip, controlling a controller in the EMMC chip to send an access address and an access data size corresponding to the history access request to a memory in the EMMC chip, so that the memory writes data sent by the system-on-chip into the memory based on the access address and the access data size, or reads data from the memory based on the access address and the access data size and sends the data to the system-on-chip.

6. The method of claim 1, further comprising:

if a target access request is acquired, analyzing the target access request to acquire target analysis data of the target access request, wherein the target analysis data comprises an address and a data size of the target access request read/write EMMC chip;

if the historical access request access execution is completed, executing the target access request to access the EMMC chip, including:

and if the historical access request access execution is finished, controlling a controller of the EMMC chip to send a target command comprising the target analysis data to a memory in the EMMC chip so that the memory responds to the target command to obtain data corresponding to the address and the data size of the EMMC chip read by the target access request and send the data to the system-level chip, or writing the data sent by the system-level chip into a storage position corresponding to the address and the data size of the EMMC chip written by the target access request in the memory.

7. The method of claim 1, wherein before the determining whether the execution of the historical access request is completed if the execution obtains the target access request, the method further comprises:

when detecting that a target access request enters an access request queue based on a preset access process, acquiring the target access request.

8. The method of claim 7, further comprising:

and if the historical access request access is not completed, blocking the preset access process so that the access request queue does not receive new access requests.

9. A software fault-tolerant recovery device is applied to a system-on-chip (SOC) which is connected with an EMMC chip, and comprises:

a target request obtaining unit, configured to, when the EMMC chip is in a working state, determine whether a historical access request is executed and completed if a target access request is obtained, where the historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-level chip to access the EMMC chip;

the access content storage unit is used for storing the content of the EMMC chip accessed in the history access request if the history access request is not completely accessed;

the fault-tolerant recovery unit is used for restarting the EMMC chip after finishing storing the content of the EMMC chip accessed in the historical access request, and executing the historical access request based on the stored content of the EMMC chip accessed in the historical access request;

and the target request execution unit is used for executing the target access request to access the EMMC chip if the historical access request access execution is completed.

10. An electronic device, comprising:

one or more processors;

a memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-8.

11. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 8.