CN114710181A

CN114710181A - Signal processing circuit of radio frequency front end and wireless communication equipment

Info

Publication number: CN114710181A
Application number: CN202210460270.5A
Authority: CN
Inventors: 黄云; 赵平; 潘世杰; 田国光
Original assignee: Shanghai Rotary Pole Information Technology Co ltd; Beijing Watertek Information Technology Co Ltd
Current assignee: Shanghai Rotary Pole Information Technology Co ltd; Beijing Watertek Information Technology Co Ltd
Priority date: 2022-04-24
Filing date: 2022-04-24
Publication date: 2022-07-05

Abstract

The embodiment of the invention discloses a signal processing circuit of a radio frequency front end and wireless communication equipment, wherein the signal processing circuit of the radio frequency front end comprises: the signal selection circuit and the signal locking circuit; the signal selection circuit receives a plurality of external control logic signals for controlling power amplification and low-noise amplification, outputs a conducting signal to the signal locking circuit according to an effective control logic signal in the plurality of control logic signals, and blocks a control logic signal which is mutually exclusive with the effective control logic signal in the plurality of control logic signals; the signal locking circuit determines whether the amplifier enabling signal of the radio frequency front end corresponding to a certain communication system is effective according to whether the received conducting signal is effective or not so as to correspondingly control the work or the non-work of a power amplifier and a low noise amplifier of the radio frequency front end. The signal processing circuit of the radio frequency front end and the wireless communication equipment disclosed by the embodiment of the invention can avoid the output of control logic signals with conflict to the radio frequency front end.

Description

Signal processing circuit of radio frequency front end and wireless communication equipment

Technical Field

The present invention relates to the field of communications, and more particularly, to a signal processing circuit of a radio frequency front end and a wireless communication device.

Background

The broadband wireless communication equipment is suitable for various vehicles, realizes the functions of data transmission exchange and voice communication among passengers in the vehicles and between passengers on the vehicles or equipment on the vehicles, and realizes the function of wireless voice communication of the passengers on the vehicles, and can be used for commanding, communication, equipment control and team coordination.

At present, broadband wireless communication equipment mainly sends a control logic signal to a radio frequency front end through a main control board so as to control a power amplifier and a low noise amplifier of the radio frequency front end to work or not work. However, since the control logic signal sent by the main control board to the rf front end is complicated, the control logic signal with conflicting operations may be generated, which may cause the power amplifier or the low noise amplifier to be damaged. For example, during the operation of the receiver, the power amplifier transmits a high-power signal to burn down the low-noise amplifier. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

Disclosure of Invention

The embodiment of the application provides a signal processing circuit of a radio frequency front end, which comprises: the signal selection circuit and the signal locking circuit;

the signal selection circuit receives a plurality of external control logic signals for controlling power amplification and low-noise amplification, outputs a conducting signal to the signal locking circuit according to an effective control logic signal in the plurality of control logic signals, and blocks a control logic signal which is mutually exclusive with the effective control logic signal in the plurality of control logic signals;

the signal locking circuit determines whether an amplifier enabling signal of a radio frequency front end corresponding to a certain communication system is effective according to whether the received conducting signal is effective or not so as to correspondingly control a power amplifier and a low noise amplifier of the radio frequency front end to work or not work; the radio frequency front end comprises a channel of radio frequency signals of a first communication system and a second communication system, and the first communication system and the second communication system share an antenna;

when a conducting signal of a certain communication system is effective, the signal locking circuit is conducted, and an amplifier enabling signal of the communication system corresponding to the radio frequency front end is ineffective, so that the power amplifier and the low noise amplifier of the radio frequency front end are correspondingly controlled not to work.

An embodiment of the present application further provides a wireless communication device, including: the antenna comprises an antenna, a main control board, a radio frequency front end chip and a signal processing circuit of the radio frequency front end in any embodiment, wherein the input end of the signal processing circuit is connected with the main control board, and the output end of the signal processing circuit is connected with the radio frequency front end chip;

the main control board is used for sending a plurality of control logic signals to the signal processing circuit;

the radio frequency front end chip is used for sending radio frequency signals to the signal processing circuit, the radio frequency front end chip comprises a channel of radio frequency signals of a first communication system and a second communication system, and the first communication system and the second communication system share the antenna.

In the signal processing circuit and the wireless communication device of the radio frequency front end according to at least one embodiment of the present application, the signal processing circuit may be located between the main control board and the radio frequency front end, and is configured to detect a plurality of control logic signals of the main control board to the radio frequency front end, and to release normal control logic signals, directly lock the control logic signals that may generate a working conflict, and do not output the control logic signals, so that the control logic signals that may generate a conflict are prevented from being output to the radio frequency front end, and it is prevented that the power amplifier transmits a high-power signal to burn out the low noise amplifier during the operation of the receiver. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a signal processing circuit of a radio frequency front end according to an exemplary embodiment of the present invention;

fig. 2 is a schematic structural diagram of a signal processing circuit of a radio frequency front end according to another exemplary embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a signal processing circuit of an rf front end according to an exemplary embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a signal processing circuit of an rf front end according to another exemplary embodiment of the present invention;

fig. 5 is a block diagram of a wireless communication device according to an embodiment of the present invention.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

Fig. 1 is a schematic structural diagram of a signal processing circuit of a radio frequency front end according to an exemplary embodiment of the present invention, and as shown in fig. 1, the signal processing circuit of the radio frequency front end may include: a signal selection circuit 11 and a signal lock-up circuit 12.

The signal selection circuit receives a plurality of external control logic signals for controlling power amplification and low-noise amplification, outputs a conducting signal to the signal locking circuit according to an effective control logic signal in the plurality of control logic signals, and blocks a control logic signal which is mutually exclusive with the effective control logic signal in the plurality of control logic signals.

The rf front end is a series of components between the rf transceiver and the antenna, and mainly includes a Power Amplifier (PA) and a Low Noise Amplifier (LNA), which directly affect the signal transmission and reception of the wireless communication device. At present, two communication systems are generally adopted for broadband wireless communication in order to improve reliability and anti-interference capability and improve equipment universality. The radio frequency front end may include a channel for radio frequency signals of a first communication system and a second communication system, and the first communication system and the second communication system share an antenna. And a plurality of control logic signals are sent to the radio frequency front end through the main control board so as to control the work or the non-work of an amplifier under a certain communication mode or control the enabling of a power supply or a radio frequency path under a certain communication mode.

However, since the control logic signal sent by the main control board to the rf front end is complicated, the control logic signal with conflicting operations may be generated, which may cause the power amplifier or the low noise amplifier to be damaged.

In this embodiment, the signal processing circuit may be located between the main control board and the rf front end U0, and is configured to detect a plurality of control logic signals of the main control board for the rf front end. The signal selection circuit can release normal control logic signals, directly locks the control logic signals which can generate work conflict and does not output the control logic signals, can prevent the control logic signals with conflict from being output to the radio frequency front end, and prevents the power amplifier from transmitting high-power signals to burn down the low-noise amplifier during the working period of the receiver. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

The signal locking circuit determines whether an amplifier enabling signal of a radio frequency front end corresponding to a certain communication system is effective according to whether the received conducting signal is effective or not so as to correspondingly control a power amplifier and a low noise amplifier of the radio frequency front end to work or not work; the radio frequency front end comprises a channel of radio frequency signals of a first communication system and a second communication system, and the first communication system and the second communication system share an antenna.

When the conducting signal of a certain communication system is effective, the signal locking circuit is conducted, the amplifier enabling signal of the communication system corresponding to the radio frequency front end is invalid, and therefore the power amplifier and the low noise amplifier of the radio frequency front end are correspondingly controlled not to work.

In this embodiment, the output end of the signal locking circuit may be connected to a signal enable end of an amplifier of the radio frequency front end, for example, the output end of the signal locking circuit may be respectively connected to a signal enable end of a power amplifier of the radio frequency front end and a signal enable end of a low noise amplifier, and the control logic signal that may generate a working conflict is directly locked by the signal locking circuit, so that the enable signal enable end of the power amplifier and the enable signal of the low noise amplifier corresponding to the radio frequency front end are invalid, and the power amplifier and the low noise amplifier of the radio frequency front end are controlled not to work, thereby preventing the power amplifier and the low noise amplifier of the radio frequency front end from being damaged.

The signal processing circuit of the radio frequency front end provided by the embodiment of the invention can be positioned between the main control board and the radio frequency front end, is used for detecting a plurality of control logic signals of the main control board to the radio frequency front end, releases the normal control logic signals, directly locks the control logic signals which can generate work conflict, does not output the control logic signals, can avoid the control logic signals with conflict from being output to the radio frequency front end, and avoids the situation that the power amplifier emits high-power signals to burn down the low-noise amplifier during the working period of the receiver. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

In an exemplary embodiment of the present invention, the signal selection circuit is further configured to determine a Radio Frequency (Radio Frequency, abbreviated as RF) signal by detecting a RF signal sent by the Radio Frequency front end, output a conducting signal to the signal locking circuit according to the RF signal, where the conducting signal is valid when the Radio Frequency signal is valid, and the signal locking circuit is conducted, so as to correspondingly control neither the power amplifier nor the low noise amplifier of the Radio Frequency front end to work.

The valid radio frequency identification signal refers to detection of radio frequency signals sent by the radio frequency front end, and the invalid radio frequency identification signal refers to non-detection of radio frequency signals sent by the radio frequency front end.

In this embodiment, the signal selection circuit may further detect whether the radio frequency front end transmits a radio frequency signal of a certain communication system, and if a radio frequency signal is detected, determine that the radio frequency flag signal is valid, and lock all control logic signals in another communication system, so that any control logic signal sent by the main control board is not output to the radio frequency front end, thereby ensuring that no error logic occurs when two communication systems work simultaneously. The locking signal is not released until the transmitted signal disappears and the time that the radio frequency signal is not detected continuously exceeds 1 s.

At present, a radio frequency front end generally adopts a switching device to switch between two communication systems, however, in practical application, conflicting control logic signals can cause damage to the radio frequency switching device, loss of signal strength, shortening of signal coverage and reduction of transmission rate. In the embodiment, the mode of combining digital logic control and radio frequency technology is adopted through the signal selection circuit and the signal locking circuit, so that the control logic signal with conflict is prevented from being output to the radio frequency front end, the error logic that two communication systems work simultaneously can be ensured, the problem that the existing radio frequency switch device is easy to damage is solved, and the working reliability of the equipment is improved.

In an example embodiment of the present invention, as shown in fig. 1, the plurality of control logic signals may include: the system comprises a first communication system transmitting enabling signal MES _ PA _ EN, a second communication system terminal transmitting enabling signal LOE _ PA _ EN, a second communication system terminal receiving enabling signal LOE _ LNA _ EN, a communication system selection signal MES _ LO _ SEL, a second communication system power supply enabling signal LOT _ PWR _ EN and a second communication system radio frequency path enabling signal LOT _ PTH _ EN.

The control logic signals output by the main control board may include six: MES _ PA _ EN, LOE _ LNA _ EN, MES _ LO _ SEL, LOT _ PWR _ EN, and LOT _ PTH _ EN. The main control board outputs the six control logic signals to the signal processing circuit for signal collision check, and only the correct control logic signals can be output to the radio frequency front end.

The MES _ PA _ EN is a first communication system transmission enable signal, is used for controlling PA operation or non-operation under the first communication system of the radio frequency front end, and may also be called MES system transmission enable, and the high level is effective.

The LOE _ PA _ EN is a second communication system terminal transmission enable signal, is used for controlling PA operation or non-operation in a second communication system of the radio frequency front end, and may also be called an LO system terminal PA transmission enable signal, and is high-level active.

The LOE _ LNA _ EN is a second communication system terminal receiving enable signal, is used for controlling the LNA of the radio frequency front end in the second communication system to work or not work, and can also be called as an LO system terminal LNA receiving enable signal, and the high level is effective.

The MES _ LO _ SEL is a communication system selection signal for determining whether to select the first communication system or the second communication system, and may also be referred to as an MES/LO system selection signal, where a high level indicates that the first communication system is valid, and a low level indicates that the second communication system is valid.

And LOT _ PWR _ EN is a second communication system power supply enabling signal and is used for enabling the second communication system power supply to be electrified, and the high level is effective.

The LOT _ PTH _ EN is a radio frequency path enabling signal of the second communication system and is used for controlling a radio frequency switch device in the radio frequency front end to select a radio frequency path, and the high level is effective.

The radio frequency front end may include five control ports: the system comprises a PA transmitting enabling port, an LNA receiving enabling port, a second communication system power supply enabling port JK1, a second communication system radio frequency path enabling port JK2 and an RF detection port.

The output end of the signal locking circuit may be connected to the PA transmission enable port and the LNA reception enable port, respectively, as shown in fig. 1, the signal locking circuit may send a PA transmission enable signal PA _ EN and an LNA reception enable signal LNA _ EN of a certain communication system to the PA transmission enable port and the LNA reception enable port, respectively, to control the PA and the LNA of the radio frequency front end to operate or not operate accordingly. The PA transmitting enable signal PA _ EN and the LNA receiving enable signal LNA _ EN are both active at a high level and inactive at a low level.

The signal locking circuit determines whether a PA enabling signal and an LNA enabling signal of a certain communication system are effective according to whether a received conducting signal is effective, when the conducting signal of the certain communication system is effective, the signal locking circuit is conducted, the PA enabling signal and the LNA enabling signal of the certain communication system are ineffective, and the PA and the LNA of the radio frequency front end do not work. The control logic signal with conflict can be prevented from being output to the radio frequency front end, and the situation that the low noise amplifier is burnt down by a high-power signal emitted by the power amplifier during the working period of the receiver is avoided. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

As shown in fig. 1, the signal selection circuit may further detect whether a radio frequency detector RF-TC at the radio frequency front end sends a radio frequency signal RF _ MONI, and if the radio frequency signal is detected, determine that the radio frequency flag signal is valid, and lock the control logic signal, so that any control logic signal sent by the main control board is not output to the radio frequency front end, thereby ensuring that no error logic occurs when two communication systems work simultaneously.

In an example, when the valid control logic signal may be a second communication system power supply enable signal LOT _ PWR _ EN or a second communication system radio frequency path enable signal LOT _ PTH _ EN, the mutually exclusive control logic signals may include: the system comprises a first communication system transmitting enabling signal MES _ PA _ EN, a second communication system terminal transmitting enabling signal LOE _ PA _ EN, a second communication system terminal receiving enabling signal LOE _ LNA _ EN and a communication system selection signal MES _ LO _ SEL.

When the operating system selects the second communication system LO and is a system device, the system device refers to a device serving as a base station. At least one of the second communication system power supply enable signal LOT _ PWR _ EN and the second communication system radio frequency path enable signal LOT _ PTH _ EN is active. The signal level states of a second communication system terminal transmitting enabling signal LOE _ PA _ EN, a second communication system terminal receiving enabling signal LOE _ LNA _ EN, a first communication system transmitting enabling signal MES _ PA _ EN and a communication system selection signal MES _ LO _ SEL are blocked by a signal selection circuit and cannot be transmitted to a signal locking circuit for output.

The signal selection circuit outputs a conducting signal to the signal locking circuit according to a second communication system radio frequency path enabling signal LOT _ PTH _ EN, when the second communication system radio frequency path enabling signal LOT _ PTH _ EN is effective, the conducting signal is effective, the signal locking circuit is in a conducting state, the PA transmitting enabling signal PA _ EN and the LNA receiving enabling signal LNA _ EN are both ineffective, the PA and the LNA at the radio frequency front end do not work, and the PA and the LNA at the radio frequency front end are guaranteed not to be burnt. The RF signal path of the radio frequency front end is configured for use by the LO system devices.

In an example, when the valid control logic signal may be the second communication system terminal transmit enable signal LOE _ PA _ EN or the second communication system terminal receive enable signal LOE _ LNA _ EN, the mutually exclusive control logic signals may include: the first communication system transmits an enable signal MES _ PA _ EN.

The precondition that the second communication system power supply enabling signal LOT _ PWR _ EN or the second communication system radio frequency path enabling signal LOT _ PTH _ EN is valid is as follows: the communication system selection signal MES _ LO _ SEL selects the second communication system, and the second communication system power supply enabling signal LOT _ PWR _ EN and the second communication system radio frequency path enabling signal LOT _ PTH _ EN are both invalid.

When the working system selects the second communication system LO and is a terminal device, under the precondition that the communication system selection signal MES _ LO _ SEL is low level, and both the second communication system power supply enabling signal LOT _ PWR _ EN and the second communication system radio frequency path enabling signal LOT _ PTH _ EN are invalid, the signal selection circuit can transmit the signal level state of the second communication system terminal emission enabling signal LOE _ PA _ EN to the signal locking circuit and block the first communication system emission enabling signal MES _ PA _ EN from being output to the signal locking circuit. The output of the signal selection circuit can comprise a first output and a second output, wherein the first output is a signal PA _ EN to a PA emission enabling port of the radio frequency front end, the other output is connected to the signal locking circuit, and the signal PA _ EN is output to the PA emission enabling port of the radio frequency front end through the signal locking circuit.

The signal selection circuit can also output a signal level state signal locking circuit of the second communication system terminal receiving enable signal LOE _ LNA _ EN and an inverted signal of the first communication system transmitting enable signal MES _ PA _ EN to the signal locking circuit. The output of the signal selection circuit can comprise a third output and a fourth output, the third output signal LNA _ EN is transmitted to the LNA receiving enabling port of the radio frequency front end, the other output is connected to the signal locking circuit, and the signal LNA _ EN is transmitted to the LNA receiving enabling port of the radio frequency front end through the signal locking circuit.

The signal selection circuit outputs a conducting signal to the signal locking circuit according to a second communication system terminal transmitting enabling signal LOE _ PA _ EN and a second communication system terminal receiving enabling signal LOE _ LNA _ EN, when the second communication system terminal transmitting enabling signal LOE _ PA _ EN and the second communication system terminal receiving enabling signal LOE _ LNA _ EN are both effective, the conducting signal is effective, the signal locking circuit is in a conducting state, the PA transmitting enabling signal PA _ EN and the LNA receiving enabling signal LNA _ EN are both ineffective, the PA and the LNA of the radio frequency front end do not work, and the PA and the LNA of the radio frequency front end are guaranteed not to be burnt.

And if the RF detector at the radio frequency front end detects that the LO system equipment of the second communication system has the RF signal RF MONI, outputting the RF signal with high level to the signal locking circuit. When the signal selection circuit detects a high-level RF signal sent by the RF detector, the signal selection circuit determines that a radio frequency mark signal is effective, a conducting signal output to the signal locking circuit is effective, so that the signal locking circuit is conducted, and a control logic signal sent by the main control board is locked, so that any control logic signal sent by the main control board is not output to the radio frequency front end, and the error logic that two communication systems work simultaneously is ensured not to occur.

In an example, when the valid control logic signals may be the first communication system transmission enable signal MES _ PA _ EN, the mutually exclusive control logic signals may include: the second communication system terminal transmits an enable signal LOE _ PA _ EN and the second communication system terminal receives an enable signal LOE _ LNA _ EN.

The precondition that the first communication system transmission enable signal MES _ PA _ EN is valid is as follows: the communication system selection signal MES _ LO _ SEL selects the first communication system, and the second communication system power supply enabling signal LOT _ PWR _ EN and the second communication system radio frequency path enabling signal LOT _ PTH _ EN are both invalid.

When the working system selects the first communication system MES, on the premise that the communication system selection signal MES _ LO _ SEL is high level and the second communication system power enable signal LOT _ PWR _ EN and the second communication system radio frequency path enable signal LOT _ PTH _ EN are invalid, the signal selection circuit can transmit the signal level state of the first communication system emission enable signal MES _ PA _ EN to the signal locking circuit and block the second communication system terminal emission enable signal LOE _ PA _ EN from being output to the signal locking circuit. The output of the signal selection circuit can comprise a first output and a second output, wherein the first output is a signal PA _ EN to a PA emission enabling port of the radio frequency front end, the other output is connected to the signal locking circuit, and the signal PA _ EN is output to the PA emission enabling port of the radio frequency front end through the signal locking circuit.

The signal selection circuit can transmit the signal level state of the inverted signal of the first communication system transmitting enabling signal MES _ PA _ EN to the signal locking circuit, and block the output of the second communication system terminal receiving enabling signal LOE _ LNA _ EN to the signal locking circuit. The output of the signal selection circuit can comprise a third output and a fourth output, the third output signal LNA _ EN is transmitted to the LNA receiving enabling port of the radio frequency front end, the other output is connected to the signal locking circuit, and the signal LNA _ EN is transmitted to the LNA receiving enabling port of the radio frequency front end through the signal locking circuit.

If the RF detector of the radio frequency front end detects that the LO system equipment of the second communication system has the RF signal RF MONI, the RF signal with high level is output to the signal locking circuit RF MONI. When the signal selection circuit detects a high-level RF signal sent by the RF detector, the signal selection circuit determines that a radio frequency mark signal is effective, a conducting signal output to the signal locking circuit is effective, so that the signal locking circuit is conducted, and a control logic signal sent by the main control board is locked, so that any control logic signal sent by the main control board is not output to the radio frequency front end, and the error logic that two communication systems work simultaneously is ensured not to occur.

The signal processing circuit provided by the embodiment of the invention adopts the hardware logic gate circuit to check the correctness of the control logic signal, has the advantages of real-time response and high speed, and can solve the fault phenomenon of the damage of the radio frequency front-end module when the signal processing circuit is used in an actual communication product.

In one example, the signal locking circuit can adopt an OC gate circuit, and can lock conflicting signals in real time; and by logical combining the incorrect signal combinations can be switched off or blocked.

Fig. 2 is a schematic structural diagram of a signal processing circuit of a radio frequency front end according to another exemplary embodiment of the present invention, and as shown in fig. 2, the signal selection circuit may include: a first logic circuit 111 and a second logic circuit 112.

The first logic circuit receives a second communication system radio frequency path enabling signal LOT _ PTH _ EN and determines a radio frequency flag signal RF _ MONI by detecting a radio frequency signal, and outputs a first intermediate signal to the second logic circuit; when the second communication system radio frequency path enable signal LOT _ PTH _ EN or the radio frequency flag signal RF _ MONI is valid, the first intermediate signal is at the first level, and when both the second communication system radio frequency path enable signal LOT _ PTH _ EN and the radio frequency flag signal RF _ MONI are invalid, the first intermediate signal is at the second level.

The second logic circuit receives a second communication system power supply enabling signal LOT _ PWR _ EN and a first intermediate signal and outputs a conducting signal to the signal locking circuit; when the first intermediate signal is the first level or the second communication system power supply enable signal LOT _ PWR _ EN is effective, the conducting signal is effective.

In this embodiment, the signal selection circuit may include a first logic circuit and a second logic circuit, an output end of the first logic circuit is connected to an input end of the second logic circuit, the first logic circuit receives the second communication system radio frequency path enable signal LOT _ PTH _ EN and determines the radio frequency flag signal by detecting the radio frequency signal, and outputs a first intermediate signal; the second logic circuit receives the first intermediate signal and a second communication system power supply enable signal LOT _ PWR _ EN, and outputs a conducting signal to the signal locking circuit.

It has the following effects: when at least one of the second communication system radio frequency path enabling signals LOT _ PTH _ EN is effective, the signal selection circuit can block signal level states of the second communication system terminal transmitting enabling signal LOE _ PA _ EN, the second communication system terminal receiving enabling signal LOE _ LNA _ EN, the first communication system transmitting enabling signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL, and cannot transmit the signal level states to the signal locking circuit for outputting. The signal locking circuit can be in a conducting state, and both the PA and the LNA at the front end of the radio frequency do not work.

The following effects are also provided: when the signal selection circuit detects a high-level RF signal sent by the RF detector, the signal selection circuit determines that a radio frequency mark signal is effective, a conducting signal output to the signal locking circuit is effective, so that the signal locking circuit is conducted, and a control logic signal sent by the main control board is locked, so that any control logic signal sent by the main control board is not output to the radio frequency front end, and the error logic that two communication systems work simultaneously is ensured not to occur.

The specific level of the first level and the specific level of the second level may be determined according to a logic circuit structure, and in this embodiment, the first level may be a high level, and the second level may be a level.

In an exemplary embodiment of the present invention, as shown in fig. 2, the signal selection circuit may further include: a third logic circuit 113, a fourth logic circuit 114, a fifth logic circuit 115, and a sixth logic circuit 116.

The third logic circuit receives the second communication system terminal transmission enable signal LOE _ PA _ EN and the communication system selection signal MES _ LO _ SEL, and outputs a third intermediate signal to the second logic circuit.

The fourth logic circuit receives the first communication system emission enable signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL and outputs a fourth intermediate signal to the second logic circuit.

The fifth logic circuit receives the first communication system emission enable signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL and outputs a fifth intermediate signal to the second logic circuit.

The sixth logic circuit receives the second communication system terminal reception enable signal LOE _ LNA _ EN and the communication system selection signal MES _ LO _ SEL, and outputs a sixth intermediate signal to the second logic circuit.

The communication system selection signal MES _ LO _ SEL is at a first level, when the first communication system emission enabling signal MES _ PA _ EN is effective, the fourth intermediate signal is at the first level, and the fifth intermediate signal is at a second level; when the first communication system emission enable signal MES _ PA _ EN is invalid, the fourth intermediate signal is at the second level, and the fifth intermediate signal is at the first level.

The communication system selection signal MES _ LO _ SEL is a second level, and when the second communication system terminal emission enable signal LOE _ PA _ EN is effective, the third intermediate signal is a first level; when the second communication system terminal receiving enable signal LOE _ LNA _ EN is active, the sixth intermediate signal is at the first level.

The second logic circuit also receives a third intermediate signal, a fourth intermediate signal, a fifth intermediate signal and a sixth intermediate signal and outputs a conducting signal to the signal locking circuit; the on signal is active when one of the third intermediate signal, the fourth intermediate signal, the fifth intermediate signal, and the sixth intermediate signal is at the first level.

When the selected communication system is the first communication system, the communication system selection signal MES _ LO _ SEL is a first level; and when the selected communication system is the second communication system, the communication system selection signal MES _ LO _ SEL is at the second level.

In this embodiment, the signal selection circuit may further check the correctness of the control logic signal through the third logic circuit, the fourth logic circuit, the fifth logic circuit and the sixth logic circuit, and turn off or block an incorrect or conflicting signal combination through the combinational logic of the four logic circuits of the third logic circuit, the fourth logic circuit, the fifth logic circuit and the sixth logic circuit.

Fig. 3 is a schematic circuit diagram of a signal processing circuit of a radio frequency front end according to an exemplary embodiment of the present invention, and as shown in fig. 3, the third logic circuit may include: the device comprises a third AND gate U3 and a first inverter U2, wherein one end of the third AND gate receives a second communication system terminal emission enabling signal LOE _ PA _ EN, the other end of the third AND gate is connected with the output end of the first inverter, the input end of the first inverter receives a communication system selection signal MES _ LO _ SEL, and the output end of the third AND gate outputs a third intermediate signal.

The fourth logic circuit may include: and one end of the fourth AND gate receives the first communication system emission enabling signal MES _ PA _ EN, the other end of the fourth AND gate receives the communication system selection signal MES _ LO _ SEL, and the output end of the fourth AND gate outputs a fourth intermediate signal.

The fifth logic circuit may include: the device comprises a fifth AND gate U5 and a second inverter U2, wherein one end of the fifth AND gate receives a communication system selection signal MES _ LO _ SEL, the other end of the fifth AND gate is connected with the output end of the second inverter, the input end of the second inverter receives a first communication system emission enabling signal MES _ PA _ EN, and the output end of the fifth AND gate outputs a fifth intermediate signal.

The sixth logic circuit may include: the second communication system terminal receiving enable signal LOE _ LNA _ EN is received by one end of a sixth AND gate U6 and a first inverter U2, the other end of the sixth AND gate is connected with the output end of the first inverter, and the output end of the sixth AND gate outputs a sixth intermediate signal.

In this embodiment, the third logic circuit mainly checks the correctness of the control logic signals and turns off or blocks the incorrect or conflicting signal combination through the combinational logic. The third logic circuit can check the correctness of the control logic signal through the AND gate and the inverter, and shut off or block incorrect or conflicting signal combinations through the combinational logic of a plurality of AND gates.

The inverted signal of the communication system selection signal MES _ LO _ SEL and the second communication system terminal enable signal LOE _ PA _ EN may be subjected to signal logic check by the third and gate U3, and a third intermediate signal may be output to a second logic circuit (such as the first or gate U7 in the embodiment described below).

The communication system selection signal MES _ LO _ SEL and the first communication system transmission enable signal MES _ PA _ EN may be signal-logically checked by a fourth and gate U4, and a fourth intermediate signal may be output to a second logic circuit (a first or gate U7 in the following embodiments).

The inverted signal of the first communication system transmission enable signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL can be signal-logically checked by the fifth and gate U5, and a fifth intermediate signal is output to a second logic circuit (a second or gate U8 in the embodiment described below).

The signal logic check of the inverted signal of the communication system selection signal MES _ LO _ SEL and the second communication system terminal reception enable signal LOE _ LNA _ EN may be performed by the sixth and gate U6, and the sixth intermediate signal may be output to the second logic circuit (such as the second or gate U8 in the embodiment described below).

In an example embodiment of the present invention, as shown in fig. 3, the second logic circuit may include: a first or gate U7 and a second or gate U8.

The first or gate may include four first input terminals, the four first input terminals respectively receive the first intermediate signal, the third intermediate signal, the fourth intermediate signal, and the second communication system power supply enable signal LOT _ PWR _ EN, an output terminal of the first or gate outputs the first on signal, one of the first intermediate signal, the third intermediate signal, and the fourth intermediate signal is a first level, or when the second communication system power supply enable signal LOT _ PWR _ EN is active, the first on signal is active.

The second or gate may include four second input terminals, the four second input terminals respectively receive the first intermediate signal, the fifth intermediate signal, the sixth intermediate signal, and the second communication system power supply enable signal LOT _ PWR _ EN, the output terminal of the second or gate outputs the second on signal, one of the first intermediate signal, the fifth intermediate signal, and the sixth intermediate signal is the first level, or when the second communication system power supply enable signal LOT _ PWR _ EN is active, the second on signal is active.

In this embodiment, the second logic circuit mainly performs signal logic conflict check on the correct control logic signal (valid logic signal) detected by the third logic circuit or the first intermediate signal output by the first logic circuit, and outputs a conducting signal to the signal locking circuit. The second logic circuit can check the correct control logic signal (valid logic signal) detected by the third logic circuit or the first intermediate signal output by the first logic circuit for logic conflict through the or gate.

The first intermediate signal output by the first logic circuit, the third intermediate signal output by the third and gate U3, the fourth intermediate signal output by the fourth and gate U4, and the second communication system power supply enable signal LOT _ PWR _ EN may be subjected to signal logic detection by the first or gate U7, and the first on signal may be output to the signal locking circuit.

The second or gate U8 can perform signal logic detection on the first intermediate level output by the first logic circuit, the fifth intermediate signal output by the fifth and gate U5, the sixth intermediate signal output by the sixth and gate U6, and the second communication system power supply enable signal LOT _ PWR _ EN, and output a second on signal to the signal locking circuit.

In an example embodiment of the present invention, as shown in fig. 3, the first logic circuit may include: a third or gate U9, one input terminal of which receives the second communication system RF path enable signal LOT _ PTH _ EN, the other input terminal of which determines the RF flag signal by detecting the RF signal RF _ MONI, and the output terminal of which outputs the first intermediate signal.

In this embodiment, the first logic circuit may receive the second communication system radio frequency path enable signal through the or gate, determine the radio frequency flag signal by detecting the radio frequency signal, and output the first intermediate signal to the second logic circuit.

In an exemplary embodiment of the present invention, as shown in fig. 3, the signal locking circuit may include: a third transistor T1, and a fourth transistor T2. The third transistor T1 and the fourth transistor T2 may be NPN transistors, or the third transistor T1 and the fourth transistor T2 may be PNP transistors. In this embodiment, an NPN type transistor is taken as an example for explanation, and the implementation principle of the PNP type transistor is similar to that of the NPN type transistor, and details are not repeated in this embodiment.

The base electrode of the third triode receives the first conduction signal, the collector electrode (or the emitter electrode) of the third triode transmits an enabling signal PA _ EN to the radio frequency front end output power amplifier, the first conduction signal is effective, the third triode is conducted, and the power amplifier transmits the enabling signal to be ineffective so as to control the power amplifier at the radio frequency front end not to work. The emitter (or collector) of the third triode is grounded to GND. The third triode can control the work or the non-work of the power amplifier at the radio frequency front end according to the first conducting signal output by the second logic circuit.

The base electrode of the fourth triode receives the second conduction signal, the collector electrode (or the emitter electrode) of the fourth triode outputs a low noise amplifier receiving enabling signal LNA _ EN to the radio frequency front end, the second conduction signal is effective, the fourth triode is conducted, the low noise amplifier receiving enabling signal is ineffective, and therefore the low noise amplifier of the radio frequency front end is controlled not to work. The emitter (or collector) of the fourth triode is grounded to GND. The third triode can control the low noise amplifier at the front end of the radio frequency to work or not work according to the second conducting signal output by the second logic circuit.

When the operating system selects the second communication system LO and is a system device, the system device refers to a device serving as a base station. The second communication system power supply enable signal LOT _ PWR _ EN and the second communication system radio frequency path enable signal LOT _ PTH _ EN are both high level, and the signal level states of the second communication system terminal transmission enable signal LOE _ PA _ EN, the second communication system terminal reception enable signal LOE _ LNA _ EN, the first communication system transmission enable signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL are blocked and cannot be transmitted to or gates (U7 and U8) for output. The transistors T1 and T2 are both in a conducting state, the PA transmit enable signal PA _ EN and the LNA receive enable signal LNA _ EN are both low, and both the power amplifier and the low noise amplifier in the rf front end are not operating. The RF signal path of the radio frequency front end is configured for use by the LO system devices.

When the working mode selects the second communication mode LO and is terminal equipment, the communication mode selection signal MES _ LO _ SEL, the second communication mode system power supply enabling signal LOT _ PWR _ EN and the second communication mode radio frequency path enabling signal LOT _ PTH _ EN are all low level, the signal level state of the second communication mode terminal emission enabling signal LOE _ PA _ EN is allowed to be transmitted to the first OR gate U7 to be output, and meanwhile, the output of the first communication mode emission enabling signal MES _ PA _ EN is blocked. The signal output by the first or gate U7 is divided into two paths, one path outputs PA _ EN to the PA transmit enable port at the rf front end, and the other path drives the first triode T1 and then outputs PA _ EN to the PA transmit enable port at the rf front end.

Likewise, the signal level state of the terminal receive enable signal LOE _ LNA _ EN of the second communication scheme may be allowed to pass to the output of the second or gate U8 while the inverted signal output of the transmit enable signal MES _ PA _ EN of the first communication scheme is blocked. The signal output by the second or gate U8 is divided into two paths, one path outputs LNA _ EN to the LNA receiving enabling port at the radio frequency front end, the other path drives the second triode T2, and then LNA _ EN is connected to the LNA receiving enabling port at the radio frequency front end

Only the configuration is correct: the MES _ LO _ SEL, the LOT _ PWR _ EN and the LOT _ PTH _ EN are all low level, only the real-time control logic signals LOE _ PA _ EN and LOE _ LNA _ EN are allowed to be output to an OR gate (U7 and U8), then collision interlock check is carried out, an OC gate circuit is adopted, if two signals LOE _ PA _ EN and LOE _ LNA _ EN are high level at the same time, the first triode T1 and the second triode T2 are conducted, the output level is pulled down, the power amplifier and the low noise amplifier are ensured not to work, and therefore the phenomenon of burnout of equipment is guaranteed to be avoided.

If the RF Detector (Detector) detects that the LO system device of the second communication system has the RF signal RF MONI, the RF signal of high level is output, the third or gate U9 outputs high level, the first or gate U7 and the second or gate U8 output high level, the first triode T1 and the second triode T2 in the OC gate circuit are turned on, and the PA _ EN and LNA _ EN outputs low level, which ensures that both the power amplifier and the low noise amplifier do not work and protects the radio frequency front end.

When the working system selects the first communication system MES, the communication system selection signal MES _ LO _ SEL is at a high level, and the second communication system power supply enabling signal LOT _ PWR _ EN and the second communication system radio frequency path enabling signal LOT _ PTH _ EN are both at a low level. The signal level of the first communication system transmission enable signal MES _ PA _ EN is allowed to pass to the output of the first or gate U7, while the second communication system terminal transmission enable signal LOE _ PA _ EN is blocked. The signal output by the first or gate U7 can be divided into two paths, one path outputs PA _ EN to the PA transmission enable port at the radio frequency front end, the other path drives the first triode T1, and then outputs PA _ EN to the PA transmission enable port at the radio frequency front end.

Likewise, the inverted signal level state of the first communication system transmission enable signal MES _ PA _ EN may be allowed to pass to the output of the second or gate U8 while the output of the second communication system terminal reception enable signal LOE _ LNA _ EN is blocked. The signal output by the second or gate U8 is divided into two paths, one path outputs LNA _ EN to the LNA reception enable port at the radio frequency front end, the other path drives the second triode T2, and then outputs LNA _ EN to the LNA reception enable port at the radio frequency front end.

Only the configuration is correct: MES _ LO _ SEL is high and LOT _ PWR _ EN and LOT _ PTH _ EN are both low to allow the real time control logic signal MES _ PA _ EN to be output to the OR gates (U7 and U8) and then output.

Fig. 4 is a schematic circuit diagram of a signal processing circuit of a radio frequency front end according to another exemplary embodiment of the present invention, and as shown in fig. 4, the third logic circuit may include: the device comprises a first resistor R1, a first diode D1 and a second diode D2, wherein one end of the first resistor is connected with the anode of the first diode, the other end of the first resistor receives a second communication system terminal emission enable signal LOE _ PA _ EN, the negative end of the first diode outputs a third intermediate signal, the anode of the second diode is connected with the anode of the first diode, and the cathode of the second diode receives a communication system selection signal MES _ LO _ SEL.

The fourth logic circuit may include: the communication system comprises a second resistor R2, a third diode D3, a fourth diode D4 and a first triode T4, wherein one end of the second resistor is connected with the anode of the third diode, the other end of the second resistor receives a first communication system emission enabling signal MES _ PA _ EN, the negative end of the third diode outputs a fourth intermediate signal, the anode of the fourth diode is connected with the anode of the third diode, the negative electrode of the fourth diode is connected with the collector or emitter of the first triode, and the base of the first triode receives a communication system selection signal MES _ LO _ SEL. The first transistor T4 may receive the communication system selection signal MES _ LO _ SEL through the ninth resistor R9, a collector (or emitter) of the first transistor T4 is connected to the high level VCC, and an emitter (or collector) of the first transistor T4 is connected to the GND.

The fifth logic circuit may include: the communication system comprises a fifth diode D5, a sixth diode D6, a first triode and a second triode T3, wherein the anode of the fifth diode is connected with the collector or emitter of the second triode, the base of the second triode receives a first communication system emission enabling signal MES _ PA _ EN, the negative end of the fifth diode outputs a fifth intermediate signal, the anode of the sixth diode is connected with the anode of the fifth diode, the cathode of the sixth diode is connected with the collector or emitter of the first triode, and the base of the first triode receives a communication system selection signal MES _ LO _ SEL. The second transistor T3 may receive the first communication system transmission enable signal MES _ PA _ ENL through the eighth resistor R8, a collector (or emitter) of the second transistor T3 is connected to the high level VCC, and an emitter (or collector) of the second transistor T3 is connected to the GND.

The sixth logic circuit may include: the communication system comprises a third resistor R3, a seventh diode D7 and an eighth diode D8, one end of the third resistor is connected with the anode of the seventh diode, the other end of the third resistor receives a second communication system terminal receiving enable signal LOE _ LNA _ EN, the negative end of the seventh diode outputs a sixth intermediate signal, and the negative end of the eighth diode receives a communication system selection signal MES _ LO _ SEL.

In this embodiment, the third logic circuit mainly checks the correctness of the control logic signals and turns off or blocks the incorrect or conflicting signal combination through the combinational logic. The third logic circuit can check the correctness of the control logic signal through the diode and the triode, obtain a reverse signal of the control logic signal through the triode, and shut off or block the incorrect or conflicting signal combination through the combinational logic of a plurality of diodes.

The communication system selection signal MES _ LO _ SEL and the second communication system terminal enable signal LOE _ PA _ EN may be signal-logically checked by the first resistor R1, the first diode D1, and the second diode D2, and a third intermediate signal may be output to a second logic circuit (a fourth resistor R4 in the following embodiments).

The reverse signal of the communication system selection signal MES _ LO _ SEL and the first communication system transmission enable signal MES _ PA _ EN may be signal-logically checked by the second resistor R2, the third diode D3, and the fourth diode D4, and a fourth intermediate signal may be output to a second logic circuit (a fourth resistor R4 in the following embodiment). The inverted signal of the communication system selection signal MES _ LO _ SEL can be obtained via the first transistor T4.

The reverse signal of the first communication system transmission enable signal MES _ PA _ EN and the reverse signal of the communication system selection signal MES _ LO _ SEL may be signal-logically checked by the fifth diode D5 and the sixth diode D6, and a fifth intermediate signal may be output to a second logic circuit (a fifth resistor R5 in the following embodiments). The reverse signal of the first communication system transmission enable signal MES _ PA _ EN can be obtained through the first transistor T4, and the reverse signal of the communication system selection signal MES _ LO _ SEL can be obtained through the second transistor T3.

The communication system selection signal MES _ LO _ SEL and the second communication system terminal enable signal LOE _ LNA _ EN may be signal-logically checked by the third resistor R3, the seventh diode D7, and the eighth diode D8, and a sixth intermediate signal may be output to a second logic circuit (a fifth resistor R5 in the following embodiments). In an example embodiment of the present invention, as shown in fig. 4, the second logic circuit may include: a fourth resistor R4, a fifth resistor R5, a ninth diode D9 and a twelfth diode D10.

A first end of a fourth resistor receives the first intermediate signal, the third intermediate signal and the fourth intermediate signal, a negative end of a ninth diode is connected with a first end of the fourth resistor, a positive end of the ninth diode receives a second communication system power supply enabling signal LOT _ PWR _ EN, and a second end of the fourth resistor outputs a first conducting signal; when one of the first intermediate signal, the third intermediate signal and the fourth intermediate signal is at the first level or the second communication system power supply enable signal LOT _ PWR _ EN is active, the first conducting signal is active.

A first end of the fifth resistor receives the first intermediate signal, the fifth intermediate signal and the sixth intermediate signal, a negative end of the twelfth diode is connected with a first end of the fifth resistor, a positive end of the twelfth diode receives a second communication system power supply enable signal LOT _ PWR _ EN, and a second end of the fifth resistor outputs a second conduction signal; when one of the first intermediate signal, the fifth intermediate signal and the sixth intermediate signal is at the first level or the second communication system power supply enable signal LOT _ PWR _ EN is active, the second conduction signal is active.

In this embodiment, the second logic circuit mainly performs signal logic conflict check on the correct control logic signal (valid logic signal) detected by the third logic circuit or the first intermediate signal output by the first logic circuit, and outputs a conducting signal to the signal locking circuit. The second logic circuit can check the correct control logic signal (valid logic signal) detected by the third logic circuit or the first intermediate signal output by the first logic circuit for logic conflict through a resistor and a diode.

The fourth resistor R4 is used to logically detect the first intermediate signal output by the first logic circuit, the third intermediate signal output by the first diode D1, the fourth intermediate signal output by the third diode D3, and the second communication system power supply enable signal LOT _ PWR _ EN received by the ninth diode, and output the first on signal to the signal locking circuit.

The first intermediate level output by the first logic circuit, the fifth intermediate signal output by the fifth diode D5, the sixth intermediate signal output by the seventh diode D7, and the second communication system power supply enable signal LOT _ PWR _ EN received by the twelfth diode may be logically detected by the fifth resistor R5, and the second on signal may be output to the signal locking circuit.

In an example, as shown in fig. 4, the first diode D1 and the third diode D3 may output the third intermediate signal and the fourth intermediate signal to the sixth resistor R6, respectively, and directly output PA _ EN to the PA transmit enable port of the rf front end through the sixth resistor R6. When the third intermediate signal or the fourth intermediate signal is at a low level, the output of the PA _ EN is at a low level, so that the power amplifier is ensured not to work, and the radio frequency front end is protected.

The fifth diode D5 and the seventh diode D7 may output a fifth intermediate signal and a sixth intermediate signal to the seventh resistor R7, respectively, and directly output the LNA _ EN to the LNA reception enable port of the rf front end through the seventh resistor R7. And when the fifth intermediate signal or the sixth intermediate signal is at a low level, the output of the LNA _ EN is at a low level, so that the low noise amplifier does not work, and the radio frequency front end is protected.

In an example embodiment of the present invention, as shown in fig. 4, the first logic circuit may include: two eleventh diodes D11 and D12 and two twelfth diodes D13 and D14;

the positive terminals of the two eleventh diodes receive the second communication system radio frequency path enable signal LOT _ PTH _ EN, the negative terminal of one of the eleventh diodes D11 outputs the first intermediate signal to the fourth resistor, and the negative terminal of the other eleventh diode D12 outputs the first intermediate signal to the fifth resistor.

The positive terminals of both the twelfth diodes determine the radio frequency identification signal by detecting the radio frequency signal, wherein the negative terminal of one of the twelfth diodes D13 outputs a first intermediate signal to the fourth resistor and the negative terminal of the other twelfth diode D14 outputs a first intermediate signal to the fifth resistor.

In this embodiment, the first logic circuit may receive the second communication system radio frequency path enable signal through two groups of diodes, determine the radio frequency flag signal by detecting the radio frequency signal, and output the first intermediate signal to the second logic circuit.

When the operating system selects the second communication system LO and is a system device, the system device refers to a device serving as a base station. The second communication system power supply enable signal LOT _ PWR _ EN and the second communication system radio frequency path enable signal LOT _ PTH _ EN are both high level, and then the signal level states of the second communication system terminal transmission enable signal LOE _ PA _ EN, the second communication system terminal reception enable signal LOE _ LNA _ EN, the first communication system transmission enable signal MES _ PA _ EN and the communication system selection signal MES _ LO _ SEL are blocked and cannot be transmitted to the fourth resistor R4 and the fifth resistor R5 for output. The transistors T1 and T2 are both in a conducting state, the PA transmit enable signal PA _ EN and the LNA receive enable signal LNA _ EN are both low, and both the power amplifier and the low noise amplifier in the rf front end are not operating. The RF signal path of the radio frequency front end is configured for use by the LO system devices.

When the working mode selects the second communication mode LO and is terminal equipment, the communication mode selection signal MES _ LO _ SEL, the second communication mode system power supply enabling signal LOT _ PWR _ EN and the second communication mode radio frequency path enabling signal LOT _ PTH _ EN are all low level, the signal level state of the second communication mode terminal emission enabling signal LOE _ PA _ EN is allowed to be transmitted to the fourth resistor R4 to be output, and meanwhile, the output of the first communication mode emission enabling signal MES _ PA _ EN is blocked. The signal output by the fourth resistor R4 drives the first transistor T1, and then outputs PA _ EN to the PA transmit enable port at the rf front end.

Likewise, the signal level state of the terminal receive enable signal LOE _ LNA _ EN of the second communication scheme may be allowed to pass to the fifth resistor R5 output while blocking the inverted signal output of the transmit enable signal MES _ PA _ EN of the first communication scheme. The signal output by the fifth resistor R5 drives the second transistor T2, and then LNA _ EN is connected to the LNA receiving enable port at the RF front end

Only the configuration is correct: the MES _ LO _ SEL, the LOT _ PWR _ EN and the LOT _ PTH _ EN are all low level, only the real-time control logic signals LOE _ PA _ EN and LOE _ LNA _ EN are allowed to be output to the fourth resistor R4 and the fifth resistor R5, then conflict interlock check is carried out, an OC gate circuit is adopted, if the two signals LOE _ PA _ EN and LOE _ LNA _ EN are high level at the same time, the first triode T1 and the second triode T2 are conducted, the output level is pulled down, the power amplifier and the low noise amplifier are ensured not to work, and therefore the device is guaranteed not to be burnt.

If the RF Detector (Detector) detects that the LO system device of the second communication system has the RF signal RF MONI, a high-level RF signal is output, two eleventh diodes output high levels, the fourth resistor R4 and the fifth resistor R5 output high levels, the first triode T1 and the second triode T2 in the OC gate circuit are conducted, the output of the PA _ EN and the output of the LNA _ EN are both low levels, the power amplifier and the low-noise amplifier are ensured not to work, and the radio frequency front end is protected.

When the working system selects the first communication system MES, the communication system selection signal MES _ LO _ SEL is at a high level, and the second communication system power supply enabling signal LOT _ PWR _ EN and the second communication system radio frequency path enabling signal LOT _ PTH _ EN are both at a low level. The signal level of the first communication system transmission enable signal MES _ PA _ EN and its inverted signal are allowed to pass to the fourth resistor R4 to be output, while the second communication system terminal transmission enable signal LOE _ PA _ EN is blocked. The signal output by the fourth resistor R4 drives the first transistor T1, and then outputs PA _ EN to the PA transmit enable port at the rf front end.

Likewise, the inverted signal level state of the first communication system transmission enable signal MES _ PA _ EN may be allowed to pass to the fifth resistor R5 output while the output of the second communication system terminal reception enable signal LOE _ LNA _ EN is blocked. The signal output by the fifth resistor R5 drives the second transistor T2, and then outputs LNA _ EN to the LNA reception enable port at the rf front end.

Only the configuration is correct: MES _ LO _ SEL is high and LOT _ PWR _ EN and LOT _ PTH _ EN are both low, allowing the real-time control logic signal MES _ PA _ EN to be output to the fourth resistor R4 and the fifth resistor R5 and then output.

Fig. 5 is a block diagram of a wireless communication device according to an embodiment of the present invention, and as shown in fig. 5, the wireless communication device may include: the antenna 51, the main control board 52, the rf front-end chip 53 and the rf front-end signal processing circuit 54 shown in any embodiment, the input end of the signal processing circuit is connected to the main control board, and the output end of the signal processing circuit is connected to the rf front-end chip.

And the main control board is used for sending a plurality of control logic signals to the signal processing circuit.

And the radio frequency front-end chip is used for sending radio frequency signals to the signal processing circuit, and comprises a channel for radio frequency signals of a first communication system and a channel for radio frequency signals of a second communication system, and the first communication system and the second communication system share the antenna.

In this embodiment, the signal processing circuit may be located between the main control board and the radio frequency front end, and is configured to detect a plurality of control logic signals of the main control board to the radio frequency front end. The main control board outputs the six control logic signals to the signal processing circuit for signal collision check, and only the correct control logic signals can be output to the radio frequency front end. The signal processing circuit can release normal control logic signals through the signal selection circuit, directly locks the control logic signals which can generate work conflict, does not output the control logic signals, can prevent the control logic signals with conflict from being output to the radio frequency front end, and prevents the power amplifier from transmitting high-power signals to burn down the low-noise amplifier during the working period of the receiver. Or during the operation of the transmitter, the low noise amplifier of the receiver enters an operating state and burns out the low noise amplifier.

The signal selection circuit can also detect whether the radio frequency front end transmits a radio frequency signal of a certain communication system, if the radio frequency signal is detected, the radio frequency mark signal is determined to be valid, and all control logic signals under another communication system are locked, so that any control logic signal sent by the main control board is not output to the radio frequency front end, and the error logic of simultaneous working of the two communication systems is ensured not to occur. The locking signal is not released until the transmitted signal disappears and the time that the radio frequency signal is not detected continuously exceeds 1 s.

In this embodiment, the signal processing circuit is used in an actual communication product, and a failure phenomenon of the radio frequency front end module damage can be solved. The signal processing circuit can adopt the technical scheme of the signal processing circuit of any of the above embodiments, and the implementation principle and the implementation effect are similar, which are not described herein again.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media or non-transitory media and communication media or transitory media. The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data as is known to one of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks, DVD, or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A signal processing circuit of a radio frequency front end, comprising: the signal selection circuit and the signal locking circuit;

when the conducting signal of a certain communication system is effective, the signal locking circuit is conducted, and the amplifier enabling signal of the communication system corresponding to the radio frequency front end is ineffective, so that the power amplifier and the low noise amplifier of the radio frequency front end are correspondingly controlled not to work.

2. The circuit of claim 1, wherein the signal selection circuit is further configured to determine a radio frequency flag signal by detecting a radio frequency signal sent by the radio frequency front end, output a conducting signal to the signal locking circuit according to the radio frequency flag signal, the conducting signal being valid when the radio frequency flag signal is valid, and the signal locking circuit being conducting to correspondingly control neither a power amplifier nor a low noise amplifier of the radio frequency front end to work;

the radio frequency identification signal is valid, that is, the radio frequency front end is detected to send the radio frequency signal, and the radio frequency identification signal is invalid, that is, the radio frequency front end is not detected to send the radio frequency signal.

3. The circuit of claim 2, wherein the plurality of control logic signals comprises: a first communication system transmitting enabling signal, a second communication system terminal receiving enabling signal, a communication system selection signal, a second communication system power supply enabling signal and a second communication system radio frequency path enabling signal;

when the effective control logic signal is a second communication system power supply enabling signal or a second communication system radio frequency path enabling signal, mutually exclusive control logic signals comprise: a first communication system transmitting enabling signal, a second communication system terminal receiving enabling signal and a communication system selection signal;

alternatively, the first and second electrodes may be,

when the effective control logic signal is an enable signal transmitted by the second communication system terminal or an enable signal received by the second communication system terminal, the mutually exclusive control logic signals comprise: a first communication system transmits an enabling signal;

the precondition that the second communication system power supply enabling signal or the second communication system radio frequency path enabling signal is effective is as follows: the communication system selection signal selects a second communication system, and both the system power supply enabling signal and the radio frequency path enabling signal of the second communication system are invalid;

alternatively, the first and second electrodes may be,

when the effective control logic signal is the first communication system transmitting enable signal, the mutually exclusive control logic signals comprise: the second communication system terminal transmits an enabling signal and the second communication system terminal receives the enabling signal;

the precondition that the first communication system is effective in transmitting the enabling signal is as follows: the communication system selection signal selects the first communication system, and the system power supply enabling signal of the second communication system is invalid.

4. The circuit of claim 3, wherein the signal selection circuit comprises: a first logic circuit and a second logic circuit;

the first logic circuit receives a second communication system radio frequency path enabling signal and determines a radio frequency marking signal by detecting the radio frequency signal, and outputs a first intermediate signal to the second logic circuit; when the second communication system radio frequency path enabling signal or the radio frequency marking signal is valid, the first intermediate signal is at a first level, and when the second communication system radio frequency path enabling signal and the radio frequency marking signal are both invalid, the first intermediate signal is at a second level;

the second logic circuit receives the second communication system power supply enabling signal and the first intermediate signal and outputs a conducting signal to the signal locking circuit; and when the first intermediate signal is a first level or the second communication system power supply enabling signal is effective, the conducting signal is effective.

5. The circuit of claim 4, wherein the signal selection circuit further comprises: a third logic circuit, a fourth logic circuit, a fifth logic circuit, and a sixth logic circuit;

the third logic circuit receives the second communication system terminal emission enabling signal and the communication system selection signal and outputs a third intermediate signal to the second logic circuit;

the fourth logic circuit receives the first communication system transmitting enabling signal and the communication system selection signal and outputs a fourth intermediate signal to the second logic circuit;

the fifth logic circuit receives the first communication system transmitting enabling signal and the communication system selection signal and outputs a fifth intermediate signal to the second logic circuit;

the sixth logic circuit receives the second communication system terminal receiving enable signal and the communication system selection signal, and outputs a sixth intermediate signal to the second logic circuit;

the communication system selection signal is a first level, when the first communication system transmission enabling signal is effective, the fourth intermediate signal is the first level, and the fifth intermediate signal is a second level; when the first communication system transmission enabling signal is invalid, the fourth intermediate signal is at a second level, and the fifth intermediate signal is at a first level;

the communication system selection signal is a second level, and when the second communication system terminal transmits an enabling signal to be effective, the third intermediate signal is a first level; when the second communication system terminal receives an enabling signal effectively, the sixth intermediate signal is a first level;

the second logic circuit further receives the third intermediate signal, the fourth intermediate signal, the fifth intermediate signal and the sixth intermediate signal, and outputs a conducting signal to the signal locking circuit; when one of the third intermediate signal, the fourth intermediate signal, the fifth intermediate signal, and the sixth intermediate signal is at a first level, the turn-on signal is active;

when the selected communication system is a first communication system, the communication system selection signal is a first level; and when the selected communication system is the second communication system, the communication system selection signal is the second level.

6. The circuit of claim 5, wherein the third logic circuit comprises: one end of the third AND gate receives a second communication system terminal emission enabling signal, the other end of the third AND gate is connected with the output end of the first phase inverter, the input end of the first phase inverter receives a communication system selection signal, and the output end of the third AND gate outputs the third intermediate signal;

the fourth logic circuit includes: one end of the fourth AND gate receives the first communication system transmission enabling signal, the other end of the fourth AND gate receives the communication system selection signal, and the output end of the fourth AND gate outputs the fourth intermediate signal;

the fifth logic circuit includes: one end of the fifth AND gate receives the communication system selection signal, the other end of the fifth AND gate is connected with the output end of the second inverter, the input end of the second inverter receives the first communication system transmission enabling signal, and the output end of the fifth AND gate outputs the fifth intermediate signal;

the sixth logic circuit includes: one end of the sixth AND gate receives the second communication system terminal receiving enabling signal, the other end of the sixth AND gate is connected with the output end of the first phase inverter, and the output end of the sixth AND gate outputs the sixth intermediate signal.

7. The circuit of claim 6, wherein the second logic circuit comprises: a first or gate and a second or gate;

the first or gate comprises four first input ends, the four first input ends respectively receive the first intermediate signal, the third intermediate signal, the fourth intermediate signal and the second communication system power supply enabling signal, the output end of the first or gate outputs a first conducting signal, one of the first intermediate signal, the third intermediate signal and the fourth intermediate signal is a first level, or when the second communication system power supply enabling signal is effective, the first conducting signal is effective;

the second or gate includes four second input ends, the four second input ends respectively receive the first intermediate signal, the fifth intermediate signal, the sixth intermediate signal and the second communication system power enable signal, an output end of the second or gate outputs a second conducting signal, one of the first intermediate signal, the fifth intermediate signal and the sixth intermediate signal is a first level, or when the second communication system power enable signal is valid, the second conducting signal is valid.

8. The circuit of any of claims 5-7, wherein the first logic circuit comprises: one input end of the third or gate receives the radio frequency path enabling signal of the second communication system, the other input end of the third or gate determines a radio frequency identification signal by detecting a radio frequency signal, and the output end of the third or gate outputs the first intermediate signal.

9. The circuit of claim 5, wherein the third logic circuit comprises: one end of the first resistor is connected with the anode of the first diode, the other end of the first resistor receives an enabling signal emitted by the second communication system terminal, the negative end of the first diode outputs the third intermediate signal, the anode of the second diode is connected with the anode of the first diode, and the cathode of the second diode receives the communication system selection signal;

the fourth logic circuit includes: the communication system comprises a second resistor, a third diode, a fourth diode and a first triode, wherein one end of the second resistor is connected with the anode of the third diode, the other end of the second resistor receives a first communication system emission enabling signal MES _ PA _ EN, the negative end of the third diode outputs a fourth intermediate signal, the anode of the fourth diode is connected with the anode of the third diode, the cathode of the fourth diode is connected with the collector or emitter of the first triode, and the base of the first triode receives a communication system selection signal;

the fifth logic circuit includes: the communication system selection circuit comprises a fifth diode, a sixth diode, a first triode and a second triode, wherein the anode of the fifth diode is connected with the collector or the emitter of the second triode, the base of the second triode receives the first communication system emission enabling signal, the negative end of the fifth diode outputs a fifth intermediate signal, the anode of the sixth diode is connected with the anode of the fifth diode, the cathode of the sixth diode is connected with the collector or the emitter of the first triode, and the base of the first triode receives the communication system selection signal;

the sixth logic circuit includes: one end of the third resistor is connected with the anode of the seventh diode, the other end of the third resistor receives the second communication system terminal receiving enabling signal, the negative end of the seventh diode outputs the sixth intermediate signal, and the negative end of the eighth diode receives the communication system selection signal.

10. The circuit of claim 9, wherein the second logic circuit comprises: a fourth resistor, a fifth resistor, a ninth diode and a twelfth diode;

a first end of the fourth resistor receives the first intermediate signal, the third intermediate signal and the fourth intermediate signal, a negative end of the ninth diode is connected with the first end of the fourth resistor, a positive end of the ninth diode receives the power supply enabling signal of the second communication system, and a second end of the fourth resistor outputs a first conducting signal; one of the first intermediate signal, the third intermediate signal and the fourth intermediate signal is a first level, or the first conducting signal is valid when the system power enable signal of the second communication system is valid;

a first end of the fifth resistor receives the first intermediate signal, the fifth intermediate signal and the sixth intermediate signal, a negative end of the twelfth diode is connected with the first end of the fifth resistor, a positive end of the twelfth diode receives the power supply enabling signal of the second communication system, and a second end of the fifth resistor outputs a second conducting signal; one of the first intermediate signal, the fifth intermediate signal, and the sixth intermediate signal is a first level, or the second conduction signal is active when the system power enable signal of the second communication system is active.

11. The circuit of claim 10, wherein the first logic circuit comprises: two eleventh diodes and two twelfth diodes;

the positive ends of the two eleventh diodes receive the radio frequency path enabling signal of the second communication system, the negative end of one of the eleventh diodes outputs the first intermediate signal to the fourth resistor, and the negative end of the other eleventh diode outputs the first intermediate signal to the fifth resistor;

the positive terminals of the two twelfth diodes each determine a radio frequency identification signal by detecting a radio frequency signal, wherein the negative terminal of one of the twelfth diodes outputs the first intermediate signal to the fourth resistor and the negative terminal of the other twelfth diode outputs the first intermediate signal to the fifth resistor.

12. The circuit of claim 7 or 10, wherein the signal locking circuit comprises: a third triode and a fourth triode;

a base electrode of the third triode receives the first conduction signal, a collector electrode or an emitter electrode of the third triode transmits an enabling signal to a radio frequency front end output power amplifier, the first conduction signal is effective, the third triode is conducted, and the power amplifier transmits the enabling signal to be ineffective so as to control the power amplifier at the radio frequency front end not to work;

the base of the fourth triode receives the second conduction signal, the collector or emitter of the fourth triode outputs a low-noise amplifier to the radio frequency front end to receive the enabling signal, the second conduction signal is effective, the fourth triode is conducted, and the low-noise amplifier receives the enabling signal and is ineffective to control the low-noise amplifier at the radio frequency front end to be out of work.

13. A wireless communication device, comprising: an antenna, a main control board, a radio frequency front end chip and a signal processing circuit of the radio frequency front end according to any one of claims 1 to 12, wherein the input end of the signal processing circuit is connected with the main control board, and the output end of the signal processing circuit is connected with the radio frequency front end chip;