CN114710156B - Analog-digital conversion device - Google Patents
Analog-digital conversion device Download PDFInfo
- Publication number
- CN114710156B CN114710156B CN202210631941.XA CN202210631941A CN114710156B CN 114710156 B CN114710156 B CN 114710156B CN 202210631941 A CN202210631941 A CN 202210631941A CN 114710156 B CN114710156 B CN 114710156B
- Authority
- CN
- China
- Prior art keywords
- switch
- pseudo
- sampling
- random
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses an analog-to-digital conversion device which comprises an integrating circuit, a pseudo-random signal generating device and a quantizer, wherein the integrating circuit samples input voltage of analog quantity and adds pseudo-random number into the output end of the integrating circuit through the pseudo-random signal generating device after integration, the output of the integrating circuit and the pseudo-random number are summed at the input end of the quantizer and converted into digital quantity signals through the quantizer to be output. Therefore, the pseudo random number is added to the output end of the integrating circuit to reduce the periodicity of a digital quantity signal code stream and suppress clutter, but the mean value of the pseudo random number is 0, so that the pseudo random number in the digital quantity signal output by the quantizer is not required to be filtered, the operation is more convenient and faster, and the signal-to-noise ratio of the digital quantity signal output by the quantizer is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to an analog-to-digital conversion apparatus.
Background
When a quantizer in the analog-to-digital conversion device outputs a digital signal based on an integrated analog input signal output by the integrator, if an input voltage input to the integrator is a direct current signal or a slowly changing alternating current signal, a digital code stream output by the quantizer is periodic, so that harmonics in the digital code stream cannot be filtered, and the output signal-to-noise ratio of the analog-to-digital conversion device is reduced.
In the prior art, in order to suppress spurious signals output by a quantizer, increasing the order of an analog-to-digital conversion device or adding pseudo-random noise to the input end of the analog-to-digital conversion device is generally adopted, but increasing the order of the analog-to-digital conversion device can suppress periodic spurious output by the quantizer, but can also increase the power consumption and area of the analog-to-digital conversion device, and after increasing the pseudo-random noise, although the periodicity of a digital quantity code stream output by the quantizer can also be reduced, the pseudo-random noise in the digital quantity signal also needs to be filtered when the digital quantity signal is output, but in general, the filtering operation of the pseudo-random noise is complex, and the design difficulty is increased.
Disclosure of Invention
The invention aims to provide an analog-digital conversion device, which reduces the periodicity of a digital quantity signal code stream by adding a pseudo-random number at the output end of an integrating circuit and realizes the suppression of clutter, but because the mean value of the pseudo-random number is 0, the pseudo-random number in the digital quantity signal output by a quantizer is not required to be filtered, the operation is more convenient and faster, and the signal-to-noise ratio of the digital quantity signal output by the quantizer is improved.
To solve the above technical problem, the present invention provides an analog-to-digital conversion apparatus, including:
the integrating circuit is used for sampling and integrating the input voltage of the analog quantity according to the clock signal and the digital quantity signal output by the quantizer;
the output end of the pseudo-random signal generating device is connected with the output end of the integrating circuit and is used for adding a pseudo-random number into the output end of the integrating circuit so as to sum the integrated input voltage and the pseudo-random number, and the mean value of the pseudo-random number is 0;
and the input end of the quantizer is connected with the output end of the integrating circuit and is used for converting the integrated input voltage added with the pseudo-random number into the digital quantity signal.
Preferably, the integrating circuit comprises a sampling circuit and an integrator;
the input end of the sampling circuit inputs the input voltage of an analog quantity so as to sample the input voltage of the analog quantity;
the input end of the integrator is connected with the sampling circuit and used for integrating the input voltage of the analog quantity output by the sampling circuit and outputting the integrated input voltage.
Preferably, the sampling circuit includes a first forward sampling switch, a second forward sampling switch, a third forward sampling switch, a first reverse sampling switch, a second reverse sampling switch, a third reverse sampling switch, a forward sampling capacitor, a reverse sampling capacitor, a first digital feedback switch, a second digital feedback switch, a first digital reverse phase feedback switch, and a second digital reverse phase feedback switch;
a first end of the first forward sampling switch is connected with the input voltage of the analog quantity, a second end of the first forward sampling switch is connected with a first end of the forward sampling capacitor, a second end of the forward sampling capacitor is connected with a first end of the second reverse sampling switch, and a second end of the second reverse sampling switch is connected with an input end of the integrator;
the first end of the first reverse sampling switch is connected with the input voltage of the analog quantity, and the second end of the first reverse sampling switch is connected with the first end of the forward sampling capacitor; a first end of the second forward sampling switch is connected with a second end of the forward sampling capacitor, and a second end of the second forward sampling switch is connected with a reference voltage;
the first end of the reverse sampling capacitor is connected with the second end of the forward sampling capacitor, and the second end of the reverse sampling capacitor is connected with the first end of the third forward sampling switch and the first end of the third reverse sampling switch; a second end of the third forward sampling switch is connected with a first end of the second digital feedback switch and a first end of the second digital inverse feedback switch; a second end of the second digital inverting feedback switch is grounded; the second end of the second digital feedback switch is connected with a reference voltage; a second end of the third inverse sampling switch is connected with a first end of the first digital feedback switch and a first end of the first digital inverse feedback switch; the second end of the first digital feedback switch is grounded; a second terminal of the first digital inverting feedback switch is connected to the reference voltage;
the first digital feedback switch and the second digital feedback switch are used for being switched on when the digital quantity signal output by the quantizer is in a high level, and the first digital inverse feedback switch and the second digital inverse feedback switch are used for being switched off when the digital quantity signal output by the quantizer is in a high level, so that the inverse sampling capacitor samples the reference voltage or the grounding voltage;
the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are simultaneously conducted, and when the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are conducted, the forward sampling capacitor conducts forward sampling on the input voltage of the analog quantity; and when the first reverse sampling switch, the second reverse sampling switch and the third reverse sampling switch are simultaneously conducted and are conducted, the forward sampling capacitor conducts reverse sampling on the input voltage of the analog quantity.
Preferably, the integrator comprises a first integrating capacitor, a second integrating capacitor and an amplifier;
the first end of the first integrating capacitor is connected with the positive input end of the amplifier, and the second end of the first integrating capacitor is connected with the negative output end of the amplifier; the first end of the second integrating capacitor is connected with the input negative end of the amplifier, and the second end of the second integrating capacitor is connected with the output positive end of the amplifier;
the positive input end and the negative input end of the amplifier are the input ends of the integrator, and the integrator is used for integrating the voltages sampled by the first forward sampling capacitor, the first reverse sampling capacitor, the second forward sampling capacitor and the second reverse sampling capacitor when the analog quantity input voltage is subjected to forward sampling or reverse sampling, and outputting the integrated input voltage.
Preferably, the pseudo random signal generating means includes:
the device comprises an inverse output switch, a first conversion control switch, a second conversion control switch, a third conversion control switch, a fourth conversion control switch, a first pseudo-random capacitor, a second pseudo-random capacitor, a first pseudo-random switch, a second pseudo-random switch, a third pseudo-random switch, a fourth pseudo-random switch and an output capacitor;
the first end of the inverting output switch is connected with the output end of the integrator, and the second end of the inverting output switch is connected with the first end of the output capacitor and the first end of the first conversion control switch; the second end of the output capacitor is connected with the first end of the third conversion control switch, the first end of the first pseudo-random capacitor and the first end of the second pseudo-random capacitor; the second end of the first pseudo-random capacitor is connected with the first end of the second pseudo-random switch, the first end of the first pseudo-random switch and the first end of the second conversion control switch; a second end of the second pseudo-random capacitor is connected with a first end of the third pseudo-random switch, a first end of the fourth pseudo-random switch and a first end of the fourth conversion control switch;
a second end of the first conversion control switch, a second end of the second conversion control switch, a second end of the third conversion control switch, and a second end of the fourth conversion control switch are connected to the reference voltage;
a second end of the second pseudo-random switch is grounded, a second end of the first pseudo-random switch is connected with the reference voltage, a second end of the third pseudo-random switch is grounded, and a second end of the fourth pseudo-random switch is connected with the reference voltage;
the first conversion control switch, the second conversion control switch, the third conversion control switch, the fourth conversion control switch and the forward sampling switch act synchronously; the reverse output switch and the reverse sampling switch act synchronously;
the first pseudo-random switch, the second pseudo-random switch, the third pseudo-random switch and the fourth pseudo-random switch are used for adding pseudo-random numbers at the output end of the integrating circuit so as to sum up the integrated input voltage and the pseudo-random numbers, and the mean value of the pseudo-random numbers is 0.
Preferably, the input end of the quantizer is connected to the second end of the third conversion control switch, and the output end outputs the digital quantity signal.
Preferably, the method further comprises the following steps:
and the output end of the digital filter is connected with the output end of the quantizer and is used for filtering the digital quantity signal.
Preferably, the method further comprises the following steps:
and the input end of the phase inverter is connected with the output end of the quantizer, and the output end of the phase inverter is connected with the control ends of the first digital inverse feedback switch and the second digital inverse feedback switch and is used for performing inverse processing on the digital quantity signal.
The application provides an analog-to-digital conversion device which comprises an integrating circuit, a pseudo-random signal generating device and a quantizer, wherein the integrating circuit samples input voltage of analog quantity and adds pseudo-random numbers into the output end of the integrating circuit through the pseudo-random signal generating device after integration, the output of the integrating circuit and the pseudo-random numbers are summed at the input end of the quantizer and converted into digital quantity signals through the quantizer to be output. Therefore, the pseudo random number is added to the output end of the integrating circuit, the periodicity of a digital quantity signal code stream is reduced, and the suppression of the clutter is realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion apparatus provided in the present invention;
fig. 2 is a schematic structural diagram of an analog-to-digital conversion apparatus provided in the present invention;
fig. 3 is a timing diagram of a sampling and conversion phase key digital signal according to the present invention.
Detailed Description
The core of the invention is to provide an analog-to-digital conversion device, which reduces the periodicity of a digital quantity signal code stream by adding a pseudo random number at the output end of an integrating circuit, and realizes the inhibition of clutter, but because the mean value of the pseudo random number is 0, the pseudo random number in the digital quantity signal output by a quantizer does not need to be filtered, the operation is more convenient, and the signal-to-noise ratio of the digital quantity signal output by the quantizer is improved.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an analog-to-digital conversion apparatus provided by the present invention, the apparatus including:
an integrating circuit 1 for sampling and integrating an input voltage of an analog quantity according to a clock signal and a digital quantity signal output from the quantizer 3;
the pseudo-random signal generation device 2 is connected with the output end of the integration circuit 1 at the output end and is used for adding pseudo-random numbers into the output end of the integration circuit 1 so as to sum up the integrated input voltage and the pseudo-random numbers, and the mean value of the pseudo-random numbers is 0;
a quantizer 3, the input terminal of which is connected to the output terminal of the integrating circuit 1, converts the integrated input voltage added with the pseudo random number into a digital quantity signal.
The applicant considers that the analog-to-Digital Conversion apparatus in the prior art, such as a sigma-delta ADC, converts an analog signal into a Digital code stream by using oversampling and noise shaping techniques, and then filters out a high-frequency signal by using a Digital filter, so as to convert the high-frequency signal into a Digital output of the ADC (analog-to-Digital converter). It is an ideal choice for processing low-frequency and high-precision analog signals, and is widely applied to the fields of automotive electronics, medical appliances and the like. Conventional first order sigma-delta ADCs have two drawbacks: 1. each system clock cycle only has time sampling of half clock cycle, and the other half time conversion, namely, each system clock cycle is sampled once and converted once, so that the efficiency is low, and the equivalent signal-to-noise ratio is relatively low. 2. The output of the integrator is coupled directly to the quantizer 3, the output of the quantizer 3 being the output of the quantizer 3 when it samples a dc signal or a slowly varying ac signalThe outgoing stream will be periodic. Assume a sampling frequency of f s The code stream period is M, then f is the frequency s The peak value will be generated at the position of/M and its harmonic wave, if it is smaller, the digital filter can filter these harmonic wave, but if the input DC signal is very small, the period M of the obtained periodic code stream will be very large, f s the/M will fall within the signal bandwidth and cannot be filtered out by the digital filter, which will significantly degrade the spurious free dynamic range of the sigma-delta ADC. In order to improve the output signal-to-noise ratio and simultaneously suppress the spurious signals output by the quantizer 3, it is generally adopted to increase the order of the sigma-delta ADC or apply a pseudo-random noise signal with a certain amplitude to the input end of the sigma-delta ADC to be superimposed on the original input signal, and subtract this part of signal in the digital processing stage, so as to avoid the periodicity of the code stream.
However, when the order of the sigma-delta ADC is increased to suppress the periodic spurs, good effects can be usually achieved, but the power consumption and area of the analog-to-digital conversion device are greatly increased, which is unacceptable for low-power and low-cost applications, and once the order is increased, the sigma-delta ADC may have a problem of loop stability.
However, by applying a certain amplitude of pseudo random noise to the input of the sigma-delta ADC, the added pseudo random noise must be subtracted in the digital processing stage, and it is not easy to subtract this part of pseudo random noise, which greatly increases the design complexity of the analog-to-digital conversion apparatus.
In the present application, in order to solve the above technical problem, an integrating circuit 1, a pseudo random signal generating device 2 and a quantizer 3 are provided in an analog-to-digital conversion device, wherein the pseudo random signal generating device 2 adds a pseudo random number at an output end of the integrating circuit 1 to sum up an integrated input voltage and the pseudo random number, but since an average value of the pseudo random number is 0, it is not necessary to subtract the pseudo random number in a digital processing stage, and the pseudo random number does not affect a final output of the analog-to-digital conversion device.
In conclusion, the pseudo random number is added to the output end of the integrating circuit to reduce the periodicity of the digital quantity signal code stream and suppress the clutter, but the mean value of the pseudo random number is 0, so that the pseudo random number in the digital quantity signal output by the quantizer is not required to be filtered, the operation is more convenient and faster, and the signal-to-noise ratio of the digital quantity signal output by the quantizer is improved.
On the basis of the above-described embodiment:
referring to fig. 2, fig. 2 is a schematic structural diagram of an analog-to-digital conversion apparatus provided in the present invention.
As a preferred embodiment, the integrating circuit 1 includes a sampling circuit and an integrator;
the input end of the sampling circuit inputs the input voltage of the analog quantity so as to sample the input voltage of the analog quantity;
the input end of the integrator is connected with the sampling circuit and used for integrating the input voltage of the analog quantity output by the sampling circuit and outputting the integrated input voltage.
The integrating circuit 1 in this embodiment is provided with a sampling circuit and an integrator, wherein the sampling circuit can sample the input voltage of the analog quantity, so that the integrator can integrate the input voltage of the analog quantity.
As a preferred embodiment, the sampling circuit includes a first forward sampling switch, a second forward sampling switch, a third forward sampling switch, a first reverse sampling switch, a second reverse sampling switch, a third reverse sampling switch, a forward sampling capacitor, a reverse sampling capacitor, a first digital feedback switch, a second digital feedback switch, a first digital reverse feedback switch, and a second digital reverse feedback switch;
the first end of the first forward sampling switch is connected with the input voltage of the analog quantity, the second end of the first forward sampling switch is connected with the first end of the forward sampling capacitor, the second end of the forward sampling capacitor is connected with the first end of the second reverse sampling switch, and the second end of the second reverse sampling switch is connected with the input end of the integrator;
the first end of the first reverse sampling switch is connected with the input voltage of the analog quantity, and the second end of the first reverse sampling switch is connected with the first end of the forward sampling capacitor; the first end of the second forward sampling switch is connected with the second end of the forward sampling capacitor, and the second end of the second forward sampling switch is connected with the reference voltage;
the first end of the reverse sampling capacitor is connected with the second end of the forward sampling capacitor, and the second end of the reverse sampling capacitor is connected with the first end of the third forward sampling switch and the first end of the third reverse sampling switch; the second end of the third forward sampling switch is connected with the first end of the second digital feedback switch and the first end of the second digital reverse-phase feedback switch; the second end of the second digital inverse feedback switch is grounded; the second end of the second digital feedback switch is connected with the reference voltage; the second end of the third reverse sampling switch is connected with the first end of the first digital feedback switch and the first end of the first digital reverse phase feedback switch; the second end of the first digital feedback switch is grounded; the second end of the first digital inverting feedback switch is connected with a reference voltage;
the first digital feedback switch and the second digital feedback switch are used for being switched on when a digital quantity signal output by the quantizer is at a high level, and the first digital inverse feedback switch and the second digital inverse feedback switch are used for being switched off when the digital quantity signal output by the quantizer is at the high level, so that the inverse sampling capacitor samples a reference voltage or a grounding voltage;
the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are simultaneously conducted, and when the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are conducted, the forward sampling capacitor conducts forward sampling on the input voltage of the analog quantity; when the first reverse sampling switch, the second reverse sampling switch and the third reverse sampling switch are simultaneously conducted and are conducted, the forward sampling capacitor conducts reverse sampling on the input voltage of the analog quantity.
Specifically, the first forward sampling switch includes a first forward sampling sub-switch S11 and a second forward sampling sub-switch S12, the second forward sampling switch includes a third forward sampling sub-switch S13 and a fourth forward sampling sub-switch S14, the third forward sampling switch includes a fifth forward sampling sub-switch S15 and a sixth forward sampling sub-switch S16, the first reverse sampling switch includes a first reverse sampling sub-switch S21 and a second reverse sampling sub-switch S22, the second reverse sampling switch includes a third reverse sampling sub-switch S23 and a fourth reverse sampling sub-switch S24, the third reverse sampling switch includes a fifth reverse sampling sub-switch S25 and a sixth reverse sampling sub-switch S26, the sampling capacitors include a first forward sampling sub-capacitor C11 and a second forward sampling sub-capacitor C12, the reverse sampling capacitors include a first reverse sampling sub-capacitor C21 and a second reverse sampling sub-capacitor C22, the first sampling sub-switch includes a first reverse sampling sub-capacitor C11 and a second forward sampling sub-capacitor C12, the reverse sampling capacitor includes a first reverse sampling sub-switch D13 and a second reverse sampling sub-switch D14, the reverse sampling sub-switch includes a first reverse digital feedback sub-switch DN, the first reverse digital switch D13 and the reverse digital feedback sub-switch D14, the reverse digital feedback sub-switch includes a second digital feedback sub-switch DN, the digital feedback sub-switch D13 and the second reverse sub-digital feedback sub-switch D14;
a first end of the first forward sampling sub-switch S11 is connected with a first analog quantity voltage, a second end of the first forward sampling sub-switch S11 is connected with a first end of the first forward sampling sub-capacitor C11, a second end of the first forward sampling sub-capacitor C11 is connected with a first end of the third reverse sampling sub-switch S23, and a second end of the third reverse sampling sub-switch S23 is connected with an input positive end of the integrator;
a first end of the second forward sampling sub-switch S12 is connected to the second analog voltage, a second end is connected to a first end of the second forward sampling sub-capacitor C12, a second end of the second forward sampling sub-capacitor C12 is connected to a first end of the fourth reverse sampling sub-switch S24, and a second end of the fourth reverse sampling sub-switch S24 is connected to the input negative terminal of the integrator;
a first end of the first reverse sampling sub-switch S21 is connected with the second analog quantity voltage, and a second end is connected with a first end of the first forward sampling sub-capacitor C11; a first end of the second reverse sampling sub-switch S22 is connected to the first analog voltage, and a second end is connected to a first end of the second forward sampling sub-capacitor C12;
a first end of the third forward sampling sub-switch S13 is connected to the second end of the first forward sampling sub-capacitor C11, and a second end thereof is connected to the reference voltage, a first end of the third forward sampling sub-switch S13 is connected to the reference voltage, and a second end thereof is connected to the second end of the second forward sampling sub-capacitor C12;
a first end of the first reverse sampling sub-capacitor C21 is connected with a second end of the first forward sampling sub-capacitor C11, and a second end of the first reverse sampling sub-capacitor C is connected with a first end of the fifth forward sampling sub-switch S15 and a first end of the fifth reverse sampling sub-switch S25; a second end of the fifth forward sampling sub-switch S15 is connected to a first end of the second digital feedback sub-switch D12 and a first end of the second digital inverting feedback sub-switch DN 12; a second end of the second digital inverting feedback sub-switch DN12 is grounded; a second end of the second digital feedback sub-switch D12 is connected to the reference voltage; a second end of the fifth inverse sampling sub-switch S25 is connected to a first end of the first digital feedback sub-switch D11 and a first end of the first digital inverse feedback sub-switch DN 11; the second end of the first digital feedback sub-switch D11 is grounded; a second end of the first digital inverting feedback sub-switch DN11 is connected to a reference voltage;
a first end of the second reverse sampling sub-capacitor C22 is connected to a second end of the second forward sampling sub-capacitor C12, and a second end is connected to a first end of the sixth forward sampling sub-switch S16 and a first end of the sixth reverse sampling sub-switch S26; a second end of the sixth forward sampling sub-switch S16 is connected to a first end of the third digital feedback sub-switch D13 and a first end of the third digital inverse feedback sub-switch DN 13; the second end of the third digital feedback sub-switch D13 is grounded; a second end of the third digital inverting feedback sub-switch DN13 is connected to the reference voltage; a second end of the sixth inverse sampling sub-switch S26 is connected to a first end of the fourth digital feedback sub-switch D14 and a first end of the fourth digital inverse feedback sub-switch DN14; a second end of the fourth digital inverting feedback sub-switch DN14 is grounded; a second end of the fourth digital feedback sub-switch D14 is connected to the reference voltage;
the first digital feedback sub-switch D11, the second digital feedback sub-switch D12, the third digital feedback sub-switch D13 and the fourth digital feedback sub-switch D14 are used for being turned on when a digital quantity signal output by the quantizer 3 is at a high level, and the first digital inverse feedback sub-switch DN11, the second digital inverse feedback sub-switch DN12, the third digital inverse feedback sub-switch DN13 and the fourth digital inverse feedback sub-switch DN14 are used for being turned off when the digital quantity signal output by the quantizer 3 is at the high level, so that the first inverse sampling sub-capacitor C21 samples a reference voltage or a ground voltage;
when the first forward sampling sub-switch S11, the second forward sampling sub-switch S12, the third forward sampling sub-switch S13, the fourth forward sampling sub-switch S14, the fifth forward sampling sub-switch S15 and the sixth forward sampling sub-switch S16 are simultaneously conducted and conducted, the first forward sampling sub-capacitor C11 samples the first analog quantity voltage, and the second forward sampling sub-capacitor C12 samples the second analog quantity voltage;
when the first reverse sampling sub-switch S21, the second reverse sampling sub-switch S22, the third reverse sampling sub-switch S23, the fourth reverse sampling sub-switch S24, the fifth reverse sampling sub-switch S25 and the sixth reverse sampling sub-switch S26 are simultaneously conducted and conducted, the second forward sampling sub-capacitor C12 samples the first analog quantity voltage, and the first forward sampling sub-capacitor C11 samples the second analog quantity voltage;
the difference between the first analog quantity voltage and the second analog quantity voltage is the input voltage of the analog quantity.
In this embodiment, an example of a sampling circuit is given, in which, because the first forward sampling sub-switch S11, the second forward sampling sub-switch S12, the third forward sampling sub-switch S13, the fourth forward sampling sub-switch S14, the fifth forward sampling sub-switch S15, and the sixth forward sampling sub-switch S16 operate simultaneously, the first reverse sampling sub-switch S21, the second reverse sampling sub-switch S22, the third reverse sampling sub-switch S23, the fourth reverse sampling sub-switch S24, the fifth reverse sampling sub-switch S25, and the sixth reverse sampling sub-switch S26 operate simultaneously, and the first forward sampling sub-switch S11 and the first reverse sampling sub-switch S21 operate oppositely, that is, when the first forward sampling sub-switch S11 is turned on, the first reverse sampling sub-switch S21 is turned off, that is, when the first forward sampling sub-switch S11 is turned on, the first forward sampling sub-capacitor C11 samples a first analog voltage, when the first forward sampling sub-switch S11 is turned on, the second forward sampling sub-switch S12 samples a second analog voltage, and the second forward sampling sub-switch S12 analog voltage.
As a preferred embodiment, the integrator includes a first integrating capacitor C31, a second integrating capacitor C32, and an amplifier;
the first end of the first integrating capacitor C31 is connected with the positive input end of the amplifier, and the second end of the first integrating capacitor C31 is connected with the negative output end of the amplifier; the first end of the second integrating capacitor C32 is connected with the input negative end of the amplifier, and the second end is connected with the output positive end of the amplifier;
the input positive end and the input negative end of the amplifier are input ends of an integrator, and are used for integrating voltages sampled by the first forward sampling sub-capacitor C11, the first reverse sampling sub-capacitor C21, the second forward sampling sub-capacitor C12 and the second reverse sampling sub-capacitor C22 when performing forward sampling or reverse sampling on an input voltage of an analog quantity, and outputting an integrated input voltage.
The integrator in this embodiment includes an amplifier, and a first integrating capacitor C31 is disposed between an input positive terminal and an output negative terminal of the amplifier, and a second integrating capacitor C32 is disposed between the input negative terminal and the output positive terminal, so that the integrator can integrate an analog input signal output by the sampling circuit.
Specifically, the positive input terminal of the amplifier is the positive input terminal of the integrator, and the negative input terminal of the amplifier is the negative input terminal of the integrator.
In this embodiment, the first half cycle and the second half cycle in a sampling cycle sample an analog input signal, but the conversion stage when the analog input signal is converted into a digital signal is in the second half cycle of the sampling cycle, that is, a sampling cycle samples twice and converts once, so that the capacitances of the first forward sampling sub-capacitor C11, the second forward sampling sub-capacitor C12, the first reverse sampling sub-capacitor C21, and the second reverse sampling sub-capacitor C22 can be reduced to half of those of the conventional scheme, the total equivalent charge obtained by two times of sampling remains unchanged, if the integrating capacitors of the integrator, that is, the capacitances of the first integrating capacitor C31 and the second integrating capacitor C32, remain unchanged, since the noise generated by the sampling circuit is increased by 3dB, since the output swing amplitude of the integrator is increased by 1 time, the corresponding to the increase of the dynamic range by 1 time by 6dB, the signal-to-noise ratio of the analog-digital conversion apparatus is increased by 3dB; if the capacitances of the first integrating capacitor C31 and the second integrating capacitor C32 are reduced by half, the total load capacitance of the output end of the integrator in the present application is reduced by half under the condition of keeping the same signal-to-noise ratio as that of the conventional scheme, which means that the power consumption of the integrator and the area of the capacitance are also reduced by half, thereby realizing cost saving.
It should be noted that the relationship between the input and output of the integrator and the reference voltage VREF in this embodiment is expressed as:
VOUT=VOUTP-VOUTN=（2C1/C3）·（z -1 /（1- z -1 ））·（VIP-VIN）+（2C2/C3）·（z -1 /（1- z -1 ））·VREF；
VOUT is an output voltage of the integrator, VOUTP is a voltage output by an output positive terminal of the integrator, VOUTN is a voltage output by an output negative terminal of the integrator, C1 is a capacitance value of the first forward sampling sub-capacitor C11 or the second forward sampling sub-capacitor C12, the capacitance values of the first forward sampling sub-capacitor C11 and the second forward sampling sub-capacitor C12 are the same, C2 is a capacitance value of the first reverse sampling sub-capacitor C21 or the second reverse sampling sub-capacitor C22, the capacitance values of the first reverse sampling sub-capacitor C21 and the second reverse sampling sub-capacitor C22 are the same, C3 is a capacitance value of the first integrating capacitor C31 or the second integrating capacitor C32, the capacitance values of the first integrating capacitor C31 and the second integrating capacitor C32 are the same, VIP is a first analog quantity voltage, VIN is a second analog quantity voltage, z represents a complex number, (2C 1/C3) is a forward gain, and (2C 2/C3) is a feedback coefficient.
It should be noted that, in this application, a sampling period is a clock period of a system.
In addition, the amplifier in the present application may be, but is not limited to, an OTA (operational transconductance amplifier).
As a preferred embodiment, the pseudo-random signal generating apparatus 2 includes:
the device comprises an inverse output switch, a first conversion control switch, a second conversion control switch, a third conversion control switch, a fourth conversion control switch, a first pseudo-random capacitor, a second pseudo-random capacitor, a first pseudo-random switch, a second pseudo-random switch, a third pseudo-random switch, a fourth pseudo-random switch and an output capacitor;
the first end of the inverting output switch is connected with the output end of the integrator, and the second end of the inverting output switch is connected with the first end of the output capacitor and the first end of the first conversion control switch; the second end of the output capacitor is connected with the first end of the third conversion control switch, the first end of the first pseudo-random capacitor and the first end of the second pseudo-random capacitor; the second end of the first pseudo-random capacitor is connected with the first end of the second pseudo-random switch, the first end of the first pseudo-random switch and the first end of the second conversion control switch; the second end of the second pseudo-random capacitor is connected with the first end of the third pseudo-random switch, the first end of the fourth pseudo-random switch and the first end of the fourth conversion control switch;
the second end of the first conversion control switch, the second end of the second conversion control switch, the second end of the third conversion control switch and the second end of the fourth conversion control switch are connected and connected with a reference voltage;
the second end of the second pseudo-random switch is grounded, the second end of the first pseudo-random switch is connected with the reference voltage, the second end of the third pseudo-random switch is grounded, and the second end of the fourth pseudo-random switch is connected with the reference voltage;
the first conversion control switch, the second conversion control switch, the third conversion control switch and the fourth conversion control switch act synchronously with the forward sampling switch; the reverse phase output switch and the reverse sampling switch act synchronously;
the first pseudo-random switch, the second pseudo-random switch, the third pseudo-random switch and the fourth pseudo-random switch are used for adding pseudo-random numbers at the output end of the integrating circuit so as to sum up the integrated input voltage and the pseudo-random numbers, and the mean value of the pseudo-random numbers is 0.
Specifically, the inverting output switch includes a first inverting output sub-switch S27 and a second inverting output sub-switch S28, the first switching control switch includes a first switching control sub-switch S17 and a second switching control sub-switch S18, the second switching control switch includes a third switching control sub-switch S19 and a fourth switching control sub-switch S10, the third switching control switch includes a fifth switching control sub-switch S111 and a sixth switching control sub-switch S112, the fourth switching control switch includes a seventh switching control sub-switch S113 and an eighth switching control sub-switch S114, the first pseudo-random capacitor includes a first pseudo-random sub-capacitor C51 and a second pseudo-random sub-capacitor C52, the second pseudo-random capacitor includes a third pseudo-random sub-capacitor C61 and a fourth pseudo-random sub-capacitor C62, the first pseudo-random switch includes a first pseudo-random sub-switch S31 and a second pseudo-random sub-switch S32, the second pseudo-random switch includes a third pseudo-random sub-switch S41 and a fourth pseudo-random sub-switch S42, the fourth pseudo-random sub-switch S42 includes a fourth pseudo-random sub-switch S41 and a pseudo-random sub-switch S52, the second pseudo-random sub-switch S41 and a pseudo-random sub-switch S42 includes a fourth pseudo-random sub-switch S42, the pseudo-random sub-switch S41 and a pseudo-random sub-switch S52;
a first end of the first inverting output sub-switch S27 is connected to the output negative end of the integrator, and a second end is connected to a first end of the first output sub-capacitor C41 and a first end of the first non-inverting control sub-switch S17; the second end of the first output sub-capacitor C41 is connected to the first end of the fifth positive phase control sub-switch S111, the first end of the first pseudo-random sub-capacitor C51, and the first end of the third pseudo-random sub-capacitor C61; a second end of the first pseudo-random sub-capacitor C51 is connected with a first end of the third pseudo-random sub-switch S41, a first end of the first pseudo-random sub-switch S31 and a first end of the third positive phase control sub-switch S19; a second end of the third pseudo-random sub-capacitor C61 is connected with a first end of the fifth pseudo-random sub-switch S51, a first end of the seventh pseudo-random sub-switch S61 and a first end of the seventh positive phase control sub-switch S113;
a first terminal of the second inverting output sub-switch S28 is connected to the positive output terminal of the integrator, and a second terminal is connected to the first terminal of the second output sub-capacitor C42 and the first terminal of the second non-inverting control sub-switch S18; the second end of the second output sub-capacitor C42 is connected to the first end of the sixth positive phase control sub-switch S112, the first end of the second pseudo-random sub-capacitor C52 and the first end of the fourth pseudo-random sub-capacitor C62; a second end of the second pseudo-random sub-capacitor C52 is connected to a first end of the fourth pseudo-random sub-switch S42, a first end of the second pseudo-random sub-switch S32, and a first end of the fourth positive phase control sub-switch S10; a second end of the fourth pseudo-random sub-capacitor C62 is connected to a first end of the sixth pseudo-random sub-switch S52, a first end of the eighth pseudo-random sub-switch S62, and a first end of the eighth positive phase control sub-switch S114;
the second end of the first positive phase control sub-switch S17, the second end of the second positive phase control sub-switch S18, the second end of the third positive phase control sub-switch S19, the second end of the fourth positive phase control sub-switch S10, the second end of the fifth positive phase control sub-switch S111, the second end of the sixth positive phase control sub-switch S112, the second end of the seventh positive phase control sub-switch S113, and the second end of the eighth positive phase control sub-switch S114 are connected to the reference voltage;
the second end of the third pseudo-random sub-switch S41 is grounded, the second end of the first pseudo-random sub-switch S31 is connected to the reference voltage, the second end of the fifth pseudo-random sub-switch S51 is grounded, the second end of the seventh pseudo-random sub-switch S61 is connected to the reference voltage, the second end of the second pseudo-random sub-switch S32 is grounded, the second end of the fourth pseudo-random sub-switch S42 is connected to the reference voltage, the second end of the eighth pseudo-random sub-switch S62 is grounded, and the second end of the sixth pseudo-random sub-switch S52 is connected to the reference voltage;
the first positive phase control sub-switch S17, the second positive phase control sub-switch S18, the third positive phase control sub-switch S19, the fourth positive phase control sub-switch S10, the fifth positive phase control sub-switch S111, the sixth positive phase control sub-switch S112, the seventh positive phase control sub-switch S113, and the eighth positive phase control sub-switch S114 operate in synchronization with the first positive direction sampling sub-switch S11; the first inverted output sub-switch S27 and the second inverted output sub-switch S28 act in synchronization with the first inverted sampling sub-switch S21;
the first pseudo-random subswitch S31, the second pseudo-random subswitch S32, the third pseudo-random subswitch S41, the fourth pseudo-random subswitch S42, the fifth pseudo-random subswitch S51, the sixth pseudo-random subswitch S52, the seventh pseudo-random subswitch S61 and the eighth pseudo-random subswitch S62 are used for adding pseudo-random numbers at the output end of the integration circuit 1 to sum up the integrated input voltage and the pseudo-random numbers, and the mean value of the pseudo-random numbers is 0.
In this embodiment, the control signals for controlling the first pseudo-random subswitch S31, the second pseudo-random subswitch S32, the third pseudo-random subswitch S41, the fourth pseudo-random subswitch S42, the fifth pseudo-random subswitch S51, the sixth pseudo-random subswitch S52, the seventh pseudo-random subswitch S61, and the eighth pseudo-random subswitch S62 are pseudo-random signals generated by pseudo-random number control logic, and in the first half period of the sampling period, the first pseudo-random subswitch S31, the second pseudo-random subswitch S32, the third pseudo-random subswitch S41, the fourth pseudo-random subswitch S42, the fifth pseudo-random subswitch S51, the sixth pseudo-random subswitch S52, the seventh pseudo-random subswitch S61, and the eighth pseudo-random subswitch S62 are all turned off, and in the second half period, the first pseudo-random subswitch S31, a second pseudo-random subswitch S32 and a third pseudo-random subswitch S41, a fourth pseudo-random subswitch S42 being inverted, a fifth pseudo-random subswitch S51, a sixth pseudo-random subswitch S52 and a seventh pseudo-random subswitch S61, an eighth pseudo-random subswitch S62 being inverted, i.e. the first pseudo-random subswitch S31 and the second pseudo-random subswitch S32 are actuated simultaneously, the third pseudo-random subswitch S41 and the fourth pseudo-random subswitch S42 are actuated simultaneously, the fifth pseudo-random subswitch S51 and the sixth pseudo-random subswitch S52 are actuated simultaneously, the seventh pseudo-random subswitch S61 and the eighth pseudo-random subswitch S62 are actuated simultaneously, but the first pseudo-random subswitch S31 and the third pseudo-random subswitch S41 are actuated oppositely, and the fifth pseudo-random subswitch S51 and the seventh pseudo-random subswitch S61 are actuated oppositely. Referring to fig. 3, fig. 3 is a timing diagram of a sampling and converting phase key digital signal according to the present invention.
Wherein D is a digital quantity signal output by the quantizer 3, and is used for controlling on and off of the first digital feedback sub-switch D11, the second digital feedback sub-switch D12, the third digital feedback sub-switch D13, and the fourth digital feedback sub-switch D14, DN is a signal opposite to the digital quantity signal output by the quantizer 3, and is used for controlling on and off of the first digital inverse feedback sub-switch DN11, the second digital inverse feedback sub-switch DN12, the third digital inverse feedback sub-switch DN13, and the fourth digital inverse feedback sub-switch DN14, and the first forward sampling sub-switch S11 is a signal for controlling on and off of the first forward sampling sub-switch S11, and since S1 is simultaneously on and off, the first forward sampling sub-switch S11 in fig. 3 is a control signal for each switch S1. However, preferably, the time of turning on and off of the third forward sampling sub-switch S13 lags the time of turning on and off of the first forward sampling sub-switch S11, that is, the third forward sampling sub-switch S13 turns on and off later than the first forward sampling sub-switch S11, and the time of turning on and off of the third reverse sampling sub-switch S23 lags the time of turning on and off of the first reverse sampling sub-switch S21, that is, the third reverse sampling sub-switch S23 turns on and off later than the first reverse sampling sub-switch S21, so as to reduce clock feedthrough.
In addition, PR in fig. 3 is a pseudo random number, PRN is PR inversion, and PR in fig. 3 is different from each other. In outputting the pseudo random number, the differential output Δ V of the integrator = VOUTN-VOUTP, the total capacitance value C of the node a between the first pseudo random sub-capacitor C51 and the third pseudo random sub-capacitor C61, or the node B between the second pseudo random sub-capacitor C52 and the fourth pseudo random sub-capacitor C62 T = C4+ C5+ C6, where C4 is a capacitance value of the first output sub-capacitor C41 or the second output sub-capacitor C42, C5 is a capacitance value of the first pseudo-random sub-capacitor C51 or the second pseudo-random sub-capacitor C52, and C6 is a capacitance value of the third pseudo-random sub-capacitor C61 or the fourth pseudo-random sub-capacitor C62.
The integrated input voltage added to the pseudo random number is:
in the above formula, V A Voltage at point A, V B For the voltage at point B, the coefficient term VREF may be, but is not limited to, a binary pseudo random number generated by a pseudo random number PRBS10 generator and a logic circuit, and randomly allocated among 4 groups to select which group is to be compared to the input terminal of the quantizer 3, that is, any one of the four groups is used as the pseudo random number added to the integrated input voltage. 2 due to PRBS10 10 The number of 0's in the-1 bit random sequence differs from the number of 1's by 1, so that the 4 sets of values have an average value close to 0 in a PRBS10 periodic sequence. AddingAfter the pseudo-random number is input, the switching point of the quantizer 3 changes from a fixed Δ V =0 to a randomly changing V A -V B =0, thus randomizing the high and low levels output by the quantizer 3. Increasing the number of bits of the pseudo random number makes the output of the quantizer 3 more randomized. The values of the first output sub-capacitor C41, the second output sub-capacitor C42, the first pseudo-random sub-capacitor C51, the second pseudo-random sub-capacitor C52, the third pseudo-random sub-capacitor C61 and the fourth pseudo-random sub-capacitor C62 can be adjusted according to practical applications.
As a preferred embodiment, the input terminal of the quantizer 3 is connected to the second terminal of the third non-inverting control switch, and the output terminal outputs a digital quantity signal.
Specifically, the input negative terminal of the quantizer 3 is connected to the second terminal of the seventh conversion control sub-switch S113, the input positive terminal is connected to the second terminal of the eighth conversion control sub-switch S114, and the output terminal outputs the digital quantity signal.
The quantizer 3 in this embodiment is connected to the seventh positive phase control sub-switch S113 and the eighth positive phase control sub-switch S114, and the seventh positive phase control sub-switch S113 and the eighth positive phase control sub-switch S114 directly input the integrated input voltage added with the pseudo random number into the quantizer 3, so that the quantizer 3 outputs a corresponding digital quantity signal.
As a preferred embodiment, the method further comprises the following steps:
and the output end of the digital filter is connected with the output end of the quantizer 3 and is used for filtering the digital quantity signal.
In this embodiment, the digital filter is disposed at the output end of the quantizer 3 to filter the digital quantity signal output by the quantizer 3, so as to avoid interference in the digital quantity signal from affecting subsequent processing of the digital quantity signal.
As a preferred embodiment, further comprising:
and the phase inverter is used for performing phase inversion processing on the digital quantity signal, and the input end of the phase inverter is connected with the output end of the quantizer 3, and the output end of the phase inverter is connected with the control ends of the first digital inverse feedback switch and the second digital inverse feedback switch.
Specifically, the input end of the inverter is connected to the output end of the quantizer 3, and the output end is connected to the control ends of the first digital inverting feedback sub-switch DN11, the second digital inverting feedback sub-switch DN12, the third digital inverting feedback sub-switch DN13, and the fourth digital inverting feedback sub-switch DN 14.
In the application, the first digital inverse feedback sub-switch DN11, the second digital inverse feedback sub-switch DN12, the third digital inverse feedback sub-switch DN13 and the fourth digital inverse feedback sub-switch DN14 are switched on or off based on the signals with the opposite digital quantity output by the quantizer 3, and the phase inverter is further arranged, so that the signals with the opposite digital quantity output by the quantizer 3 are directly output, and the first digital inverse feedback sub-switch DN11, the second digital inverse feedback sub-switch DN12, the third digital inverse feedback sub-switch DN13 and the fourth digital inverse feedback sub-switch DN14 are directly controlled, so that the normal work of the analog-to-digital conversion device is ensured.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. An analog-to-digital conversion apparatus, comprising:
the integrating circuit is used for sampling and integrating the input voltage of the analog quantity according to the clock signal and the digital quantity signal output by the quantizer;
the output end of the pseudo-random signal generating device is connected with the output end of the integrating circuit and is used for adding a pseudo-random number into the output end of the integrating circuit so as to sum the integrated input voltage and the pseudo-random number, and the mean value of the pseudo-random number is 0;
the input end of the quantizer is connected with the output end of the integrating circuit and is used for converting the integrated input voltage added with the pseudo-random number into the digital quantity signal;
the integration circuit comprises a sampling circuit and an integrator;
the input end of the sampling circuit inputs the input voltage of an analog quantity so as to sample the input voltage of the analog quantity;
the input end of the integrator is connected with the sampling circuit and is used for integrating the input voltage of the analog quantity output by the sampling circuit and outputting the integrated input voltage;
the sampling circuit comprises a first forward sampling switch, a second forward sampling switch, a third forward sampling switch, a first reverse sampling switch, a second reverse sampling switch, a third reverse sampling switch, a forward sampling capacitor, a reverse sampling capacitor, a first digital feedback switch, a second digital feedback switch, a first digital reverse phase feedback switch and a second digital reverse phase feedback switch;
a first end of the first forward sampling switch is connected with the input voltage of the analog quantity, a second end of the first forward sampling switch is connected with a first end of the forward sampling capacitor, a second end of the forward sampling capacitor is connected with a first end of the second reverse sampling switch, and a second end of the second reverse sampling switch is connected with an input end of the integrator;
the first end of the first reverse sampling switch is connected with the input voltage of the analog quantity, and the second end of the first reverse sampling switch is connected with the first end of the forward sampling capacitor; a first end of the second forward sampling switch is connected with a second end of the forward sampling capacitor, and a second end of the second forward sampling switch is connected with a reference voltage;
the first end of the reverse sampling capacitor is connected with the second end of the forward sampling capacitor, and the second end of the reverse sampling capacitor is connected with the first end of the third forward sampling switch and the first end of the third reverse sampling switch; a second end of the third forward sampling switch is connected with a first end of the second digital feedback switch and a first end of the second digital inverse feedback switch; a second end of the second digital inverting feedback switch is grounded; the second end of the second digital feedback switch is connected with a reference voltage; a second end of the third inverse sampling switch is connected with a first end of the first digital feedback switch and a first end of the first digital inverse feedback switch; the second end of the first digital feedback switch is grounded; a second terminal of the first digital inverting feedback switch is connected to the reference voltage;
the first digital feedback switch and the second digital feedback switch are used for being switched on when the digital quantity signal output by the quantizer is in a high level, and the first digital inverse feedback switch and the second digital inverse feedback switch are used for being switched off when the digital quantity signal output by the quantizer is in a high level, so that the inverse sampling capacitor samples the reference voltage or the grounding voltage;
the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are simultaneously conducted, and when the first forward sampling switch, the second forward sampling switch and the third forward sampling switch are conducted, the forward sampling capacitor conducts forward sampling on the input voltage of the analog quantity; when the first reverse sampling switch, the second reverse sampling switch and the third reverse sampling switch are simultaneously conducted and conducted, the forward sampling capacitor conducts reverse sampling on the input voltage of the analog quantity;
the pseudo random signal generating apparatus includes:
the device comprises an inverse output switch, a first conversion control switch, a second conversion control switch, a third conversion control switch, a fourth conversion control switch, a first pseudo-random capacitor, a second pseudo-random capacitor, a first pseudo-random switch, a second pseudo-random switch, a third pseudo-random switch, a fourth pseudo-random switch and an output capacitor;
the first end of the inverting output switch is connected with the output end of the integrator, and the second end of the inverting output switch is connected with the first end of the output capacitor and the first end of the first conversion control switch; the second end of the output capacitor is connected with the first end of the third conversion control switch, the first end of the first pseudo-random capacitor and the first end of the second pseudo-random capacitor; the second end of the first pseudo-random capacitor is connected with the first end of the second pseudo-random switch, the first end of the first pseudo-random switch and the first end of the second conversion control switch; a second end of the second pseudo-random capacitor is connected with a first end of the third pseudo-random switch, a first end of the fourth pseudo-random switch and a first end of the fourth conversion control switch;
a second end of the first conversion control switch, a second end of the second conversion control switch, a second end of the third conversion control switch, and a second end of the fourth conversion control switch are connected to the reference voltage;
a second end of the second pseudo-random switch is grounded, a second end of the first pseudo-random switch is connected with the reference voltage, a second end of the third pseudo-random switch is grounded, and a second end of the fourth pseudo-random switch is connected with the reference voltage;
the first conversion control switch, the second conversion control switch, the third conversion control switch, the fourth conversion control switch and the forward sampling switch act synchronously; the reverse output switch and the reverse sampling switch act synchronously;
the first pseudo-random switch, the second pseudo-random switch, the third pseudo-random switch and the fourth pseudo-random switch are used for adding pseudo-random numbers at the output end of the integrating circuit so as to sum up the integrated input voltage and the pseudo-random numbers, and the mean value of the pseudo-random numbers is 0.
2. The analog-to-digital conversion device of claim 1, wherein the integrator comprises a first integrating capacitor, a second integrating capacitor, and an amplifier;
the first end of the first integrating capacitor is connected with the positive input end of the amplifier, and the second end of the first integrating capacitor is connected with the negative output end of the amplifier; the first end of the second integrating capacitor is connected with the input negative end of the amplifier, and the second end of the second integrating capacitor is connected with the output positive end of the amplifier;
the input positive end and the input negative end of the amplifier are input ends of the integrator, and the amplifier is used for integrating the voltage sampled by the forward sampling capacitor and the reverse sampling capacitor and outputting the integrated input voltage when the forward sampling or the reverse sampling is carried out on the input voltage of the analog quantity.
3. The analog-to-digital conversion apparatus of claim 1, wherein an input terminal of the quantizer is connected to a second terminal of the third conversion control switch, and an output terminal thereof outputs the digital quantity signal.
4. The analog-to-digital conversion apparatus of claim 3, further comprising:
and the output end of the digital filter is connected with the output end of the quantizer and is used for filtering the digital quantity signal.
5. The analog-to-digital conversion apparatus of claim 3, further comprising:
and the phase inverter is used for performing phase inversion processing on the digital quantity signal, and the input end of the phase inverter is connected with the output end of the quantizer, and the output end of the phase inverter is connected with the control ends of the first digital inverse feedback switch and the second digital inverse feedback switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210631941.XA CN114710156B (en) | 2022-06-07 | 2022-06-07 | Analog-digital conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210631941.XA CN114710156B (en) | 2022-06-07 | 2022-06-07 | Analog-digital conversion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114710156A CN114710156A (en) | 2022-07-05 |
| CN114710156B true CN114710156B (en) | 2022-10-04 |
Family
ID=82177766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210631941.XA Active CN114710156B (en) | 2022-06-07 | 2022-06-07 | Analog-digital conversion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114710156B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972705B1 (en) * | 2004-12-14 | 2005-12-06 | Cirrus Logic, Inc. | Signal processing system having an ADC delta-sigma modulator with single-ended input and feedback signal inputs |
| CN105027433A (en) * | 2013-01-15 | 2015-11-04 | 美商楼氏电子有限公司 | Telescopic op-amp with slew rate control |
| CN109787633A (en) * | 2018-12-24 | 2019-05-21 | 哈尔滨工程大学 | The Σ Δ ADC suitable for mixed type ADC structure with chopped wave stabilizing |
| CN114095030A (en) * | 2021-10-14 | 2022-02-25 | 中国兵器工业集团第二一四研究所苏州研发中心 | Sigma-delta ADC (analog to digital converter) for fully-differential chord tone elimination |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7084799B1 (en) * | 2005-05-09 | 2006-08-01 | Sls International, Inc. | Sigma-delta modulated amplifier |
| CN111490787B (en) * | 2019-01-29 | 2023-07-21 | 江苏润石科技有限公司 | Sigma-delta modulator and method for reducing nonlinearity and gain error |
-
2022
- 2022-06-07 CN CN202210631941.XA patent/CN114710156B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972705B1 (en) * | 2004-12-14 | 2005-12-06 | Cirrus Logic, Inc. | Signal processing system having an ADC delta-sigma modulator with single-ended input and feedback signal inputs |
| CN105027433A (en) * | 2013-01-15 | 2015-11-04 | 美商楼氏电子有限公司 | Telescopic op-amp with slew rate control |
| CN109787633A (en) * | 2018-12-24 | 2019-05-21 | 哈尔滨工程大学 | The Σ Δ ADC suitable for mixed type ADC structure with chopped wave stabilizing |
| CN114095030A (en) * | 2021-10-14 | 2022-02-25 | 中国兵器工业集团第二一四研究所苏州研发中心 | Sigma-delta ADC (analog to digital converter) for fully-differential chord tone elimination |
Non-Patent Citations (2)
| Title |
|---|
| A CT 2–2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction;M. Fukazawa等;《IEEE Journal of Solid-State Circuits》;20210610;2943-2955 * |
| 基于Sigma-Delta调制器的小数分频锁相环研究与设计;高君益;《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》;20211215;I136-38 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114710156A (en) | 2022-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5495200A (en) | Double sampled biquad switched capacitor filter | |
| US5030954A (en) | Double rate oversampled interpolative modulators for analog-to-digital conversion | |
| US5416481A (en) | Analog-to-digital converter with multi-level dither current input | |
| JP3245113B2 (en) | Sampling, down-conversion and digitization of bandpass signals using digital predictive coder | |
| JP2001517014A5 (en) | ||
| US7388533B2 (en) | Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor | |
| US20060132341A1 (en) | Systems and methods for mismatch cancellation in switched capacitor circuits | |
| GB2425416A (en) | Switched capacitor DAC | |
| US6184811B1 (en) | Double-sampled ΣΔ modulator of second order having a semi-bilinear architecture | |
| US7916054B2 (en) | K-delta-1-sigma modulator | |
| JP4662826B2 (en) | Switch control circuit, ΔΣ modulation circuit, and ΔΣ modulation AD converter | |
| US6137431A (en) | Oversampled pipeline A/D converter with mismatch shaping | |
| CN112865798B (en) | Noise shaping successive approximation analog-to-digital converter and noise shaping method | |
| CN111669177B (en) | Analog-to-digital converter | |
| KR102499229B1 (en) | High-linearity sigma-delta converter | |
| Brewer et al. | A 100dB SNR 2.5 MS/s output data rate/spl Delta//spl Sigma/ADC | |
| CN113315522B (en) | 24-bit low-distortion Sigma-Delta analog-to-digital converter | |
| CN114710156B (en) | Analog-digital conversion device | |
| US20020000927A1 (en) | A circuit device for cancelling out spurious pulses in a switched capacitance low-pass filter, and a filter incorporating it | |
| JPH04243326A (en) | Oversampling d/a converter | |
| CN111510082B (en) | High-resolution gain-adjustable low-noise switched capacitor amplifier and design method thereof | |
| KR20190021634A (en) | Discrete-time integrator circuit with operational amplifier gain compensation function | |
| US11115042B1 (en) | Low pass filter embedded digital-to-analog converter | |
| Tang et al. | A 108-dB SNDR 2–1 MASH $\Delta\Sigma $ Modulator with First-Stage Multibit for Audio Application | |
| JPH07143006A (en) | Delta sigma type a/d converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |