CN114710151A - Charge pump phase-locked loop - Google Patents

Charge pump phase-locked loop Download PDF

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Publication number
CN114710151A
CN114710151A CN202210377733.1A CN202210377733A CN114710151A CN 114710151 A CN114710151 A CN 114710151A CN 202210377733 A CN202210377733 A CN 202210377733A CN 114710151 A CN114710151 A CN 114710151A
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China
Prior art keywords
charge pump
module
delay
output end
phase
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Chinese (zh)
Inventor
周玉梅
何远慧
乔树山
尚德龙
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Zhongke Nanjing Intelligent Technology Research Institute
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Zhongke Nanjing Intelligent Technology Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

The invention relates to a charge pump phase-locked loop, and belongs to the technical field of phase-locked loop circuit structures. In the charge pump phase-locked loop provided by the invention, in the locking process, the phase error between the reference signal and the feedback signal is identified by the phase frequency detector module, the charge and discharge of the charge pump module are controlled by the phase error information, the output signal is further controlled, and after the output signal is input to the pressure cavity oscillator module, the control of signal output frequency is realized, so that the control of the charge and discharge of the charge pump by the error information can be effectively accelerated, the output frequency of the pressure cavity oscillator module can be adjusted more quickly, the error elimination speed of the phase or frequency between the feedback signal and the reference signal is accelerated, and the locking process of the charge pump phase-locked loop is accelerated. In addition, the flexibility and configurability of the charge pump phase-locked loop can be greatly improved by adjusting the delay signals in the delay module and the frequency detection module, meanwhile, the power consumption is saved, and unnecessary power consumption waste is avoided.

Description

Charge pump phase-locked loop
Technical Field
The invention relates to the technical field of phase-locked loop circuit structures, in particular to a charge pump phase-locked loop.
Background
The phase-locked loop is a key component of the SoC chip and mainly functions to provide clocks meeting requirements of different subsystems. For example, the method is applied to a low frequency Double Data Rate (DDR) synchronous dynamic random access memory. The performance of the phase-locked loop determines the working stability of the whole system and the quality of each index. Therefore, the pll needs to respond rapidly and correctly to unpredictable phase fluctuations and transient overshoots, and the research on fast-locking plls is very necessary.
Therefore, it is an urgent technical problem to be solved in the art to provide a phase-locked loop having the advantages of fast locking speed, high flexibility, power consumption saving, and the like.
Disclosure of Invention
In view of the technical problems in the prior art, the present invention provides a charge pump phase-locked loop.
In order to achieve the purpose, the invention provides the following scheme:
a charge pump phase locked loop comprising: the device comprises a phase frequency detector module, a charge pump module, a delay module, a filter module, a pressure cavity oscillator module, a frequency detection module and a frequency divider module;
a first output end of the phase frequency detector module is respectively connected with a first input end of the charge pump module and a first input end of the delay module; a second output end of the phase frequency detector module is respectively connected with a second input end of the charge pump module and a second input end of the delay module; the first output end of the delay module is connected with the third input end of the charge pump module; the second output end of the delay module is connected with the fourth input end of the charge pump module; the output end of the charge pump module is connected with the input end of the filter module; the output end of the filter module is connected with the input end of the pressure cavity oscillator module; the output end of the pressure cavity oscillator module is respectively connected with the input end of the frequency detection module and the input end of the frequency divider module; the output end of the frequency detection module is connected with the fifth input end of the charge pump module; the output end of the frequency divider module is connected with the second input end of the phase frequency detector module; and a first input end of the phase frequency detector module is a signal receiving end.
Preferably, the charge pump module includes: a first charge pump unit, a second charge pump unit and a third charge pump unit;
a first output end of the phase frequency detector module is connected with a first input end of the first charge pump unit; a second output end of the phase frequency detector module is connected with a second input end of the first charge pump unit; the first output end of the delay module is connected with the first input end of the second charge pump module; the second output end of the delay module is connected with the second input end of the second charge pump module; the output end of the frequency detection module is connected with the input end of the third charge pump module; the output end of the first charge pump unit, the output end of the second charge pump unit and the output end of the third charge pump unit are connected with the input end of the filter module.
Preferably, the first charge pump unit and the second charge pump unit each include a PMOS transistor, a first switch, a second switch, and an NMOS transistor connected in series in sequence;
a first output end of the phase frequency detector module is connected with a first switch in the first charge pump unit; a second output end of the phase frequency detector module is connected with a second switch in the first charge pump unit;
a first output end of the delay module is connected with a first switch in the second charge pump unit; the second output terminal of the delay module is connected to the second switch in the second charge pump unit.
Preferably, the third charge pump unit block comprises an NMOS tube, a third switch, a fourth switch and an NMOS tube which are connected in series in sequence;
and the output end of the frequency detection module is connected with the third switch.
Preferably, the delay module includes a first delay unit and a second delay unit;
the input end of the first delay unit is connected with the first output end of the phase frequency detector module; the output end of the first delay unit is connected with the first input end of the second charge pump unit; the input end of the second delay unit is connected with the second output end of the phase frequency detector module; the output end of the second delay unit is connected with the second input end of the second charge pump unit.
Preferably, the first delay unit and the second delay unit each include a delay subunit and an and gate.
Preferably, in the first delay unit, an input end of the delay subunit and a first input end of the and gate are both connected to a first output end of the phase frequency detector module, an output end of the delay subunit is connected to a second input end of the and gate, and an output end of the and gate is connected to a first input end of the second charge pump unit;
preferably, in the second delay unit, an input end of the delay subunit and a first input end of the and gate are both connected to a second output end of the phase frequency detector module, an output end of the delay subunit is connected to a second input end of the and gate, and an output end of the and gate is connected to a second input end of the second charge pump unit.
Preferably, the frequency detection module includes: the circuit comprises a first trigger, a first inverter, a second trigger, a second inverter and a delay chain;
the input end of the first trigger is connected with the output end of the pressure cavity oscillator module; the output end of the first trigger is connected with the input end of the first inverter; the output end of the first inverter is connected with the first input end of the second trigger; the output end of the second trigger is connected with the input end of the second inverter; the output end of the second inverter is connected with the fifth input end of the charge pump module; the input end of the delay chain is connected with the output end of the first trigger; the output end of the delay chain is connected with the second input end of the second trigger.
Preferably, the filter module comprises: a first capacitor, a resistor and a second capacitor;
one end of the resistor and one end of the second capacitor are both connected with the output end of the charge pump module; the other end of the resistor is connected with one end of the first capacitor; the other end of the second capacitor and the other end of the first capacitor are both grounded.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
in the charge pump phase-locked loop provided by the invention, in the locking process, the phase error between the reference signal and the feedback signal is identified by the phase frequency detector module, the charge and discharge of the charge pump module are controlled by the phase error information, the output signal is further controlled, and after the output signal is input to the pressure cavity oscillator module, the control of signal output frequency is realized, so that the control of the charge and discharge of the charge pump by the error information can be effectively accelerated, the output frequency of the pressure cavity oscillator module can be adjusted more quickly, the error elimination speed of the phase or frequency between the feedback signal and the reference signal is accelerated, and the locking process of the charge pump phase-locked loop is accelerated. Moreover, by adjusting the delay signals in the delay module and the frequency detection module, the flexibility and configurability of the charge pump phase-locked loop can be greatly improved, the power consumption is saved, and unnecessary power consumption waste is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic diagram of a charge pump phase-locked loop according to the present invention;
fig. 2 is a schematic structural diagram of a frequency detection module according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating lock-in time simulation provided by an embodiment of the present invention;
fig. 4 is a diagram of Vctrl analysis according to an embodiment of the present invention.
Description of the symbols:
the phase frequency detector comprises a phase frequency detector module 1, a charge pump module 2, a first charge pump unit 2-1, a second charge pump unit 2-2, a third charge pump unit 2-3, a delay module 3, a first delay unit 3-1, a second delay unit 3-2, a filter module 4, a cavity oscillator module 5, a frequency detection module 6, a first trigger 6-1, a first phase inverter 6-2, a second trigger 6-3, a second phase inverter 6-4, a delay chain 6-5 and a frequency divider module 7.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a charge pump phase-locked loop with the advantages of high locking speed, strong flexibility, power consumption saving and the like, so that the control of error information on the charge pump charging and discharging can be effectively accelerated, the output frequency of a VCO (voltage controlled oscillator) can be adjusted more quickly, the elimination of errors of phases or frequencies of a feedback signal and a reference signal is accelerated, and the locking process of the charge pump phase-locked loop is accelerated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, the charge pump phase locked loop provided by the present invention includes: the phase frequency detector comprises a phase frequency detector module 1, a charge pump module 2, a delay module 3, a filter module 4, a pressure cavity oscillator module 5, a frequency detection module 6 and a frequency divider module 7.
A first output end of the phase frequency detector module 1 is connected to a first input end of the charge pump module 2 and a first input end of the delay module 3, respectively. A second output end of the phase frequency detector module 1 is connected with a second input end of the charge pump module 2 and a second input end of the delay module 3 respectively. A first output of the delay module 3 is connected to a third input of the charge pump module 2. A second output of the delay module 3 is connected to a fourth input of the charge pump module 2. The output of the charge pump module 2 is connected to the input of the filter module 4. The output end of the filter module 4 is connected with the input end of the pressure cavity oscillator module 5. The output end of the pressure cavity oscillator module 5 is respectively connected with the input end of the frequency detection module 6 and the input end of the frequency divider module 7. The output end of the frequency detection module 6 is connected with the fifth input end of the charge pump module 2. The output end of the frequency divider module 7 is connected with the second input end of the phase frequency detector module 1. A first input end of the phase frequency detector module 1 is a signal receiving end.
Wherein, the charge pump module 2 includes: a first charge pump unit 2-1, a second charge pump unit 2-2 and a third charge pump unit 2-3.
A first output end of the phase frequency detector module 1 is connected with a first input end of the first charge pump unit 2-1. A second output end of the phase frequency detector module 1 is connected with a second input end of the first charge pump unit 2-1. A first output of the delay module 3 is connected to a first input of the second charge pump module 2. A second output of the delay module 3 is connected to a second input of the second charge pump module 2. The output end of the frequency detection module 6 is connected with the input end of the third charge pump module 2. The output end of the first charge pump unit 2-1, the output end of the second charge pump unit 2-2 and the output end of the third charge pump unit 2-3 are all connected with the input end of the filter module 4.
In order to realize accurate control of the discharge time, the control principles of the three charge pump units are basically the same, but the structure of the third charge pump unit 2-3 is different from that of the first charge pump unit 2-1 and the second charge pump unit 2-2, specifically: the first charge pump unit 2-1 and the second charge pump unit 2-2 both comprise a PMOS tube, a first switch, a second switch and an NMOS tube which are sequentially connected in series. A first output terminal of the phase frequency detector module 1 is connected to a first switch in the first charge pump unit 2-1. A second output end of the phase frequency detector module 1 is connected with a second switch in the first charge pump unit 2-1. A first output of the delay block 3 is connected to a first switch in the second charge pump unit 2-2. A second output of the delay block 3 is connected to a second switch in the second charge pump unit 2-2. The third charge pump unit 2-3 comprises an NMOS tube, a third switch, a fourth switch and an NMOS tube which are sequentially connected in series. The output end of the frequency detection module 6 is connected with the third switch.
The first charge pump unit 2-1 and the second charge pump unit 2-2 adopt drain switch charge pumps, the upper and lower switches are respectively a PMOS and an NMOS, when a control signal of the PMOS switch is low, the switch is closed, and when the control signal of the PMOS switch is high, the switch is opened. When the control signal of the NMOS switch is high, the switch is closed, and when the control signal of the NMOS switch is low, the switch is opened. Different from the first charge pump unit 2-1 and the second charge pump unit 2-2, the third charge pump unit 2-3 adopts an NMOS switch type charge pump, the upper and lower switches are both NMOS, and the switch is closed if the control signal of the switch is high level, and is opened if the control signal of the switch is low level.
In order to enable accurate control of the phase locked loop, the present invention employs a delay block 3 comprising a first delay unit 3-1 and a second delay unit 3-2.
The input end of the first delay unit 3-1 is connected with the first output end of the phase frequency detector module 1. The output of the first delay unit 3-1 is connected to a first input of the second charge pump unit 2-2. The input end of the second delay unit 3-2 is connected with the second output end of the phase frequency detector module 1. The output of the second delay unit 3-2 is connected to a second input of the second charge pump unit 2-2.
The first delay unit 3-1 and the second delay unit 3-2 both comprise a delay subunit and an and gate. In the first delay unit 3-1, the input end of the delay subunit and the first input end of the and gate are both connected to the first output end of the phase frequency detector module 1, the output end of the delay subunit is connected to the second input end of the and gate, and the output end of the and gate is connected to the first input end of the second charge pump unit 2-2. In the second delay unit 3-2, the input end of the delay subunit and the first input end of the and gate are both connected to the second output end of the phase frequency detector module 1, the output end of the delay subunit is connected to the second input end of the and gate, and the output end of the and gate is connected to the second input end of the second charge pump unit 2-2.
Further, as shown in fig. 2, the frequency detection module 6 provided by the present invention includes: a first flip-flop 6-1, a first inverter 6-2, a second flip-flop 6-3, a second inverter 6-4 and a delay chain 6-5.
The input end of the first trigger 6-1 is connected with the output end of the pressure cavity oscillator module 5. The output of the first flip-flop 6-1 is connected to the input of the first inverter 6-2. The output of the first inverter 6-2 is connected to a first input of a second flip-flop 6-3. The output of the second flip-flop 6-3 is connected to the input of the second inverter 6-4. The output of the second inverter 6-4 is connected to the fifth input of the charge pump module 2. The input of the delay chain 6-5 is connected to the output of the first flip-flop 6-1. The output of the delay chain 6-5 is connected to a second input of the second flip-flop 6-3.
The frequency detection module 6 having the above-described structure functions to detect the output frequency CLK of the cavity oscillator module 5OUTAnd the difference value of the frequency of the delay chain 6-5 enables the third charge pump unit 2-3 to work from power-on, the rising of the output signal Vctrl is accelerated until the output frequency of the cavity oscillator module 5 rises to be 2 times of the frequency of the delay chain 6-5, and the third charge pump unit 2-3 is disconnected, so that the locking speed of the phase-locked loop is accelerated.
The input of the frequency detection module 6 is a signal CLKOUTOutput is a signal FOUT. The inputs D and CLK of the first flip-flop 6-1 are connected to the output QN of the first flip-flop 6-1 and the output CLK of the cavity oscillator module 5, respectivelyOUTAt this time, the other output Q of the first flip-flop 6-1 has a frequency CLKOUTHalf the frequency. Q outputs signals CLK _1 and CLK _2 after passing through a first inverter 6-2 and a delay chain 6-5, the signals CLK _1 and CLK _2 are respectively connected with the input D and CLK of a second flip-flop 6-3, the output Q of the first flip-flop 6-1 is connected with the output F of the second inverter 6-4OUT。
Based on this structure, the working principle of the frequency detection module 6 is as follows:
the delay chain 6-5, which is a key part of the frequency detection module 6 and whose delay corresponds to the frequency of the input signal CLKOUTThe working process can be divided into two parts by comparing the sizes of the two parts. The first part is that when the phase-locked loop circuit is just started, the output signal Vctrl is not fast enough to rise, and the output signal Vctrl is small, so that the frequency of the cavity oscillator module 5 is small, and at this time, the input signal CLK is smallOUTIs less than the frequency of the delay chain 6-5, the input signal CLKOUTAfter the frequency of the first flip-flop 6-1, the frequency of the output Q of the first flip-flop 6-1 is CLKOUTHalf of the frequency, the signal Q generates the signals CLK _1 and CLK _2 after passing through the first inverter 6-2 and the delay chain 6-5, the signals CLK _1 and CLK _2 are used as the inputs D and CLK of the second flip-flop 6-3, because the signal CLK _1 sampled by the sampling signal CLK _2 of the second flip-flop 6-3 at the rising edge is always low, the output Q of the second flip-flop 6-3 always remains low, and the output F after the Q passes through the second inverter 6-4OUT，FOUTAlways remains high. Due to FOUTKeeping high at all times, switch S of third charge pump unit 2-35Under the control of high level, the circuit is always in a closed state, and the signal I is in the closed stateCP3For signal ICPCharging, signal ICPAfter the increase, the output signal Vctrl rises after passing through the filter module 4, and the output frequency CLK of the cavity oscillator module 5OUTAnd is increased. Up to the output frequency CLK of the cavity oscillator module 5OUTWhen the frequency is increased to 2 times the corresponding frequency of the delay chain 6-5, the operation state of the frequency detection module 6 enters the second part.
The second part is as follows: when the output frequency CLK of the cavity oscillator module 5OUTWhen the frequency of the signal CLK _1 and CLK _2 is increased to 2 times of the corresponding frequency of the delay chain 6-5, the signals CLK _1 and CLK _2 are used as the input D and CLK of the second flip-flop 6-3, because the signal CLK _1 sampled by the sampling signal CLK _2 of the second flip-flop 6-3 at the rising edge is always high, the output Q of the second flip-flop 6-3 always keeps high, and Q outputs F after passing through the second inverter 6-4OUT，FOUTAlways remains low. Due to FOUTAlways kept low, thirdSwitch S of charge pump unit 2-35Under the control of the low level, the third charge pump unit 2-3 is always in the off state and stops working at this time.
As can be seen from the working principle of the frequency detection module 6, the module has great flexibility, and the working time of the third charge pump units 2-3 can be controlled according to the magnitude of the delay, so as to adjust the locking time.
Further, the filter module 4 employed comprises: a first capacitor, a resistor and a second capacitor.
One end of the resistor and one end of the second capacitor are both connected with the output end of the charge pump module 2. The other end of the resistor is connected with one end of the first capacitor. The other end of the second capacitor and the other end of the first capacitor are both grounded.
Based on the above description, the present invention uses the first charge pump unit 2-1 as a fine-tuning charge pump, and is in an operating state until the phase-locked loop does not complete the locking operation. As shown in FIG. 1, the first charge pump unit 2-1 has an UP signal and a DN signal as inputs and an I signal as an outputCP1A signal. The UP signal and the DN signal each control a first switch S of the first charge pump unit 2-11And a second switch S2To control the charging and discharging time if the first switch S1Closing the second switch S2Switching off the charging current source I of the first charge pump unit 2-1UPTo ICP1Charging, thereby ICP1And (4) rising. If the first switch S1The second switch S is turned off2Closed, the first charge pump unit 2-1 passes through the discharge current source IDNTo ICP1Discharge thereby ICP1And (4) descending.
The second charge pump unit 2-2 is used as a coarse charge pump, as shown in fig. 1, only at FDIVSum of signals FREFThe frequency or phase error of the signal being greater than the delay taueThe second charge pump unit 2-2 is operated until the signal FDIVAnd FREFError of less than τeThereafter, the second charge pump unit 2-2 stops operating. The input signals of the second charge pump unit 2-2 are UPN and DNN, and the output signal is ICP2. UPN and DNN GenerationThe UP and DN signals are generated by a delay module 3, and the delay module 3 is used for respectively processing the UP and DN signals by taueThe delay outputs UPN and DNN, the UPN and DNN are used for controlling the coarse tuning charge switch, and the coarse tuning charge pump and the fine tuning charge pump play a role in controlling the coarse tuning charge pump and the fine tuning charge pump when the phase error is larger than taueIn the case of (2) and simultaneously, thereby accelerating the locking process.
In the setting process, the time for turning on the third charge pump unit 2-3 is synchronized with the phase-locked loop circuit until the output frequency CLK of the voltage cavity oscillator moduleOUTRising to twice the frequency corresponding to the delay chain 6-5 in the frequency detection module 6, the third charge pump unit 2-3 stops operating. The input of the third charge pump unit 2-3 is the output signal F of the frequency detection module 6OUTOutput signal FOUTControl switch S5(i.e. third switch) opening or closing, switch S6(i.e. the fourth switch) is always in an off state, and the output is ICP3A signal.
The third charge pump unit 2-3 is arranged to switch S on the pll circuit when it is first activated5Is closed so that signal ICP3And signal ICP1、ICP2Together form ICPAnd further increase the signal ICPSignal ICPAfter passing through the filter module 4, the output signal Vctrl increases, and the output frequency CLK of the cavity oscillator module is then increasedOUTThe final result is that the output signal Vctrl can be quickly adjusted to a certain value due to the action of the third charge pump units 2-3, the increasing time of the output signal Vctrl is reduced, and the locking process is accelerated. Meanwhile, due to the delay chain in the frequency detection module 6, the working time of the third charge pump units 2-3 can be adjusted by adjusting the delay size, so that the locking acceleration degree can be selected, and the flexibility of the whole circuit is improved.
Based on this, the working principle of the obtained phase-locked loop is as follows:
discrimination signal F of frequency and phase discriminator module 1DIVSum signal FREFUP and DN to control the switch S, respectively1And switch S2Is opened and closed, and further controlsTime of charging and discharging, if switch S1Closing switch S2Is disconnected, the first charge pump unit 2-1 passes through the charging current source IUPTo ICP1Charging, thereby ICP1And (4) rising. If switch S1Disconnect switch S2Closed, the first charge pump unit 2-1 passes through the discharge current source IDNTo ICP1Discharge thereby ICP1And (4) descending. First charge pump unit 2-1 output ICP1. The working principle of the three charge pumps is the same, and the operation can be repeated.
At the same time, UPN and DNN control the switch S of the second charge pump unit 2-2, respectively3Switch S4To control the charging and discharging time, the second charge pump unit 2-2 outputs ICP2. Switch S of the third charge pump unit 2-36Kept always open, the switch S of the third charge pump unit 2-35The open or closed state being determined by the output F of the frequency detection module 6OUTControl the third charge pump unit 2-3 to output ICP3。ICP1，ICP2And ICP3The additive output is ICP。ICPAs input to the filter module 4, an output Vctrl of the filter module 4 is generated, which controls the output CLK of the cavity oscillator module 5OUTOutput CLKOUTRespectively input into the frequency detection module 6 and the frequency divider module 7, and the frequency detection module 6 outputs FOUTSignal FOUTSwitch S input to third charge pump unit 2-35The frequency divider module 7 outputs a signal FDIV。FDIVAnd FREFThe two signals pass through the above process again to carry out phase error identification and adjustment until FDIVAnd FREFThe phase locked loop works when the frequency and phase errors of the two signals cancel or a fixed phase error, such as 100ps, exists.
The three charge pump modules in the phase-locked loop design have the same principle, but have different functions and input signals, and are not described again. The experimental results of the charge pump phase-locked loop provided by the invention are shown in fig. 3 and 4.
From the simulation results shown in fig. 3 and fig. 4, the time for the signal Vctrl to start to become stable is 4us, the locking time is 4us, and the signal Vctrl rises faster in 0.5us, which achieves the effects that the Vctrl described by the charge pump rises faster in the initial stage of the charge pump power-on, and the locking time is shorter.
Based on the above description, the charge pump phase-locked loop provided by the present invention has the following advantages over the prior art:
1. compared with the traditional phase-locked loop circuit, the charge pump phase-locked loop designed by the invention is additionally provided with a coarse charge pump (namely a second charge pump unit) and a third charge pump unit, and the output I of the two charge pump unitsCP2And ICP3Is injected into ICPIn ICP1On the basis of increasing or decreasing ICPAfter passing through the filter module, the generated output signal is also increased or reduced, and the output frequency of the cavity oscillator module is also correspondingly increased or reduced, so that the process of adjusting the frequency or phase error between the input signals is greatly accelerated, and the frequency locking process of the charge pump phase-locked loop is further accelerated.
2. In the charge pump phase-locked loop designed by the invention, the working time of the second charge pump unit is shortened by the delay tau in the delay moduleeDetermining that only if the phase error between the inputs is greater than the delay τeThe second charge pump unit is only operated to be able to increase or decrease the delay taueTo correspondingly decrease or increase the operating time of the second charge pump unit. The length of the working time of the third charge pump unit is determined by the delay size of the delay chain, and the working time of the third charge pump unit can be correspondingly reduced or increased by increasing or reducing the delay of the delay chain. Therefore, the working states of the second and third charge pump units can be adjusted by adjusting the delay taueAnd the delay chain is flexibly controlled, so that the flexibility and configurability of the charge pump phase-locked loop are greatly improved, the power consumption is saved, and unnecessary power consumption waste is avoided.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the foregoing, the description is not to be taken in a limiting sense.

Claims (10)

1. A charge pump phase locked loop, comprising: the device comprises a phase frequency detector module, a charge pump module, a delay module, a filter module, a pressure cavity oscillator module, a frequency detection module and a frequency divider module;
a first output end of the phase frequency detector module is respectively connected with a first input end of the charge pump module and a first input end of the delay module; a second output end of the phase frequency detector module is respectively connected with a second input end of the charge pump module and a second input end of the delay module; the first output end of the delay module is connected with the third input end of the charge pump module; the second output end of the delay module is connected with the fourth input end of the charge pump module; the output end of the charge pump module is connected with the input end of the filter module; the output end of the filter module is connected with the input end of the pressure cavity oscillator module; the output end of the pressure cavity oscillator module is respectively connected with the input end of the frequency detection module and the input end of the frequency divider module; the output end of the frequency detection module is connected with the fifth input end of the charge pump module; the output end of the frequency divider module is connected with the second input end of the phase frequency detector module; the first input end of the phase frequency detector module is a signal receiving end.
2. The charge pump phase locked loop of claim 1, wherein the charge pump module comprises: a first charge pump unit, a second charge pump unit and a third charge pump unit;
a first output end of the phase frequency detector module is connected with a first input end of the first charge pump unit; a second output end of the phase frequency detector module is connected with a second input end of the first charge pump unit; the first output end of the delay module is connected with the first input end of the second charge pump module; the second output end of the delay module is connected with the second input end of the second charge pump module; the output end of the frequency detection module is connected with the input end of the third charge pump module; the output end of the first charge pump unit, the output end of the second charge pump unit and the output end of the third charge pump unit are all connected with the input end of the filter module.
3. The charge pump phase locked loop of claim 2 wherein the first charge pump unit and the second charge pump unit each comprise a PMOS transistor, a first switch, a second switch, and an NMOS transistor connected in series in that order;
a first output end of the phase frequency detector module is connected with a first switch in the first charge pump unit; a second output end of the phase frequency detector module is connected with a second switch in the first charge pump unit;
a first output end of the delay module is connected with a first switch in the second charge pump unit; the second output terminal of the delay module is connected to the second switch in the second charge pump unit.
4. The charge pump phase-locked loop of claim 2, wherein the third charge pump unit comprises an NMOS transistor, a third switch, a fourth switch and an NMOS transistor connected in series in sequence;
and the output end of the frequency detection module is connected with the third switch.
5. The charge pump phase locked loop of claim 2 wherein the delay module comprises a first delay cell and a second delay cell;
the input end of the first delay unit is connected with the first output end of the phase frequency detector module; the output end of the first delay unit is connected with the first input end of the second charge pump unit; the input end of the second delay unit is connected with the second output end of the phase frequency detector module; the output end of the second delay unit is connected with the second input end of the second charge pump unit.
6. The charge pump phase locked loop of claim 5 wherein the first delay cell and the second delay cell each comprise a delay sub-cell and an AND gate.
7. The charge pump phase locked loop of claim 6 wherein in the first delay unit, the input terminal of the delay subunit and the first input terminal of the AND gate are both connected to the first output terminal of the phase frequency detector module, the output terminal of the delay subunit is connected to the second input terminal of the AND gate, and the output terminal of the AND gate is connected to the first input terminal of the second charge pump unit.
8. The charge pump phase locked loop of claim 6 wherein in the second delay unit, the input terminal of the delay subunit and the first input terminal of the AND gate are both connected to the second output terminal of the phase frequency detector module, the output terminal of the delay subunit is connected to the second input terminal of the AND gate, and the output terminal of the AND gate is connected to the second input terminal of the second charge pump unit.
9. The charge pump phase locked loop of claim 1, wherein the frequency detection module comprises: the circuit comprises a first trigger, a first inverter, a second trigger, a second inverter and a delay chain;
the input end of the first trigger is connected with the output end of the pressure cavity oscillator module; the output end of the first trigger is connected with the input end of the first inverter; the output end of the first inverter is connected with the first input end of the second trigger; the output end of the second trigger is connected with the input end of the second inverter; the output end of the second inverter is connected with the fifth input end of the charge pump module; the input end of the delay chain is connected with the output end of the first trigger; the output end of the delay chain is connected with the second input end of the second trigger.
10. The charge pump phase locked loop of claim 1 wherein the filter module comprises: a first capacitor, a resistor and a second capacitor;
one end of the resistor and one end of the second capacitor are both connected with the output end of the charge pump module; the other end of the resistor is connected with one end of the first capacitor; the other end of the second capacitor and the other end of the first capacitor are both grounded.
CN202210377733.1A 2022-04-12 2022-04-12 Charge pump phase-locked loop Pending CN114710151A (en)

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