CN114710139B - Harmonic extraction and synthesizer of APF control system - Google Patents
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Abstract
The invention relates to the technical field of digital signal processing of a power electronic control circuit and the technical field of active power filter design, in particular to a harmonic wave extraction and synthesis device of an APF control system, which comprises a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module; the sampling data processing module stores the acquisition signal of the network side current into a data queue according to the time sequence, calculates the difference value x between the data entering the data queue for the nth time and the data sliding out, and outputs the difference value x to the rotation index module. By adopting an improved main control algorithm, the Sliding Discrete Fourier Transform (SDFT) is combined with the non-iterative discrete Fourier transform to complete harmonic extraction, so that the robustness and stability of the main control algorithm are improved; meanwhile, coordination control of all frequency components of the instruction current is realized based on quasi-proportional resonance control.
Description
Technical Field
The invention relates to the technical field of digital signal processing of a power electronic control circuit and the technical field of active power filter design, in particular to a harmonic extraction and synthesizer of an APF control system.
Background
The widespread use of power electronics has led to increased overall harmonic interference in power distribution systems, where nonlinear loads can absorb harmonic and reactive power components of current from ac power sources, and can also lead to imbalance in three-phase systems. An Active Power Filter (APF) can suppress harmonics while compensating reactive power by injecting a compensation current opposite to the harmonic current. The current response speed of the conventional APF current tracking control is low, and when the load current changes rapidly, the line current is affected by dynamic distortion, and the harmonic content in the line current is increased and the proportion of total harmonic distortion is increased due to the influence.
Disclosure of Invention
Aiming at the technical problems, the technical scheme provided by the invention improves and designs the core module of the three-phase parallel active power filter. By proposing a harmonic extraction and synthesizer of an APF control system, the harmonic extraction and synthesizer includes a recursive discrete fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores sampling signals of the network side current into a data queue according to time sequence, calculates a difference value delta x between data entering the data queue for the nth time and data sliding out of the data queue, and outputs the delta x to the rotation index module.
Further, the rotation index module includes: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module, a DFT inverse transformation and phase angle compensation sub-module; the rotation index module is configured to implement the steps comprising:
and after the timing control submodule receives the calculation completion signal of the sampling data processing module, the DFT data calculation is completed once in five continuous clock cycles.
Further, the DFT main calculation sub-module completes one DFT data calculation in each frequency unit; the DFT data computation includes SDFT computation.
Further, the DFT data computation may further comprise a non-iterative DFT computation.
The technical scheme provided by the invention has the advantages that the core module of the three-phase parallel active power filter is improved and designed, and the improved main control algorithm is adopted, so that the Sliding Discrete Fourier Transform (SDFT) is combined with the non-iterative discrete Fourier transform to complete the harmonic extraction, and the robustness and the stability of the main control algorithm are improved; meanwhile, coordination control of all frequency components of the instruction current is realized based on quasi-proportional resonance control.
Drawings
FIG. 1, a schematic diagram of a harmonic extraction and synthesizer of some embodiments;
FIG. 2, a block diagram of a DFT main computation module of some embodiments, where each identifier specifically represents: data_In, input sampling signal; cal_ready: completing the calculation signal; numaddress: a current calculation time point; data_new: the latest sampling signal; data_sub: a sliding sampling signal; k: harmonic frequency of current DFT operation; x is X k (n): nth data in DFT computation of K-th harmonic; x is X k (n-1): k times harmonicsN-1 st data in DFT calculation of wave; k1, k20: the 1 st and 20 th harmonics; fre_sel: the frequency of the harmonic wave needs to be compensated; x_out: outputting a signal; out_done: outputting a completion signal; rd_En: a read enable signal for the SDFT data storage RAM; wr_En: a write enable signal for the SDFT data storage RAM; rd_Q: a notification signal for finishing the reading of the SDFT data storage RAM data; rd_Add: a data read address of the SDFT data storage RAM; wr_Add: a data write address of the SDFT data storage RAM; xout_q: giving a subharmonic DFT completion signal; pi_rd: a read enable signal of the PR data storage module; pi_wr: a write enable signal of the PR data storage module; pi_q: a notification signal of the PR data storage module after the data reading is finished; j < 4 >. 0]: when the kth harmonic is calculated.
FIG. 3, a flow chart of a SDFT implementation method of some embodiments;
FIG. 4, a timing diagram of a timing control module of some embodiments, wherein each identifier specifically represents: clock_100M: a clock signal at a frequency of 100M; cal_ready: completing the calculation signal; rd_En: a read enable signal for the SDFT data storage RAM; rd_Q: a notification signal for finishing the reading of the SDFT data storage RAM data; wr_En: a write enable signal for the SDFT data storage RAM; pi_rd: a read enable signal of the PR data storage module; pi_wr: a write enable signal of the PR data storage module; pi_q: a notification signal of the PR data storage module after the data reading is finished; xout_q: the DFT completion signal is given.
Detailed Description
The APF control system of some embodiments comprises a harmonic extraction and synthesizer, a recursive discrete Fourier transform module, a Soft Digital Fourier Transform (SDFT) main control algorithm program and a rotating index module, wherein the module comprises a sampling data processing module and a rotating index module, and the specific module structure of each module is shown in figure 1;
the harmonic extraction and synthesizer comprises a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores the sampling signal of the network side current into a data queue according to time sequence, calculates the difference delta x between the data entering the data queue for the nth time and the data sliding out, and outputs the delta x to the rotation index module.
First, the SDFT (sliding discrete fourier) algorithm will be further described. From the definition of the fourier series, any periodic non-sinusoidal signal can be decomposed into a superposition of several periodic sinusoidal signals. The load current is a periodic nonstandard sine signal (containing harmonic waves), and the harmonic wave components of the load current can be obtained by expanding the load current through Fourier series.
The term "queue" refers to any linear table that allows only delete operations (slide out) at the front of the table, and insert operations (in) at the back of the table, in an embodiment as a sliding window data structure. The term "twiddle factor" refers to the complex constant multiplied by each term in the fourier series of the fourier transform, which lies above the unit circle in the complex plane, and is called twiddle factor for the effect of the multiplicand rotating above the complex plane.
The harmonic extraction and synthesizer of some preferred embodiments are realized based on FPGA, and parallel processing and pipeline operation are adopted, so that the method has the advantages of flexible logic unit, high integration level, wide application range and the like, and is suitable for separating fundamental wave and each subharmonic component of an error signal by fourier transform.
Some embodiments relate to a rotation index module that basically includes: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module, a DFT inverse transformation and phase angle compensation sub-module; each sub-module completes the following steps under the coordination of the time sequence control sub-module:
after receiving the calculation signal, the timing control submodule completes one time of DFT data calculation in five continuous clock cycles, and specifically comprises the following steps:
in a first clock period, the timing control sub-module outputs a reading enabling signal, and the DFT main calculation sub-module reads DFT data calculated last time from each subharmonic DFT data storage sub-module;
in the second clock period, the time sequence control sub-module outputs a read notification signal, and the DFT main calculation sub-module latches the DFT data calculated last time;
in the third and fourth clock cycles, the DFT main calculation module completes one DFT data calculation;
in a fifth clock period, the timing control module outputs a write-in enabling signal, the DFT main calculation module writes the DFT data calculated at the time into each subharmonic DFT data storage sub-module, and the DFT inverse conversion and the phase angle compensation module conduct DFT inverse conversion.
The twiddle index module of some embodiments further comprises a twiddle factor selection sub-module comprising a 1024 byte sine function table and a 1024 byte cosine function table; the twiddle factor selecting submodule calculates and outputs twiddle factors, and specifically comprises the following steps:
recording the remaining Nmod1024 of the time sequence N pairs 1024 of the current sampling signal;
and searching sine values and cosine values corresponding to Nmod1024 in the sine function table and the cosine function table respectively, and outputting the sine values and the cosine values which correspond to the twiddle factors after being unfolded by using an Euler formula.
Some embodiments relate to a DFT main computation sub-module that performs DFT data computation once per frequency unit; the DFT data calculation comprises SDFT calculation, and specifically comprises the following steps:
acquiring a twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value which correspond to the twiddle formula after being unfolded;
obtaining the difference of the sampling signals calculated at the present time;
multiplying the rotation factor by the difference of the sampling signals calculated at the present time, and accumulating the rotation factor with the SDFT data calculated by the last frequency unit to obtain the SDFT data of the current frequency unit;
and outputting the SDFT data of each frequency unit and maintaining the SDFT data to each subharmonic DFT data storage sub-module.
The DFT computation is completed once per frequency unit. The twiddle factor is outputted by the twiddle factor selection module through the Euler formula to develop complex factors into a trigonometric function form, and preferably, sine values and cosine values are respectively stored in a data queue.
The sliding window discrete fourier transform iterative calculation formula is formula I:
wherein, the liquid crystal display device comprises a liquid crystal display device,
as a twiddle factor, X (n) is a sampling signal of the nth network side current, X k (n) is the nth calculated DFT data, and k represents the corresponding harmonic order.
The harmonic extraction and synthesizer of some embodiments, the computation of the loading of the DFT main computation module further comprises non-iterative DFT computation, specifically comprising the following steps:
acquiring a twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value which correspond to the twiddle formula after being unfolded;
acquiring a current sampling signal x;
multiplying the rotation factor with x, and accumulating the rotation factor with non-iterative DFT data calculated by the last frequency unit to obtain non-iterative DFT data of the current frequency unit;
outputting non-iterative DFT data of each frequency unit and maintaining the non-iterative DFT data to each subharmonic DFT data storage sub-module;
each time after one sampling period, assigning non-iterative DFT data to the SDFT data, and zeroing the non-iterative DFT data of all frequency units of each subharmonic stored in each subharmonic DFT data storage sub-module.
It should be noted that if the DFT computation is performed by the SDFT method alone, an unstable problem is easily generated, so that an interactive update step is added, after a sampling period has elapsed, the value of the frequency unit calculated by the non-iterative DFT is updated to the value of the frequency unit corresponding to the DFT, and the value of the frequency unit of each subharmonic of the non-iterative DFT is zeroed.
In some embodiments, in the DFT main computation sub-module, the accumulated computation in the SDFT computation and the non-iterative DFT computation share one calculator.
Some embodiments relate to a rotation index module further comprising: a proportional resonance control regulator sub-module, a proportional resonance control regulator data storage sub-module, and a harmonic synthesis sub-module; the rotation index module is configured to implement the steps comprising: in a sixth clock period, the time sequence control sub-module outputs a proportional resonance control reading enabling signal, and reads an intermediate value calculated by the proportional resonance control regulator sub-module in a data storage unit of the proportional resonance control regulator sub-module;
in a seventh clock period, the time sequence control sub-module outputs a notification signal of the completion of data reading of the data storage unit of the proportional resonance control regulator sub-module, and then latches intermediate value data;
and after a plurality of clock cycles, the proportional resonance control regulator submodule outputs a reference signal to the harmonic synthesis submodule, and the calculation result is written into a data storage unit of the proportional resonance control regulator submodule.
The proportional resonance control regulator (PR) submodule of some embodiments employs a pre-modified Tustin transformation algorithm. Discretization of the control system is actually discretization of PR, and Tustin transformation can be adopted. However, the high-frequency characteristic of the conventional Tustin transform is severely distorted, and is not suitable for PR having a high resonance frequency. To ensure a linear relationship between the s-domain and z-domain of the controller frequency domain, a frequency pre-modified Tustin transformation algorithm may be used.
The term "proportional resonance control regulator (PR)" is composed of a proportional link and a resonance link, can realize no static difference control on the sine quantity, and an integration link in PR is also called a generalized integrator, and can realize amplitude integration on the sine quantity of the resonance frequency.
Preferably, all twiddle factors are quantized to Q15, and the multiplication is calculated by multiplying 16 bits first and 16 bits then taking the 16 bits high, i.e. dividing by 2 16 And then the calculated result is enlarged by 2 times.
It should be noted that Q15 represents that the decimal part has 15 bits, one short type data occupies 2 bytes, the highest bit is the sign bit, the latter 15 bits are the decimal places, and it is assumed that the decimal point is at the first15 bits to the left, the indicated range is: -1<X<0.9999695; conversion of floating point data to Q15, multiplying the data by 2 15 The method comprises the steps of carrying out a first treatment on the surface of the Conversion of Q15 data to floating point data, dividing the data by 2 15 。
In some implementations based on FPGA, since the mainstream FPGA cannot implement floating point number operation, in order to implement high-precision digital discretization of quasi-R control, quantization processing is required for coefficients of the differential equation, and floating point number operation is required for the quantized differential equation.
In some embodiments, the sample data processing module comprises the following steps based on a random access memory implementation:
the latest sampling signal is sent into a storage unit corresponding to a write address Wr_addr, data in the storage unit corresponding to a read address Rd_addr is output, and the read address always leads 1 to be positioned at the write address;
every 1024 signals are sampled consecutively as one sampling period, in each sampling period:
the data output by the random access memory each time is the last sampling signal, and the difference obtained by subtracting the last sampling signal from the latest sampling signal is δx;
outputting deltax obtained by each calculation and simultaneously outputting a calculation completion signal;
and performing overflow verification on delta x.
Random access memory enables the storage of data queues.
The sub-harmonic DFT data storage module of some embodiments is implemented based on four readable and writable dual-port random access memories; wherein each of the readable and writable dual-port random access memories is configured to:
each address corresponds to a frequency unit;
the first readable and writable dual-port random access memory is used for storing a twiddle factor sine value obtained by carrying out Euler transformation on twiddle factors in SDFT calculation;
the second readable and writable dual-port random access memory is used for storing a twiddle factor cosine value obtained by carrying out Euler transformation on twiddle factors in SDFT calculation;
the third readable and writable dual-port random access memory is used for storing a twiddle factor sine value obtained by carrying out Euler transformation on twiddle factors in non-iterative DFT calculation;
the fourth readable and writable dual-port random access memory is used for storing a twiddle factor cosine value obtained by carrying out Euler transformation on twiddle factors in non-iterative DFT calculation;
each readable and writable dual-port random access memory is provided with at least 20 memory cells, and for facilitating the later expansion, each readable and writable dual-port random access memory is configured with 25 memory cells.
The invention will be explained in more detail below with reference to specific embodiments. These embodiments use 3 identical harmonic extraction and synthesis modules, corresponding to the ABC three phases, respectively, and are described here by way of example only with the a phase. The module comprises a plurality of sub-modules, and the functions are shown in Table 1:
TABLE 1 submodule Functions
The core module in the above sub-module is DFT main calculation module, in the harmonic wave selection compensation module, K_1-K_20 represent 20 kinds of harmonic waves to be compensated, the number of harmonic wave times to be compensated is recorded in variables K_1-K_20 respectively, and the total number of harmonic wave types to be compensated is recorded in variable sel_K4.
SDFT sampling control module
The module is essentially a pulse match. The pulse notification signal for controlling the SDFT operation once is a narrow pulse with a width of 1/100Ms, but the externally input notification signal may have a width greater than 1/100Ms, so that pulse width matching is required to avoid repetitive operations. After the first detection of the DFT start operation signal, the next start signal is detected after a delay of 3 clocks.
DFT main calculation module
The module comprises two large modules, three functions are realized, current harmonic waves on the network side are extracted, closed-loop adjustment is carried out through PR, and a harmonic current reference is synthesized. After each subharmonic is extracted, the output of each subharmonic PR is the final harmonic current reference for each subharmonic. The structure of the module is shown in fig. 2.
It should be noted that the actual calculation of SDFT is flexible, and the method is various, and the above formula is a formula used in some embodiments. The calculation process includes three steps as shown in fig. 3. The principle of the step 1 is that a 1025-byte 16-bit RAM is established, the latest sampled data is sent to a storage unit corresponding to a write address Wr_addr, the number in the storage unit corresponding to a read address Rd_addr is output, the read address always leads 1 to be positioned at the write address, 1024 data are sampled, namely, after a period, the value output by the RAM each time is sampled data at the last sampling moment, the value of Deltax is obtained by subtracting the value read in the RAM from the latest sampled data, error calculation is carried out in order to prevent the data from overflowing, an error detection module is added after the Deltax calculation result is obtained, if the calculation result overflows, 16' h4000 is output, otherwise, the data are normally output. Data_sub is the difference between the newly slipped in sample Data and the slipped out Data. Steps 2 and 3 of fig. 3 are implemented in a set of rotation index modules.
3. Rotation index module (group)
The rotation index module (group) comprises 8 sub-modules, namely a time sequence control module, a rotation factor selection module, a sub-harmonic DFT data storage module, a DFT main calculation module, a DFT inverse transformation and phase angle compensation module, a PR data storage module and a harmonic synthesis module. The timing control module coordinates the working timing among the modules, the twiddle factor selection module, the subharmonic DFT data storage module and the DFT main calculation module realize the harmonic extraction function of SDFT, the DFT inverse transformation module, the PR module and the PR data storage module realize the PR function, the harmonic synthesis module synthesizes the extracted subharmonic, and the functions realized by the functional modules are shown in Table 2 in detail.
TABLE 2 function realized by each module in the rotation index module group
3.1 the time sequence control module is mainly used for coordinating the working time sequence among the modules, the input data of the module is a Ready signal for completing the calculation of the difference between the new sampling data and the old sampling data of the DFT and selecting the compensated subharmonic times, the correlation effect of the output signals is shown in the table 3, and the time sequence among the output signals is shown in fig. 4.
TABLE 3 sense of output signals from the timing control module
When the external new and old sampling data are ready, starting to perform SDFT calculation, step 2 and step 3 shown in FIG. 3, giving an enabling signal of an SDFT data storage RAM in the next clock period, reading out the calculated data value at the previous time, then generating a high-level signal of a clock Rd_Q, latching the data read out from the RAM of the DFT main calculation module, storing the amplitude of each newly calculated subharmonic into the SDFT data storage RAM after two clocks, simultaneously performing DFT inverse transformation, starting PR operation after each subharmonic extraction of network side current is completed, firstly giving a reading enabling signal of the PR data storage module, the intermediate value of each subharmonic PR operation, latching the read-out data by PI_Q, after PR calculation is completed in 4 periods, sending the obtained reference signal into the harmonic synthesis module, and writing the intermediate value data of the latest calculated PR into the PRRAM.
3.2 twiddle factor selection module
The twiddle factor selection module is used for storing sine function values sin and cosine function values cos obtained by the twiddle factors of the SDFT module after being unfolded by an Euler formula, wherein the unfolding formula of the twiddle factors is as follows:
the time sequence control module gives out the kth harmonic to be calculated currently, the sampling data processing module outputs the current calculation time point as numaddress, the signal is equivalent to n in a formula, k×numaddress is obtained to be a Rotation factor rotation_address, namely k×n, rotation_address is used as a storage address of sin and cos values after the Euler formula is expanded, the sampling frequency of one sampling period is 1024 due to the periodicity of a trigonometric function, the size of the trigonometric function lookup table can be positioned for 1024 bytes, and the lower 10 bits of data of the rotation_address (equivalent to taking the rotation_address/1024 as the lookup address of the trigonometric function lookup table) is obtained.
3.3DFT main calculation module
With the calculation result of SDFT alone, instability is easy to generate, so that a non-iterative DFT module is added in the module. The formula is:
where k ranges from 0 to N-1, x (N) represents the newly incoming sample data,
is a twiddle factor, which is the same twiddle factor as the twiddle factor calculated by SDFT, X (k) is the non-iterative DFT calculated value calculated by the kth time, and N is 1024.
After 1024 points of a sampling period are completed, the frequency unit value calculated by non-iterative DFT is used for updating the corresponding frequency unit value of SDFT, meanwhile, the value of the frequency unit of the non-iterative DFT is cleared, and the calculation of a new period is restarted, and the module comprises two sub-modules: DFT_Cal and Cal_Recurrive modules. The dft_cal module is used for completing the computation of step 2 in fig. 3, the corresponding step 2 in the non-iterative DFT computation is also implemented in the dft_cal module, and the cal_repetitive module is implemented to accumulate the computed current SDFT computation value and the current non-iterative DFT computation value with the last SDFT computation value and the non-iterative DFT computation value, respectively, thereby completing the computation corresponding to step 3. Rotation_sin (twiddle factor sine value) and rotation_cos (twiddle factor cosine value) in the DFT_Cal module are input by a twiddle factor selection module, and data_new and data_sub are input by a sampling Data processing module; and the output result of the Cal_Recurrive module is sent to each subharmonic DFT data storage module.
3.4 As can be seen from the calculation formula (formula III) of SDFT, the DFT data storage module of each subharmonic needs to use the DFT value of the subharmonic at the previous time when calculating the DFT at the current time, so that the DFT data calculated at the previous time needs to be stored by using a storage space and used as iteration data in the next SDFT calculation. Non-iterative DFT computation also requires storing the last value. So there are two types of data (frequency units of DFT and non-iterative DFT) in total, four types of data (frequency units are complex, have sine and cosine values of frequency units), so four readable and writable dual port RAMs are required. In the RAM, since one address corresponds to one frequency unit, and at most 20 frequency units are simultaneously used, at least 20 memory units are required, and 25 memory units are preferable for facilitating subsequent expansion.
3.5 inverse transform module
The inverse transformation module comprises two functions, the former half module is DFT inverse transformation, the latter half module is phase compensation of each subharmonic, and the reason for adding the phase compensation to each subharmonic is that the compensated harmonic has time delay in sampling and calculation in the actual process.
3.6PR Module
PR parameters are 5 groups, corresponding to A of the formula 0 ，A 1 ，A 2 ，B 1 ，B 2 。
G (z) is obtained by PR dispersion, and the adopted method is a pre-corrected Tustin transformation algorithm, as shown in the following formula,
in the actual calculation process, after the dispersion, PR is used for the coefficient A 0 ，A 1 ，A 2 ，B 1 ，B 2 The required accuracy of (2) is very high, so that the above-mentioned coefficients are first expanded 220 times when PR adjustment parameters are calculated in the program, and then removed 220 again when the final data is output.
The iterative formula for the output data of the current PR, which can be obtained from equation 2.6, is:
y(k)＝A 0 x(k)+A 1 x(k-1)+A 2 x(k-2)-B 1 y(k-1)-B 2 y(k-2)
the coefficient of each subharmonic is calculated by Matlab software, the Matlab has a self-contained pre-correction Tustin conversion algorithm for converting S domain into Z domain, the coefficient corresponding to each subharmonic calculated by Matlab is stored into a grid_PR_Index module, it is noted that the parameters in transfer functions of PR corresponding to different subharmonics are not the same, the values of the parameters are given according to the system stability and compensation effect in the actual debugging process, and the input data of the grid_current_PR_Re module is the coefficient A generated by the grid_PR_Index module 0 ，A 1 ，A 2 ，B 1 ，B 2 The PR data storage module provides the values x (k-1), x (k-2), y (k-1), y (k-2) and the amplitude corresponding to the current harmonic frequency output by the IDFT module, so that the output data of the current PR are calculated.
The 3.7PR data storage module uses 4 RAM memories RE_DFT_PR_Dual_RAM to store the input signals of the grid_current_PR_Re module because the input signals of the first two times and the output signals of PR are needed to be used for calculating the DFT data of the Current time according to the calculation formula after PR dispersion. The number of data bits stored is 45 bits, which is Q20 data.
3.8 harmonic synthesis module
The module is used for synthesizing the current amounts of all subharmonics to be compensated, generating a compensation current reference signal and sending the compensation current reference signal to a slave board, when PR data is calculated, an xout_Q generated in the time sequence control module generates a high level signal with a clock length, the harmonic synthesis module is informed of adding a current amplitude signal PR_Out [15..0] of the subharmonics, and when the fact that the number j [4..0] of the harmonic to be compensated which is currently calculated is detected to be smaller than the total number Sel_K4..0 ] of the input harmonic types to be compensated, the current reference signal output by PR is continuously accumulated; when the number j 4.0 of the harmonic to be compensated which is calculated currently is detected to be equal to the total number sel_k4.0 of the input harmonic types to be compensated, a harmonic synthesis completion signal is generated in the next clock cycle, and a harmonic current reference synthesis signal is output.
4. Output data conversion module
The current parameters of PR of the main board network side current closed loop and the related parameters of PI regulator tracked by the slave board harmonic current reference are defaults, and the turn ratio of the current transformer of the network side current is 600:5. When the turn ratio of the external current transformer is changed, the parameters of PR should also be changed in the same ratio. And the output data conversion module carries out corresponding processing on the harmonic current reference output by the harmonic current extraction and synthesis module. When the method is realized, the harmonic current reference output by PR is subjected to corresponding proportion change.
The ABC three-phase harmonic current reference time sharing shares the data conversion module.
In some preferred embodiments, an SDFT slow-down module is further provided to avoid current spikes and triggering over-current protection caused by PR saturation when the harmonic compensation is more frequently started and when the APF system begins to close loop. The module is only active after the voltage stabilization from the three-phase dc side of the board, i.e. after the APF has been successfully grid-connected and the dc side voltage PFC has stabilized. If the actual number of compensating harmonic types is sel_kk, sel_kk is added every 100ms, that is, every 100ms, the number of compensating harmonic types is increased by one harmonic compared with the original compensating current, until the total number of the harmonic types required to be compensated is reached.
The embodiments and functional operations of the subject matter described in this specification can be implemented in the following: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed in this specification and structural equivalents thereof, or a combination of one or more of the foregoing. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on one or more tangible, non-transitory program carriers, for execution by, or to control the operation of, data processing apparatus. The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows described in this specification can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an ASIC (application specific integrated circuit).
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may embody particular embodiments of particular invention. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as acting in combination and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments.
Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the activities recited in the claims can be executed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying drawings do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
Claims (8)
1. A harmonic extraction and synthesizer of an APF control system, the harmonic extraction and synthesizer comprising a recursive discrete fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores sampling signals of the network side current into a data queue according to time sequence, calculates a difference value delta x between data entering the data queue for the nth time and data sliding out of the data queue, and outputs the delta x to the rotation index module;
the rotation index module includes: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module, a DFT inverse transformation and phase angle compensation sub-module;
after the timing control submodule receives the calculation completion signal of the sampling data processing module, the DFT data calculation is completed once in five continuous clock cycles, and the method specifically comprises the following steps:
in a first clock period, the timing control sub-module outputs a reading enabling signal, and the DFT main calculation sub-module reads DFT data calculated last time from the sub-harmonic DFT data storage sub-module;
in a second clock period, the timing control sub-module outputs a read notification signal, and the DFT main calculation sub-module latches the DFT data calculated last time;
in the third and fourth clock cycles, the DFT main calculation submodule completes one DFT data calculation;
in a fifth clock period, the timing control submodule outputs a write-in enabling signal, the DFT main calculation submodule writes the DFT data calculated at the time into each subharmonic DFT data storage submodule, and the DFT inverse transformation and phase angle compensation submodule performs DFT inverse transformation; the DFT main calculation sub-module completes DFT data calculation comprising sliding discrete Fourier transform SDFT and non-iterative discrete Fourier transform once in each frequency unit.
2. The harmonic extraction and synthesizer of claim 1, wherein the twiddle index module further comprises a twiddle factor selection sub-module comprising a 1024 byte sine function table and a 1024 byte cosine function table; the twiddle factor selecting submodule calculates and outputs twiddle factors, and specifically comprises the following steps: recording the remaining Nmod1024 of the time sequence N pairs 1024 of the current sampling signal;
and searching the sine value and the cosine value corresponding to the Nmod1024 in the sine function table and the cosine function table respectively, and outputting the sine value and the cosine value which are corresponding to the twiddle factor after being unfolded by an Euler formula respectively.
3. The harmonic extraction and synthesizer of claim 2 wherein the DFT main computation sub-module performs a DFT data computation within each frequency bin; the DFT data calculation comprises SDFT calculation, and specifically comprises the following steps:
acquiring the twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value which correspond to the twiddle factor after the Euler formula is unfolded;
obtaining the difference of the sampling signals calculated at the present time;
multiplying the twiddle factor by the difference of the sampling signals calculated at present, and accumulating the twiddle factor with the SDFT data calculated by the last frequency unit to obtain the SDFT data of the current frequency unit;
and outputting the SDFT data of each frequency unit and maintaining the SDFT data to the subharmonic DFT data storage submodule.
4. A harmonic extraction and synthesizer as in claim 3 wherein the DFT data computation further comprises a non-iterative DFT computation, comprising the steps of:
acquiring the twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value which correspond to the twiddle factor after the Euler formula is unfolded;
acquiring a current sampling signal;
multiplying the rotation factor with the sampling signal, and accumulating the rotation factor with non-iterative DFT data obtained by calculation of the last frequency unit to obtain non-iterative DFT data of the current frequency unit; outputting non-iterative DFT data of each frequency unit and maintaining the non-iterative DFT data to the sub-module for storing the DFT data of each subharmonic;
and assigning non-iterative DFT data to the SDFT data every time a sampling period is passed, and setting the non-iterative DFT data of all frequency units of each subharmonic stored in the subharmonic DFT data storage submodule to zero.
5. The harmonic extraction and synthesizer of claim 1, wherein the rotation index module further comprises: a proportional resonance control regulator sub-module, a proportional resonance control regulator data storage sub-module, and a harmonic synthesis sub-module; the rotation index module is configured to implement the steps comprising:
in a sixth clock period, the time sequence control sub-module outputs a proportional resonance control reading enabling signal and reads an intermediate value calculated by the proportional resonance control regulator sub-module in a data storage unit of the proportional resonance control regulator sub-module;
in a seventh clock period, the timing control submodule outputs a notification signal that the data of the data storage unit of the proportional resonance control regulator submodule is read completely, and then latches the intermediate value data;
and after a plurality of clock cycles, the proportional resonance control regulator submodule outputs a reference signal to the harmonic synthesis submodule, and the calculation result is written into a data storage unit of the proportional resonance control regulator submodule.
6. A harmonic extraction and synthesis as in claim 5 wherein the proportional resonance control regulator sub-module employs a pre-modified Tustin transformation algorithm.
7. The harmonic extraction and synthesizer of claim 4, wherein the sampled data processing module is based on a random access memory implementation comprising the steps of:
sending the latest sampling signal into a storage unit corresponding to a write address Wr_addr, and outputting data in the storage unit corresponding to a read address Rd_addr, wherein the read address always leads 1 to be positioned at the write address;
every 1024 signals are sampled consecutively as one of the sampling periods, in each of which:
the data output by the random access memory each time is the last sampling signal, and the difference of the last sampling signal subtracted by the latest sampling signal is δx;
outputting the delta x obtained by each calculation and outputting the calculation completion signal once;
and performing overflow verification on the delta x.
8. The harmonic extraction and synthesizer of claim 4, wherein the subharmonic DFT data storage sub-module is implemented based on four readable and writable dual-port random access memories; wherein each of the readable and writable dual-port random access memories is configured to: each address corresponds to a frequency unit;
the first readable and writable dual-port random access memory is used for storing a twiddle factor sine value obtained by Euler transformation of the twiddle factor in SDFT calculation;
the second readable and writable dual-port random access memory is used for storing a twiddle factor cosine value obtained by carrying out Euler transformation on the twiddle factor in SDFT calculation;
the third readable and writable dual-port random access memory is used for storing a twiddle factor sine value obtained by carrying out Euler transformation on the twiddle factor in non-iterative DFT calculation;
the fourth readable and writable dual-port random access memory is used for storing a twiddle factor cosine value obtained by carrying out Euler transformation on the twiddle factor in non-iterative DFT calculation;
each readable and writable dual-port random access memory is provided with at least 20 memory units.
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