CN114710139A - Harmonic extraction and synthesizer of APF control system - Google Patents
Harmonic extraction and synthesizer of APF control system Download PDFInfo
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Abstract
The invention relates to the technical field of digital signal processing of a power electronic control circuit and the technical field of active power filter design, in particular to a harmonic extraction and synthesizer of an APF control system, which comprises a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module; the sampling data processing module stores the acquisition signal of the network side current into a data queue according to the time sequence, calculates the difference x between the data entering the data queue at the nth time and the data sliding out, and outputs the difference x to the rotation index module. By adopting an improved main control algorithm, harmonic extraction is completed by combining Sliding Discrete Fourier Transform (SDFT) with non-iterative discrete Fourier transform, so that the robustness and stability of the main control algorithm are improved; meanwhile, the coordination control of each frequency component of the command current is realized based on the quasi-proportional resonance control.
Description
Technical Field
The invention relates to the technical field of digital signal processing of power electronic control circuits and the technical field of active power filter design, in particular to a harmonic extraction and synthesizer of an APF control system.
Background
The widespread use of power electronics results in increased total harmonic interference in the power distribution system, nonlinear loads can absorb harmonic and reactive power components of current from the ac power source, and can also result in imbalance in the three-phase system. An Active Power Filter (APF) can suppress harmonics while compensating for reactive power by injecting a compensation current in the opposite direction to the harmonic current. The response speed of the current common APF current tracking control is slow, and when the load current changes rapidly, the line current is influenced by dynamic distortion, and the influence causes the harmonic content in the line current to increase, and the proportion of the total harmonic distortion to increase.
Disclosure of Invention
Aiming at the technical problems, the technical scheme provided by the invention improves and designs the core module of the three-phase parallel active power filter. The harmonic extraction and synthesizer comprises a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores the sampling signal of the network side current into a data queue according to time sequence, calculates the difference value of the data entering the data queue and the data sliding out at the nth time, and outputs the Δ x to the rotation index module.
Further, the rotation index module includes: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module and a DFT inverse transformation and phase angle compensation sub-module; the rotation index module is configured to implement steps comprising:
and the time sequence control sub-module completes one time of DFT data calculation in five continuous clock cycles after receiving the calculation completion signal of the sampling data processing module.
Further, the DFT main calculation sub-module completes one DFT data calculation in each frequency unit; the DFT data computation includes an SDFT computation.
Further, the DFT data computation also includes a non-iterative DFT computation.
The technical scheme provided by the invention improves and designs the core module of the three-phase parallel active power filter, and the harmonic extraction is completed by adopting an improved main control algorithm and combining a Sliding Discrete Fourier Transform (SDFT) with a non-iterative discrete Fourier transform, so that the robustness and the stability of the main control algorithm are improved; meanwhile, the coordination control of each frequency component of the command current is realized based on the quasi-proportional resonance control.
Drawings
FIG. 1, a schematic diagram of a harmonic extraction and synthesizer structure of some embodiments;
fig. 2, some specific embodiments of a block diagram of a DFT main computation module structure, where each identifier specifically indicates: inputting a sampling signal as Data _ In; cal _ Ready: completing the calculation of the signal; numaddress: current calculation time point; data _ new: the latest sampled signal; data _ Sub: a slipped sample signal; k: the number of harmonics of the current DFT operation; xk(n): nth data in DFT calculation of K harmonic; xk(n-1): the n-1 th data in DFT calculation of K harmonic; k _1, K _ 20: 1 st, 20 th harmonics; fre _ Sel: the frequency of the harmonic to be compensated; x _ Out: outputting the signal; out _ done: outputting a completion signal; rd _ En: a read enable signal for the SDFT data storage RAM; wr _ En: a write enable signal to the SDFT data storage RAM; rd _ Q: an SDFT data storage RAM data reading completion notification signal; rd _ Add: data read addresses of the SDFT data storage RAM; wr _ Add: data write addresses of the SDFT data storage RAM; xout _ Q: giving a subharmonic DFT completion signal; PI _ Rd: a read enable signal of the PR data storage module; PI _ Wr: a write enable signal of the PR data storage module; PI _ Q: a notification signal for finishing data reading of the PR data storage module; j 4. 0]: when the k-th harmonic is calculated.
FIG. 3 is a flow diagram of a SDFT implementation of some embodiments;
fig. 4 is a timing diagram of a timing control module of some embodiments, where each identifier specifically indicates: clock _ 100M: a clock signal of frequency 100M; cal _ Ready: completing the calculation of the signal; rd _ En: a read enable signal for the SDFT data storage RAM; rd _ Q: an SDFT data storage RAM data reading completion notification signal; wr _ En: a write enable signal to the SDFT data storage RAM; PI _ Rd: a read enable signal of the PR data storage module; PI _ Wr: a write enable signal of the PR data storage module; PI _ Q: a notification signal for finishing data reading of the PR data storage module; xout _ Q: given a subharmonic DFT completion signal.
Detailed Description
The APF control system of some embodiments comprises a harmonic extraction and synthesizer, and an SDFT main control algorithm program is loaded through a recursive discrete Fourier transform module and is used for generating harmonic references of each phase current, the module comprises a sampling data processing module and a rotation index module, and the specific module structure of each module is shown in FIG. 1;
the harmonic extraction and synthesizer comprises a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores the sampling signal of the network side current into a data queue according to a time sequence, calculates the difference value x of the data entering the data queue and the data sliding out at the nth time, and outputs the difference value x to the rotation index module.
First, the SDFT (sliding discrete fourier) algorithm is further explained. As can be seen from the definition of fourier series, any periodic non-sinusoidal signal can be decomposed into a superposition of several periodic sinusoidal signals. The load current is a periodic non-standard sinusoidal signal (containing harmonic waves), and each subharmonic component of the load current can be obtained by expanding the periodic non-standard sinusoidal signal through a Fourier series.
The term "queue" refers to any linear table that allows only delete operations (out) at the front of the table, and insert operations (in) at the back of the table, in embodiments as a sliding window data structure. The term "twiddle factor" refers to the complex constant multiplied by each term in the fourier series of the fourier transform, which lies above the unit circle on the complex plane, and hence the name twiddle factor, for the effect that the multiplicand has a rotation on the complex plane.
It should be noted that, some preferred embodiments of the harmonic extraction and synthesizer are implemented based on an FPGA, and adopt parallel processing and pipeline operation, so that the harmonic extraction and synthesizer has the advantages of flexible logic unit, high integration level, wide application range, and the like, and is suitable for separating fundamental wave and each subharmonic component of an error signal by using fourier transform.
Some embodiments relate to a rotation index module that substantially comprises: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module and a DFT inverse transformation and phase angle compensation sub-module; the method comprises the following steps that each submodule completes the following steps under the coordination of the time sequence control submodule:
after receiving the calculation completion signal, the timing control submodule completes one-time DFT data calculation in five continuous clock cycles, and specifically comprises the following steps:
in a first clock period, the time sequence control submodule outputs a read enabling signal, and the DFT main calculation submodule reads DFT data calculated last time from each sub-harmonic DFT data storage submodule;
in a second clock period, the timing control submodule outputs a reading completion notification signal, and the DFT main calculation submodule latches DFT data calculated last time;
in the third and fourth clock cycles, the DFT main calculation module completes one DFT data calculation;
in the fifth clock period, the time sequence control module outputs a write-in enabling signal, the DFT main calculation module writes the calculated DFT data into each sub-harmonic DFT data storage sub-module, and meanwhile, the DFT inverse transformation and phase angle compensation module carries out DFT inverse transformation.
The twiddle index module of some embodiments also includes a twiddle factor selection sub-module that includes a 1024 byte sine function table and a 1024 byte cosine function table; the twiddle factor selection submodule calculates and outputs the twiddle factor, and specifically comprises the following steps:
recording the remaining Nmod1024 of the time sequence N of the current sampling signal to 1024;
and respectively searching a sine value and a cosine value corresponding to Nmod1024 in a sine function table and a cosine function table, and respectively outputting the sine value and the cosine value corresponding to the rotation factor after the rotation factor is expanded by an Euler formula.
Some embodiments relate to a DFT primary computation submodule that performs a DFT data computation in each frequency bin; the DFT data calculation comprises SDFT calculation, and specifically comprises the following steps:
acquiring a twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value corresponding to an expanded Euler formula;
acquiring the difference of the sampling signals calculated at the current time;
multiplying the difference between the twiddle factor and the sampling signal calculated at the current time, and accumulating the result with the SDFT data calculated by the last frequency unit to obtain the SDFT data of the current frequency unit;
and outputting the SDFT data of each frequency unit and keeping the SDFT data to each harmonic DFT data storage submodule.
The DFT computation process is completed once in each frequency bin. The twiddle factor is output by a twiddle factor selection module through expanding a complex factor into a trigonometric function form through an Euler formula, and preferably, a sine value and a cosine value are respectively stored in a data queue.
The iterative calculation formula of the sliding window discrete Fourier transform is shown as formula I:
wherein the content of the first and second substances,
in order to be a factor of rotation,x(n) Is a firstnA sampling signal of the current on the sub-grid side,X k (n) Is as followsnThe DFT data of the sub-calculation is,krepresenting the corresponding harmonic order.
In some embodiments of the harmonic extraction and combiner, the computation performed by the DFT primary computation module further comprises a non-iterative DFT computation, which comprises the following steps:
acquiring a twiddle factor, wherein the twiddle factor comprises a sine value and a cosine value corresponding to an expanded Euler formula;
acquiring a current sampling signal x;
multiplying the twiddle factor by x, and accumulating the twiddle factor with the non-iterative DFT data obtained by calculation of the previous frequency unit to obtain the non-iterative DFT data of the current frequency unit;
outputting the non-iterative DFT data of each frequency unit and keeping the data to each sub-harmonic DFT data storage sub-module;
and assigning the non-iterative DFT data to the SDFT data every time after a sampling period, and setting the non-iterative DFT data of all frequency units of each harmonic stored in each harmonic DFT data storage submodule to zero.
It should be noted that if the DFT calculation is performed by using the SDFT method alone, instability is easily caused, so that an interactive updating step is added, after a sampling period, the values of the frequency bins calculated by the non-iterative DFT are updated to the corresponding frequency bin values of the DFT, and the values of the frequency bins of each sub-harmonic of the non-iterative DFT are set to zero.
In some embodiments, the accumulation calculation in the SDFT calculation and the non-iterative DFT calculation share one calculator in the DFT primary calculation submodule.
Some embodiments relate to a rotation index module further comprising: the device comprises a proportional resonance control regulator submodule, a proportional resonance control regulator data storage submodule and a harmonic synthesis submodule; the rotation index module is configured to implement steps comprising:
in a sixth clock period, the time sequence control submodule outputs a proportional resonance control read enabling signal and reads an intermediate value calculated by a proportional resonance control regulator submodule in a data storage unit of the proportional resonance control regulator submodule;
in a seventh clock cycle, after the time sequence control submodule outputs a notification signal that the data reading of a data storage unit of the proportional resonant control regulator submodule is finished, the intermediate value data is latched;
after a plurality of clock cycles, the proportional resonance control regulator submodule outputs a reference signal to the harmonic synthesis submodule and writes a calculation result into a data storage unit of the proportional resonance control regulator submodule.
The proportional resonant control regulator (PR) sub-module of some embodiments employs a pre-modified Tustin transform algorithm. The discretization of the control system is actually the discretization of the PR, and the Tustin transform can be used. However, generally, the high-frequency characteristic of the Tustin transform is distorted seriously and is not suitable for PR having a high resonance frequency. In order to ensure the linear relation between the s domain and the z domain of the controller frequency domain, a frequency pre-modified Tustin transformation algorithm can be adopted.
The term 'proportional resonance control regulator (PR)' is composed of a proportional link and a resonance link, and can realize non-static control on sinusoidal quantity, and an integral link in the PR is also used as a generalized integrator and can realize amplitude integration on the sinusoidal quantity of resonance frequency.
Preferably, all twiddle factors are quantized to Q15, and the multiplication is performed by first multiplying 16 bits by 16 bits and then taking the 16bit higher, i.e., dividing by 216And then the calculation result is enlarged by 2 times.
It should be noted that Q15 indicates that the decimal part has 15 bits, a short type data occupies 2 bytes, the most significant bit is the sign bit, the following 15 bits are the decimal place, and it is assumed that the decimal point is left of the 15 th bit, and the range is represented as: -1<X<0.9999695, respectively; the floating point data is converted to Q15, and the data is multiplied by 215(ii) a Q15 data is converted to floating point data, and the data is divided by 215。
In some embodiments implemented based on the FPGA, because the mainstream FPGA cannot implement floating point arithmetic, in order to implement high-precision digital discretization of quasi-R control, it is necessary to quantize the coefficients of the differential equation and perform floating point arithmetic on the quantized differential equation.
In some embodiments, the sample data processing module is implemented based on random access memory and comprises the following steps:
the latest sampling signal is sent to a storage unit corresponding to a write address Wr _ Addr, and data in the storage unit corresponding to a read address Rd _ Addr is output, wherein the read address is always ahead of 1 and is positioned at the write address;
taking 1024 signals as a sampling period in each succession, in each sampling period:
the data output by the random access memory each time is the last sampling signal, and the difference of subtracting the last sampling signal from the latest sampling signal is deltax;
outputting delta x obtained by each calculation, and simultaneously outputting a calculation completion signal;
an overflow check is performed on δ x.
The random access memory realizes the storage of the data queue.
Each sub-harmonic DFT data storage module of some embodiments is implemented based on four readable and writable dual-port random access memories; wherein each of the read-writable dual-port random access memories is configured to:
each address corresponds to a frequency unit;
the first readable and writable double-port random access memory is used for storing a sine value of a twiddle factor obtained by Euler transformation of the twiddle factor in the SDFT calculation;
the second readable and writable double-port random access memory is used for storing a twiddle factor cosine value obtained by Euler transformation of the twiddle factor in the SDFT calculation;
the third readable and writable double-port random access memory is used for storing the sine value of the twiddle factor obtained by Euler transformation of the twiddle factor in the non-iterative DFT calculation;
the fourth readable and writable double-port random access memory is used for storing a twiddle factor cosine value obtained by Euler transformation of the twiddle factor in the non-iterative DFT calculation;
each of the readable and writable dual-port random access memories is provided with at least 20 memory cells, and each of the readable and writable dual-port random access memories is configured to be provided with 25 memory cells in order to facilitate later expansion.
The present invention is explained in detail below with more specific embodiments. These embodiments use 3 identical harmonic extraction and synthesis modules, corresponding to ABC three phases, respectively, and are described here only by way of example as phase a. The module comprises a plurality of sub-modules, and the functions are detailed in table 1:
TABLE 1 submodule Functions
The core module in the above sub-modules is the DFT main computation module, K _ 1-K _20 in the harmonic selection compensation module represents 20 kinds of harmonics selected for compensation, the number of the harmonics to be compensated is recorded in variables K _ 1-K _20, respectively, and the total number of the kinds of the harmonics to be compensated is recorded in a variable Sel _ K [4.
1. SDFT sampling control module
The module is essentially a pulse match. The pulse notification signal for controlling the SDFT operation once is a narrow pulse having a width of 1/100Ms, but the externally input notification signal may have a width of more than 1/100Ms, and thus pulse width matching is required to avoid repetitive operations. After the DFT starting operation signal is detected for the first time, delaying for 3 clocks, and detecting the next starting signal again.
2. DFT main computing module
The module comprises two large modules, three functions are realized, network side current harmonic waves are extracted, closed-loop adjustment is carried out through PR, and harmonic current reference is synthesized. After each harmonic is extracted, the output of each harmonic PR is the final harmonic current reference for each harmonic PR as the input to each harmonic PR. The structure of the module is shown in fig. 2.
It should be noted that the actual calculation of the SDFT is flexible and various, and the above formula is used in some embodiments. The calculation process includes three steps as shown in fig. 3. The principle of the step 1 is that a 16-bit RAM with 1025 bytes is established, data obtained by latest sampling is sent into a storage unit corresponding to a write address Wr _ Addr, the number in the storage unit corresponding to a read address Rd _ Addr is output, the read address is always ahead of 1 and is located at the write address, after 1024 data are sampled, namely after one week, the value output by the RAM each time is the sampling data at the last sampling moment, the value read out from the RAM is subtracted from the data obtained by latest sampling to obtain the value of Delta x, error calculation is carried out to prevent data overflow, an error detection module is added after the calculation result of Delta x is obtained, if the calculation result overflows, 16' h4000 is output, otherwise, normal output is carried out. Data _ Sub is the difference between the newly slipped sample Data and the slipped Data. Steps 2 and 3 of fig. 3 are implemented in a rotating finger module set.
3. Rotation index module (group)
The rotation index module (group) comprises 8 submodules which are respectively a time sequence control module, a rotation factor selection module, each subharmonic DFT data storage module, a DFT main calculation module, a DFT inverse transformation and phase angle compensation module, a PR data storage module and a harmonic synthesis module. The time sequence control module coordinates the working time sequence among the modules, the twiddle factor selection module, the sub-harmonic DFT data storage module and the DFT main calculation module realize the harmonic extraction function of SDFT, the DFT inverse transformation module, the PR module and the PR data storage module realize the PR function, the harmonic synthesis module synthesizes the extracted sub-harmonic, and the functions realized by the functional modules are detailed in Table 2.
TABLE 2. function realized by each module in rotary index module group
3.1 sequential control Module
The method is mainly used for coordinating the working time sequence among modules, the input data of the modules are Ready signals for finishing calculating the difference between the new and old sampling data of DFT and selecting the times of each sub-harmonic for compensation, the relevant action of the output signals is shown in a table 3, and the time sequence among the output signals is shown in a figure 4.
TABLE 3 output signal meaning of sequential control module
When the new and old external sampling data are ready, starting to perform SDFT calculation, as shown in step 2 and step 3 in fig. 3, giving an enable signal of an SDFT data storage RAM in the next clock cycle, reading out the data value calculated at the last moment, generating a high level signal of a clock from Rd _ Q, latching the data read out from the RAM of the DFT main calculation module, storing the amplitude of each newly calculated sub-harmonic into the SDFT data storage RAM after two clocks, and simultaneously performing DFT inverse transformation, starting PR operation after extraction of each subharmonic of the network side current is finished, firstly providing a read enabling signal of a PR data storage module, latching the read data by PI _ Q, completing PR calculation after 4 periods, sending the output reference signal to a harmonic synthesis module, and writing the newly calculated middle value data of PR into a PRRAM.
3.2 twiddle factor selection Module
The twiddle factor selection module is used for storing a sine function value sin and a cosine function value cos which are obtained by unfolding the twiddle factor of the SDFT module through an Euler formula, wherein the unfolding formula of the twiddle factor is as follows:
the time sequence control module gives the current second calculationkSub-harmonic, the sampled data processing block outputs the current point in time of computation numaddress, which is equivalent to n in the formula,
the Rotation factor Rotation address is obtained
The Rotation _ address is used as the storage address of sin and cos values after the euler formula is expanded, and the sampling frequency of one sampling period is 1024 due to the periodicity of the trigonometric function, so the size of the trigonometric function lookup table can be positioned into 1024 bytes, and the lower 10-bit data (equivalent to the remainder of the Rotation _ address/1024) of the Rotation _ address is used as the lookup address of the trigonometric function lookup table.
3.3 DFT Primary compute Module
The calculation result of the SDFT is used alone, instability is easy to generate, and therefore a non-iterative DFT module is added in the module. The formula is as follows:
whereinkThe value ranges from 0 to N-1,x(n) Representing the newly incoming sample data and,
is a twiddle factor, which is the same twiddle factor as the computed twiddle factor for the SDFT,X(k) Is as followskThe non-iterative DFT of the sub-calculation is calculated, N is 1024.
After 1024 points of a sampling period are finished, updating a frequency unit value corresponding to the SDFT by using a frequency unit value calculated by the non-iterative DFT, simultaneously resetting the value of the frequency unit of the non-iterative DFT, and restarting the calculation of a new period, wherein the module comprises two sub-modules: DFT _ Cal and Cal _ regenerative modules. The DFT _ Cal module is used for completing calculation of the SDFT calculation as in step 2 of fig. 3, the corresponding step 2 in the non-iterative DFT calculation is also realized in the DFT _ Cal module, and the Cal _ Recursive module is used for accumulating the calculated current SDFT calculation value and the calculated current non-iterative DFT calculation value with the previous SDFT calculation value and the calculated non-iterative DFT calculation value respectively, that is, completing the calculation corresponding to step 3. Rotation _ Sin (sine value of Rotation factor) and Rotation _ Cos (cosine value of Rotation factor) in the DFT _ Cal module are input by a Rotation factor selection module, and Data _ new and Data _ Sub are input by a sampling Data processing module; the output result of the Cal _ Recursive module is sent to each harmonic DFT data storage module.
3.4 each harmonic DFT data storage module
Formula (formula) by SDFT
) It can be known that, when calculating the DFT of the current time, the DFT value of the sub-harmonic at the previous time is needed, and therefore, a storage space is needed to store the DFT data calculated at the previous time and use the DFT data as iteration data in the next SDFT calculation. The non-iterative DFT computation also requires the storage of the last value. There are two types of data (frequency units of DFT and non-iterative DFT) and four types of data (frequency units are complex numbers, and sine and cosine values of frequency units), so four readable and writable dual-port RAMs are required. In RAM, from address 1Initially, one address corresponds to one frequency unit, and at most 20 frequency units are available at the same time, so at least 20 memory units are needed, and 25 memory units are preferred for facilitating subsequent expansion.
3.5 inverse transformation module
The inverse transformation module comprises two functions, the first half module is DFT inverse transformation, the second half module is phase compensation of each harmonic wave, and the reason for adding phase compensation to each harmonic wave is that the harmonic wave compensated in the actual process has time delay due to sampling and calculating.
3.6 PR module
PR parameters were 5 groups, each corresponding to A of the formula0，A1，A2，B1，B2。
G(z) Is obtained by PR discrete, and the adopted method is a pre-corrected Tustin transformation algorithm, as shown in the following formula,
in the actual calculation process, after dispersion, PR is used for the coefficient A0，A1，A2，B1，B2The required accuracy is very high, so that the coefficients are enlarged by 220 times when the PR adjustment parameters are calculated in the program, and the coefficients are removed by 220 when the final data is output.
The iterative formula of the output data of the current PR obtained from equation 2.6 is:
y(k)＝A0x(k)+A1x(k-1)+A2x(k-2)-B1y(k-1)-B2y(k-2)
the coefficient of each subharmonic is calculated by Matlab software, a self-contained pre-corrected Tustin transformation algorithm for converting an S domain into a Z domain is arranged in Matlab, the coefficient corresponding to each subharmonic obtained by Matlab calculation is stored in a Grid _ PR _ Index module, and the requirement for calculating the coefficient is metIt should be noted that the parameters in the transfer function of PR corresponding to different times of harmonics are not the same, and their values are given according to the system stability and compensation effect in the actual debugging process, and the input data of the Grid _ Current _ PR _ Re module is the coefficient a generated by the Grid _ PR _ Index module0，A1，A2，B1，B2And the values x (k-1), x (k-2), y (k-1), y (k-2) calculated at the first two moments provided by the PR data storage module and the amplitude corresponding to the current harmonic frequency output by the IDFT module, so as to calculate the output data of the current PR.
3.7 PR data storage module
As known from the calculation formula after PR discretization, the input signals of the first two time instants and the output signal of PR are required to be used for calculating the DFT data of the Current time instant, so that 4 RAM memories RE _ DFT _ PR _ Dual _ RAM are used for storing the input signals of the Grid _ Current _ PR _ RE module. The number of data bits stored is 45 bits, which is the data of Q20.
3.8 harmonic synthesis module
The module is used for synthesizing the current amount of each subharmonic needing to be compensated, generating a compensation current reference signal and sending the compensation current reference signal to the slave board, when PR data is calculated, generating a high level signal with a clock length by an Xout _ Q generated in the time sequence control module, informing the harmonic synthesis module to add a current amplitude signal PR _ Out [15..0] of the subharmonic, and continuously accumulating the current reference signal output by PR when the number j [4..0] of the harmonic needing to be compensated which is currently calculated is detected to be less than the total number Sel _ K [4..0] of the input harmonic kind needing to be compensated; and when detecting that the number j [4..0] of the harmonics needing to be compensated, which are calculated at present, is equal to the total number Sel _ K [4..0] of the input harmonic species needing to be compensated, generating a harmonic synthesis completion signal in the next clock period, and outputting the harmonic current reference synthesis signal.
4. Output data conversion module
The current parameter of PR of the main board network side current closed loop and the related parameter of the PI regulator tracked by the slave board harmonic current reference are defaults, and the turn ratio of a current transformer of the network side current is 600: 5. When the turn ratio of the external current transformer is changed, the parameter of PR should be changed in the same proportion. And the output data conversion module carries out corresponding processing on the harmonic current reference output by the harmonic current extraction and synthesis module. In implementation, the harmonic current reference output by the PR is subjected to corresponding proportional change.
The ABC three-phase harmonic current reference shares the data conversion module in a time sharing mode.
In some preferred embodiments, in order to avoid the problems that the frequency of compensating the harmonic waves is high when compensation is started and PR is saturated when the APF system starts to be closed, so that current spikes are generated and overcurrent protection is triggered, an SDFT slow-start module is further arranged. The module only works after the three-phase direct-current side voltage of the slave board is stabilized, namely the APF is successfully connected with the grid and the direct-current side voltage PFC is stabilized. If the actual number of the compensated harmonic wave types is Sel _ KK times, the Sel _ KK is added once every 100ms, namely, the original compensation current is compared every 100ms, and the harmonic wave is compensated once more until the total number of the harmonic wave types needing to be compensated is reached.
Implementations and functional operations of the subject matter described in this specification can be implemented in: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed in this specification and their structural equivalents, or combinations of more than one of the foregoing. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on one or more tangible, non-transitory program carriers, for execution by, or to control the operation of, data processing apparatus. The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows described in this specification can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an ASIC (application specific integrated circuit).
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features that may embody particular implementations of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in combination and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
In certain situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments.
Particular embodiments of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the activities recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
Claims (10)
1. A harmonic extraction and synthesizer of an APF control system is characterized by comprising a recursive discrete Fourier transform module; the recursive discrete Fourier transform module comprises a sampling data processing module and a rotation index module;
the sampling data processing module stores the sampling signal of the network side current into a data queue according to time sequence, calculates the difference value of the data entering the data queue and the data sliding out at the nth time, and outputs the Δ x to the rotation index module.
2. The harmonic extraction and synthesizer of claim 1 wherein the rotation exponent module comprises: the system comprises a time sequence control sub-module, each subharmonic DFT data storage sub-module, a DFT main calculation sub-module, a DFT inverse transformation and phase angle compensation sub-module;
the sequential control submodule completes one-time DFT data calculation in five continuous clock cycles after receiving the calculation completion signal of the sampling data processing module, and specifically comprises the following steps:
in a first clock cycle, the timing control submodule outputs a read enable signal, and the DFT main calculation submodule reads DFT data calculated last time from each sub-harmonic DFT data storage submodule;
in a second clock cycle, the timing control submodule outputs a reading completion notification signal, and the DFT main calculation submodule latches the DFT data calculated last time;
in the third and fourth clock cycles, the DFT main calculation module completes one DFT data calculation;
in a fifth clock cycle, the timing control module outputs a write-in enable signal, the DFT main calculation module writes the calculated DFT data into each sub-harmonic DFT data storage sub-module, and the DFT inverse transformation and phase angle compensation module performs DFT inverse transformation.
3. The harmonic extraction and synthesizer of claim 2 wherein the twiddle index module further comprises a twiddle factor selection sub-module comprising a 1024 byte sine function table and a 1024 byte cosine function table; the twiddle factor selection submodule calculates and outputs the twiddle factor, and specifically comprises the following steps:
recording the remaining Nmod1024 of the time sequence N of the current sampling signal to 1024;
and respectively searching a sine value and a cosine value corresponding to the Nmod1024 in the sine function table and the cosine function table, and respectively outputting the sine value and the cosine value corresponding to the rotation factor after the rotation factor is expanded by an Euler formula.
4. The harmonic extraction and synthesizer of claim 3 wherein the DFT main computation sub-module performs a DFT data computation in each frequency bin; the DFT data calculation comprises SDFT calculation, and specifically comprises the following steps:
acquiring the twiddle factors, wherein the twiddle factors comprise sine values and cosine values corresponding to the expanded Euler formula;
acquiring the difference of the sampling signals calculated at the current time;
multiplying the difference between the twiddle factor and the sampling signal calculated at the current time, and accumulating the difference with the SDFT data calculated by the previous frequency unit to obtain the SDFT data of the current frequency unit;
and outputting the SDFT data of each frequency unit and keeping the SDFT data to the DFT data storage submodule of each subharmonic.
5. The harmonic extraction and combiner of claim 4 wherein the DFT data calculations further comprise non-iterative DFT calculations, including the steps of:
acquiring the twiddle factors, wherein the twiddle factors comprise sine values and cosine values corresponding to the expanded Euler formula;
acquiring a current sampling signal;
multiplying the twiddle factor by the sampling signal, and accumulating the twiddle factor and the non-iterative DFT data obtained by calculation of the previous frequency unit to obtain the non-iterative DFT data of the current frequency unit;
outputting the non-iterative DFT data of each frequency unit and keeping the data to each sub-harmonic DFT data storage sub-module;
and assigning non-iterative DFT data to the SDFT data every time after a sampling period passes, and setting the non-iterative DFT data of all frequency units of each harmonic stored in the DFT data storage submodule of each harmonic to zero.
6. The harmonic extraction and combiner of claim 2 wherein the rotation index module further comprises: the device comprises a proportional resonance control regulator submodule, a proportional resonance control regulator data storage submodule and a harmonic synthesis submodule; the rotation index module is configured to implement steps comprising:
in a sixth clock period, the timing control submodule outputs a proportional resonance control read enable signal and reads an intermediate value calculated by the proportional resonance control regulator submodule in a data storage unit of the proportional resonance control regulator submodule;
in a seventh clock cycle, after the timing control submodule outputs a notification signal that the data reading of the data storage unit of the proportional resonant control regulator submodule is finished, the intermediate value data is latched;
after a plurality of clock cycles, the proportional resonance control regulator submodule outputs a reference signal to the harmonic synthesis submodule and writes a calculation result into a data storage unit of the proportional resonance control regulator submodule.
7. The harmonic extraction and synthesizer of claim 6 in which the proportional resonant control regulator sub-module employs a pre-modified Tustin transform algorithm.
8. The harmonic extraction and synthesizer of claim 7 wherein the twiddle factor is quantized to Q15.
9. The harmonic extraction and synthesizer of claim 5 wherein the sampled data processing module is implemented based on random access memory comprising the steps of:
the latest sampling signal is sent to a storage unit corresponding to a write address Wr _ Addr, and data in the storage unit corresponding to a read address Rd _ Addr is output, wherein the read address is always ahead of 1 and is positioned at the write address;
taking 1024 signals per one consecutive sampling period as one sampling period, in each of the sampling periods:
the data output by the random access memory each time is the last sampling signal, and the difference of the latest sampling signal minus the last sampling signal is deltax;
outputting the delta x obtained by each calculation and outputting the calculation completion signal once;
and performing overflow check on the delta x.
10. The harmonic extraction and synthesizer of claim 5 wherein the sub-module for each harmonic DFT data storage is implemented based on four read-write dual port random access memories; wherein each of the read-writable dual-port random access memories is configured to:
each address corresponds to a frequency unit;
the first readable and writable double-port random access memory is used for storing a sine value of a twiddle factor obtained by Euler transformation of the twiddle factor in SDFT calculation;
the second readable and writable double-port random access memory is used for storing a twiddle factor cosine value obtained by Euler transformation of the twiddle factor in the SDFT calculation;
the third readable and writable double-port random access memory is used for storing the sine value of the twiddle factor obtained by Euler transformation of the twiddle factor in non-iterative DFT calculation;
the fourth readable and writable double-port random access memory is used for storing a twiddle factor cosine value obtained by Euler transformation of the twiddle factor in non-iterative DFT calculation;
at least 20 memory cells are arranged in each read-write double-port random access memory.
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| JP2009270895A (en) * | 2008-05-02 | 2009-11-19 | Advantest Corp | Sampling device and testing device |
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