CN114709190A - 包括背面导通孔的集成电路及其制造方法 - Google Patents

包括背面导通孔的集成电路及其制造方法 Download PDF

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CN114709190A
CN114709190A CN202210047968.4A CN202210047968A CN114709190A CN 114709190 A CN114709190 A CN 114709190A CN 202210047968 A CN202210047968 A CN 202210047968A CN 114709190 A CN114709190 A CN 114709190A
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layer
semiconductor
wafer
fully
gate transistor
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程仲良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路包括与第二芯片接合的第一芯片。第一芯片包括衬底上的全环绕栅极晶体管。第一芯片包括从衬底延伸到全环绕栅极晶体管的背面导通孔。第二芯片包括通过背面导通孔电连接到晶体管的电子线路。

Description

包括背面导通孔的集成电路及其制造方法
技术领域
本发明涉及一种包括背面导通孔的集成电路及其制造方法。
背景技术
对提高电子装置(包括智能手机、平板电脑、台式计算机、膝上型计 算机和许多其他类型的电子装置)的计算能力的需求一直存在。在集成电 路中增加计算能力的一种方法是增加给定半导体衬底区域可以包含的晶 体管和其他集成电路特征的数量。
为了在集成电路中继续减小特征的尺寸，实施了各种薄膜沉积技术、 刻蚀技术和其他处理技术。这些技术可以形成非常小的特征。然而，这些 技术在确保特征正确形成方面也面临着严重的困难。
许多集成电路包括存储器阵列。集成电路特征大小的减小扩展到存储 器阵列的存储器单元。然而，以越来越小的技术节点形成有效的存储单元 可能很困难。
发明内容
在一实施例中，集成电路包括第一芯片。第一芯片包括衬底、在衬底 上并具有源极区的第一全环绕栅极晶体管以及通过衬底延伸到源极区的 背面导通孔。
在一实施例中，方法包括在第一晶片中的半导体衬底上形成第一全环 绕栅极晶体管。半导体衬底包括第一半导体层、第一半导体层上的刻蚀停 止层和刻蚀停止层上的第二半导体层。方法包括形成通过半导体衬底延伸 到第一全环绕栅极晶体管的源极区的背面导通孔并将第二晶片接合到半 导体衬底。
在一实施例中，方法包括在第一晶片中的半导体衬底上形成第一全环 绕栅极晶体管并去除半导体衬底。方法包括沉积介电层以代替半导体衬底 并形成穿过介电层并接触第一全环绕栅极晶体管的源极区的背面导通孔。
附图说明
结合附图阅读以下详细描述会最好地理解本揭露的各方面。应注意，根 据业界中的标准惯例，各个特征未按比例绘制。实际上，为了论述清楚起见， 可任意增大或减小各个特征的尺寸。
图1是集成电路的框图，根据一些实施例。
图2A-2P是根据一些实施例的在制造过程的各个阶段的集成电路的横 截面图。
图3A-3H是根据一些实施例的在制造过程的各个阶段的集成电路的 横截面图。
图4是根据一些实施例的多个晶片结合在一起的图示。
图5A是根据一些实施例的半导体工艺系统的控制系统的框图。
图5B是根据一些实施例的分析模型的框图。
图6是根据实施例的用于操作电子装置的方法的流程图。
图7是根据实施例的用于操作电子装置的方法的流程图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或 实例。下文描述组件和布置的具体实例以简化本揭露。当然，这些仅为实例 且并不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上 方或第二特征上的形成可包含第一特征与第二特征直接接触地形成的实施 例，且还可包含额外特征可在第一特征与第二特征之间形成以使得第一特征 与第二特征可不直接接触的实施例。另外，本揭露可在各种实例中重复附图 标号和/或字母。此重复是出于简化和清楚的目的，且本身并不指示所论述的 各种实施例和/或配置之间的关系。
另外，为易于描述，本文中可使用例如“在…下面”、“在…下方”、“下部”、 “在…上方”、“上部”等空间相对术语来描述如图式中所示出的一个元件或特 征与另一(些)元件或特征的关系。除图式中所描绘的定向外，空间相对术 语意图涵盖器件在使用或操作中的不同定向。装置可以其它方式定向(旋转 90度或处于其它定向)，且本文中所使用的空间相对描述词可同样相应地进 行解释。
在以下描述中，阐述了某些具体细节以提供对本揭露的各种实施例的 透彻理解。然而，本领域技术人员将理解，可以在没有这些具体细节的情 况下实践本揭露。在其他情况下，与电子元件和制造技术相关的众所周知 的结构没有被详细描述，以避免不必要地模糊本揭露的实施例的描述。
除非上下文另有要求，在整个说明书和随后的权利要求书中，词语“包 含”及其变体应被解释为开放的、包容性的，即“包含，但不限于”。
第一、第二和第三等序数的使用并不一定意味着排序的顺序感，而可 能只是区分一个动作或结构的多个实例。
本说明书中对“一个实施例”或“一实施例”的引用是指特定的特征、结 构或结合实施例描述的特征包括在至少一个实施例中。因此，本说明书各 处出现的短语“在一些实施例中”或“在一实施例中”不一定都指代相同的实 施例。此外，特定的特征、结构或特性可以以任何合适的方式组合成一个 或多个实施例。
除非内容另有明确规定，否则术语“或”通常以其包括“和/或”的含义使 用。
本揭露中的实施例为集成电路提供了全环绕栅极晶体管的密集阵列。 全环绕栅极晶体管形成在半导体衬底上方的第一晶片中，其包括相邻半导 体层之间的刻蚀停止层。全环绕栅极晶体管形成后，翻转第一晶片。从第 一晶片的背面通过半导体衬底形成背面导通孔，以接触晶体管的源极区和 漏极区。然后将第二晶片接合到第一晶片。第二晶片包括电子线路。电子 线路通过导电的背面通孔与晶体管电连接。半导体衬底中的刻蚀停止层有助于确保半导体衬底不会发生过刻蚀，从而保护全环绕栅极晶体管。
背面导通孔提供了许多好处。举例来说、存储器阵列或传感器阵列等 电子线路形成在第二晶片中，而逻辑晶体管则形成在第一晶片中。这使得 晶体管在第一晶片中形成高密度成为可能。由于刻蚀停止层可防止过度刻 蚀，因此可确保全环绕栅极晶体管的正常功能。集成电路的性能更高，报 废的晶片更少，从而导致更高的产量。
图1是根据一些实施例的集成电路100框图。集成电路100包括第一 晶片101和第二晶片105。第一晶片包括逻辑晶体管107。第二晶片包括 电子线路111。第一晶片101包括将逻辑晶体管107电连接到电子线路111 的背面导通孔109。如下文将更详细地阐述的，背面通孔109以降低损坏 逻辑晶体管107的风险的方式形成。
逻辑晶体管107可以包括纳米结构晶体管。每个纳米结构晶体管可以 包括充当晶体管的沟道区的多个纳米结构。纳米结构可以包括半导体纳米 片、半导体纳米线或其他类型的纳米结构。纳米结构晶体管可以包括全环 绕栅极晶体管。每个全环绕栅极晶体管包括一个或多个围绕半导体纳米结 构的栅极金属，栅极介电材料位于半导体纳米结构和栅极金属之间。在不 脱离本揭露的范围的情况下，逻辑晶体管107可以包括其他类型的晶体管。
全环绕栅极晶体管结构可由任何合适的方法图案化。举例来说，可以 使用一种或多种光刻工艺对结构进行图案化，光刻工艺包括双重图案化或 多重图案化工艺。通常，双重图案化或多重图案化工艺结合了光刻和自对 准工艺，允许创造例如具有间距小于使用单一且直接的光刻工艺可获得的 间距的图案。
电子线路111可以包括一个或多个存储器阵列。存储器阵列可包括磁 性随机存取存储器(MRAM)单元、电阻式随机存取存储器(RRAM)单元、 相变随机存取存储器(PCRAM)单元、动态随机存取存储器(DRAM)单元、 闪存单元、或其他类型的存储单元。电子线路111可以包括图像传感器或 其他类型的传感器。由于电子线路111定位在第二晶片105中，第一晶片 101可以主要保留给逻辑晶体管107，使得逻辑晶体管107在第一晶片101 中密集形成。
第一晶片101包括将逻辑晶体管107电连接到电子线路111的背面通 孔109。背面通孔109通过第一晶片101的背面衬底形成以电连接到逻辑 晶体管107的源极区和漏极区。因此，在图1所示的方向上，第一晶片101 已翻转，使第一晶片101的背面朝上。
在第一晶片101中形成逻辑晶体管107后，将第一晶片101翻转，使 背面衬底朝上。背面衬底最初包括第一厚的半导体层，第二薄的半导体层， 以及位于第一半导体层和第二半导体层之间的刻蚀停止层。在翻转第一晶 片之后，第一厚的半导体层将被刻蚀，这样第一半导体层不是被大部分移 除，就是被完全移除，这取决于特定的工艺。刻蚀停止层的存在有助于确 保不会发生过度刻蚀。因为第一半导体层很厚，所以用比较长的刻蚀工艺 来完全或大部分去掉第一半导体层。由于这个刻蚀工艺的持续时间长，在 刻蚀工艺的过程中可能会有一些不均匀的刻蚀。如果刻蚀停止层不存在， 这种不均匀的刻蚀会完全刻蚀穿过部分的第一和第二半导体层，并可能损 坏逻辑晶体管107。刻蚀停止层的存在保证了第一厚半导体层的刻蚀不会 损坏逻辑晶体管107，因为刻蚀工艺不会刻蚀刻蚀停止层。
在一些实施例中，第一半导体层仅被部分移除。背面通孔109已经形 成通过第一半导体层、刻蚀停止层和第二半导体层的剩余部分以接触逻辑 晶体管107的源极区和漏极区。在这种情况下，背面通孔109可以称为“硅 通孔”或“半导体通孔”。
在一些实施例中，第一半导体层被完全移除。完全移除第一半导体层 后，移除刻蚀停止层。刻蚀停止层移除后，第二薄半导体层被小心的移除。 由于第二半导体层非常薄，因此可以使用短且经过精心控制的刻蚀工艺来 移除第二薄半导体层，而不会损坏逻辑晶体管107。第二薄的半导体层移 除后，在第一晶片101的背面上形成介电层以代替半导体衬底。背面通孔 109形成通过介电层以接触逻辑晶体管107的源极区和漏极区。在这种情 况下，背面通孔109可以被称为“氧化物通孔”或“电介质通孔”。
在一些实施例中，刻蚀停止层是介电层。在图举例来说中，半导体衬 底可以是绝缘体上半导体(semiconductor on insulator,SOI)衬底。这可能包括 单晶硅的第一厚的层、二氧化硅的刻蚀停止层和单晶硅的第二薄的层。在 不脱离本揭露的范围的情况下，其他半导体和介电材料可用于SOI衬底。
在一些实施例中，刻蚀停止层是与第一和第二半导体层不同的材料的 半导体层。举例来说、第一和第二半导体层可以是单晶硅。刻蚀停止层可 以是硅锗，所述硅锗的成分可以使得单晶硅相对于所述硅锗选择性地被刻 蚀。在不脱离本揭露的范围的情况下，其他半导体材料可用于半导体层和 刻蚀停止层。
背面通孔109形成后，第二晶片105与第一晶片101的背面接合。第 二晶片105可以包括在晶片接合工艺期间物理接触背面通孔109的导电表 面结构。导电表面结构和背面通孔109实现逻辑晶体管107和电子线路111 之间的电连接。
在一些实施例中，集成电路100可能包括一个载体晶片103。在翻转 第一晶片101之前，将载体晶片103接合到第一晶片101的正面。
图1指的是第一和第二“晶片”，因为逻辑晶体管107、背面通孔109 和电子线路最初是在未切割的晶片中形成，然后接合在一起。在晶片接合 过程之后，单个集成电路100将从接合的晶片上切下。每个集成电路100 将包括第一晶片101的芯片和第二晶片105的芯片。因此，最终封装的集 成电路100将不包括整个第一和第二晶片，而是包括第一和第二晶片中的 芯片。
图2A-2P是根据一些实施例的在制造过程的各个阶段的集成电路100 的横截面图。图2A-2P示出了用于形成图1的集成电路100的工艺的一个 示例。更具体地，图2A-2P示出了示例性的工艺，用于生产集成电路100， 包括第一晶片中的逻辑晶体管，并将第一晶片接合到第二晶片，第二晶片 包括电连接到逻辑晶体管的电子线路。图2A-2P示出了如何根据本揭露的 原理以简单有效的工艺形成集成电路100。在不脱离本揭露的范围的情况 下，可以使用其他工艺步骤和工艺步骤的组合。
图2A是根据一些实施例在制造过程的中间阶段的集成电路100的横 截面图。在图2A中，集成电路100包括第一晶片101。如下文将更详细 地阐述，全环绕栅极晶体管将在第一晶片101中形成。
第一晶片101包括半导体衬底106。在图2A的例子中，半导体衬底 106包括第一半导体层112、第一半导体层112上的刻蚀停止层114和刻 蚀停止层112上的第二半导体层116。在一些实施例中，第一半导体层112 和第二半导体层116包括硅。然而，本揭露中的实施例不限于此，并且在 各种实施例中，第一半导体层112和第二半导体层116可以包括任何合适 的半导体材料。第一半导体层112、第二半导体层116和刻蚀停止层114 可以共同充当半导体衬底106。
在一些实施例中，半导体衬底106在SOI衬底中。在这种情况下，刻 蚀停止层114可以包括二氧化硅或其他电介质。选择刻蚀停止层114中的 材料使得第一半导体层112和第二半导体层116相对于刻蚀停止层114是 可选择性刻蚀的。刻蚀停止层114相对于第一半导体层112和第二半导体 层116也是可选择性刻蚀的。
在一些实施例中，刻蚀停止层114是半导体材料。选择刻蚀停止层114 的半导体材料使得第一半导体层112和第二半导体层116相对于刻蚀停止 层114是可选择性刻蚀的。刻蚀停止层114相对于第一半导体层112和第 二半导体层116也是可选择性刻蚀的。
在不脱离本揭露的范围的情况下，半导体衬底106可以包括与图2A 中所示和上面描述的那些的不同层数的不同的半导体材料。半导体衬底 106可以包括各种掺杂区，包括N型和P型掺杂剂。N型掺杂剂可包括磷。 P型掺杂剂可以包括硼。在不脱离本揭露的范围的情况下，可以使用其他 类型的掺杂剂。
与刻蚀停止层114和第二半导体层116相比，第一半导体层112非常 厚。举例来说，第一半导体层可以具有介于10μm和700μm之间的初始厚 度。通常，第一半导体层112可以具有大于500μm的初始厚度。刻蚀停止 层114和第二半导体层116可以各自具有在30纳米和500纳米之间厚度。 如下文将更详细地阐述，在随后的步骤中，第一半导体层112可被完全或 大部分刻蚀掉。刻蚀停止层114的存在有助于防止在第一半导体层112的 刻蚀期间损坏其他敏感的结构。
在图2B中，在半导体衬底106上方形成第一晶体管102和第二晶体 管104。第一晶体管102和第二晶体管104具有相同类型的结构并且共享 源端/漏端。因此，虽然主要为第一晶体管102中的结构提供参考编号，但 第二晶体管104具有相同或可比较的结构。
第一晶体管102是全环绕栅极晶体管。晶体管102包括多个半导体纳 米片120或纳米线。半导体纳米片120是半导体材料的层。半导体纳米片 120对应于晶体管102的沟道区域。半导体纳米片120形成在衬底106上 方，并且可以形成在半导体衬底106上。半导体纳米片120可以包括Si、 Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb 或InP中的一种或多种层。在一些实施例中，半导体纳米片120与第二半 导体层116是相同的半导体材料。在不脱离本揭露的范围的情况下，可以 将其他半导体材料用于半导体纳米片120。
在一些实施例中，半导体纳米片120是通过从第二半导体层116交替 外延生长工艺形成的。举例来说，第一外延生长工艺可能导致在第二半导 体层116的顶面上形成牺牲半导体纳米片。第二外延生长工艺可能导致在 牺牲半导体纳米片上形成半导体纳米片120。交替进行外延生长工艺，直 到形成选定数量的半导体纳米片120和牺牲半导体纳米片。
在形成半导体纳米片120和半导体纳米片120之间的牺牲纳米片后， 去除牺牲纳米片。去除牺牲纳米片会导致半导体纳米片120之间出现间隙。
在图2B中，晶体管102有四个半导体纳米片120。然而，在实践中， 晶体管102可能具有四个之外的其他数量的半导体纳米片120。与举例来 说不同，晶体管102在一些实施例中可能包括三个到二十个半导体纳米片 120。在不脱离本揭露的范围的情况下，可以使用其他数量的半导体纳米 片120。
半导体纳米片120可以有在2纳米和100纳米之间的厚度。在一些实 施例中，半导体纳米片120有在2纳米和20纳米之间的厚度。该范围提 供合适的半导体纳米片电导率，同时保持低厚度。在一些实施例中，每个 纳米片120比其上方的(多个)半导体纳米片120更厚。在不脱离本揭露范 围的情况下，半导体纳米片120可以有其他厚度。
在一些实施例中，底介电层131可能位于底部半导体纳米片120和第 二半导体层116之间。底介电层131可以包括氮化硅或其他合适的材料。
片内间隔层128位于半导体纳米片120之间。片内间隔层128可以通 过ALD工艺、CVD工艺或其他合适的工艺沉积。在一个示例中，片内间 隔层128包括氮化硅。
半导体纳米片120在源极区和漏极区130之间延伸。源极区和漏极区 130包括半导体材料。源极区和漏极区130可以从半导体纳米片120或第 二半导体层116外延生长。在N型晶体管的情况下，源极区和漏极区130 可以掺杂有N型掺杂剂物种。在P型晶体管的情况下，源极区和漏极区 130可以掺杂有P型掺杂剂物种。可以在外延生长期间进行原位(in-situ)掺杂。虽然源极区和漏极区130标有相同的参考编号和标号，但实际上， 晶体管102将具有源极区域和漏极区。举例来说，晶体管102左侧的区域 130可以对应于晶体管102的源极，而晶体管102右侧的区域130可以对 应于晶体管102的漏极。或者，漏极可在左侧而源极可在右侧。
层间介电层132位于源极区和漏极区130上方。层间介电层132可以 包括氧化硅。层间介电层132可以通过CVD、ALD或其他合适的工艺沉 积。在不脱离本揭露的范围的情况下，其他材料和工艺可以用于层间介电 层132。
栅极间隔件126位于半导体纳米片120上方的层间介电层132中形成 的栅电极沟槽的侧壁上。栅极间隔件126在一些实施例中包括SiCON。栅 极间隔件126可以通过CVD、PVD或ALD沉积。在不脱离本揭露的范围 的情况下，可以将其他材料和沉积工艺用于栅极间隔件126。
尽管在图2B中未示出，但是在半导体纳米片120的表面上形成了薄 的界面介电层。界面介电层可包括介电材料，例如氧化硅、氮化硅或其他 合适的介电材料。界面介电层可以通过热氧化工艺、CVD工艺或ALD工 艺形成。界面介电层可以有介于0.5纳米和2纳米之间的厚度。在不脱离 本揭露的范围的情况下，其他材料、沉积工艺和厚度可用于界面介电层。
界面介电层围绕着半导体纳米片120。特别地，半导体纳米片120具 有对应于在源极区和漏极区130之间延伸的板条或线的形状。界面介电层 环绕每个半导体纳米片120。界面介电层环绕或部分环绕半导体纳米片 120。
虽然在图、2B中未示出，但是在界面介电层上、在栅极间隔件126 的侧壁上以及在片内间隔件128的侧壁上形成了高K栅极介电层。高K 栅极介电层和界面介电层一起对应于晶体管102的栅极电介质。除了界面 介电层介于半导体纳米片120和高K栅极介电层之间之外，高K介电层 以与界面介电层相关的描述相同的方式包围或部分包围半导体纳米片120。
高K栅极介电层包括一种或多种层介电材料，例如HfO2、HfSiO、 HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪- 氧化铝(HfO2-Al2O3)合金、其他合适的高K介电材料材料和/或其组合。高 K栅极介电层可以通过CVD、ALD或任何合适的方法形成。在一些实施 例中，高K栅极介电层是使用高度保形沉积工艺(例如ALD)形成的， 以确保形成每个半导体纳米片120周围具有均匀的厚度的栅极介电层。在 一些实施例中，高K介电层的厚度在约1纳米至约4纳米的范围内。在不 脱离本揭露的范围的情况下，其他厚度、沉积工艺和材料可用于高K栅极 介电层。
栅电极148填充半导体纳米片120和栅极间隔件126之间半导体纳米 片120上方的沟槽之间的剩余空间。栅电极148可以包括栅极金属的多个 个别的层。可以选择栅极金属的各种层中的材料和厚度，以提供所需的晶 体管102阈值电压。栅电极148可以包括衬于栅极间隔件126且覆盖半导 体纳米片120上的栅极电介质的氮化钛140的层。
栅电极148包括金属层140和位于沟槽中的金属层140上且在半导体 纳米片120之间的栅极填充材料146。在一实例中，栅极填充材料146包 括钨。栅极填充材料146可以使用PVD、ALD、CVD或其他合适的沉积 工艺来沉积。栅极填充材料146填充沟槽中和半导体纳米片120之间的剩 余空间。栅极填充材料具有高导电性。
金属层140和栅极填充材料146以与上述关于界面介电层和高K栅极 介电层相同的方式围绕或部分围绕半导体纳米片120，除了界面介电层和 高K栅极介电层位于半导体纳米片120和金属层140以及栅极填充材料 146之间。
在图2C中，在层间介电层132上形成介电层150。介电层150可以包 括氮化硅或其他类型的介电材料。介电层150可以通过CVD、PVD或ALD 沉积。层间介电层152已沉积在介电层150上。层间介电层152可以包括 氧化硅。层间介电层152可以通过CVD、ALD或其他合适的工艺沉积。 在不脱离本揭露的范围的情况下，其他材料和工艺可以用于层间介电层 152。
在层间介电层152中形成接触插塞154。接触插塞154与晶体管102 的栅电极148电接触。接触插塞154可以包括钨或其他合适的导电材料。
在层间介电层152上形成介电层156。介电层156可以包括氮化硅或 其他类型的介电材料。介电层156可以通过CVD、PVD或ALD沉积。层 间介电层158已沉积在介电层150上。层间介电层158可以包括氧化硅。 层间介电层158可以通过CVD、ALD或其他合适的工艺沉积。在不脱离 本揭露的范围的情况下，其他材料和工艺可以用于层间介电层158。
在层间介电层158中形成金属线160。金属线160与接触插塞154接 触。金属线160可以包括铜或其他合适的导电材料。
接合介电层162已沉积在介电层158和信号线160上。接合介电层162 用于将第一晶片101接合到载体晶片，如下文将更详细地描述。接合介电 层162可以包括氧化硅。接合层162可以通过高密度等离子体沉积形成， 因此可以称为高密度等离子体氧化物。在不脱离本揭露的范围的情况下， 接合介电层162可以包括其他材料和沉积工艺。
在沉积接合介电层162之后，在接合介电层162上执行化学机械平坦 化(CMP)工艺。执行CMP工艺以准备用于晶片接合工艺的晶片101，如下 文将更详细地阐述。
晶片101可以包括比图2C中显示的更多层级的层间介电层、导电插 塞和金属线。接合介电层162可能形成在最后的层间介电层上。
如本文所述，可以说晶片101具有前端和后端。传统上，后端对应于 块状半导体衬底。在这种情况下，衬底106可以称为第一晶片101的后端 或背面。晶片101所在的接合介电层164的一侧可以称为晶片103的前端 或前侧。
在图2D中，载体晶片103已接合到第一晶片101。接合介电层164 可以形成在载体晶片103上。或者，接合介电层164可以是载体晶片103 的一部分。在将载体晶片103接合到第一晶片101之前，接合介电层164 可以进行CMP工艺。将载体晶片103接合到第一晶片101可以包括将接 合介电层164接合到接合介电层162。载体晶片103可以包括半导体材料。 在一些实施例中，载体晶片103包括硅。载体晶片103可以包括绝缘体上 硅(SOI)结构。载体晶片能够翻转第一晶片101，从而可以在背面或第一晶 片101的后端形成额外的结构，如下文将更详细地阐述。
晶片接合工艺可以包括在接合介电层162与接合介电层164接触之后 执行热退火工艺。热退火工艺可导致接合介电层162或接合介电层164表 面的官能团结合在一起。举例来说，官能团可包括OH。接合过程导致形 成代替官能团的SiO2。或者，可以执行其他类型的晶片接合工艺。其他技 术可包括直接接合、表面活化接合、阳极接合、共晶接合、反应接合或其 他合适的接合工艺。晶片接合工艺导致了第一晶片101接合到载体晶片 103。
在图2E中，集成电路100已相对于图2A-2D中所示的位置翻转。载 体晶片103现在在底部。第一晶片101的后端，尤其是第一半导体层112， 现在位于顶部。这个位置允许在晶片101的后端执行进一步的工艺。如下 文将更详细地阐述，另外的工艺包括形成背面导通孔。
在图2F中，已经执行了刻蚀工艺以减少第一半导体层112的厚度。 如前所述，第一半导体层112可能有数百微米厚。如果通过第一半导体层 112形成背面导通孔而第一半导体层112是数百微米厚，那么背面导通孔 可能具有相对较高的电阻并且可能使用大量昂贵的导电材料。因此，在形 成背面导通孔之前，执行刻蚀工艺以减少第一半导体层112的厚度。
由于刻蚀工艺的长度，可能会在某些位置发生过刻蚀，并且会损坏源 极区和漏极区130和半导体纳米片120。刻蚀停止层114有助于确保不会 发生这种过度刻蚀。这是因为刻蚀工艺相对于刻蚀停止层114选择性地刻 蚀了第一半导体层112。因此，不会发生过刻蚀。在一些实施例中，第一 半导体层112最初的厚度超过100μm。第一半导体层112的最终厚度小于 10μm。这样的最终厚度可以足够薄以提供低电阻背面导通孔。在一些实施 例中，第一半导体层112中剩余的厚度介于0.5μm和6μm之间。在不脱 离本揭露的范围的情况下，可以利用其他剩余的厚度。
在图2F中，介电层166已沉积在第一半导体层112的其余部分。介 电层166可以包括SiCN并且具有在50纳米和100纳米之间的厚度。介电 层166还可包括在SiCN上的氧化硅。介电层166可以通过ALD、CVD 或PVD沉积。在不脱离本揭露的范围的情况下，可以使用其他厚度、材 料和沉积工艺。
在图2F中，介电层166上已形成了光刻胶167的层。光刻胶167的 层已使用光刻工艺进行图案化。光刻胶167的层的图案对应于将在半导体 衬底106中形成的背面导通孔的图案。
在图2G中，在介电层166、第一半导体层112、刻蚀停止层114和第 二半导体层116中已经形成了开口169。开口169暴露了晶体管102和晶 体管104的共同的源极区/漏极区130。开口169可以通过刻蚀工艺的组合 形成，包括一种或多种湿刻蚀、一种或多种干刻蚀、或其他刻蚀工艺。选 择刻蚀工艺的组合以确保刻蚀半导体衬底106的每个层以暴露源极区/漏 极区130。开口169可以称为孔、沟槽或通孔。如本文所用，通孔可对应 于尚未填充导电材料的开口。导电通孔可以对应于已经填充有导电材料的 开口。在图2H中，光刻胶167的层已被移除。
在图2I中，介电衬层171已经形成在开口169的侧壁上。介电衬层 171可包括氮化硅、SiC、SiCN或其他合适的材料。介电衬层171可以通 过ALD、CVD、PVD或其他合适的工艺沉积。在不脱离本揭露的范围的 情况下，介电衬层171可以包括其他材料和沉积工艺。
在图2J中，已在暴露的源极区/漏极区130上形成硅化物173。硅化 物173作为与源极区/漏极区130的半导体材料的电接触件。硅化物173 可以通过沉积钛和氮化钛然后进行热退火工艺来形成。硅化物173可以包 括TiSi、CoSi、NiSi、TaSi、PtSl、WSi、MoSi或CuSi。热退火工艺完成 后，形成硅化物173。在这种情况下，硅化物173是钛硅化物。在不脱离 本揭露的范围的情况下，可以利用其他工艺和材料来形成硅化物173。
在图2J中，已完成了一个背面导通孔109。特别是在开口169中已形 成了导电插塞168。导电插塞168填充开口169。导电插塞168与硅化物 173接触。导电插塞168可以包括Co、W、Al、Cu、Mo、Ru。Ir、Au、 Ag、Sn、Ni、Fe、RuO2、IrO2、Ti、TiAl、Pt或其他合适的材料。导电插塞168可以通过PVD、ALD、CVD或其他合适的工艺沉积。
在图2K中，第二晶片105已与第一晶片101结合。第二晶片105可 以包括电子线路111(参见图1)。电子线路111可以包括存储器阵列、 传感器电路或其他类型的电子线路。第二晶片105包括接合介电层175。 金属结构179形成于接合介电层175中。金属结构179与第一晶片101的 背面导通孔109电接触。金属结构179和背面导通孔109将第一晶片101 的晶体管102和104电气连接到第二晶片105的电子线路111。实际上， 接合介电层175和金属结构179是第二晶片105的一部分。
介电层166可以对应于或可以包括接合介电层。因此，第一晶片101 通过介电层166与第二晶片105的接合介电层175接合而与第二晶片105 接合。接合工艺可以包括如关于图2D所描述的执行热退火工艺。在不脱 离本揭露的范围的情况下，可以使用其他工艺和材料将第二晶片105接合 到第一晶片101。
图2L-2P示出了形成连接到稍微不同的晶体管结构的背面导通孔109。 图2L的处理阶段对应于图2F的处理阶段。但是，在图2L的示例中，浅 沟渠隔离181将晶体管102的源极区/漏极区130与晶体管104的源极区/ 漏极区130分开。浅沟渠隔离可以包括氧化硅或其他合适的介电材料。因 此，在这种情况下，晶体管102和晶体管104不共用源极区/漏极区130。
在图2M中，开口169已在介电层166与然后的半导体衬底106的层 中形成。开口169暴露晶体管102的源极区/漏极区130、晶体管104的源 极区/漏极区130和浅沟渠隔离181。
在图2N中，介电衬层171已沉积在开口169的侧壁上。硅化物173 已在晶体管102和104的源极区/漏极区130上形成。在浅沟渠隔离181 上形成金属氮化物层183。金属氮化物层可以包括与浅沟渠隔离181的氮 化硅接合的硅化物173相同的金属。基于浅沟渠隔离181的材料和用于形 成硅化物173的材料，金属氮化物层183可以有其他材料。
在图2O中，背面导通孔109已通过在开口169中形成导电插塞168 而完成。导电插塞168与晶体管104和晶体管102两者的源极区和漏极区 130的硅化物173电接触。因此，背面导通孔109将晶体管102电连接到 晶体管104。
在图2P中，第二晶片105已与第一晶片101接合。第二晶片105包 括接合介电层175和与背面导通孔109电接触的金属结构179。
尽管图1-2P已经公开了背面导通孔109，但集成电路也可以包括以与 背面导通孔109相同的方式形成的背面金属线或金属槽。
图3A-3H根据一些实施例示出了用于形成背面导通孔109并将第一晶 片101接合到第二晶片105的工艺。图3A-3H图示了用于形成图1的集成 电路100的工艺的一个示例。图3A的视图对应于与图2E相同的处理阶段。
在图3B中，第一半导体层112已被完全移除。第一半导体层112可 以通过一个或多个工艺去除，工艺包括湿刻蚀、干刻蚀和研磨工艺。刻蚀 工艺在刻蚀停止层114处停止。这是因为第一半导体层112的材料相对于 刻蚀停止层114的材料是可选择性刻蚀的。刻蚀停止层114的存在可防止 可能损坏晶体管102和104的过度刻蚀。刻蚀停止层114的存在使得半导 体层112的刻蚀工艺能够更快地执行，因为不需要严格控制工艺参数来防 止过度刻蚀。
在图3C中，刻蚀停止层114已被移除。刻蚀停止层114可以用刻蚀 工艺去除，刻蚀工艺相对于第二半导体层116选择性刻蚀刻蚀停止层114。 刻蚀工艺可包括湿刻蚀和干刻蚀中的一种或多种。
在图3D中，第二半导体层112已被移除。第二半导体层112可以通 过刻蚀工艺去除，刻蚀工艺包括湿刻蚀和干刻蚀中的一种或多种。由于第 二半导体层112相对较薄，因此可以完全移除第二半导体层112，而不会 在某些位置产生可能会损坏晶体管102和晶体管104的较大的刻蚀变化风 险。控制时间的刻蚀足以去除半导体层112，而不会损坏晶体管102和晶 体管104。
在图3E中，介电层166已沉积。介电层166可以包括SiCN和氧化硅 层的组合。特别是，可以先沉积SiCN的层，然后是高密度等离子体沉积 的氧化硅。这样，介电层166就可以充当接合介电层。介电层166的厚度 可以在100纳米和5μm之间。在不脱离本揭露的范围的情况下，其他工艺、 厚度和材料可用于介电层166。
在图3F中，开口169已在介电层166中形成。尽管未在图3F中示出， 但可以通过沉积和图案化光刻胶167来形成开口169。因此，可以在如前 所述的图案化的光刻胶167的存在下刻蚀开口169。开口169暴露了晶体 管102和晶体管104共用的源极区/漏极区130。
在图3G中，背面导通孔109已形成。背面导通孔109是通过在开口 169的侧壁上沉积介电衬层171、在源极区/漏极区130上形成硅化物173 以及在开口169中形成导电插塞168来形成的，如前所述。在这种情况下， 背面导通孔109可以被认为是电介质通孔。
在图3H中，第二晶片105已以与前面所述相同的方式与第一晶片101 接合。接合介电层175的金属结构179是与背面导通孔109的物理和电接 触件。
图4是根据一些实施例示出了第一晶片101与载体晶片103和第二晶 片105接合。图2的视图示出了切割前的接合的晶片。切割线185显示在 第二晶片105上。切割线表示接合的晶片将如何切割成个别的集成电路 100。每个个别的集成电路100包括逻辑晶体管107、背面通孔109和电子 线路111。在集成电路从晶片101和晶片103中切出后，集成电路100可 以耦合到引线框架或其他衬底并封装在集成电路封装中。在不脱离本揭露 范围的情况下，集成电路100可以使用各种切割和封装技术、组件和系统。
图5A是根据一些实施例的用于控制原子层刻蚀(ALE)工艺的控制系 统500的框图。根据一些实施例，图5A的控制系统500被配置为在执行 ALE工艺时控制ALE刻蚀系统的操作以形成图1至4的集成电路100的 方面。在一些实施例中，控制系统500用于控制ALE工艺以形成如关于 图2B所述的晶体管102的栅电极148的金属层。特别地，ALE工艺可用 于严密控制栅电极148的金属层140或其他金属层和栅电极148的厚度和 高度。
虽然图5A和5B的描述主要针对栅电极148中的层的受控刻蚀，但受 控刻蚀工艺也可用于图案化其他薄膜。举例来说，受控刻蚀可用于图案化 各种栅极介电层或与全环绕栅极晶体管102相关联的其他层。此外，受控 刻蚀工艺可用于去除或减少半导体衬底106的层的厚度。
控制系统500利用机器学习来调整ALE系统的参数。控制系统500 可以在ALE运行之间甚至在ALE周期之间调整ALE系统的参数，以确保 栅电极148的一或多种栅极金属落在选定的规格内。
在一些实施例中，控制系统500包括分析模型502和训练模块504。 训练模块用机器学习程序训练分析模型502。机器学习程序训练分析模型 502以为ALE工艺选择参数，这将导致晶体管102的栅电极具有选定的特 征。尽管训练模块504被图示为与分析模型502分离，但实际上，训练模 块504可以是分析模型502的一部分。
控制系统500包括或存储训练集资料506。训练集资料506包括历史 栅极金属资料508和历史工艺条件资料510。历史栅极金属资料508包括 与由ALE工艺产生的栅电极相关的资料。历史工艺条件资料510包括在 刻蚀栅极金属的ALE工艺期间与工艺条件相关的资料。如下文将更详细 地阐述，训练模块504利用历史栅极金属资料508和历史工艺条件资料510 来使用机器学习程序训练分析模型502。
在一些实施例中，历史栅极金属资料508包括与先前刻蚀的栅极金属 的剩余厚度相关的资料。举例来说，在半导体制造工厂的运行过程中，可 能会在几个月或几年的时间内处理数千或数百万个半导体晶片。半导体晶 片中的每一个可以包括由ALE工艺刻蚀的栅极金属。在每个ALE工艺之 后，薄膜的厚度将作为质量控制工艺的一部分进行测量。历史栅极金属资 料508包括由ALE工艺刻蚀的栅极金属中的每一个的剩余厚度。因此， 对于由ALE工艺刻蚀的大量薄膜，历史栅极金属资料508可以包括厚度 资料。
在一些实施例中，历史栅极金属资料508还可以包括与薄膜刻蚀工艺 中间阶段的栅极金属的厚度相关的资料。举例来说，ALE工艺可包括大量 刻蚀循环，在此期间刻蚀栅极金属中的个别层。历史栅极金属资料508可 以包括在个别的刻蚀循环或刻蚀循环组之后的栅极金属的厚度资料。因 此，历史栅极金属资料508不仅包括在ALE工艺完成之后与栅极金属的 总厚度相关的资料，而且还可以包括在ALE工艺的各个阶段与栅极金属 的厚度相关的资料。
在一些实施例中，历史栅极金属资料508包括与由ALE工艺刻蚀的 剩余栅极金属的成分相关的资料。刻蚀栅极金属后，可以进行测量以确定 栅极金属的元素或分子组成。栅极金属中的成功刻蚀导致栅极金属包括特 定的剩余厚度。不成功的刻蚀工艺可能导致栅极金属不包括指定比例的元 素或化合物。历史栅极金属资料508可以包括来自指示构成各种栅极金属 的元素或化合物的测量值的资料。
在一些实施例中，历史工艺条件510包括与历史栅极金属资料508相 关联的刻蚀栅极金属的ALE工艺期间的各种工艺条件或参数。因此，对 于历史栅极金属资料508中具有资料的每个栅极金属，历史工艺条件资料 510可以包括在栅极金属的刻蚀期间存在的工艺条件或参数。举例来说， 历史工艺条件资料510可以包括与ALE工艺期间工艺室内的压力、温度 和流体流速相关的资料。
历史工艺条件资料510可以包括与ALE工艺期间流体源中的前驱物 材料的剩余量相关的资料。历史工艺条件资料510可以包括与ALE刻蚀 室的年份相关的资料、在ALE刻蚀室中已执行的刻蚀工艺的次数、自最 近的ALE刻蚀室的清洁周期以来在ALE刻蚀室中执行的刻蚀工艺的次数 或与ALE刻蚀腔室相关的其他资料。历史工艺条件资料510可以包括与在刻蚀工艺期间引入ALE刻蚀室的化合物或流体相关的资料。与化合物 相关的资料可以包括化合物的类型、化合物的相(固体、气体或液体)、 化合物的混合物或与引入到ALE刻蚀室中的化合物或流体相关的其他方 面。历史工艺条件资料510可以包括与ALE工艺期间ALE刻蚀室内的湿 度相关的资料。历史工艺条件资料510可以包括与相关于ALE刻蚀室的 光吸收、光吸附(light adsorption)和光反射相关的资料。历史工艺条件资料 510可以包括与在ALE工艺期间将化合物或流体运送到ALE刻蚀室中的 管道、管子或导管的长度相关的资料。历史工艺条件资料510可以包括与 在ALE工艺期间将化合物或流体携带到ALE刻蚀室中的载气的条件相关 的资料。
在一些实施例中，历史工艺条件资料510可以包括单一ALE工艺的 多个个别循环中的每一个的工艺条件。因此，历史工艺条件资料510可以 包括非常大量的用于ALE循环的工艺条件资料。
在一些实施例中，训练集资料506将历史栅极金属资料508与历史工 艺条件资料510联系起来。换句话说，与历史栅极金属资料508中的栅极 金属相关联的薄膜厚度、材料成分或晶体结构与与该刻蚀工艺相关联的工 艺条件资料相关联。如下文将更详细地阐述，标记的训练集资料可用于机 器学习程序以训练分析模型502以预测将产生正确地形成的栅极金属的半 导体工艺条件。
在一些实施例中，控制系统500包括处理资源512、存储器资源514 和通讯资源516。处理资源512可以包括一个或多个控制器或处理器。处 理资源512被配置为执行软件指令、工艺资料、做出薄膜刻蚀控制决策、 执行讯号处理讯从存储器读取资料、将资料写入存储器以及执行其他处理 操作。处理资源512可以包括位于ALE系统的站点或工厂处的物理处理 资源512。处理资源可以包括远离站点ALE系统或ALE系统所在的工厂 的虚拟处理资源512。处理资源512可以包括包括经由一个或多个云计算 平台存取的处理器和服务器的云端处理资源。
在一些实施例中，存储器资源514可以包括一个或多个计算机可读存 储器。存储器资源514配置为存储与控制系统及其构件的功能相关联的软 件指令，包括但不限于分析模型502。存储器资源514可以存储与控制系 统500及其构件的功能相关联的资料。资料可以包括训练集资料506、当 前工艺条件资料和与控制系统500或其任何一个构件的操作相关联的任何 其他资料。存储器资源514可以包括位于ALE系统的站点或工厂的物理 存储器资源。存储器资源可以包括远离ALE系统的站点或工厂的虚拟存 储器资源。存储器资源514可以包括通过一个或多个云计算平台存取的云 端存储器资源。
在一些实施例中，通讯资源可以包括使控制系统500能够与与ALE 系统相关联的设备进行通讯的资源。例如，通讯资源516可以包括有线和 无线通讯资源，使控制系统500能够接收与ALE系统相关联的传感器资 料并控制ALE系统的设备。通讯资源516可以使控制系统500能够控制 来自流体源以及来自净化源的流体或其他材料的流动。通讯资源516可以 使控制系统500控制加热器、电压源、阀门、排气通道、晶片传输设备以 及与ALE系统相关联的任何其他设备。通讯资源516可以使控制系统500 与远程系统通讯。通讯资源516可以包括或可以促进经由一个或多个网络 的通讯，例如有线网络、无线网络、互联网或内联网。通讯资源516可以 使控制系统500中的构件相互通讯。
在一些实施例中，分析模型502是通过处理资源512、存储器资源514 和通讯资源516来实现的。控制系统500可以是具有彼此远离并且远离 ALE系统的构件和资源以及位置的分散控制系统。
图5B是根据一些实施例的图5A的分析模型502的操作方面和训练方 面绘示的框图。分析模型502可用于为ALE系统执行的ALE工艺选择参 数，以形成图1至图4的集成电路100的方面。在一些实施例中，图5B 的分析模型502用于控制ALE工艺以形成关于图2B描述的栅电极148的 个别栅极金属层。
虽然分析模型502的描述主要针对栅极金属的形成或图案化，但分析 模型502可用于图案化晶体管102或相变存储器元件的其他材料。例如， 分析模型502可以控制ALE工艺以形成或图案化与栅电极148和顶部电 极162相关联的金属层。
如前所述，训练集资料506包括与先前执行的多个栅极金属刻蚀工艺 相关的资料。每个先前执行的栅极金属刻蚀工艺都发生在特定的工艺条件 中，并导致栅极金属具有特定的特性。每个先前执行的栅极金属刻蚀工艺 的工艺条件被格式化为相应的工艺条件向量552。工艺条件向量包括多个 资料栏位554。每个资料栏位554对应一个特定的工艺条件。
图5B的示例绘示了在训练程序期间将传递给分析模型502的单一工 艺条件向量552。在图5B的例子中，工艺条件向量552包括9个资料栏 位554。第一资料栏位554对应于先前执行的栅极金属刻蚀工艺期间的温 度。第二资料栏位554对应于先前执行的栅极金属刻蚀工艺期间的压力。 第三资料栏位554对应于先前执行的栅极金属刻蚀工艺期间的湿度。第四 资料栏位554对应于先前执行的栅极金属刻蚀工艺期间刻蚀材料的流量。 第五资料栏位554对应于先前执行的栅极金属刻蚀工艺期间刻蚀材料的相 (液体、固体或气体)。第六资料栏位554对应于先前执行的栅极金属刻 蚀工艺中使用的安瓿的年份。第七资料栏位554对应于先前执行的栅极金 属刻蚀工艺期间的晶片上的刻蚀面积的大小。第八资料栏位554对应于先 前执行的栅极金属刻蚀工艺期间使用的晶片的表面特征的密度。第九资料栏位对应于先前执行的栅极金属刻蚀工艺期间表面特征的侧壁的角度。在 实践中，在不脱离本揭露的范围的情况下，每个工艺条件向量552可以包 括比图5B绘示的更多或更少的资料栏位。在不脱离本揭露的范围的情况 下，每个工艺条件向量552可以包括不同类型的工艺条件。图5B绘示的 特定工艺条件仅作为示例给出。每个工艺条件由相应资料栏位554中的数 字值表示。对于不理所当然用数字表示的条件类型，例如材料相，可以为 每个可能的阶段分配一个数字。
分析模型502包括多个神经层556a至556e。每个神经层包括多个节 点558。每个节点558也可以称为一个神经元。第一神经层556a的每个节 点558接收工艺条件向量552的每个资料栏位的资料值。因此，在图5B 的示例中，自第一神经层556a的每个节点558接收九个资料值，因为工 艺条件向量552有九个资料栏位。每个神经元558包括在图5B中标记为 F(x)的相应内部数学函数。通过将内部数学函数F(x)应用到来自工艺条件 向量552的资料栏位554的资料值，第一神经层556a的每个节点558生 成标量值。下面提供了有关内部数学函数F(x)的更多细节。
第二神经层556b的每个节点558接收由第一神经层556a的每个节点 558生成的标量值。因此，在图5B的例子中，第二神经层556b的每个节 点接收四个标量值，因为在第一神经层556a中有四个节点558。通过将相 应的内部数学函数F(x)应用到来自第一神经层556a的标量值，第二神经 层556b的每个节点558生成标量值。
第三神经层556c的每个节点558接收由第二神经层556b的每个节点 558生成的标量值。因此，在图5B的例子中，第三神经层556c的每个节 点接收五个标量值，因为在第二神经层556b中有五个节点558。通过将相 应的内部数学函数F(x)应用到来自第二神经层556b的节点558的标量值， 第三神经层556c的每个节点558生成标量值。
神经层556d的每个节点558接收由前一个神经层(未示出)的每个 节点558生成的标量值。通过将相应的内部数学函数F(x)应用到来自前一 个神经层的节点558的标量值，神经层556d的每个节点558生成标量值。
最后的神经层只包含一个节点558。最后的神经层接收前一个神经层 556d的每个节点558生成的标量值。通过将数学函数F(x)应用于从神经层 556d的节点558接收到的标量值，最终神经层556e的节点558生成资料 值568。
在图5B的例子中，资料值568对应于栅极金属的预测剩余厚度，所 述栅极金属由对应工艺条件向量552中包含的值的工艺条件资料生成。在 其他实施例中，最后的神经层556e可以生成多个资料值，每个资料值对 应于特定的栅极金属特性，例如栅极金属晶体取向、栅极金属均匀性或栅 极金属的其他特性。最后的神经层556e将包括要生成的每个输出资料值 的相应节点558。在预测的栅极金属厚度的情况下，在一个示例中，工程 师可以提供约束，指定预测的栅极金属厚度568必须落在选定范围内，例 如介于0纳米和50纳米之间。分析模型502将调整内部函数F(x)以确保 与预测的栅极金属厚度对应的资料值568将落在指定范围内。
在机器学习程序期间，分析模型将资料值568中栅极金属的预测的剩 余厚度与实际剩余的厚度进行比较，如资料值570所示。如前所述，对于 每组资料历史工艺条件资料，训练集资料506包括指示由历史栅极金属刻 蚀工艺产生的栅极金属特性的栅极金属特性资料。因此，资料值570包括 由工艺条件向量552中反映的刻蚀工艺产生的栅极金属的实际剩余的厚 度。分析模型502将来自资料值568的预测剩余厚度与来自资料值570的 实际剩余厚度进行比较。分析模型502生成错误值572，错误值572表示 来自资料值568的预测剩余厚度与来自资料值570的实际剩余厚度之间的 误差或差异。错误值572用于训练分析模型502。
通过讨论内部数学函数F(x)可以更全面地理解分析模型502的训练。 虽然所有节点558都标有内部数学函数F(x)，但每个节点的数学函数F(x) 都是独特的。在一个示例中，每个内部数学函数具有以下形式：
F(x)＝x1*w1+x2*w2+…xn*wn+b。
在上面的等式中，每个值x1至xn对应于从前一个神经层中的节点558 接收的资料值，或者，在第一神经层556a的情况下，每个值x1至xn对应 于来自工艺条件向量552的资料栏位554的相应资料值。因此，对于给定 的节点，n等于前一个神经层中节点的数量。值w1至wn是标量权重值， 与之前层中的相应节点相关联。分析模型502选择权重值w1至wn的值。 常数b是一个标量偏置值，也可以乘以一个加权值。节点558生成的值是 根据权重值w1至wn。因此，每个节点558具有n个权重值w1至wn。尽 管上面没有显示，每个函数F(x)也可以包括一个激活函数(Activation Function)。上式中给出的总和乘以激活函数。激活函数的示例可以包括整 流线性单元(ReLU)函数、乙状(sigmoid)函数、双曲张力(hyperbolic tension) 函数或其他类型的激活函数。
在计算出错误值572后，分析模型502会为各种神经层556a至556e 的各种节点558调整权重值w1至wn。在分析模型502调整权重值w1至 wn后，分析模型502再提供工艺条件向量552给输入神经层556a。由于 分析模型502的各种节点558的权重值不同，因此预测的剩余厚度568将 不同于前一次的迭代。通过将实际剩余的厚度570与预测的剩余厚度568 进行比较，分析模型502再次生成错误值572。
分析模型502再次调整与各种节点558相关的权重值w1至wn。分析 模型502再次处理工艺条件向量552并生成预测的剩余厚度568和相关联 的错误值572。训练程序包括在迭代中调整权重值w1至wn，直到错误值 572最小化。
图5B绘示了单一工艺条件向量552被传递到分析模型502。在实践中， 训练程序包括通过将大量工艺条件向量552传递给分析模型502，为每个 工艺条件向量552生成预测的剩余厚度568，以及为每个预测的剩余厚度 生成相关的错误值572。训练程序还可以包括生成一个聚合的错误值，指 示一批工艺条件向量552的所有预测的剩余厚度的平均误差。分析模型 502在处理每批工艺条件向量552后调整权重值w1至wn。训练程序持续 进行，直到所有工艺条件向量552的平均误差小于选定的阈值容差。当平 均误差小于选定的阈值容差时，分析模型502训练完成，且分析模型被训 练为在工艺条件的基础上准确预测栅极金属的厚度。然后可以使用分析模 型502来预测栅极金属厚度，并选择可以产生所需的栅极金属厚度的工艺 条件。在使用训练模型502的期间，向经训练的分析模型502提供工艺条 件向量，工艺条件向量代表用于当前栅极金属刻蚀工艺的当前要执行的工 艺条件，并且在工艺条件向量552处具有相同格式。经训练的分析模型502 然后可以预测从那些工艺条件将产生的栅极金属的厚度。
已经相对于图5B描述了根据神经网络的分析模型502的特定示例。 然而，在不脱离本揭露的范围的情况下，可以利用其他类型的根据神经网 络的分析模型或不同于神经网络的类型的分析模型。此外，在不脱离本揭 露的范围的情况下，神经网络可以具有不同数量的神经层和不同数量的节 点。
图6是根据一些实施例用于形成集成电路的方法600的流程图。方法 600可以利用与图1-6相关的工艺、构件和系统。在步骤602，方法600 包括在第一晶片中的半导体衬底上形成第一全环绕栅极晶体管，其中半导 体衬底包括第一半导体层、第一半导体层上的刻蚀停止层和刻蚀停止层上 的第二半导体层。全环绕栅极晶体管的一个例子是图2B的全环绕栅极晶 体管102。第一晶片的一个例子是图2K的第一晶片101。半导体衬底的一 个例子是图2K的半导体衬底106。第一半导体层的一个例子是图2K的第 一半导体层112。刻蚀停止层的一个例子是图2K的刻蚀停止层114。第二 半导体层的一个例子是图2K的第二半导体层116。在步骤604，方法600 包括形成通过半导体衬底延伸到第一全环绕栅极晶体管的源极区的背面 导通孔。背面导通孔的一个例子是图2K的背面导通孔109。源极区的一 个例子是图2K的源极区130。在步骤606，方法600包括将第二晶片接合 到半导体衬底。第二晶片的一个例子是图2K的第二晶片105。
图7是根据一些实施例用于形成集成电路的方法700的流程图。方法 700可以利用与图1-6相关的工艺、构件和系统。在步骤702，方法700 包括在第一晶片中的半导体衬底上形成第一全环绕栅极晶体管。全环绕栅 极晶体管的一个例子是图3A的全环绕栅极晶体管102。半导体衬底的一 个例子是图3A的半导体衬底106。在步骤704，方法700包括移除半导体 衬底。在步骤706，方法700包括沉积介电层以代替半导体衬底。介电层 的一个例子是图3H的介电层166。在步骤708，方法700包括形成穿过介 电层并接触第一全环绕栅极晶体管的源极区的背面导通孔。
背面导通孔提供了许多好处。举例来说、电子线路等存储器阵列或传 感器阵列形成在第二晶片中，而逻辑晶体管则形成在第一晶片中。这使得 晶体管在第一晶片中形成高密度成为可能。由于刻蚀停止层可防止过度刻 蚀，因此可确保全环绕栅极晶体管的正常功能。集成电路的性能更高，报 废的晶片更少，从而导致更高的产量。
在一实施例中，集成电路包括第一芯片。第一芯片包括衬底、在衬底 上并具有源极区的第一全环绕栅极晶体管以及通过衬底延伸到源极区的 背面导通孔。在一实施例中，所述衬底包括：第一半导体层；所述第一半 导体层上的刻蚀停止层；以及所述刻蚀停止层上的第二半导体层，其中所 述导电通孔延伸通过所述第一半导体层、所述刻蚀停止层和所述第二半导 体层。在一实施例中，所述刻蚀停止层相对于所述第一半导体层和所述第 二半导体层是可以被选择性刻蚀的。在一实施例中，所述刻蚀停止层是介 电层。在一实施例中，所述刻蚀停止层是第三半导体层。在一实施例中， 集成电路还包括与所述第一芯片接合的第二芯片，且所述第二芯片包括电 子线路以及与所述背面导通孔接触并将所述第一全环绕栅极晶体管电连 接到所述电子线路的金属结构。在一实施例中，所述电子线路包括存储器 阵列。在一实施例中，所述第一芯片包括与所述第一全环绕栅极晶体管共 用所述源极区的第二全环绕栅极晶体管。在一实施例中，所述第一芯片包 第二全环绕栅极晶体管以及浅沟渠隔离，第二全环绕栅极晶体管具有源极 区，浅沟渠隔离分隔所述第一全环绕栅极晶体管的所述源极区和所述第二 全环绕栅极晶体管的所述源极区，其中所述背面导通孔接触所述第一全环 绕栅极晶体管的所述源极区和所述第二全环绕栅极晶体管的所述源极区。
在一实施例中，方法包括在第一晶片中的半导体衬底上形成第一全环 绕栅极晶体管。半导体衬底包括第一半导体层、第一半导体层上的刻蚀停 止层和刻蚀停止层上的第二半导体层。方法包括形成通过半导体衬底延伸 到第一全环绕栅极晶体管的源极区的背面导通孔并将第二晶片接合到半 导体衬底。在一实施例中，将所述第二晶片接合到所述半导体衬底包括将 所述第二晶片中的金属结构电连接到所述背面导通孔。在一实施例中，方法还包括在形成所述背面导通孔之前减少所述第一半导体层的厚度。在一 实施例中，将所述第一半导体层的厚度从大于100微米的初始厚度减小到 小于10微米的最终厚度。在一实施例中，方法还包括：在所述半导体衬 底上形成第二全环绕栅极晶体管；以及在所述第一全环绕栅极晶体管的所 述源极区和所述第二全环绕栅极晶体管的源极区之间形成浅沟渠隔离，其 中所述背面导通孔接触所述第一全环绕栅极晶体管的所述源极区和所述 第二全环绕栅极晶体管的所述源极区。在一实施例中，形成所述背面导通 孔包括：在所述第一半导体层、所述刻蚀停止层和所述第二半导体层中刻 蚀出开口，所述源极区暴露于所述开口中；在所述开口中的所述源极区上 形成硅化物；以及以导电插塞填充所述开口。
在一实施例中，方法包括在第一晶片中的半导体衬底上形成第一全环 绕栅极晶体管并去除半导体衬底。方法包括沉积介电层以代替半导体衬底 并形成穿过介电层并接触第一全环绕栅极晶体管的源极区的背面导通孔。
在一实施例中，移除所述半导体衬底包括：用第一刻蚀工艺移除所述 半导体衬底的第一半导体层；用第二刻蚀工艺移除所述半导体衬底的刻蚀 停止层；以及用第三刻蚀工艺移除所述半导体衬底中的第二半导体层。在 一实施例中，方法还包括通过所述第三刻蚀工艺暴露所述源区。在一实施 例中，方法还包括将第二晶片接合至所述第一晶片的所述介电层。在一实 施例中，方法还包括通过所述背面导通孔将所述第二晶片的电子线路电连接到所述第一全环绕栅极晶体管。
前文所概述的一些实施例的特征是用来让本领域技术人员更佳地理 解本揭露的态样。本领域技术人员应了解他们是可径以本揭露作为基础来 设计或修改与本文实施例具有相同目的且/或达成相同优势的其他工艺及 结构。本领域技术人员也应理解，这类均等的设计并不脱离本揭露的精神 和保护范围，且不背离本揭露的精神和保护范围的情况下，是有可能设计 出各种改变、替换和变更的设计。
上述各种实施例可以组合以提供进一步的实施例。如有必要，可以修 改实施例的方面，以采用各种专利、申请和出版物的概念来提供更进一步 的实施例。
根据以上详细描述，可以对实施例进行这些和其他改变。一般而言， 在权利要求中，所使用的术语不应被解释为将权利要求限制在说明书和权 利要求中公开的特定实施例，而应被解释为包括权利要求有权利的等效的 完整范围的所有可能的实施例。因此，权利要求不受本揭露的限制。

Claims (10)

1.一种集成电路，包括：
第一芯片，包括：
衬底；
第一全环绕栅极晶体管，在所述衬底上，且具有源极区；以及
背面导通孔，通过所述衬底延伸至所述源极区。
2.根据权利要求1所述的集成电路，其中所述衬底包括：
第一半导体层；
所述第一半导体层上的刻蚀停止层；以及
所述刻蚀停止层上的第二半导体层，其中所述导电通孔延伸通过所述第一半导体层、所述刻蚀停止层和所述第二半导体层。
3.根据权利要求1所述的集成电路，还包括与所述第一芯片接合的第二芯片，且所述第二芯片包括：
电子线路；以及
金属结构，与所述背面导通孔接触，并将所述第一全环绕栅极晶体管电连接到所述电子线路。
4.根据权利要求1所述的集成电路，其中所述第一芯片包括与所述第一全环绕栅极晶体管共用所述源极区的第二全环绕栅极晶体管。
5.根据权利要求1的所述集成电路，其中所述第一芯片包括：
第二全环绕栅极晶体管，具有源极区；以及
浅沟渠隔离，分隔所述第一全环绕栅极晶体管的所述源极区和所述第二全环绕栅极晶体管的所述源极区，其中所述背面导通孔接触所述第一全环绕栅极晶体管的所述源极区和所述第二全环绕栅极晶体管的所述源极区。
6.一种集成电路的制造方法，包括：
在第一晶片中的半导体衬底上形成第一全环绕栅极晶体管，其中所述半导体衬底包括第一半导体层、所述第一半导体层上的刻蚀停止层和所述刻蚀停止层上的第二半导体层；
形成通过所述半导体衬底延伸至所述第一全环绕栅极晶体管的源极区的背面导通孔；以及
将第二晶片接合到所述半导体衬底。
7.根据权利要求6所述的集成电路的制造方法，还包括：
在所述半导体衬底上形成第二全环绕栅极晶体管；以及
在所述第一全环绕栅极晶体管的所述源极区和所述第二全环绕栅极晶体管的源极区之间形成浅沟渠隔离，其中所述背面导通孔接触所述第一全环绕栅极晶体管的所述源极区和所述第二全环绕栅极晶体管的所述源极区。
8.根据权利要求6所述的集成电路的制造方法，其中形成所述背面导通孔包括：
在所述第一半导体层、所述刻蚀停止层和所述第二半导体层中刻蚀出开口，所述源极区暴露于所述开口中；
在所述开口中的所述源极区上形成硅化物；以及
以导电插塞填充所述开口。
9.一种集成电路的制造方法，包括：
在第一晶片中的半导体衬底上形成第一全环绕栅极晶体管；
移除所述半导体衬底；
沉积介电层以代替所述半导体衬底；以及
形成穿过所述介电层并接触所述第一全环绕栅极晶体管的源极区的背面导通孔。
10.根据权利要求9所述的集成电路的制造方法，还包括将第二晶片接合至所述第一晶片的所述介电层。
CN202210047968.4A 2021-03-12 2022-01-17 包括背面导通孔的集成电路及其制造方法 Pending CN114709190A (zh)

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