CN114708825A - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN114708825A CN114708825A CN202210430571.3A CN202210430571A CN114708825A CN 114708825 A CN114708825 A CN 114708825A CN 202210430571 A CN202210430571 A CN 202210430571A CN 114708825 A CN114708825 A CN 114708825A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
According to the pixel circuit and the display panel, the pixel circuit with the 6T3C structure is adopted to effectively compensate the threshold voltage of the driving transistor in the pixel, the compensation structure of the pixel circuit is simple, and the operation difficulty is low; the pixel circuit provided by the application is characterized in that a first power supply end and a second power supply end are both set to be in a first state mode and a second state mode, and the first power supply end and the second power supply end are connected with signals in the first state mode; in the second state mode, the second power supply terminal and the second power supply terminal are floating, so that part of the device can be omitted, and the compensation effect is ensured.
Description
Technical Field
The application relates to the field of display, in particular to a pixel circuit and a display panel.
Background
Light emitting devices such as Micro-LEDs (Micro light emitting diodes)/Mini-LEDs (Mini light emitting diodes) have the advantages of high brightness, high contrast, high color gamut, and the like, and are currently and rapidly applied to the field of novel displays.
In the driving backplane, pixels are arranged in a matrix including a plurality of rows and a plurality of columns, and each pixel is generally formed by two transistors and a capacitor, which is commonly referred to as a 2T1C circuit. However, the transistors have the problem of threshold voltage shift, so that the pixel circuit needs a corresponding compensation structure. At present, the compensation structure of the pixel circuit is complex, and the operation difficulty is high.
Disclosure of Invention
The application provides a pixel circuit and a display panel, which can solve the technical problems that the compensation structure of the existing pixel circuit is complex and the operation difficulty is high.
In a first aspect, the present application provides a pixel circuit comprising:
a light emitting device;
a first transistor having a source and a drain connected in series with the light emitting device between a first power supply terminal and a second power supply terminal;
a second transistor, one of a source and a drain of which is connected to one of a source and a drain of the first transistor, and the other of the source and the drain of which is connected to a gate of the first transistor;
a third transistor, one of a source and a drain of which is connected to a drain terminal, and the other of the source and the drain of which is connected to the second terminal of the first capacitor;
a first capacitor, a first end of the first capacitor being connected to the gate of the first transistor;
a fourth transistor, one of a source and a drain of which is connected to a reset terminal, and the other of the source and the drain of which is connected to the second terminal of the first capacitor;
a second capacitor, a first end of the second capacitor is connected with the grid electrode of the first transistor, and a second end of the second capacitor is connected with the other of the source electrode and the drain electrode of the first transistor; wherein,
the first power supply end and the second power supply end are both set to a first state mode and a second state mode; in the first state mode, the first power supply end and the second power supply end access signals; in the second state mode, the second power source terminal and the second power source terminal are floated.
In the pixel circuit provided by the application, the pixel circuit further comprises a data writing module;
the data writing module is electrically connected to a data terminal and the second terminal of the first capacitor, and the data writing module is used for outputting a data signal supplied by the data terminal to the second terminal of the first capacitor.
In the pixel circuit provided by the application, the data writing module comprises a fifth transistor, a sixth transistor and a third capacitor;
the fifth transistor and the sixth transistor are connected in series between the data terminal and the second terminal of the first capacitor; the first end of the third capacitor is connected between the fifth transistor and the sixth transistor, and the second end of the third capacitor is electrically connected with a ground terminal.
In the pixel circuit provided by the application, the driving timing sequence of the pixel circuit comprises a reset stage, a threshold stage, a writing stage and a light-emitting stage;
in the reset phase, the first transistor, the second transistor, and the fourth transistor are turned on, the third transistor, the fifth transistor, and the sixth transistor are turned off, the first power terminal is floating, and the second power terminal receives a signal;
in the threshold stage, the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on, the fifth transistor and the sixth transistor are turned off, and the first power source terminal and the second power source terminal are floated;
in the write phase, the first transistor and the fifth transistor are turned on, the second transistor, the third transistor, the fourth transistor and the sixth transistor are turned off, the first power terminal is floating, and the second power terminal is connected to a signal;
in the light emitting phase, the first transistor and the sixth transistor are turned on, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are turned off, and the first power source terminal and the second power source terminal are connected to a signal.
In the pixel circuit provided by the present application, in the reset phase, the reset terminal outputs a ground potential to the first terminal of the first capacitor through the fourth transistor, and the second power terminal outputs a first potential to the second terminal of the first capacitor through the first transistor and the second transistor.
In the pixel circuit provided by the present application, in the threshold stage, the potential of the gate of the first transistor leaks to the drain terminal through the second transistor, the first transistor, and the third transistor until the first transistor is turned off, and the potential of the drain terminal is the ground potential.
In the pixel circuit provided by the present application, in the writing phase, the data potential stored in the third capacitor is output to the first end of the first capacitor through the fifth transistor.
In the pixel circuit provided by the application, in the light-emitting stage, the data terminal stores a data potential in the third capacitor, and the light-emitting device emits light.
In the pixel circuit provided by the application, the light emitting device is a micro light emitting diode or a mini light emitting diode.
In a second aspect, the present application further provides a display panel, which includes a plurality of pixel units arranged in an array, where each of the pixel units includes the pixel circuit described above.
According to the pixel circuit and the display panel, the threshold voltage of the driving transistor in the pixel is effectively compensated by adopting the pixel circuit with the 6T3C structure, the compensation structure of the pixel circuit is simple, and the operation difficulty is low; the pixel circuit provided by the application is characterized in that a first power supply end and a second power supply end are both set to be in a first state mode and a second state mode, and the first power supply end and the second power supply end are connected with signals in the first state mode; in the second state mode, the second power supply terminal and the second power supply terminal are floating, so that part of the device can be omitted, and the compensation effect is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a driving timing sequence of a pixel circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a state of a pixel circuit in a reset phase according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a state of a pixel circuit in a threshold stage according to an embodiment of the present disclosure;
FIG. 5 is a diagram illustrating a state of a pixel circuit in a write phase according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a state of a pixel circuit in a light-emitting stage according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating an effect of a pixel circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the source and the drain of the transistor used herein are symmetrical, the source and the drain can be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain.
In addition, the transistors used in the embodiments of the present application may include two types, i.e., a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pixel circuit 10 according to an embodiment of the present disclosure. As shown in fig. 1, a pixel circuit 10 provided in the embodiment of the present application includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and a light emitting device D.
The light emitting device D may be a micro light emitting diode or a mini light emitting diode. In some embodiments, the light emitting device D may include a micro light emitting diode or a mini light emitting diode. In other embodiments, the light emitting device D may include a plurality of micro light emitting diodes or a plurality of mini light emitting diodes, the plurality of micro light emitting diodes may be arranged in series or in parallel, and the plurality of mini light emitting diodes may be arranged in series or in parallel.
The source and drain of the first transistor T1 and the light emitting device D are connected in series between the first power source terminal VDD and the second power source terminal VSS. One of a source and a drain of the second transistor T2 is connected with one of a source and a drain of the first transistor T1. The other of the source and the drain of the second transistor T2 is connected to the gate of the first transistor T1. One of a source and a drain of the third transistor T3 is connected to the drain terminal N. The other of the source and the drain of the third transistor T3 is connected to the second terminal of the first capacitor C1. A first terminal of the first capacitor C1 is connected to the gate of the first transistor T1. One of a source and a drain of the fourth transistor T4 is connected to the reset terminal M. The other of the source and the drain of the fourth transistor T4 is connected to the second terminal of the first capacitor C1. A first terminal of the second capacitor C2 is connected to the gate of the first transistor T1. A second terminal of the second capacitor C2 is connected to the other of the source and the drain of the first transistor T1.
The gate of the first transistor T1 is connected to the first node a1, one of the source and the drain of the first transistor T1 is connected to the second node a2, and the other of the source and the drain of the first transistor T1 is connected to the third node a 2.
The gate of the second transistor T2 is connected to the first control signal terminal AC2, one of the source and the drain of the second transistor T2 is connected to the second node a2, and the other of the source and the drain of the second transistor T2 is connected to the first node a 1.
The gate of the third transistor T3 is connected to the second control signal terminal AC1, one of the source and the drain of the third transistor T3 is connected to the drain terminal N, and the other of the source and the drain of the third transistor T3 is connected to the third node a 2.
A gate of the fourth transistor T4 is connected to the first control signal terminal AC2, one of a source and a drain of the fourth transistor T4 is connected to the reset terminal M, and the other of the source and the drain of the fourth transistor T4 is connected to the fourth node a 4.
A first terminal of the first capacitor C1 is connected to the first node a1, and a second terminal of the first capacitor C1 is connected to the fourth node a 4.
A first terminal of the second capacitor C2 is connected to the first node a1, and a second terminal of the second capacitor C2 is connected to the third node a 2.
A first terminal of the light emitting device D is connected to a first power source terminal VDD, a second terminal of the light emitting device D is connected to a second node a2, and a third node a2 is connected to a second power source terminal VSS.
The leakage terminal N is used for connecting a lower potential. In the embodiment of the present application, the drain terminal N is the ground terminal GND; that is, the drain terminal N is connected to the ground potential. Of course, in some embodiments, the drain terminal may be switched in other potentials as desired. In the embodiment of the present application, the drain terminal N is connected to the ground terminal GND, so that the leakage of the first node a1 to the drain terminal N through the second transistor T2 and the first transistor T1 can be accelerated.
The reset terminal M is used for accessing a reset potential, and is used for resetting the fourth node a 4. In the embodiment of the present application, the reset is the ground GND; that is, the reset terminal M is connected to the ground potential. Of course, in some embodiments, the reset terminal M may be connected to other potentials as needed. In the embodiment of the present application, the reset terminal M and the drain terminal N share one port, so that the architecture of the pixel circuit 10 in the embodiment of the present application can be simplified.
In the embodiment of the present application, the first power source terminal VDD and the second power source terminal VSS are both set to the first state mode and the second state mode; in a first state mode, the first power supply terminal VDD and the second power supply terminal VSS are connected with signals; in the second state mode, the second power source terminal VSS and the second power source terminal VSS float. That is, the first power source terminal VDD and the second power source terminal VSS in the embodiment of the present invention may be connected to a signal or float as needed, so that there is no need to directly provide a transistor between the first power source terminal VDD and the first end of the light emitting device D, and there is no need to provide a transistor between the second power source terminal VSS and the third node a2, and thus, a part of devices may be omitted, and the compensation effect is ensured.
Further, the pixel circuit 10 provided in the embodiment of the present application further includes a data writing module 101. The Data writing module 101 is electrically connected to the Data terminal Data and the second terminal of the first capacitor C1. The Data writing module 101 is configured to output a Data signal supplied by the Data terminal Data to a second terminal of the first capacitor C1.
The data writing module 101 includes a fifth transistor T5, a sixth transistor T6, and a third capacitor C3. The fifth transistor T5 and the sixth transistor T6 are connected in series between the Data terminal Data and the second terminal of the first capacitor C1. A first terminal of the third capacitor C3 is connected between the fifth transistor T5 and the sixth transistor T6. The second terminal of the third capacitor C3 is electrically connected to the ground GND.
The gate of the fifth transistor T5 is connected to the third control signal terminal AC3, one of the source and the drain of the fifth transistor T5 is connected to the fifth node a5, and the other of the source and the drain of the fifth transistor T5 is connected to the fourth node a 4.
The gate of the sixth transistor T6 is connected to the fourth control signal terminal AC4, one of the source and the drain of the sixth transistor T6 is connected to the Data terminal Data, and the other of the source and the drain of the sixth transistor T6 is connected to the fourth node a 4.
The first terminal of the third capacitor C3 is connected to the fourth node a4, and the second terminal of the third capacitor C3 is connected to the ground GND.
The Data terminal Data is used for accessing a Data potential. In particular, the Data terminal Data in the pixel circuit 10 provided by the embodiment of the present application is connected to the Data potential with a time delay. That is, in the embodiment of the present application, the sixth transistor T6 is turned on, and the fifth transistor T5 is turned off, so that the Data potential accessed by the Data terminal Data is stored in the third capacitor C3 first; subsequently, the sixth transistor T6 is turned off, and the fifth transistor T5 is turned on, so that the data potential stored in the third capacitor C3 is written. Based on this design, the pixel circuit 10 provided in the embodiment of the present application has more flexibility, and the timing of inputting the data potential can be reasonably set as required.
It should be noted that, in the embodiment of the present application, the first node a1 is a connection point between the gate of the first transistor T1, the other of the source and the drain of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2. The second node a2 is a connection point between one of the source and the drain of the first transistor T1, one of the source and the drain of the second transistor T2, and the second terminal of the light emitting device D. The third node a2 is a connection point between the other of the source and the drain of the first transistor T1, the other of the source and the drain of the third transistor T3, the second terminal of the second capacitor C2, and the second power source terminal VSS. The fourth node a4 is a connection point between the other of the source and the drain of the fourth transistor T4, the other of the source and the drain of the fifth transistor T5, and the second terminal of the first capacitor C1. The fifth node a5 is a connection point between one of the source and the drain of the fifth transistor T5, the other of the source and the drain of the sixth transistor T6, and the first end of the third capacitor C3.
The driving timing of the pixel circuit 10 provided in the embodiment of the present application will be described in detail with reference to fig. 1 and 2. Fig. 2 is a schematic diagram of a driving timing sequence of the pixel circuit 10 according to an embodiment of the present disclosure. Specifically, the driving timing of the pixel circuit 10 provided in the embodiment of the present disclosure includes a reset phase t1, a threshold phase t2, a writing phase t3, and a light emitting phase t 4.
In the reset period T1, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off, the first power terminal VDD is floated, and the second power terminal VSS is connected to the signal. In the threshold period T2, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on, the fifth transistor T5 and the sixth transistor T6 are turned off, and the first power source terminal VDD and the second power source terminal VSS are floated. In the write phase T3, the first transistor T1 and the fifth transistor T5 are turned on, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off, the first power source terminal VDD is floated, and the second power source terminal VSS is connected to the signal. In the light-emitting period T4, the first transistor T1 and the sixth transistor T6 are turned on, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off, and the first power terminal VDD and the second power terminal VSS are connected to the signals.
It is understood that, in the embodiment of the present application, the first power supply terminal VDD needs to be floated during the reset phase t1, the threshold phase t2 and the write phase t3, and the first power supply terminal VDD needs to be connected to the signal during the light-emitting phase t 4; the second power source terminal VSS needs to be floated during the threshold phase t2, and the second power source terminal VSS needs to access signals during the reset phase t1, the write phase t3, and the light-emitting phase t 4. Compared with the prior art, in the prior art, the first power terminal VDD and the second power terminal VSS are always the access signals, and a transistor is disposed between the first power terminal VDD and the first terminal of the light emitting device D and a transistor is disposed between the second power terminal VSS and the third node a2, and the access timing of the signals is controlled by the transistors; in the present application, the transistor is directly omitted, and the timing of accessing the signal is directly controlled by controlling the first power supply terminal VDD and the second power supply terminal VSS, so that a part of devices can be omitted.
Specifically, referring to fig. 2 and fig. 3, fig. 3 is a schematic diagram of a state of the pixel circuit 10 in the reset phase t1 according to the embodiment of the present disclosure. In the reset period T1, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off, the first power terminal VDD is floated, and the second power terminal VSS is connected to the signal. The reset terminal M outputs the ground potential to the first terminal of the first capacitor C1 through the fourth transistor T4, and the second power terminal VSS outputs the first potential to the second terminal of the first capacitor C1 through the first transistor T1 and the second transistor T2, thereby completing the resetting of the first node a1 and the fourth node a 4.
Specifically, referring to fig. 2 and fig. 4, fig. 4 is a schematic diagram of a state of the pixel circuit 10 at the threshold stage t2 according to the embodiment of the present disclosure. In the threshold period T2, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on, the fifth transistor T5 and the sixth transistor T6 are turned off, and the first power terminal VDD and the second power terminal VSS are floating. The potential of the gate of the first transistor T1 leaks to the drain terminal N through the second transistor T2, the first transistor T1 and the third transistor T3 until the first transistor T1 is turned off, and at this time, the potential of the first node a1 includes the threshold voltage information of the first transistor T1.
Specifically, referring to fig. 2 and 5, fig. 5 is a schematic diagram of a state of the pixel circuit 10 in the write phase t3 according to the embodiment of the present disclosure. In the write phase T3, the first transistor T1 and the fifth transistor T5 are turned on, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off, the first power terminal VDD is floating, and the second power terminal VSS is connected to the signal. The data potential stored in the third capacitor C3 is output to the first end of the first capacitor C1 through the fifth transistor T5, and the first node a1 includes voltage information of the data potential through the coupling effect of the first capacitor C1.
Specifically, referring to fig. 2 and fig. 6, fig. 6 is a schematic diagram of a state of the pixel circuit 10 in the light-emitting period t4 according to the embodiment of the present disclosure. In the light-emitting period T4, the first transistor T1 and the sixth transistor T6 are turned on, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off, and the first power terminal VDD and the second power terminal VSS are connected to the signal. The Data terminal Data stores the Data potential in the third capacitor C3, and the light emitting device D emits light. The value of the threshold voltage of the first transistor T1 included in the voltage difference between the first node a1 and the third node a2 is removed, and an effect of compensating the threshold voltage of the first transistor T1 is achieved.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating an effect of the pixel circuit 10 according to the embodiment of the present disclosure. As shown in fig. 7, the pixel circuit 10 according to the embodiment of the present application can make the threshold voltage Δ Vth of the first transistor T1 within 0 to nV, and the current variation can be maintained within 5% variation.
According to the pixel circuit 10, the pixel circuit 10 with the 6T3C structure is adopted to effectively compensate the threshold voltage of the driving transistor in the pixel, the compensation structure of the pixel circuit 10 is simple, and the operation difficulty is low; in the pixel circuit 10 provided by the present application, the first power source terminal VDD and the second power source terminal VSS are both set to the first state mode and the second state mode, and in the first state mode, the first power source terminal VDD and the second power source terminal VSS receive signals; in the second state mode, the second power source terminal VSS and the second power source terminal VSS float, so that a part of devices can be omitted while ensuring a compensation effect.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides a display panel 200, which includes a plurality of pixel units 2000 arranged in an array, each pixel unit 2000 includes the pixel circuit 10 described above, and specific reference may be made to the description of the pixel circuit 10, which is not repeated herein.
The foregoing is a preferred embodiment of the present application and it should be noted that modifications and embellishments could be made by those skilled in the art without departing from the principle described in the present application and should also be considered as within the scope of the present invention.
Claims (10)
1. A pixel circuit, comprising:
a light emitting device;
a first transistor having a source and a drain connected in series with the light emitting device between a first power supply terminal and a second power supply terminal;
a second transistor, one of a source and a drain of which is connected to one of a source and a drain of the first transistor, and the other of the source and the drain of which is connected to a gate of the first transistor;
a third transistor, one of a source and a drain of which is connected to a drain terminal, and the other of the source and the drain of which is connected to the second terminal of the first capacitor;
a first capacitor, a first end of the first capacitor being connected to the gate of the first transistor;
a fourth transistor, one of a source and a drain of which is connected to a reset terminal, and the other of the source and the drain of which is connected to the second terminal of the first capacitor;
a second capacitor, a first end of the second capacitor being connected to the gate of the first transistor, and a second end of the second capacitor being connected to the other of the source and the drain of the first transistor; wherein,
the first power supply end and the second power supply end are both set to a first state mode and a second state mode; in the first state mode, the first power supply end and the second power supply end access signals; in the second state mode, the second power supply terminal and the second power supply terminal are floated.
2. The pixel circuit according to claim 1, further comprising a data writing module;
the data writing module is electrically connected to a data terminal and the second terminal of the first capacitor, and the data writing module is used for outputting a data signal supplied by the data terminal to the second terminal of the first capacitor.
3. The pixel circuit according to claim 2, wherein the data writing module includes a fifth transistor, a sixth transistor, and a third capacitor;
the fifth transistor and the sixth transistor are connected in series between the data terminal and the second terminal of the first capacitor; the first end of the third capacitor is connected between the fifth transistor and the sixth transistor, and the second end of the third capacitor is electrically connected with a ground terminal.
4. The pixel circuit according to claim 3, wherein the driving timing of the pixel circuit includes a reset phase, a threshold phase, a write phase, and a light-emitting phase;
in the reset phase, the first transistor, the second transistor, and the fourth transistor are turned on, the third transistor, the fifth transistor, and the sixth transistor are turned off, the first power terminal is floating, and the second power terminal receives a signal;
in the threshold stage, the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on, the fifth transistor and the sixth transistor are turned off, and the first power supply terminal and the second power supply terminal are floated;
in the write phase, the first transistor and the fifth transistor are turned on, the second transistor, the third transistor, the fourth transistor and the sixth transistor are turned off, the first power terminal is floating, and the second power terminal is connected to a signal;
in the light emitting phase, the first transistor and the sixth transistor are turned on, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are turned off, and the first power source terminal and the second power source terminal are connected to a signal.
5. The pixel circuit according to claim 4, wherein during the reset phase, the reset terminal outputs a ground potential to the first terminal of the first capacitor via the fourth transistor, and the second power terminal outputs a first potential to the second terminal of the first capacitor via the first transistor and the second transistor.
6. The pixel circuit according to claim 4, wherein in the threshold stage, a potential of a gate of the first transistor leaks to the drain terminal through the second transistor, the first transistor, and the third transistor until the first transistor is turned off, and the potential of the drain terminal is a ground potential.
7. The pixel circuit according to claim 4, wherein in the writing phase, the data potential stored in the third capacitor is output to the first end of the first capacitor through the fifth transistor.
8. The pixel circuit according to claim 4, wherein the data terminal stores a data potential in the third capacitor during the light emission phase, and the light emitting device emits light.
9. The pixel circuit according to claim 1, wherein the light emitting device is a micro light emitting diode or a mini light emitting diode.
10. A display panel, comprising a plurality of pixel units arranged in an array, wherein each of the pixel units comprises the pixel circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210430571.3A CN114708825A (en) | 2022-04-22 | 2022-04-22 | Pixel circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210430571.3A CN114708825A (en) | 2022-04-22 | 2022-04-22 | Pixel circuit and display panel |
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| CN114708825A true CN114708825A (en) | 2022-07-05 |
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| CN202210430571.3A Pending CN114708825A (en) | 2022-04-22 | 2022-04-22 | Pixel circuit and display panel |
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| CN114038413A (en) * | 2021-11-30 | 2022-02-11 | Tcl华星光电技术有限公司 | Pixel driving method and display panel |
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| JP2006091923A (en) * | 2003-05-19 | 2006-04-06 | Seiko Epson Corp | Electro-optical device and electronic equipment |
| CN101976545A (en) * | 2010-10-26 | 2011-02-16 | 华南理工大学 | Pixel drive circuit of OLED (Organic Light Emitting Diode) display and drive method thereof |
| CN109801595A (en) * | 2019-03-07 | 2019-05-24 | 深圳市华星光电半导体显示技术有限公司 | Pixel-driving circuit and display panel |
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