CN114707413A - Wafer test detection method based on long-short term memory network and sliding window - Google Patents

Wafer test detection method based on long-short term memory network and sliding window Download PDF

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CN114707413A
CN114707413A CN202210366653.6A CN202210366653A CN114707413A CN 114707413 A CN114707413 A CN 114707413A CN 202210366653 A CN202210366653 A CN 202210366653A CN 114707413 A CN114707413 A CN 114707413A
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test
time sequence
term memory
long
memory network
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赵英伟
杨柳
卢旭坤
袁俊
周佳雄
辜诗涛
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Guangdong Leadyo Ic Testing Co ltd
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    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract

The method comprises the steps that a test head executes wafer test to generate test data, and the test data are input into long and short term memory network training and generate a test time sequence and time sequence characteristics thereof; determining the window length k and defining the nearest neighbor window of the window length k based on the test time sequence, and inputting the test time sequence into the trained long-short term memory network to obtain a predicted value d'n+1D 'is predicted value'n+1Comparing with the real measured value to obtain a difference value, and judging when the difference value exceeds a single step threshold value aBreaking single step failure, increasing system anomaly score and predicting value d'n+1Updating the test time sequence to carry out the next detection, and judging that the test environment is wrong when the system abnormity score exceeds a system abnormity threshold value x; and sending an instruction to stop testing and alarm, and uploading fault information through a TCP/IP protocol.

Description

Wafer test detection method based on long-short term memory network and sliding window
Technical Field
The invention belongs to the technical field of wafer testing, and particularly relates to a wafer testing and detecting method based on a long-term and short-term memory network and a sliding window.
Background
In Wafer testing, due to the complexity of the testing environment, such as the stability of the automatic test equipment ATE, the variation of external environmental conditions, the contact condition between the ATE and the Loadboard, and the contact condition between the probe card and the Wafer all affect the accuracy of the testing. In wafer testing, the reused tips become slippery, which may lead to contact anomalies. In addition, the offset needle, particles on the needle tip, and contamination can also create improper contact resistance, resulting in test failure. The misdetection causes an increase in time and economic cost. The existing bad error reporting function of continuous test can only stop the test, and still needs to manually analyze test data to check errors, which wastes time and labor.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is well known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a wafer Test detection method based on a long-short term memory network and a sliding window, which is characterized in that a PC (personal computer) is used for processing Test-head Test data in real time, an abnormity detection model is established, the Test is stopped in time after misdetection caused by abnormal Test environment is detected, possible reasons are analyzed, a GUI window is compiled based on a python pyqt5 component, the operation of a production line is simplified, the Test cost is reduced, and the Test reliability is improved. In order to achieve the above purpose, the invention provides the following technical scheme:
the invention discloses a wafer test detection method based on a long-short term memory network and a sliding window, which comprises the following steps:
the test head executes the wafer test to generate test data, and the test data is input into the long-term and short-term memory network training and generates a test time sequence and the time sequence characteristics thereof;
determining the window length k and defining the nearest neighbor window of the window length k based on the test time sequence and the time sequence characteristics thereof, and inputting the test time sequence into the trained long-short term memory network to obtain a predicted value d'n+1D 'will be predicted value'n+1Comparing the measured value with a real measured value to obtain a difference value, judging single step failure when the difference value exceeds a single step threshold value a, increasing a system abnormal score and predicting a value d'n+1Updating the test time sequence to carry out the next detection, and judging that the test environment is wrong when the system abnormity score exceeds a system abnormity threshold value x;
and sending an instruction to stop testing and alarm, and uploading fault information through a TCP/IP protocol.
In the wafer test detection method based on the long-short term memory network and the sliding window, the test data is analyzed by the principal component after the test data is generated.
In the wafer test detection method based on the long-short term memory network and the sliding window, the test data comprises open-short circuit test data to monitor the contact state of the probe and the chip.
In the wafer test detection method based on the long-short term memory network and the sliding window, the test data comprises coordinate data of an IC under test.
In the wafer test detection method based on the long-short term memory network and the sliding window, after the test is finished, the test data and the fault information are uploaded to a server database.
In the above technical solution, the wafer test detection method based on the long and short term memory network and the sliding window provided by the invention has the following beneficial effects: the invention excavates the time sequence characteristic of the test sequence based on the long-short term memory network LSTM, is more reliable and accurate in the prediction of the wafer test, and after the time sequence characteristic is utilized, the output value of each step of the network is jointly determined according to the previous time points, which is more accurate than the input of the last time point. The time sequence characteristics of sequence data are captured and transmitted inside the LSTM network, and the Root Mean Square Error (RMSE) can reach 0.01V by taking an open-short circuit test as an example; the length of the sliding window can be determined to avoid abnormal error reporting caused by IC abnormity caused by manufacturing process, the GUI window developed based on the pyqt5 component enables operation to be simpler and more convenient, and the defect caused by the manufacturing process is represented as single-step abnormity, and the error detection of the defect alarm belongs to error detection. If the test environment is abnormal, such as probe abnormality, the contact is unstable and appears as unstable abnormality in a window, and the abnormality can be determined by using a sliding window method. The invention finds and warns in time at the early stage of the abnormal occurrence, reduces the testing cost, improves the testing reliability, and has important significance for finding and analyzing the reason in time at the early stage of the abnormal occurrence for the problem that the testing result is wrong due to the external environment.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a block diagram of one embodiment of a wafer test inspection method based on a long-short term memory network and a sliding window in accordance with the present invention;
FIG. 2 is a schematic diagram of a long short term memory network training interface of an embodiment of a wafer test detection method based on a long short term memory network and a sliding window according to the present invention;
FIG. 3 is a schematic diagram of a testing interface of a wafer testing and testing method based on a long/short term memory network and a sliding window according to an embodiment of the present invention;
FIG. 4 is a schematic view of a wafer test inspection method based on a long/short term memory network and a sliding window according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a long-short term memory network according to an embodiment of a wafer test inspection method based on the long-short term memory network and a sliding window;
FIG. 6 is a schematic diagram of a long-short term memory network model of a wafer test inspection method based on a long-short term memory network and a sliding window according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail and completely with reference to the accompanying drawings. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Thus, the following detailed description of the embodiments of the present invention presented in the accompanying fig. 1-6 is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In order to make the technical solutions of the present invention better understood, those skilled in the art will now describe the present invention in further detail with reference to the accompanying drawings.
As shown in fig. 1 to 6, a wafer test inspection method based on a long-short term memory network and a sliding window includes,
the test head executes wafer test to generate test data, and the test data is input into the long-term and short-term memory network training and generates a test time sequence and time sequence characteristics thereof; the test data is a voltage value sequence of each pin obtained by open short circuit test of the wafer test. The long-short term memory network comprises an input layer, a single-layer LSTM layer, a full-connection layer and an output layer, the input is a matrix of N x 3, N represents the number of pins needing to monitor open-short circuit test voltage values, 3 represents that the prediction result of the next voltage value is determined by the voltage values of the previous 3 steps, and a schematic diagram is shown in FIG. 5. A schematic diagram of the network model is shown in fig. 6. The time sequence characteristics refer to test time sequences such as voltage value sequences of the first time points input by the network, the time characteristics are mined and transmitted inside the LSTM network, the time characteristics are output as voltage predicted values of one time point, and the time sequence characteristics are transmitted on a time axis inside the LSTM network and are not physical quantities which can be seen actually.
Determining the window length k and defining the nearest neighbor window of the window length k based on the test time sequence and the time sequence characteristics thereof, and inputting the test time sequence into the trained long-short term memory network to obtain a predicted value d'n+1D 'will be predicted value'n+1Comparing the measured value with a real measured value to obtain a difference value, judging single step failure when the difference value exceeds a single step threshold value a, increasing a system abnormal score and predicting a value d'n+1Updating the test time sequence to carry out the next detection, and judging that the test environment is wrong when the system abnormity score exceeds a system abnormity threshold value x;
and sending an instruction to stop testing and alarm, and uploading fault information through a TCP/IP protocol. The environment error is that the station number and the pin number of the corresponding probe can be positioned because the voltage values of one or more pins are abnormal in a specified window.
In the preferred embodiment of the wafer test detection method based on the long-short term memory network and the sliding window, the test data is analyzed by the principal component after the test data is generated.
In a preferred embodiment of the wafer test detection method based on the long-short term memory network and the sliding window, the test data includes open/short circuit test data to monitor a contact state between the probe and the chip.
In a preferred embodiment of the wafer test detection method based on the long-short term memory network and the sliding window, the test data includes coordinate data of an IC under test.
In the preferred embodiment of the wafer test detection method based on the long-short term memory network and the sliding window, after the test is finished, the test data and the fault information are uploaded to the server database.
In one embodiment, in the detection method, based on the system block diagram shown in fig. 1, the PC processes the Test data datalog of the Test-head in real time, and after the number of samples is sufficient, the training of the long-short term memory network LSTM is performed, so that the problems of gradient extinction and gradient explosion in the gradient back propagation process are solved, the method is very suitable for processing the problem highly related to the time sequence, and the prediction of the Test data is more accurate. The Python programming language has rich libraries and GUI development environment, and the Pyqt5 is used for developing a graphical user interface, so that the operation of the production line is simplified, and the operation interface is shown in FIG. 2. Anomaly detection may then be performed, and the operational interface is shown in FIG. 3. The measured IC coordinates, the measured true values and prediction errors, the single step anomaly scores and the system anomaly ratings can be displayed in real time. Considering that the wafer test has the defect of unqualified dies due to the manufacturing process and the defect of cluster property, and the strict control of individual test items can lead to the failure of a certain item. Therefore, the sliding window model is selected and certain data processing steps are combined to analyze the reasons of test failure.
Selecting proper window length k, defining k nearest neighbor window, inputting the sequence into LSTM network to obtain predicted value d'n+1This is compared to the true measurement, which would decrease the system anomaly score. Otherwise, the difference exceeds the single step threshold aWill be considered a single step failure, the system anomaly score will increase, since the measurement is not a normal value, this time with predicted value d'n+1Updating the sequence and carrying out the next detection. In one embodiment, the voltage value of the current test point plus the voltage values of the first k-1 time points form a k-length window, and k is generally 5; updating the window every time a new wafer is tested; the LSTM network outputs n-dimensional voltage data at the same time point, the voltage data belong to predicted values of n pins, a real measured value is an open-short circuit test voltage value measured by a test machine, contact abnormity of a probe and the pins can cause tiny change of contact impedance, and a is set to be 0.1 to capture the abnormity.
And when the system anomaly score exceeds a defined system anomaly threshold value x, determining that the test environment is wrong. The computer analyzes the test data, if the abnormality of the probe of a certain site is judged, the computer sends an instruction to control the probe station (Prober) to stop the test and give an alarm through GPIB communication, and transmits fault information to a production workshop control master station through a TCP/IP protocol to inform corresponding personnel of solving the abnormality. And after the test is finished, the computer uploads the complete test data datalog to a server database.
In one embodiment, the operator imports the test data in the early stage of the test, such as csv files, into a deep learning long-short term memory network, and the computer background performs preprocessing on the data to be monitored, including Principal Component Analysis (PCA), analysis of the principal features of the multidimensional test data and mapping to a low-dimensional space. Optionally, the test items to be monitored are manually imported. For example, the contact state of the probe and the chip is monitored, and the open short circuit test data is selected for monitoring. The computer then deletes the missing data and clears the outliers. The processed data is trained and after completion, anomaly detection is performed, and the operation interface is shown in fig. 3. The coordinates of the IC to be measured, the actual value and the prediction error of the measurement, single step abnormal conditions and system abnormal conditions can be displayed in real time. Considering that the wafer test has unqualified dies due to the manufacturing process, and the unqualified dies have the clustering characteristic, and in addition, the strict control of individual test items can also cause the continuity of some item to be bad, the sliding window model is selected and combined with a certain data processing stepTo analyze the cause of test failure. Selecting proper window length k, defining k nearest neighbor window, inputting the sequence into LSTM network to obtain predicted value d'n+1This is compared to the true measurement, which would decrease the system anomaly score. Conversely, if the difference exceeds the single step threshold a, it will be considered as a single step failure and the system anomaly score will increase, since the measurement is not normal, and then the predicted value d'n+1And updating the sequence and carrying out the next detection. The system detects the abnormity and carries out preliminary analysis on test data, and judges the reasons of single site failure/failure of a certain needle, falling to a cluster failure area at the edge of the wafer and the like. Optionally, the coordinate of the anomaly and the instruction for checking the pin mark are sent to the probe station through a GPIB interface, and the pin mark check is started to further determine the cause. The computer controls the probe station Prober to stop testing through the GPIB general interface, the TCP/IP protocol is used for sending the number of the abnormal machine station and the fault information to the main station, and the manager informs the corresponding personnel of solving the abnormality according to the fault reason. And after the test is finished, the computer uploads the complete test data to the server database.
Finally, it should be noted that: the embodiments described are only a part of the embodiments of the present application, and not all embodiments, and all other embodiments obtained by those skilled in the art without making creative efforts based on the embodiments in the present application belong to the protection scope of the present application.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the invention.

Claims (5)

1. A wafer test detection method based on a long-short term memory network and a sliding window is characterized by comprising the following steps:
the test head executes the wafer test to generate test data, and the test data is input into the long-term and short-term memory network training and generates a test time sequence and the time sequence characteristics thereof;
determining the window length k and defining the nearest neighbor window of the window length k based on the test time sequence and the time sequence characteristics thereof, and inputting the test time sequence into the trained long-short term memory network to obtain a predicted value d'n+1D 'will be predicted value'n+1Comparing the actual measured value with the predicted value to obtain a difference value, judging single step failure when the difference value exceeds a single step threshold value a, increasing system abnormity score and enabling the predicted value d'n+1Updating the test time sequence to carry out the next detection, and judging that the test environment is wrong when the system abnormity score exceeds a system abnormity threshold value x;
and sending an instruction to stop testing and alarm, and uploading fault information through a TCP/IP protocol.
2. The wafer test detection method based on the long-short term memory network and the sliding window as claimed in claim 1, wherein preferably, the test data is analyzed by principal component after the test data is generated.
3. The method as claimed in claim 1, wherein the test data includes open/short circuit test data to monitor the contact status between the probe and the chip.
4. The method as claimed in claim 1, wherein the test data includes coordinate data of the IC under test.
5. The wafer test detection method based on the long-short term memory network and the sliding window as claimed in claim 1, wherein the test data and the failure information are uploaded to a server database after the test is finished.
CN202210366653.6A 2022-04-08 2022-04-08 Wafer test detection method based on long-short term memory network and sliding window Pending CN114707413A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117290189A (en) * 2023-11-27 2023-12-26 悦芯科技股份有限公司 Monitoring control system for memory chip CP testing machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117290189A (en) * 2023-11-27 2023-12-26 悦芯科技股份有限公司 Monitoring control system for memory chip CP testing machine
CN117290189B (en) * 2023-11-27 2024-02-06 悦芯科技股份有限公司 Monitoring control system for memory chip CP testing machine

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