CN114706810A - Baud rate self-adaptive serial port communication extension device and method based on FPGA - Google Patents
Baud rate self-adaptive serial port communication extension device and method based on FPGA Download PDFInfo
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Abstract
The invention discloses a baud rate self-adaptive serial port communication extension device and a baud rate self-adaptive serial port communication extension method based on FPGA, wherein the device comprises a main serial port interface chip, a logic processor FPGA and a plurality of branch serial port interface chips; the logic processor FPGA is used for receiving total serial port data sent by the main serial port interface chip, automatically identifying a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing and receiving the serial port data, and outputting the total serial port data through each first branch serial port through a preset frame format; and receiving the branch serial port data sent by the plurality of branch serial port interface chips, automatically identifying the baud rate of the second branch serial port by adopting the same calculation method, analyzing the received serial port data, combining the branch serial port data through a preset frame format, and sending the combined branch serial port data through the second total serial port. The circuit of the invention is simple, and is suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
Description
Technical Field
The invention relates to the technical field of serial port communication, in particular to a baud rate self-adaptive serial port communication extension device and method based on an FPGA (field programmable gate array).
Background
The serial communication means that one data line is used for data transmission one bit by one bit in a single direction, the data transmission can be realized by using a simple cable, the equipment is simple, the cost is low, the current common serial communication mode and the asynchronous serial communication UART take one character as a transmission unit, the time interval between two characters in communication is not fixed, and the time interval between two adjacent bits in the same character is fixed. The data transmission rate is expressed by baud rate, i.e. the number of binary bits transmitted per second, and the commonly used baud rates are 2400bps, 9600bps, 51200bps, 115200bps and the like. A character of UART generally includes a start bit, a data bit, a check bit, a stop bit, the start bit: firstly, a logic '0' signal is sent out to indicate the beginning of the character transmission; data bit: the code can be 5-8 bit logic '0' or '1', such as ASCII (7 bit), extension BCD (8 bit) code and small-end transmission; checking the bit: the data bit is added with this bit so that the number of bits of "1" should be either even (even parity) or odd (odd parity); stopping the position: which is an end flag of character data. High level which can be 1 bit, 1.5 bit, 2 bit; idle bit: i.e., idle state between UART character transmissions, is in a logic "1" state.
In the electronic industry, the expansion of the serial communication interface is mainly performed through a special-purpose ASCI chip (ASCI: Application Specific interconnected Circuits), which is generally a parallel interface or a high-speed serial interface, the implementation scheme is relatively troublesome, different designs are required in different use scenes, and the general serial interface expansion design does not adopt a baud rate adaptive design, so that when the baud rate of the external device changes, the expansion device needs to change the configuration again through hardware or modify the baud rate through software parameters, and the usability is greatly reduced. For the baud rate self-adaptive technology of the serial interface, the main method steps of the prior art are as follows: acquiring an input signal by using a higher sampling rate, and caching the acquired data; detecting characteristic parameters of a target signal received on the serial port receiving data line, determining a second sampling rate according to the change width of the target signal when the characteristic parameters meet preset conditions, and sampling the target signal by using the second sampling rate to obtain new sampling data; reconstructing the sampled data by using a second sampling rate, and caching the reconstructed data and the newly sampled data; determining a suspected baud rate of the cache data according to the relation between the baud rate and the minimum data width; analyzing the cached data by using the suspected baud rate; and judging the analyzed data by using a preset baud rate judgment standard, and determining the suspected baud rate as the correct baud rate when the analyzed data meets the preset baud rate judgment standard.
Therefore, in the prior art, serial communication expansion is generally performed through a special ASCI chip, the special ASCI chip is generally a parallel interface or a high-speed serial interface, the implementation scheme is relatively troublesome, special design is required in different application scenes, the universal application is not high, the baud rate of the special ASIC serial communication expansion chip is generally generated through internal clock frequency division, a clock source is provided by an external crystal oscillator of the ASCI chip, and the baud rate can only be a plurality of common fixed values due to the fixed frequency of the external crystal oscillator clock, and can not meet the application requirements of some special scenes; the prior serial port baud rate self-adaptive technology is relatively complex in logic, needs to perform data sampling with different clock frequencies for multiple times, has high requirements on the time sequence of software logic design, and causes low baud rate detection speed and low instantaneity through multiple sampling and multi-level data caching.
In view of the above disadvantages in the prior art, it is necessary to provide a serial port communication extension device based on an FPGA, and the self-baud rate can be adaptively adjusted according to the baud rate of an external communication device.
Disclosure of Invention
The technical problem to be solved by the invention is that the serial port communication expansion is generally carried out by a special ASCI chip in the prior art, the implementation scheme is relatively troublesome, and the baud rate of the serial port of the special ASCI chip needs to be preset to be a fixed value and cannot adapt to different application scenes; the conventional serial port baud rate self-adaptive technology is relatively complex in logic, needs to perform data sampling with different clock frequencies for multiple times, has high requirements on the time sequence of software logic design, and can cause the problems of low baud rate detection speed, low instantaneity and the like in a mode of sampling for multiple times and multi-level data caching.
The invention aims to provide a baud rate self-adaptive serial port communication expansion device and a method based on FPGA, the device has one path of total serial port in the data uplink direction and multiple paths of branch serial ports in the data downlink direction, the device expands one path of serial port to ten paths, when the device receives the total serial port data, the device automatically identifies the baud rate of the total serial port and analyzes and receives the serial port data, the total serial port data is output through each branch serial port through a pre-designed frame format, and the baud rate of the branch serial port is automatically set according to the baud rate of the total serial port; when the device receives the sub-serial port data, the device automatically identifies the baud rate of the sub-serial port, analyzes and receives the serial port data, and sends out the sub-serial port data after merging the sub-serial port data through the total serial port through a pre-designed frame format. The logic part of the device is realized by FPGA, the circuit is simple, the logic is clear, the transportability is strong, and the invention is mainly suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
The invention is realized by the following technical scheme:
in a first aspect, the invention provides a baud rate self-adaptive serial port communication expansion device based on an FPGA (field programmable gate array), wherein the data uplink direction of the device is a main serial port, and the data downlink direction is a multi-branch serial port;
the device comprises a main path serial port interface chip, a logic processor FPGA and a plurality of branch path serial port interface chips; the main path serial port interface chip is connected with a logic processor FPGA, and the logic processor FPGA is connected with each branch path serial port interface chip; the main path serial port interface chip and the branch path serial port interface chip have data receiving and sending functions;
the logic processor FPGA is used for receiving total serial port data sent by the main serial port interface chip, automatically identifying a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing the received serial port data, and outputting the total serial port data to the corresponding branch serial port interface chips through the first branch serial ports through a preset frame format; the baud rate of the first branch serial port is automatically calculated according to the baud rate of the first total serial port;
and the branch serial port data receiving module is used for receiving the branch serial port data sent by the branch serial port interface chips, automatically identifying the second branch serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing and receiving the serial port data, combining the branch serial port data through a preset frame format, and sending the combined branch serial port data to the main serial port interface chip through a second main serial port. And the baud rate of the second main serial port is set as the baud rate of the channel with the maximum branch serial port rate multiplied by the number of the branch channels actually receiving the data.
Wherein, the FPGA is a field-Programmable Gate Array.
The working principle is as follows: based on the prior art, serial port communication expansion is generally carried out through a special ASCI chip, the implementation scheme is relatively troublesome, and the serial port baud rate of the special ASCI chip needs to be preset to be a fixed value and cannot adapt to different application scenes; the prior serial port baud rate self-adaptive technology is more complex logically, needs to sample data with different clock frequencies for multiple times, has higher requirement on the time sequence of software logic design, and causes the problems of slower baud rate detection speed, low real-time performance and the like in a mode of sampling for multiple times and caching data in multiple levels,
therefore, the invention designs the baud rate self-adaptive serial port communication expansion device based on the FPGA, the data uplink direction of the device is a main serial port, the data downlink direction is a multi-path branch serial port, the device expands a path of serial ports to a plurality of paths, and combines the plurality of paths of serial ports into a path. The device receives total serial port data sent by the main serial port interface chip, automatically identifies a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzes and receives the serial port data, and outputs the total serial port data to corresponding branch serial port interface chips through each first branch serial port through a preset frame format; the baud rate of the first branch serial port is automatically calculated according to the baud rate of the first total serial port; the device receives the branch serial port data sent by the branch serial port interface chips, automatically identifies the second branch serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzes and receives the serial port data, combines the branch serial port data through a preset frame format, and sends the combined branch serial port data to the main serial port interface chip through a second main serial port.
According to the method, the baud rate of the serial port is not required to be set as a fixed value in advance, but the baud rate of the input serial port data can be automatically analyzed according to an external input serial signal, and the baud rate of the output serial port data is obtained through logic internal calculation of the FPGA according to system requirements; meanwhile, the invention does not need to sample data with different clock frequencies for many times, has low requirement on the time sequence of software logic design, only samples the data with one clock, and has higher baud rate detection speed and high real-time property. In addition, the serial port baud rate in the invention is not limited to the common standard baud rate, and the baud rate which continuously changes within the maximum baud rate can be processed.
The device has simple circuit and clear logic; the logic control function of the invention is realized by FPGA, and the FPGA adopts hardware description language to program, thus having strong portability; the serial port communication expansion technology provided by the invention has higher flexibility, and the number of expansion channels can be increased or reduced according to specific application; the serial port baud rate self-adaption method provided by the invention can be applied to various serial port communication systems. The invention is mainly suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
Furthermore, the self-adaptive serial port baud rate calculation method automatically analyzes the baud rate of the input serial port data according to the external input serial signals, and calculates the baud rate of the output serial port data through the logic processor FPGA according to the requirements of the device.
Further, the logic processor FPGA comprises a first logic processor and a second logic processor;
the first logic processor comprises a main path serial port baud rate judging module, a main path serial port data receiving and caching module, a first main path branch data interaction module, a plurality of branch serial port data sending and caching module and a plurality of branch serial port data sending modules;
the main-line serial port baud rate judging module is connected with the main-line serial port interface chip, the main-line serial port baud rate judging module is connected with the main-line serial port data receiving module, and the main-line serial port baud rate judging module is connected with the first main-line branch data interaction module; the main-path serial port data receiving module is connected with the main-path serial port interface chip, the main-path serial port data receiving module is connected with a main-path serial port data receiving cache module, the main-path serial port data receiving cache module is connected with a first main-path branch data interaction module, the first main-path branch data interaction module is connected with a plurality of branch serial port data sending cache modules, and each branch serial port data sending cache module is connected with a branch serial port data sending module; each branch serial port data sending module is connected with a corresponding branch serial port interface chip;
the main serial port baud rate judging module is used for analyzing to obtain the baud rate of the input total serial signal by collecting the total serial signal input by the main serial port interface chip;
the main serial port data receiving module is used for receiving a main serial port signal input by the main serial port interface chip and performing serial-parallel conversion on serial data in the main serial port signal to obtain main parallel data;
the main route serial port data receiving and caching module is used for realizing caching of the received main route parallel data;
the first main road branch data interaction module is used for realizing the distribution of the cached main road parallel data to branch data; avoiding the data speed mismatching of the main road and the branch road through proper time sequence processing; the data speed mismatching between the main road and the branch road is avoided, so that the data is blocked or lost; analyzing the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the branch serial port data sending and caching module is used for realizing caching of sending and outputting serial data;
and the branch serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
Further, the second logic processor comprises a plurality of branch serial port baud rate judging modules, a plurality of branch serial port data receiving and caching modules, a second main route branch data interaction module, a main route serial port data sending and caching module and a main route serial port data sending module;
each branch serial port baud rate judging module is connected with a corresponding branch serial port interface chip, the branch serial port baud rate judging module is connected with a branch serial port data receiving cache module, and the branch serial port baud rate judging module is connected with a second main branch data interaction module; each branch serial port data receiving module is connected with a corresponding branch serial port interface chip, and each branch serial port data receiving module is connected with a corresponding branch serial port data receiving cache module; each branch serial port data receiving and caching module is connected with a second main branch data interaction module, the second main branch data interaction module is connected with a main serial port data sending and caching module, and the main serial port data sending and caching module is connected with a main serial port data sending module;
the branch serial port baud rate judging module is used for analyzing the baud rate of the input branch serial signal by collecting the branch serial port signal input by the branch serial port interface chip;
the branch serial port data receiving module is used for receiving a branch serial port signal input by the branch serial port interface chip and performing serial-parallel conversion on serial data in the branch serial port signal to obtain branch parallel data;
the branch serial port data receiving and caching module is used for realizing caching of the received branch parallel data;
the second main road branch data interaction module is used for realizing the collection of the cached branch parallel data to the main road data and avoiding the speed mismatch of the main road and the branch data through proper time sequence processing; the data speed mismatching between the main road and the branch road is avoided, and the data is blocked or lost; analyzing the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the main path serial port data sending and caching module is used for realizing the caching of sending and outputting serial data;
and the main path serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
Further, the total serial port baud rate determination module and the branch serial port baud rate determination module both adopt the following determination processes (that is, the total serial port baud rate determination module and the branch serial port baud rate determination module both adopt an adaptive serial port baud rate calculation method to determine the baud rate):
performing primary oversampling on an external signal through a high-speed clock inside the FPGA to obtain a signal edge of an external input signal; calculating the time interval of the signal edges through the high-speed clock period between the signal edges, wherein the time interval between the adjacent falling edge and rising edge of the data waveform acquired by the receiving end is the serial port transmission data period; and counting the time intervals of a plurality of adjacent falling edges and rising edges, and averaging the data periods transmitted by a plurality of serial ports to obtain the baud rate of the serial signals.
Further, the calculation process of the baud rate of the serial signal is as follows:
collecting a signal falling edge for the first time, and starting to calculate by using a counter;
continuously acquiring a signal rising edge and taking the signal rising edge and the first signal falling edge as a time interval;
continuously acquiring the next signal falling edge, counting once by adopting a counter, and circulating for multiple times to respectively obtain a count value;
averaging the multiple counting values by adopting corresponding serial port transmission data periods to obtain serial port transmission data periods; and calculating the reciprocal of the serial port transmission data period to obtain the serial port baud rate.
Furthermore, the main path serial port data receiving and caching module, the branch path serial port data sending and caching module, the branch path serial port data receiving and caching module and the main path serial port data sending and caching module are all realized by a BLOCK RAM module in FPGA;
the main path serial port data receiving module and the branch path serial port data receiving module convert serial data into 8-bit parallel data in a shift register mode;
the main path serial port data sending module and the branch path serial port data sending module convert 8-bit parallel data into single-bit serial data in a mode of a shift register.
Further, the baud rate of the first branch serial port in the logic processor FPGA is automatically calculated according to the baud rate of the first total serial port.
Further, the baud rate of the second main serial port in the logic processor FPGA is set as the baud rate of the channel with the maximum branch serial port rate multiplied by the number of branch channels actually receiving data.
In a second aspect, the invention also provides a baud rate adaptive serial port communication expansion method based on the FPGA, which is applied to the baud rate adaptive serial port communication expansion device based on the FPGA; the method comprises the following steps:
receiving an external input serial signal, analyzing the baud rate of the external input serial signal at the moment through a trunk serial port baud rate judging module, acquiring effective data of the input serial signal through the baud rate, converting the serial data into parallel data, and storing the parallel data into a trunk serial port receiving cache; according to a preset frame format, splitting a data frame, sending parallel data in a main path serial port receiving cache to branch serial port sending caches, simultaneously converting data in the branch serial port sending caches into serial data, and outputting the branch serial data; and
each branch serial port receives a serial port signal input from the outside, the baud rate of the input signal of each branch serial port is analyzed through a branch serial port baud rate judging module, data input from a self port is analyzed through the respective baud rate, serial data are converted into parallel data, and the parallel data are stored in a receiving cache of each branch serial port; and combining data frames according to a preset frame format, sending the combined data into a main serial port sending buffer according to a certain sequence, simultaneously converting the combined data into total serial data, and outputting the total serial data.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. according to the method, the baud rate of the serial port is not required to be set as a fixed value in advance, but the baud rate of the input serial port data can be automatically analyzed according to an external input serial signal, and the baud rate of the output serial port data is obtained through logic internal calculation of the FPGA according to system requirements;
2. the invention does not need to sample data with different clock frequencies for many times, has low requirement on the time sequence of software logic design, only samples in one clock, and has higher baud rate detection speed and high real-time property.
3. The device has simple circuit and clear logic; the logic control function of the invention is realized by FPGA, and the FPGA adopts hardware description language to program, thus having strong portability; the serial port communication expansion technology provided by the invention has higher flexibility, and the number of expansion channels can be increased or reduced according to specific application; the serial port baud rate self-adaption method provided by the invention can be applied to various serial port communication systems. The invention is mainly suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
4. The serial port baud rate in the invention is not limited to the common standard baud rate, and can process the baud rate which continuously changes within the maximum baud rate.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a hardware schematic diagram of the baud rate adaptive serial port communication expansion device based on the FPGA.
Fig. 2 is a logic block diagram of the logic processor FPGA of the baud rate adaptive serial port communication extension apparatus based on the FPGA.
Fig. 3 is a flow chart of the serial port baud rate determination timing in the trunk serial port baud rate determination module and the branch serial port baud rate determination module according to the present invention.
Fig. 4 is a flowchart of the baud rate adaptive serial port communication extension method based on the FPGA of the present invention.
Detailed Description
Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "or" at least one of a or/and B "includes any or all combinations of the words listed simultaneously. For example, the expression "a or B" or "at least one of a or/and B" may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
As shown in fig. 1 to fig. 3, the baud rate adaptive serial port communication extension device based on the FPGA of the present invention has a single-path total serial port in the data uplink direction and multiple-path branch serial ports in the data downlink direction; in this embodiment, the example apparatus extends one-way serial ports to ten-way serial ports.
The device comprises a main path serial port interface chip, a logic processor FPGA and a plurality of branch path serial port interface chips; the main path serial port interface chip is connected with a logic processor FPGA, and the logic processor FPGA is connected with each branch path serial port interface chip; the main path serial port interface chip and the branch path serial port interface chip have data receiving and sending functions;
the invention relates to a main path serial port interface chip and a plurality of branch serial port interface chips, which are different according to specific application, and an RS422 level conversion chip is adopted in the design of the invention. The logic processor FPGA selects XC7A35T of XILINX company, the trunk serial interface chip and the branch serial interface chip select ADM2582 of ADI company, the number of branch channels is 10 channels in the example, and a hardware schematic diagram is as shown in the following figure 1:
the logic processor FPGA is used for receiving total serial port data sent by the main serial port interface chip, automatically identifying a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing the received serial port data, and outputting the total serial port data to the corresponding branch serial port interface chips through the first branch serial ports through a preset frame format; the baud rate of the first branch serial port is automatically calculated according to the baud rate of the first total serial port;
and the branch serial port data receiving module is used for receiving the branch serial port data sent by the branch serial port interface chips, automatically identifying the second branch serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing and receiving the serial port data, combining the branch serial port data through a preset frame format, and sending the combined branch serial port data to the main serial port interface chip through a second main serial port. And setting the baud rate of the second main serial port as the baud rate of the channel with the maximum branch serial port rate multiplied by the number of the branch channels actually receiving the data.
The self-adaptive serial port baud rate calculation method automatically analyzes the baud rate of input serial port data according to an external input serial signal, and calculates the baud rate of the output serial port data through the FPGA according to the requirement of the device.
The logic part of the invention is realized by logic programming inside the logic processor FPGA, the logic processor FPGA has the following internal logic block diagram as shown in FIG. 2, and FIG. 2 shows the data receiving and sending flow direction as follows:
the logic processor FPGA comprises a first logic processor and a second logic processor;
specifically, the method comprises the following steps: the first logic processor comprises a main path serial port baud rate judging module, a main path serial port data receiving and caching module, a first main path branch data interaction module, a plurality of branch serial port data sending and caching module and a plurality of branch serial port data sending modules; the main-line serial port baud rate judging module is connected with the main-line serial port interface chip, the main-line serial port baud rate judging module is connected with the main-line serial port data receiving module, and the main-line serial port baud rate judging module is connected with the first main-line branch data interaction module; the main-path serial port data receiving module is connected with the main-path serial port interface chip, the main-path serial port data receiving module is connected with a main-path serial port data receiving cache module, the main-path serial port data receiving cache module is connected with a first main-path branch data interaction module, the first main-path branch data interaction module is connected with a plurality of branch serial port data sending cache modules, and each branch serial port data sending cache module is connected with a branch serial port data sending module; each branch serial port data sending module is connected with a corresponding branch serial port interface chip;
the main serial port baud rate judging module is used for analyzing to obtain the baud rate of the input total serial signal by collecting the total serial signal input by the main serial port interface chip;
the main serial port data receiving module is used for receiving a main serial port signal input by the main serial port interface chip and performing serial-parallel conversion on serial data in the main serial port signal to obtain main parallel data;
the main route serial port data receiving and caching module is used for caching the received main route parallel data;
the first main path branch data interaction module is used for realizing the distribution of the cached main path parallel data to branch data; avoiding the data speed mismatching of the main road and the branch road through proper time sequence processing; the data speed mismatching between the main road and the branch road is avoided, and the data is blocked or lost; analyzing the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the branch serial port data sending and caching module is used for realizing caching of sending and outputting serial data;
and the branch serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
Serial data are sent from the main path serial port data receiving module and the plurality of branch serial port data sending modules, and parallel data are sent from the main path serial port data receiving cache module, the first main path branch data interaction module and the plurality of branch serial port data sending cache modules;
specifically, the method comprises the following steps: the second logic processor comprises a plurality of branch serial port baud rate judging modules, a plurality of branch serial port data receiving and caching modules, a second main branch data interaction module, a main serial port data sending and caching module and a main serial port data sending module; each branch serial port baud rate judging module is connected with a corresponding branch serial port interface chip, the branch serial port baud rate judging module is connected with a branch serial port data receiving cache module, and the branch serial port baud rate judging module is connected with a second main branch data interaction module; each branch serial port data receiving module is connected with a corresponding branch serial port interface chip, and each branch serial port data receiving module is connected with a corresponding branch serial port data receiving cache module; each branch serial port data receiving and caching module is connected with a second main road branch data interaction module, the second main road branch data interaction module is connected with a main road serial port data sending and caching module, and the main road serial port data sending and caching module is connected with a main road serial port data sending module;
the branch serial port baud rate judging module is used for analyzing the baud rate of the input branch serial signal by collecting the branch serial port signal input by the branch serial port interface chip;
the branch serial port data receiving module is used for receiving a branch serial port signal input by the branch serial port interface chip and performing serial-parallel conversion on serial data in the branch serial port signal to obtain branch parallel data;
the branch serial port data receiving and caching module is used for realizing caching of the received branch parallel data;
the second main road branch data interaction module is used for realizing the collection of the cached branch parallel data to the main road data and avoiding the speed mismatch of the main road and the branch data through proper time sequence processing; the data speed mismatching between the main road and the branch road is avoided, and the data is blocked or lost; resolving the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the main path serial port data sending and caching module is used for realizing the caching of sending and outputting serial data;
and the main serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
The plurality of branch serial port data receiving modules and the main line serial port data sending module are serial data, and the plurality of branch serial port data receiving cache modules, the second main line branch data interaction module and the main line serial port data sending cache module are parallel data.
In this embodiment, the main-line serial port data receiving and caching module, the branch-line serial port data sending and caching module, the branch-line serial port data receiving and caching module and the main-line serial port data sending and caching module are all implemented by using a BLOCK RAM module in an FPGA;
the main path serial port data receiving module and the branch path serial port data receiving module convert serial data into 8-bit parallel data in a shift register mode;
the main path serial port data sending module and the branch path serial port data sending module convert 8-bit parallel data into single-bit serial data in a mode of a shift register.
Specifically, the serial port baud rate determination timing flow chart in the main-path serial port baud rate determination module and the branch-path serial port baud rate determination module is as shown in fig. 3, and by convention with an external input/output device, a first data character of a serial port data frame is a baud rate check character, in this example, the baud rate check character is 01010101, a serial port adopts small-end transmission and priority transmission of low-bit data, so that a received character is 10101010, according to the serial data communication format described above, serial data is in a high level "1" in an idle state, transmission data is first a start bit "0", then last characters are sequentially sent, and after combination, the last characters are "1010101010", an external signal is subjected to one-time oversampling by an internal high-speed clock (for example, 100 megabits) of an FPGA, and a signal edge of an external input signal is obtained; calculating the time interval of the signal edges through the high-speed clock period between the signal edges, wherein the time interval between the adjacent falling edge and rising edge of the data waveform acquired by the receiving end is the serial port transmission data period; the time interval of 4 adjacent falling edges and rising edges continuously appears, the average value of the data cycle transmitted by 4 serial ports is calculated, and finally the baud rate of the serial signals can be obtained through conversion.
The invention adopts standard UART characters to describe according to the most common 1-bit start bit, 8-bit data bit, 1-bit check bit and 1-bit stop bit at present.
In this embodiment, the calculation process of the baud rate of the serial signal is as follows:
collecting a signal falling edge for the first time, and starting to calculate by using a counter;
continuously acquiring a signal rising edge and taking the signal rising edge and the first signal falling edge as a time interval;
continuously acquiring the next signal falling edge, counting once by adopting a counter, and circulating for multiple times to respectively obtain a count value;
averaging the multiple counting values by adopting corresponding serial port transmission data periods to obtain serial port transmission data periods; and calculating the reciprocal of the serial port transmission data period to obtain the serial port baud rate.
According to the scheme, the baud rate in the design is determined by sampling the high-speed clock signal in the FPGA, the speed of the high-speed clock signal in the FPGA is much higher than that of the serial signal input from the outside, so that the serial signal input from the outside can be any baud rate within the maximum baud rate of a serial interface, the limitation that the baud rate of a traditional ASCI chip is only limited to a plurality of fixed values is avoided, and meanwhile, as the FPGA can process continuous arbitrary baud rates, the total path baud rate is decomposed into branch path baud rates and the branch path baud rates are combined into the total path baud rate, and the limitation that the total path baud rate is not limited by the fixed values of the traditional baud rate is also avoided.
The working principle is as follows: the invention designs a baud rate self-adaptive serial port communication extension device based on FPGA, the device has one path of main serial port in the data uplink direction and multiple paths of branch serial ports in the data downlink direction, and the device extends one path of serial ports to multiple paths and combines the multiple paths of serial ports into one path. The device receives total serial port data sent by the main serial port interface chip, automatically identifies a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzes and receives the serial port data, and outputs the total serial port data to corresponding branch serial port interface chips through each first branch serial port through a preset frame format; the baud rate of the first branch serial port is automatically calculated according to the baud rate of the first total serial port; the device receives the branch serial port data sent by the branch serial port interface chips, automatically identifies the second branch serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzes and receives the serial port data, combines the branch serial port data through a preset frame format, and sends the combined branch serial port data to the main serial port interface chip through a second main serial port.
According to the method, the baud rate of the serial port is not required to be set as a fixed value in advance, but the baud rate of the input serial port data can be automatically analyzed according to an external input serial signal, and the baud rate of the output serial port data is obtained through logic internal calculation of the FPGA according to system requirements; meanwhile, the invention does not need to sample data with different clock frequencies for many times, has low requirement on the time sequence of software logic design, only samples in one clock, and has higher baud rate detection speed and high real-time property. In addition, the serial port baud rate in the invention is not limited to the common standard baud rate, and the baud rate which continuously changes within the maximum baud rate can be processed.
The device has simple circuit and clear logic; the logic control function of the invention is realized by FPGA, and the FPGA adopts hardware description language to program, thus having strong portability; the serial port communication expansion technology provided by the invention has higher flexibility, and the number of expansion channels can be increased or reduced according to specific application; the serial port baud rate self-adaption method provided by the invention can be applied to various serial port communication systems. The invention is mainly suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
Example 2
As shown in fig. 4, the difference between this embodiment and embodiment 1 is that this embodiment provides a baud rate adaptive serial port communication extension method based on an FPGA, and the method is applied to the baud rate adaptive serial port communication extension device based on an FPGA described in embodiment 1; the operation flow chart is shown in fig. 4, and the whole operation flow includes (1) receiving data by the main serial port and sending data by the branch serial port; (2) the two data flow directions of the data received by the branch serial port and the data sent by the main serial port are explained:
the method comprises the following steps:
(1) receiving data by the main serial port and sending data by the branch serial port: receiving an external input serial signal, analyzing the baud rate of the external input serial signal at the moment through a trunk serial port baud rate judging module, acquiring effective data of the input serial signal through the baud rate, converting the serial data into parallel data, and storing the parallel data into a trunk serial port receiving cache; according to a preset frame format, splitting a data frame, sending parallel data in a main path serial port receiving cache to a branch path serial port sending cache, simultaneously converting data in each branch path serial port sending cache into serial data, and outputting each branch path serial data;
in this example, 1 way of the serial port of the main route, 10 way of the serial port of the branch road, the data in the serial port receiving buffer memory of the main route are sent to the sending buffer memory of 10 serial ports of the branch road sequentially according to the precedence, send the data in the buffer memory of 10 serial ports of the branch road to change into the serial data to send out the apparatus at the same time, and, the baud rate that the serial port of the branch road sends the data is determined according to the baud rate that the serial port of the main route that the external input analyzes and gets, in this example, the serial port of the branch road sends the data baud rate to 1/10 of the serial port analytic baud rate of the main route; ensuring the bandwidth of the main path and the branch path to be consistent.
(2) The branch serial port receives data and the main serial port sends data: each branch serial port receives a serial port signal input from the outside, the baud rate of the input signal of each branch serial port is analyzed through a branch serial port baud rate judging module, data input from a self port is analyzed through the respective baud rate, serial data are converted into parallel data, and the parallel data are stored in a receiving cache of each branch serial port; and combining data frames according to a preset frame format, sending the combined data into a main serial port sending buffer according to a certain sequence, simultaneously converting the combined data into total serial data, and outputting the total serial data.
In this embodiment, in order to ensure that the main serial port can send out the data received by the branch serial ports in time and avoid data blockage, the baud rate of the main serial port is set as the baud rate of the channel with the maximum branch serial port rate multiplied by the number of the branch channels actually receiving the data.
The total serial port baud rate judging module and the branch serial port baud rate judging module adopt the serial port baud rate self-adaptive metering algorithm in the embodiment 1 to calculate.
According to the method, the baud rate of the serial port is not required to be set as a fixed value in advance, but the baud rate of the input serial port data can be automatically analyzed according to an external input serial signal, and the baud rate of the output serial port data is obtained through logic internal calculation of the FPGA according to system requirements; meanwhile, the invention does not need to sample data with different clock frequencies for many times, has low requirement on the time sequence of software logic design, only samples in one clock, and has higher baud rate detection speed and high real-time property. In addition, the serial port baud rate in the invention is not limited to the common standard baud rate, and the continuously-changing baud rate within the maximum baud rate can be processed.
The logic control function of the invention is realized by FPGA, and the FPGA adopts hardware description language to program, thus having strong portability; the serial port communication expansion technology provided by the invention has higher flexibility, and the number of expansion channels can be increased or reduced according to specific application; the serial port baud rate self-adaptive calculation method provided by the invention can be applied to various serial port communication systems. The invention is mainly suitable for the application environment with insufficient serial ports, definite baud rate and frequent variation of the baud rate.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. The Baud rate self-adaptive serial port communication extension device based on the FPGA is characterized by comprising a main serial port interface chip, a logic processor FPGA and a plurality of branch serial port interface chips; the main path serial port interface chip is connected with a logic processor FPGA, and the logic processor FPGA is connected with each branch path serial port interface chip; the main path serial port interface chip and the branch path serial port interface chip have data receiving and sending functions;
the logic processor FPGA is used for receiving total serial port data sent by the main serial port interface chip, automatically identifying a first total serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing the received serial port data, and outputting the total serial port data to the corresponding branch serial port interface chips through the first branch serial ports through a preset frame format;
and the branch serial port data receiving module is used for receiving the branch serial port data sent by the branch serial port interface chips, automatically identifying the second branch serial port baud rate by adopting a self-adaptive serial port baud rate calculation method, analyzing and receiving the serial port data, combining the branch serial port data through a preset frame format, and sending the combined branch serial port data to the main serial port interface chip through a second main serial port.
2. The baud rate adaptive serial port communication expansion device based on the FPGA of claim 1, wherein the baud rate calculation method of the adaptive serial port automatically analyzes the baud rate of the input serial port data according to an external input serial signal, and calculates the baud rate of the output serial port data through the FPGA according to the requirement of the device.
3. The FPGA-based baud rate adaptive serial communications expansion device of claim 1, wherein said logic processor FPGA comprises a first logic processor and a second logic processor;
the first logic processor comprises a main path serial port baud rate judging module, a main path serial port data receiving and caching module, a first main path branch data interaction module, a plurality of branch serial port data sending and caching module and a plurality of branch serial port data sending modules;
the main serial port baud rate judging module is used for acquiring a main serial port signal input by the main serial port interface chip and analyzing to obtain the baud rate of the input main serial signal;
the main serial port data receiving module is used for receiving a main serial port signal input by the main serial port interface chip and performing serial-parallel conversion on serial data in the main serial port signal to obtain main parallel data;
the main route serial port data receiving and caching module is used for realizing caching of the received main route parallel data;
the first main road branch data interaction module is used for realizing the distribution of the cached main road parallel data to branch data; avoiding the data speed mismatching of the main road and the branch road through time sequence processing; analyzing the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the branch serial port data sending and caching module is used for realizing caching of sending and outputting serial data;
and the branch serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
4. The baud rate adaptive serial port communication extension device based on the FPGA of claim 3, wherein the second logic processor comprises a plurality of branch serial port baud rate determination modules, a plurality of branch serial port data receiving and caching modules, a second main branch data interaction module, a main serial port data sending and caching module, and a main serial port data sending module;
the branch serial port baud rate judging module is used for analyzing the baud rate of the input branch serial signal by collecting the branch serial port signal input by the branch serial port interface chip;
the branch serial port data receiving module is used for receiving a branch serial port signal input by the branch serial port interface chip and performing serial-parallel conversion on serial data in the branch serial port signal to obtain branch parallel data;
the branch serial port data receiving and caching module is used for realizing caching of the received branch parallel data;
the second main road branch data interaction module is used for realizing the collection of the cached branch parallel data to the main road data and avoiding the speed mismatching of the main road and the branch data through time sequence processing; analyzing the baud rate of the corresponding data sending end through the baud rate according to a preset data format and a time sequence requirement;
the main path serial port data sending and caching module is used for realizing the caching of sending and outputting serial data;
and the main path serial port data sending module is used for realizing parallel-serial conversion of externally output serial data.
5. The baud rate adaptive serial port communication extension device based on the FPGA of claim 4, wherein the total serial port baud rate determination module and the branch serial port baud rate determination module both adopt the following determination processes:
performing primary oversampling on an external signal through a high-speed clock in the FPGA to obtain a signal edge of an external input signal; calculating the time interval of the signal edges according to the high-speed clock period between the signal edges; and counting the time intervals of a plurality of adjacent falling edges and rising edges, and averaging the data periods transmitted by a plurality of serial ports to obtain the baud rate of the serial signals.
6. The FPGA-based baud rate adaptive serial port communication extension device of claim 5, wherein the calculation process of the baud rate of the serial signal is as follows:
collecting a signal falling edge for the first time, and starting to calculate by using a counter;
continuously acquiring a signal rising edge and taking the signal rising edge and the first signal falling edge as a time interval;
continuously acquiring the next signal falling edge, counting once by adopting a counter, and circulating for multiple times to respectively obtain a count value;
averaging the multiple counting values by adopting corresponding serial port transmission data periods to obtain a serial port transmission data period; and calculating the reciprocal of the serial port transmission data period to obtain the serial port baud rate.
7. The baud rate adaptive serial port communication extension device based on the FPGA of claim 4, wherein the main serial port data receiving and buffering module, the branch serial port data sending and buffering module, the branch serial port data receiving and buffering module and the main serial port data sending and buffering module are all realized by using a BLOCK RAM module in the FPGA;
the main path serial port data receiving module and the branch path serial port data receiving module convert serial data into 8-bit parallel data in a shift register mode;
the main path serial port data sending module and the branch path serial port data sending module convert 8-bit parallel data into single-bit serial data in a mode of a shift register.
8. The FPGA-based baud rate adaptive serial port communication extension device of claim 1, wherein the baud rate of a first branch serial port in the logic processor FPGA is automatically calculated according to a first total serial port baud rate.
9. The FPGA-based baud rate adaptive serial port communication expansion device of claim 1, wherein the baud rate of the second main serial port in the FPGA of the logic processor is set as the baud rate of the channel with the maximum branch serial port rate multiplied by the number of branch channels actually receiving data.
10. The baud rate self-adaptive serial port communication expansion method based on the FPGA is characterized in that the method is applied to the baud rate self-adaptive serial port communication expansion device based on the FPGA as claimed in any one of claims 1 to 9; the method comprises the following steps:
receiving an external input serial signal, analyzing the baud rate of the external input serial signal at the moment through a trunk serial port baud rate judging module, acquiring effective data of the input serial signal through the baud rate, converting the serial data into parallel data, and storing the parallel data into a trunk serial port receiving cache; according to a preset frame format, splitting a data frame, sending parallel data in a main path serial port receiving cache to a branch path serial port sending cache, simultaneously converting data in each branch path serial port sending cache into serial data, and outputting each branch path serial data; and
each branch serial port receives a serial port signal input from the outside, the baud rate of the input signal of each branch serial port is analyzed through a branch serial port baud rate judging module, data input from a self port is analyzed through the respective baud rate, serial data are converted into parallel data, and the parallel data are stored in a receiving cache of each branch serial port; and combining data frames according to a preset frame format, sending the combined data into a main serial port sending buffer according to a certain sequence, simultaneously converting the combined data into total serial data, and outputting the total serial data.
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