CN114706803A - Multi-rate adaptation method and PCIe device - Google Patents
Multi-rate adaptation method and PCIe device Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
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Abstract
The embodiment of the invention discloses a multi-rate adaptation method and PCIe equipment. The method comprises the following steps: acquiring the speed grade of a PCIe host end and the speed grade of a PCIe equipment end; if the speed grade of the PCIe host end is lower than that of the PCIe equipment end, the speed grade of the PCIe equipment end is adjusted so that the adjusted speed grade of the PCIe equipment end is the same as that of the PCIe host end; and carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end. The problem that the speed grade of the PCIe host end is not matched with the speed grade of the PCIe equipment end, normal communication cannot be achieved, and the PCIe analyzer cannot capture PCIe bus data with the speed grade higher than the speed grade allowed by the PCIe analyzer is solved, and the cost for replacing the PCIe analyzer equipment is saved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a multi-rate adaptation method and a PCIe device.
Background
The PCIe interface is used for an expansion slot interface on a PC at first and used for transmitting data between devices of a high-speed interface, and the 5G communication module needs to use the PCIe interface for data transmission in order to better meet the requirement of a network on large data transmission when the 5G era comes. The PCIe interface hardware characteristics also determine the specific conditions required by the enumeration adaptation, and the PCIe interface is an end-to-end connection topology mode, so that an opposite-end PCIe device is required to be provided at first; secondly, two opposite-end devices need to have own interface working modes, one device is used as a PCIe host end (Root Complex), and the other device is used as a PCIe device end (Endpoint); finally, enumeration of two opposite-end devices requires information interaction and configuration synchronization.
The PCIe analyzer is an instrument for capturing PCIe physical bus signals in a professional way, can capture interactive information of a PCIe host end (Root Complex) and an equipment end (Endpoint) in real time, is an effective debugging and positioning analysis auxiliary tool, and has a strict PCIe physical bus speed matching relation, and correct and effective debugging information cannot be captured due to speed mismatching. At present, PCIe analyzers with different speed grades cannot be completely compatible, and a PCIe analyzer with a higher speed grade needs to be updated with new hardware equipment; moreover, the cost for purchasing and upgrading the PCIe analyzer with higher speed grade is high, the period from submitting the application for upgrading the speed grade to updating software and hardware equipment is long, and the problem of urgent need cannot be solved; because the BIOS configuration of the PCIe Root Complex at the host end is fixed and is not allowed to be modified, and the PCIe bus speed configuration risk of randomly upgrading the BIOS is large, the conventional PCIe Root Complex host end is configured to be Automatic; debugging M.2 equipment of different PCIe bus speed grades at every turn is loaded down with trivial details and consuming time long, and the bus signal attenuation compensation of debugging every time can not all be compatible with the PCIe analysis appearance application of different PCIe bus speed grades, the cost of very big increase manpower man-hour, and is inefficient.
Disclosure of Invention
Based on this, the present application provides a multi-rate adaptation method and a PCIe device to overcome the above technical drawbacks.
In a first aspect, the present application provides a multi-rate adaptation method, comprising:
acquiring the speed grade of a PCIe host end and the speed grade of a PCIe equipment end; if the speed grade of the PCIe host end is lower than that of the PCIe equipment end, the speed grade of the PCIe equipment end is adjusted so that the adjusted speed grade of the PCIe equipment end is the same as that of the PCIe host end; and carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
With reference to the first aspect, in a possible embodiment, if the speed level of the PCIe host side is higher than or equal to the speed level of the PCIe device side, the PCIe host side performs data communication with the PCIe host side through the PCIe bus according to the speed level of the PCIe device side.
With reference to the first aspect, if the speed class of the PCIe host end is smaller than the speed class of the PCIe device end, adapting the speed class of the PCIe device end according to the speed class of the PCIe host end includes: and reducing the speed grade of the PCIe equipment end according to the speed grade of the PCIe host end so as to ensure that the speed grade of the PCIe equipment end is the same as that of the PCIe host end.
With reference to the first aspect, adapting the speed class of the PCIe device side according to the speed class of the PCIe host side, further includes:
and triggering the physical link RE-train of the PCIe bus according to the speed grade of the PCIe host end so as to ensure that the PCIe device end and the PCIe host end normally communicate.
With reference to the first aspect, in one possible embodiment, triggering the PCIe bus physical link RE-train according to the PCIe host-side speed level includes:
training the speed grade of a physical link of the PCIe bus;
training the link bandwidth of a physical link of a PCIe bus;
a signal quality value for a physical link of a PCIe bus is trained.
With reference to the first aspect, data communication is performed with the PCIe host end through the PCIe bus according to the speed level of the PCIe host end and the adjusted speed level of the PCIe device end:
matching impedance matching parameters and signal attenuation compensation parameters corresponding to the speed grade according to the speed grade of the PCIe host end;
and selecting a communication line corresponding to the parameters of the impedance matching and the signal attenuation compensation, and then carrying out data communication with the PCIe host end through a PCIe bus.
With reference to the first aspect, in a possible embodiment, before obtaining the speed class of the PCIe host side and the speed class of the PCIe device side, the method further includes: and the PCIe device side initializes hardware, configures a clock signal and configures a DDR type.
In a second aspect, an embodiment of the present application provides a PCIe device, including:
an acquisition module: the method comprises the steps of obtaining a speed grade of a PCIe host end and a speed grade of a PCIe device end;
an adjusting module: the speed grade adjusting device is used for adjusting the speed grade of the PCIe device end if the speed grade of the PCIe host end is lower than that of the PCIe device end, so that the adjusted speed grade of the PCIe device end is the same as that of the PCIe host end;
a communication module: and the PCIe bus is used for carrying out data communication with the PCIe host end through the PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
In a third aspect, an embodiment of the present application provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements part or all of the method in the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is implemented to implement part or all of the method in the first aspect when executed by a computer device.
The PCIe analyzer needs to be strictly matched with the speed of a PCIe physical bus to obtain the speed grades of a PCIe device end and a PCIe host end, when the speed grades of the PCIe device end and the PCIe host end are not matched, the speed grade between the PCIe device end and the PCIe host end is adapted by adjusting the speed grade of the PCIe device end, so that when the speed grades of the PCIe device end and the PCIe host end are not matched, a PCIe module adapts to the PCIe analyzer with a lower speed grade at present, and the purchase cost of the device instrument and the labor hour debugging impedance matching cost are saved.
Drawings
In order to more clearly illustrate the technical solution in the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below.
Fig. 1 is a schematic structural diagram of a PCIe module according to an embodiment of the present application;
FIG. 2 is a schematic flow chart diagram of a multi-rate adaptation method provided by an embodiment of the present application;
fig. 3 is a schematic structural diagram of a multi-speed-class communication line according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of another PCIe device provided in the embodiments of the present application;
fig. 5 is a schematic structural diagram of another PCIe device according to an embodiment of the present application.
Detailed Description
The terminology used in the following embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In this application, "at least one" means one or more, "a plurality" means two or more, "at least two" means two or three and three or more, "and/or" for describing an association relationship of associated objects, which means that there may be three relationships, for example, "a and/or B" may mean: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one item(s) below" or similar expressions refer to any combination of these items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b," a and c, "" b and c, "or" a and b and c.
The present application is described in further detail below with reference to the attached figures.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a PCIe module according to an embodiment of the present application. As shown in fig. 1, the PCIe module includes a PCIe device side 101, a PCIe controller 1011, a PCIe host side 102, a PCIe analyzer 1021;
the PCIe End (PE) 101, as an initiator of PCIe bus operation, is located at the very end of a PCIe bus topology structure, and mainly includes devices such as a Solid State Disk (SSD), a Read-Only Memory (ROM), a Graphics Processing Unit (GPU), and the like;
the PCIe controller 1011 is configured to obtain speed levels of the PCIe host end and the PCIe device end, and adjust the speed level of the PCIe device end to adapt to the speed level of the PCIe host end when the speed levels of the PCIe host end and the PCIe device end are not matched;
the PCIe host side 102 can be regarded as a Root Complex (RC), and the RC is an interface between the CPU and the PCle bus, and may include several components (processor interface, DRAM interface, etc.), and may even include several chips. The RC is located at the "root" of the PCI inverted tree topology and communicates with the rest of the system on behalf of the CPU.
The PCIe analyzer 1021 is used for capturing interactive information of a PCIe host end and a PCIe device end in real time, and is an effective debugging and positioning analysis auxiliary tool.
Referring to fig. 2, fig. 2 is a schematic flow chart of a multi-rate adaptation method according to an embodiment of the present application. As shown in fig. 2, the method includes:
s201, obtaining the speed grade of the PCIe host end and the speed grade of the PCIe equipment end.
Specifically, the PCIe interface is an end-to-end link topology mode, the PCIe interface needs a PCIe device at an opposite end, that is, a PCIe host end and a PCIe device end, if the speed level of data received by the PCIe host end cannot be matched with the speed level of data transmission by the PCIe device end, the PCIe module cannot work normally, and the PCIe analyzer cannot capture PCIe bus data higher than the speed level of the PCIe analyzer itself, so that the speed level of the PCIe host end and the PCIe device end are obtained to compare whether the speed levels of the host end and the PCIe device end are matched, and whether adaptation needs to be adjusted.
In a possible embodiment, if the speed level of the PCIe host is higher than or equal to the speed level of the PCIe device, the PCIe host performs data communication with the PCIe host according to the speed level of the PCIe device.
Specifically, when the speed level of the PCIe host side is higher than or equal to that of the PCIe device side, the PCIe bus may normally transmit data, and the PCIe analyzer may capture PCIe bus data.
S202, if the speed grade of the PCIe host end is lower than that of the PCIe device end, the speed grade of the PCIe device end is adjusted, so that the adjusted speed grade of the PCIe device end is the same as that of the PCIe host end.
Specifically, only when the speed level of the PCIe device end is greater than the device level of the PCIe host end, the speed level of the PCIe device end needs to be adjusted to adapt to the speed level of the PCIe host end, so that the PCIe bus normally transmits data, and the PCIe analyzer can capture PCIe bus data.
In one example, a maximum Gen1 speed class PCIe analyzer can only capture PCIe bus data for the Gen1 speed class and cannot capture PCIe bus data for the Gen2, Gen3, Gen4 speed classes;
in one example, a maximum Gen2 speed class PCIe analyzer can only capture Gen1, Gen2 speed class PCIe bus data, and cannot capture Gen3, Gen4 speed class PCIe bus data;
in one example, the largest Gen3 speed class PCIe analyzer can only capture the Gen1, Gen2, Gen3 speed classes PCIe bus data, and cannot capture the Gen4 speed class PCIe bus data.
In a possible embodiment, if the speed class of the PCIe host end is smaller than the speed class of the PCIe device end, adapting the speed class of the PCIe device end according to the speed class of the PCIe host end includes: and reducing the speed grade of the PCIe equipment end according to the speed grade of the PCIe host end so as to ensure that the speed grade of the PCIe equipment end is the same as that of the PCIe host end.
Specifically, since the data communication between the PCIe host end and the PCIe device end needs to be performed normally at the same speed level, when the speed level of the PCIe host end is less than the speed level of the PCIe device end, the speed level of the PCIe device end needs to be limited to the speed level of the PCIe host end, that is, the speed level of the PCIe device end needs to be reduced, so that the speed level of the PCIe device end is the speed level of the PCIe host end, and the normal communication between the PCIe host end and the PCIe device end is further ensured.
In one possible embodiment, adapting the speed level of the PCIe device side according to the PCIe host side speed level further comprises: and triggering the physical link RE-train of the PCIe bus according to the speed grade of the PCIe host end so as to ensure that the PCIe device end and the PCIe host end normally communicate.
Specifically, after the speed level of the PCIe host end is synchronized with the speed level of the PCIe device end, the bus speed level of the PCIe physical link may still be in a speed level state before the PCIe device end is adjusted, and at this time, the PCIe bus physical link RE-train is triggered according to the speed level of the PCIe host end, and the PCIe host end and the PCIe device end can normally communicate after the physical link is retrained.
In one possible embodiment, triggering the PCIe bus physical link RE-train according to the PCIe host-side speed level comprises: training the speed grade of a physical link of the PCIe bus; training the link bandwidth of a physical link of a PCIe bus; a signal quality value for a physical link of a PCIe bus is trained.
Specifically, after limiting the speed class of the PCIe device end, the PCIe controller needs to retrain the PCIe bus physical link to adapt to a new data transmission speed class, including training the speed class of the PCIe bus physical link, for example, when the PCIe bus physical link needs to be adjusted from Gen1 to Gen2, parameters such as Bit Lock and Symbol Lock need to be retrained, no clock exists on the receiving end link of the PCIe bus, Symbol Lock represents a process of acquiring a marker COM character starting training on the PCIe link, and Bit Lock represents a process of acquiring clock information by receiving message information (with clock information) sent by the sending end; training the link bandwidth of the physical link of the PCIe bus, wherein the bandwidth refers to the amount of data which can be transmitted in a fixed time, namely the capacity of transmitting data in a transmission pipeline, and when the speed grade of the physical link of the PCIe bus is changed, the link bandwidth of the physical link needs to be retrained; and training a signal quality value of the physical link of the PCIe bus, wherein the signal quality value refers to the training of parameters such as strength, transmission rate and the like of transmission on the physical PCIe bus.
In a possible embodiment, the data communication is performed with the PCIe host end through the PCIe bus according to the speed level of the PCIe host end and the adjusted speed level of the PCIe device end: matching impedance matching parameters and signal attenuation compensation parameters corresponding to the speed grade according to the speed grade of the PCIe host end; and selecting a communication line corresponding to the parameters of the impedance matching and the signal attenuation compensation, and then carrying out data communication with the PCIe host end through a PCIe bus.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a multi-speed-level communication line provided in an embodiment of the present application, where data transmission of a PCIe host end and a PCIe device end at different speed levels correspond to different impedance matching parameters and signal attenuation compensation parameters, and the different impedance matching parameters and signal attenuation compensation parameters need to be implemented by corresponding electronic elements, and transmission lines corresponding to the impedance matching parameters and signal attenuation compensation parameters at different speed levels are preset in a PCIe device end, and according to a speed level of an adapted PCIe device end, transmission lines corresponding to the impedance matching parameters and signal attenuation compensation parameters are selected for data transmission.
And S203, carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
Specifically, the speed grade of the PCIe device end is limited by the PCIe controller, and after the PCIe bus physical link is retrained according to the new speed grade, the PCIe device end and the PCIe host end perform data transmission through the new speed grade, the PCIe analyzer captures PCIe bus data according to its own license (license), where the PCIe analyzer license has a corresponding relationship with the speed grade, and the PCIe analyzer license of the speed grade of Gen1 can only capture bus data with the speed grade of Gen1, so when the speed grade of the PCIe device end is higher than the speed grade permitted by the PCIe analyzer license, the PCIe analyzer cannot normally capture data on the PCIe bus. After the speed grade of the PCIe equipment end is adjusted, the PCIe host end can carry out data communication with the PCIe equipment end through a PCIe bus, and the PCIe analyzer captures data on the PCIe bus according to the license of the PCIe analyzer.
In a possible embodiment, before obtaining the speed class of the PCIe host side and the speed class of the PCIe device side, the method further includes: the PCIe device side initializes basic hardware, configures clock signals and configures DDR types.
Specifically, before starting to acquire the speed grades of the PCIe host end and the PCIe device end, the PCIe module needs to perform a series of initialization operations, including start initialization of the basic hardware; configuring a clock signal PCIe bus physical link Data transmission mechanism to use a clock-based synchronous transmission mechanism, but no clock line exists on the physical link, a receiving end of the PCIe bus comprises a Clock Data Recovery (CDR) module, and the CDR module extracts a receiving clock from a received message so as to transmit synchronous Data; the Double Data Rate (DDR) type is configured, the Data transmission speed can be twice the system clock frequency through the DDR technology, and different types of DDR are different in terms of bandwidth speed, operating frequency, and the like, so that the DDR type of the PCIe module needs to be determined before acquiring the speed grades of the PCIe host side and the PCIe device side.
In a possible embodiment, the multi-rate adaptation method applied to the PCIe device side may be implemented on any interface supporting the PCIe protocol.
Specifically, the multirate adaptation method of this embodiment is implemented based on a PCIe module, and may be implemented on any interface supporting a PCIe protocol, for example, an m.2 interface, a PCIe interface, an MPCIe interface, and the like.
It can be seen that, in the embodiment of the present application, the speed level of the PCIe host end and the speed level of the PCIe device end are obtained; if the speed grade of the PCIe host end is lower than that of the PCIe equipment end, the speed grade of the PCIe equipment end is adjusted so that the adjusted speed grade of the PCIe equipment end is the same as that of the PCIe host end; and carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end. The PCIe equipment end and the PCIe host end with different speed grades can normally communicate, the PCIe analyzer can capture PCIe bus data between the PCIe equipment and the PCIe host end which are not matched with the speed grades of the PCIe analyzer, the license of the PCIe analyzer and the strong dependence of bus physical signal impedance matching can be reduced, the current scene of the PCIe analyzer with a lower speed grade can be adapted, the compatibility of the PCIe analyzer at the PCIe host end is improved, the PCIe bus speed does not need to be adjusted by a BIOS at the host end, the adaptability superior to a competitive product module is achieved, and the purchase cost of equipment and instruments and the cost of manpower man-hour debugging impedance matching are saved.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a PCIe device according to an embodiment of the present application. As shown in fig. 4, the PCIe device includes:
the acquisition module 401: the method comprises the steps of obtaining a speed grade of a PCIe host end and a speed grade of a PCIe device end;
the adjustment module 402: the speed grade adjusting device is used for adjusting the speed grade of the PCIe device end if the speed grade of the PCIe host end is lower than that of the PCIe device end, so that the adjusted speed grade of the PCIe device end is the same as that of the PCIe host end;
the communication module 403: and the PCIe bus is used for carrying out data communication with the PCIe host end through the PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
In a possible embodiment, the communication module 403 is further configured to:
when the speed grade of the PCIe host end is higher than or equal to that of the PCIe device end, the speed grade of the PCIe device end carries out data communication with the PCIe host end through a PCIe bus.
In one possible embodiment, in terms of adapting the speed level of the PCIe device side according to the speed level of the PCIe host side, the adjusting module 402 is specifically configured to:
and reducing the speed grade of the PCIe equipment end according to the speed grade of the PCIe host end so as to ensure that the speed grade of the PCIe equipment end is the same as that of the PCIe host end.
In one possible embodiment, in adapting the speed level on the PCIe device side according to the speed level on the PCIe host side, the adjusting module 402 is further specifically configured to:
and triggering a PCIe bus physical link RE-train according to the speed grade of the PCIe host end so as to enable the PCIe device end to normally communicate with the PCIe host end.
In one possible embodiment, in triggering the PCIe bus physical link RE-train according to the PCIe host-side speed level, the adjusting module 402 is specifically configured to:
training the speed grade of a physical link of the PCIe bus;
training the link bandwidth of a physical link of a PCIe bus;
a signal quality value for a physical link of a PCIe bus is trained.
In a possible embodiment, the communication module 403 is further configured to match, according to a speed class at the PCIe host end, an impedance matching parameter and a signal attenuation compensation parameter corresponding to the speed class; and selecting a communication line corresponding to the parameters of impedance matching and signal attenuation compensation, and then carrying out data communication with the PCIe host end through a PCIe bus.
In a possible embodiment, the adjusting module 402 is further configured to:
and hardware initialization is carried out on the PCIe equipment terminal, a clock signal is configured, and a DDR type is configured.
It should be noted that the above modules (the obtaining module 401, the adjusting module 402, and the communication module 403) are used to execute relevant steps of the above method. For example, the obtaining module 401 is configured to execute the relevant content of step S201, and the adjusting module 402 is configured to execute the relevant content of step S202; the communication module 403 is used for executing the relevant content of step S203.
In this embodiment, the PCIe device 400 is presented in the form of a module. A "module" herein may refer to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other devices that may provide the described functionality. Further, the above obtaining module 401, the adjusting module 402 and the communication module 403 may be implemented by the processor 501 and the communication interface 503 of the PCIe device shown in fig. 5.
As shown in fig. 5, PCIe device 500 may be implemented as the architecture in fig. 5, where PCIe device 500 includes at least one processor 501, at least one memory 502, and at least one communication interface 503. The processor 501, the memory 502, and the communication interface 503 are connected via the communication bus to complete communication therebetween.
The processor 501 may be a general purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs according to the above schemes.
The Memory 502 may be, but is not limited to, a Read-Only Memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 602 may be separate and connected to the processor 501 via a bus. The memory 502 may also be integrated with the processor 501.
The memory 502 is used for storing application program codes for executing the above scheme, and is controlled by the processor 501 for execution. The processor 501 is used to execute application program code stored in the memory 502.
The memory 502 stores code that may perform one of the multi-rate adaptation methods provided above, such as:
acquiring the speed grade of a PCIe host end and the speed grade of a PCIe equipment end; if the speed grade of the PCIe host end is lower than that of the PCIe equipment end, the speed grade of the PCIe equipment end is adjusted so that the adjusted speed grade of the PCIe equipment end is the same as that of the PCIe host end; and carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
Embodiments of the present application also provide a computer storage medium, where the computer storage medium may store a program, and the program includes some or all of the steps of any one of the multi-rate adaptation methods described in the above method embodiments when executed.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art will recognize that the embodiments described in this specification are preferred embodiments and that acts or modules referred to are not necessarily required for this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solutions of the present application, in essence or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A multi-rate adaptation method is applied to a PCIe device side, and is characterized by comprising the following steps:
acquiring a speed grade of a PCIe host end and a speed grade of the PCIe equipment end;
if the speed grade of the PCIe host end is lower than that of the PCIe equipment end, adjusting the speed grade of the PCIe equipment end so as to enable the adjusted speed grade of the PCIe equipment end to be the same as that of the PCIe host end;
and carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
2. The method of claim 1, further comprising:
and if the speed grade of the PCIe host end is higher than or equal to the speed grade of the PCIe equipment end, carrying out data communication with the PCIe host end through the PCIe bus according to the speed grade of the PCIe equipment end.
3. The method of claim 1 or 2, wherein said adapting the speed class on the PCIe device side from the speed class on the PCIe host side comprises:
and reducing the speed grade of the PCIe equipment end according to the speed grade of the PCIe host end so as to ensure that the speed grade of the PCIe equipment end is the same as that of the PCIe host end.
4. The method of claim 4, wherein said adapting the speed level on the PCIe device side according to the PCIe host side speed level further comprises:
and triggering a PCIe bus physical link RE-train according to the PCIe host end speed grade so as to enable the PCIe device end to normally communicate with the PCIe host end.
5. The method of claim 5, wherein triggering a PCIe bus physical link RE-train according to the PCIe host side speed level comprises:
training a speed level of the PCIe bus physical link;
training the link bandwidth of the PCIe bus physical link;
training a signal quality value for the PCIe bus physical link.
6. The method of claim 1, wherein the performing data communication with the PCIe host according to the adjusted speed class of the PCIe host and the adjusted speed class of the PCIe device via the PCIe bus comprises:
matching impedance matching parameters and signal attenuation compensation parameters corresponding to the speed grade according to the speed grade of the PCIe host end;
and selecting a communication line corresponding to the parameters of the impedance matching and the signal attenuation compensation, and then carrying out data communication with the PCIe host end through the PCIe bus.
7. The method of claims 1-6, wherein prior to obtaining the speed class on the PCIe host side and the speed class on the PCIe device side, the method further comprises:
and the PCIe equipment terminal initializes hardware, configures a clock signal and configures a DDR type.
8. A PCIe device, comprising:
an acquisition module: the speed grade acquisition module is used for acquiring the speed grade of a PCIe host end and the speed grade of the PCIe equipment end;
an adjusting module: the speed grade adjusting module is used for adjusting the speed grade of the PCIe device end if the speed grade of the PCIe host end is lower than that of the PCIe device end, so that the adjusted speed grade of the PCIe device end is the same as that of the PCIe host end;
a communication module: and the PCIe bus is used for carrying out data communication with the PCIe host end through a PCIe bus according to the speed grade of the PCIe host end and the regulated speed grade of the PCIe equipment end.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method according to any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a computer device, carries out the steps of the method according to any one of claims 1 to 7.
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