CN114706605A

CN114706605A - Flash upgrading method, device, equipment and storage medium

Info

Publication number: CN114706605A
Application number: CN202210188825.5A
Authority: CN
Inventors: 王金友; 韩威
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2022-07-05

Abstract

The application discloses a Flash upgrading method, a device, equipment and a storage medium, comprising the following steps: obtaining an upgrading instruction, and reading identification information of an off-chip Flash according to the upgrading instruction; judging whether the read identification information is identification information in a preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to an FPGA chip through PCIE main equipment on the processor; and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip. According to the method and the device, only new Flash identification information needs to be added into the preset list in subsequent application, upper-layer driving is not needed to be adjusted, and only multi-model Flash upgrading is compatible to FPGA logic, so that the software processing complexity is reduced, and the development efficiency is improved.

Description

Flash upgrading method, device, equipment and storage medium

Technical Field

The invention relates to the technical field of computers, in particular to a Flash upgrading method, a Flash upgrading device, Flash upgrading equipment and a Flash upgrading storage medium.

Background

As data center services have rapidly developed, data center switch demand has also increased rapidly. The FPGA has rich logic resources and flexible logic programming, can realize high-speed customized forwarding service, meets the high-speed virtualization requirement, and is widely applied to data centers. With the large deployment of FPGA equipment, the demand of an on-line updating function of an FPGA mirror image is increased, the current on-line updating function supports single-model Flash, the supply chain fluctuates, and the demand that each manufacturer can support the Flash of multiple manufacturers for an FPGA external program memory is stronger and stronger.

Therefore, how to provide a Flash upgrading scheme compatible with multiple models is a technical problem to be solved urgently by technical personnel in the field.

Disclosure of Invention

In view of this, the present invention provides a Flash upgrading method, apparatus, device and storage medium, which are compatible with multi-model Flash upgrading, reduce software processing complexity and improve development efficiency.

The specific scheme is as follows:

a first aspect of the present application provides a Flash upgrading method, including:

obtaining an upgrading instruction, and reading identification information of an off-chip Flash according to the upgrading instruction;

judging whether the read identification information is identification information in a preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to an FPGA chip through PCIE main equipment on the processor;

and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip.

Optionally, after determining whether the read identification information is identification information in a preset identification list, the method further includes:

if so, switching the off-chip Flash to the processor side by using a multiplexer so as to write the FPGA mirror image to be upgraded into an upgrade mirror image area of the corresponding off-chip Flash through an SPI controller of the processor.

if so, initializing the off-chip Flash and erasing the upgrade mirror area;

and reporting successful erasing information after successful erasing so as to generate a mirror image issuing instruction and transmit the FPGA mirror image to be upgraded to the FPGA chip through PCIE main equipment on the processor according to the mirror image issuing instruction.

Optionally, after the SPI controller of the FPGA chip writes the to-be-upgraded FPGA image into the upgrade image area of the corresponding off-chip Flash, the method further includes:

judging whether the FPGA mirror image to be upgraded is completely written, if not, switching the FPGA chip to an idle state after waiting for a preset time;

if yes, the FPGA chip is used for reading the written FPGA mirror image to be upgraded from the off-chip Flash, the read FPGA mirror image to be upgraded is verified, if the verification is passed, the upgrading is judged to be successful, the FPGA chip is switched to an idle state, and if the verification is not passed, the FPGA chip is switched to the idle state.

Optionally, the reading the written FPGA image to be upgraded from the off-chip Flash by using the FPGA chip, and checking the read FPGA image to be upgraded includes:

starting from an initial address in off-chip Flash by using the FPGA chip and jumping to a first timing mirror image address so as to jump to the upgrading mirror image area after waiting for the first time defined by the first timing mirror image and read and check the FPGA mirror image to be upgraded written in the upgrading mirror image area.

Optionally, after reading and verifying the FPGA image to be upgraded written in the upgrade image area, the method further includes:

if the verification is not passed, jumping to a second timing mirror image address, so as to jump to an inherent mirror image area after waiting for second time defined by the second timing mirror image and read and verify the mirror image in the inherent mirror image area;

and if the verification is not passed, jumping to the first timing mirror address, so as to jump to the initial address after waiting for the first time.

if not, the FPGA chip is switched to an idle state, and a new upgrading instruction is waited for.

A second aspect of the present application provides a Flash upgrade apparatus, including:

the identification reading module is used for acquiring an upgrading instruction and reading identification information of the off-chip Flash according to the upgrading instruction;

the identification matching module is used for judging whether the read identification information is the identification information in the preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to the FPGA chip through PCIE main equipment on the processor;

and the first write-in module is used for writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the corresponding off-chip Flash through the SPI controller of the FPGA chip when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded.

A third aspect of the application provides an electronic device comprising a processor and a memory; the memory is used for storing a computer program, and the computer program is loaded and executed by the processor to realize the Flash upgrading method.

A fourth aspect of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are loaded and executed by a processor, the Flash upgrade method is implemented.

In the application, an upgrading instruction is obtained first, and identification information of an off-chip Flash is read according to the upgrading instruction; then judging whether the read identification information is identification information in a preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to an FPGA chip through PCIE main equipment on the processor; and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip. Therefore, after the identification information of the off-chip Flash is read, whether the identification information is the identification information in the preset identification list or not is judged, namely whether the identification information matched with the identification information exists in the preset identification list or not is judged, and if the identification information is matched with the identification information, the FPGA mirror image to be upgraded is written into the corresponding off-chip Flash through the SPI controller of the FPGA chip. In subsequent application, only new Flash identification information needs to be added into a preset list, upper-layer drive does not need to be adjusted, and only multi-model Flash upgrading is compatible on FPGA logic, so that software processing complexity is reduced, and development efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a flowchart of a Flash upgrading method provided in the present application;

FIG. 2 is a schematic diagram of a specific Flash upgrade architecture provided in the present application;

FIG. 3 is a flowchart of a specific Flash upgrading method provided by the present application;

FIG. 4 is a flowchart illustrating a specific mirror read verify process provided herein;

FIG. 5 is a specific structure diagram of Flash provided by the present application;

FIG. 6 is a schematic structural diagram of a Flash upgrading apparatus provided in the present application;

fig. 7 is a structural diagram of an electronic device for Flash upgrade provided by the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

With the large deployment of FPGA equipment, the demand of an on-line updating function of an FPGA mirror image is increased, the current on-line updating function supports single-model Flash, the supply chain fluctuates, and the demand that each manufacturer can support the Flash of multiple manufacturers for an FPGA external program memory is stronger and stronger. Aiming at the technical defects, the method and the device for upgrading the Flash only need to add new Flash identification information to a preset list according to requirements, do not need to adjust upper-layer drivers, are only compatible with multi-model Flash upgrading on FPGA logic, reduce software processing complexity and improve development efficiency.

Fig. 1 is a flowchart of a Flash upgrading method provided in an embodiment of the present application. Referring to fig. 1, the Flash upgrading method includes:

s11: and acquiring an upgrading instruction, and reading identification information of the off-chip Flash according to the upgrading instruction.

In this embodiment, an implementation architecture of the implementation is as shown in fig. 2, and includes a processor CPU and an FPGA chip, where the CPU is a management chip and mainly includes a PCIE master device, a general IO, a serial port controller, and an SPI controller. The PCIE master device mainly achieves access from the PCIE register, and the serial port controller mainly achieves access of the upper computer to the CPU. The FPGA chip is an interface module and mainly comprises PCIE slave equipment, a register and an SPI controller. The PCIE slave device mainly achieves interconnection of the PCIE master device and a register interface, the register mainly achieves read-write access of the register, the SPI controller mainly achieves off-chip Flash register access and an on-line upgrading function of the FPGA, and logic mirror images can be upgraded according to needs. In addition, the PCIE source end can select an Intel BDED-1527 chip which is a core management chip; the PCIE slave, registers, and SPI controller are all implemented on xc7a35tfgg484 chip of Xlinx.

Therefore, in this embodiment, an upgrade instruction is first obtained, and identification information of the off-chip Flash is read according to the upgrade instruction. The identification information is Flash Device ID of Flash. Based on the framework, the Flash of multiple manufacturers can be compatible only in FPGA logic, a unified interface is provided for upper-layer software, unified processing of the software is facilitated, and the complexity of software processing is reduced, so that the development difficulty and risk are reduced, the operation cost is reduced, and the aim of improving economic benefits is fulfilled. It should be noted that, at present, three types of flashes, namely mt25ql512, mx25q512 and winbond25q512, are supported, and a new Flash support can be completed only by adding a new Flash model and a corresponding command support in the preset identification list, so that the method has good expansibility.

S12: and judging whether the read identification information is identification information in a preset identification list, and if so, transmitting the FPGA mirror image to be upgraded to the FPGA chip through PCIE main equipment on the processor.

In this embodiment, it is determined whether the read identification information is identification information in a preset identification list, and if so, the PCIE master device on the processor transmits the FPGA image to be upgraded to the FPGA chip. If not, the FPGA chip is switched to an idle state, and a new upgrading instruction is waited for. Specifically, the PC accesses upper software through a serial port terminal tool, and the upper software accesses the FPGA register by calling PCIE drive, so that the SPI controller can be accessed. Defaulting that the FPGA chip is in an idle state, after software issues an upgrade command, the FPGA chip firstly reads a Flash Device ID of Flash, then matches the Flash Device ID with a Flash ID list (the preset identification list), and if the Flash Device ID is not matched with the preset identification list, the FPGA chip enters the idle state. And if the updating mirror image area is matched with the updating mirror image area, initializing the off-chip Flash and erasing the updating mirror image area. And reporting the successful erasing information after successful erasing, namely reporting upper-layer software after the erasing is completed to generate a mirror image issuing instruction and transmitting the FPGA mirror image to be upgraded to the FPGA chip through PCIE (peripheral component interface express) main equipment on the processor according to the mirror image issuing instruction. The specific process described above is shown in fig. 3.

It should be noted that, as can be seen from fig. 2, the Flash upgrade in this embodiment supports not only the CPU upgrading Flash through FPGA, but also the CPU directly upgrading Flash. That is, after the read identification information is judged to be the identification information in the preset identification list, the off-chip Flash is switched to the processor side by using the multiplexer, so that the FPGA mirror image to be upgraded is written into the upgrading mirror image area of the corresponding off-chip Flash through the SPI controller of the processor. Specifically, regarding the direct upgrading of Flash by a CPU: the CPU switches the Flash to the SPI controller on the CPU side through the general IO, and the FPGA mirror image is written into the Flash through the CPU. The general IO mainly controls the peripheral to switch two groups of SPI channel signals, the FPGA and the Flash channel are enabled by default, and the SPI controller mainly realizes FLASH read-write access. The method can be used for batch burn-recording FPGA mirror images in a factory. Upgrading Flash of a CPU through an FPGA: firstly, a CPU switches Flash to an FPGA side through a general IO, the CPU is connected with the FPGA through a group of PCIE interfaces, the FPGA mirror image is sent to an SPI controller according to the upgrading requirement of the SPI controller, and the SPI controller writes the mirror image into a Flash upgrading mirror image area.

S13: and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip.

In this embodiment, when the PCIE slave device of the FPGA chip receives the FPGA image to be upgraded, the SPI controller of the FPGA chip writes the FPGA image to be upgraded into the upgrade image area of the Flash outside the corresponding chip. And then, judging whether the FPGA mirror image to be upgraded is completely written, if not, switching the FPGA chip to an idle state after waiting for preset time. I.e., the image has not been written to, then waits, e.g., 30s without writing and then transitions to the idle state over time.

And if the mirror image writing is finished, reading the written FPGA mirror image to be upgraded from the off-chip Flash by using the FPGA chip, verifying the read FPGA mirror image to be upgraded, judging that the upgrading is successful if the verification is passed, switching the FPGA chip to an idle state, and switching the FPGA chip to the idle state if the verification is not passed. This process is also illustrated in fig. 3. In addition, the check may be a cyclic Redundancy check crc (cyclic Redundancy check). That is, the FPGA chip reads the written mirror image to perform CRC check, if the CRC check is wrong, the CRC check is reported to the upper layer software, and if the CRC check is correct, the upper layer software is informed that the upgrade is successful. And at the moment, the FPGA chip returns to the idle state again to wait for the next upgrading operation of the CPU.

Therefore, the method and the device for upgrading the Flash card firstly acquire the upgrading instruction, and read the identification information of the off-chip Flash according to the upgrading instruction; then judging whether the read identification information is identification information in a preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to an FPGA chip through PCIE main equipment on the processor; and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip. According to the embodiment of the application, after the identification information of the off-chip Flash is read, whether the identification information is the identification information in the preset identification list or not is judged, that is, whether the identification information matched with the identification information exists in the preset identification list or not is judged, and if the identification information is matched with the identification information, the FPGA mirror image to be upgraded is written into the corresponding off-chip Flash through the SPI controller of the FPGA chip. In subsequent application, only new Flash identification information needs to be added into a preset list, upper-layer drive does not need to be adjusted, and only multi-model Flash upgrading is compatible on FPGA logic, so that software processing complexity is reduced, and development efficiency is improved.

On the basis of the above embodiment, fig. 4 is a corresponding mirror read verification process. Referring to fig. 4, the mirror read verification process includes:

s21: starting from an initial address in off-chip Flash by using the FPGA chip and jumping to a first timing mirror image address so as to jump to the upgrading mirror image area after waiting for the first time defined by the first timing mirror image and read and check the FPGA mirror image to be upgraded written in the upgrading mirror image area.

In this embodiment, the off-chip Flash structure is divided into an inherent mirror area, a first timing mirror area, an upgrade mirror area, a second timing mirror area, and an unused area, as shown in fig. 5. Wherein, an inherent mirror image is put at 4Mbit in front of the Flash, and the mirror image mainly completes the function of mirror image skip; the first timing mirror image of 4Kbit mainly completes the timing function; 4 Mbit-8 Mbit of the FPGA mirror image to be upgraded is placed, and the mirror image mainly completes the logic function of the user; the second timing mirror of 60 bits mainly performs the timing function. The inherent mirror image and the mirror image to be upgraded are bit files or bin files directly generated by a compiling tool. The timing image file is defined according to the requirements of xc7a35 tfgg-2. The specific 16-ary format is shown in the following table:

the timing mirror image mainly defines a watchdog, and returns to a Flash initial address to wait for next mirror image loading after the FPGA mirror image to be upgraded is checked to be wrong. The timing mirror image is not added, and the intrinsic mirror image area cannot be returned after the FPGA mirror image to be upgraded is checked to be wrong. The minimum timing period of the timer is about 4us, and a user only needs to select a proper timing count value according to the actual Flash performance and the program loading time.

In this embodiment, after the normal FPGA is powered on, the FPGA chip is first started from an initial address in the off-chip Flash and jumps to a first timing mirror address, so as to jump to the upgrade mirror area after waiting for a first time defined by the first timing mirror and read and check the FPGA mirror image to be upgraded written in the upgrade mirror area. I.e. first starts from the 0x0000 — 0000 address of Flash and jumps to the first timing mirror. And waiting for a fixed time, skipping to an upgrading mirror image area, reading the written FPGA mirror image to be upgraded and checking.

S22: if the verification is not passed, jumping to a second timing mirror image address, so as to jump to an inherent mirror image area after waiting for second time defined by the second timing mirror image and read and verify the mirror image in the inherent mirror image area;

s23: and if the verification is not passed, jumping to the first timing mirror address, so as to jump to the initial address after waiting for the first time.

In this embodiment, if the verification fails, jumping to a second timing mirror address, so as to jump to an intrinsic mirror area after waiting for a second time defined by the second timing mirror and perform reading and verification on the mirror in the intrinsic mirror area. That is, the upgrade image area fails to be checked, the system waits for a fixed time to jump to the inherent image area. And if the upgrade image area is successfully verified, the FPGA works in the upgrade image area. Further, if the check of the intrinsic mirror image area is not passed, jumping to the first timing mirror image address, so as to jump to the initial address after waiting for the first time. That is, the check of the intrinsic mirror area fails, jumps to the first timing mirror, and waits for a fixed time to jump to the address 0x0000 — 0000.

Referring to fig. 6, an embodiment of the present application further discloses a Flash upgrading apparatus, which includes:

the identification reading module 11 is used for acquiring an upgrading instruction and reading identification information of the off-chip Flash according to the upgrading instruction;

the identifier matching module 12 is configured to determine whether the read identifier information is identifier information in a preset identifier list, and if so, transmit the FPGA image to be upgraded to the FPGA chip through a PCIE master device on the processor;

and the first write-in module 13 is configured to, when the PCIE slave device of the FPGA chip receives the FPGA image to be upgraded, write the FPGA image to be upgraded into an upgrade image area of the off-chip Flash through the SPI controller of the FPGA chip.

Therefore, in the embodiment of the application, the upgrading instruction is firstly obtained, and the identification information of the off-chip Flash is read according to the upgrading instruction; then judging whether the read identification information is identification information in a preset identification list or not, and if so, transmitting the FPGA mirror image to be upgraded to an FPGA chip through PCIE main equipment on the processor; and when the PCIE slave equipment of the FPGA chip receives the FPGA mirror image to be upgraded, writing the FPGA mirror image to be upgraded into an upgrade mirror image area of the Flash outside the corresponding chip through the SPI controller of the FPGA chip. According to the embodiment of the application, after the identification information of the off-chip Flash is read, whether the identification information is the identification information in the preset identification list or not is judged, that is, whether the identification information matched with the identification information exists in the preset identification list or not is judged, and if the identification information is matched with the identification information, the FPGA mirror image to be upgraded is written into the corresponding off-chip Flash through the SPI controller of the FPGA chip. In subsequent application, only new Flash identification information needs to be added into a preset list, upper-layer drive does not need to be adjusted, and only multi-model Flash upgrading is compatible on FPGA logic, so that software processing complexity is reduced, and development efficiency is improved.

In some specific embodiments, when the read identification information is identification information in a preset identification list, the Flash upgrading apparatus further includes:

the second write-in module is used for switching the off-chip Flash to the processor side by using the multiplexer so as to write the FPGA mirror image to be upgraded into the upgrading mirror image area of the corresponding off-chip Flash through the SPI controller of the processor;

the erasing module is used for initializing off-chip Flash and erasing the upgrading mirror image area;

and the reporting module is used for reporting the successful erasing information after successful erasing so as to generate a mirror image issuing instruction and transmitting the FPGA mirror image to be upgraded to the FPGA chip through PCIE (peripheral component interface express) main equipment on the processor according to the mirror image issuing instruction.

In some specific embodiments, the Flash upgrading apparatus further includes:

the write-in judging module is used for judging whether the FPGA mirror image to be upgraded is completely written in, and if not, the FPGA chip is switched to an idle state after waiting for preset time;

the read checking module is used for reading the written FPGA mirror image to be upgraded from the off-chip Flash by using the FPGA chip and checking the read FPGA mirror image to be upgraded if the read FPGA mirror image to be upgraded passes the check, judging that the upgrade is successful if the read FPGA mirror image to be upgraded passes the check, and switching the FPGA chip to an idle state if the read FPGA mirror image to be upgraded does not pass the check;

and the switching module is used for switching the FPGA chip to an idle state and waiting for a new upgrading instruction when the read identification information is not the identification information in the preset identification list.

In some specific embodiments, the read check module specifically includes:

the first skipping unit is used for starting from an initial address in the off-chip Flash by using the FPGA chip and skipping to a first timing mirror image address;

and the second jumping unit is used for jumping to the upgrading mirror image area after waiting for the first time defined by the first timing mirror image and reading and verifying the FPGA mirror image to be upgraded written in the upgrading mirror image area.

A third jumping unit, configured to jump to a second timing mirror address if the verification fails, so as to jump to an intrinsic mirror area after waiting for a second time defined by the second timing mirror and perform reading and verification on a mirror in the intrinsic mirror area;

and the fourth jumping unit is used for jumping to the first timing mirror image address if the verification is not passed so as to jump to the initial address after waiting for the first time.

Further, the embodiment of the application also provides electronic equipment. FIG. 7 is a block diagram illustrating an electronic device 20 according to an exemplary embodiment, and the contents of the diagram should not be construed as limiting the scope of use of the present application in any way.

Fig. 7 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present disclosure. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. The memory 22 is configured to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the Flash upgrading method disclosed in any of the foregoing embodiments.

In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.

In addition, the storage 22 is used as a carrier for resource storage, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon may include an operating system 221, a computer program 222, data 223, etc., and the storage may be a transient storage or a permanent storage.

The operating system 221 is configured to manage and control each hardware device and the computer program 222 on the electronic device 20, so as to implement the operation and processing of the mass data 223 in the memory 22 by the processor 21, and may be Windows Server, Netware, Unix, Linux, or the like. The computer programs 222 may further include computer programs that can be used to perform other specific tasks in addition to the computer programs that can be used to perform the Flash upgrade method performed by the electronic device 20 disclosed in any of the embodiments described above. Data 223 may include instructional information collected by electronic device 20.

Further, an embodiment of the present application further discloses a storage medium, in which a computer program is stored, and when the computer program is loaded and executed by a processor, the steps of the Flash upgrading method disclosed in any of the foregoing embodiments are implemented.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The Flash upgrading method, device, equipment and storage medium provided by the invention are described in detail, a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A Flash upgrading method is characterized by comprising the following steps:

2. The Flash upgrading method according to claim 1, wherein after judging whether the read identification information is identification information in a preset identification list, the method further comprises:

3. The Flash upgrading method according to claim 1, wherein after judging whether the read identification information is identification information in a preset identification list, the method further comprises:

if so, initializing the off-chip Flash and erasing the upgrade mirror area;

4. The Flash upgrade method according to claim 1, wherein after the SPI controller of the FPGA chip writes the FPGA image to be upgraded into an upgrade image area of the off-chip Flash, the method further comprises:

if so, reading the written FPGA mirror image to be upgraded from the off-chip Flash by using the FPGA chip, verifying the read FPGA mirror image to be upgraded, judging that the upgrading is successful if the verification is passed, switching the FPGA chip to an idle state, and switching the FPGA chip to the idle state if the verification is not passed.

5. The Flash upgrading method according to claim 4, wherein the reading the written FPGA mirror image to be upgraded from the off-chip Flash by using the FPGA chip and checking the read FPGA mirror image to be upgraded comprise:

6. The Flash upgrading method according to claim 5, after reading and checking the FPGA mirror image to be upgraded written in the upgrade mirror image area, further comprising:

7. The Flash upgrading method according to any one of claims 1 to 6, wherein after judging whether the read identification information is identification information in a preset identification list, the method further includes:

8. A Flash upgrade apparatus, comprising:

9. An electronic device, wherein the electronic device comprises a processor and a memory; wherein the memory is for storing a computer program that is loaded and executed by the processor to implement the Flash upgrade method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium storing computer-executable instructions that, when loaded and executed by a processor, implement the Flash upgrade method of any one of claims 1 to 7.