CN114697171A - Apparatus, and associated method, for a receiver using multiple modulation schemes - Google Patents

Abstract

An apparatus includes a Radio Frequency (RF) receiver to receive an RF signal. The RF receiver includes a plurality of Modulated Signal Detectors (MSDs) to generate a plurality of detected signals upon detection of a plurality of RF signals modulated using a plurality of modulation schemes. The RF receiver further includes a controller to cause reception of the plurality of RF signals in response to the plurality of detection signals.

Description

Apparatus, and associated method, for a receiver using multiple modulation schemes

Cross Reference to Related Applications

The present application is a partial continuation of the application (CIP) attorney docket number sil 423, U.S. patent application serial No. 16/886,645 entitled "Apparatus for receivers with Concurrent Detection and Associated Methods" filed on 28.5.2020, which is a CIP attorney docket number sil 416, filed on 30.10.2019, entitled "Apparatus for Radio-Frequency Receiver with Reduced Power Consumption and delay and Associated Methods" CIP application serial No. 16/668,834. The above application is incorporated by reference herein in its entirety for all purposes.

Technical Field

The present disclosure relates generally to communication devices and related methods. More particularly, the present disclosure relates to apparatus for Radio Frequency (RF), such as RF receivers using multiple modulation schemes, and associated methods.

Background

As technology advances, more and more circuit elements are integrated into devices such as Integrated Circuits (ICs). In addition, more and more devices (such as ICs or subsystems) have been integrated into products. This trend is expected to continue with the development of internet of things (IoT), for example.

The ever increasing number of circuit elements, devices, subsystems, etc., also results in a corresponding increase in the amount of power consumed by products containing such components. In certain applications, such as battery-powered, mobile or portable products, the amount of power or energy available is limited. Given the relatively small amount of power or energy available in such applications, reducing the power consumption of a component or product may provide advantages or benefits, such as, for example, extending battery life, increasing the "uptime" or active time of the system, and the like.

Even in a non-portable environment, increased power consumption always results in more heat being generated, since electrical energy is not used 100% efficiently. Thus, reduced power consumption of a component or product provides advantages or benefits, such as reduced heat, reduced power costs, and the like.

The description in this section and any one or more of the corresponding figures are included as background information material. The materials in this section should not be construed as an admission that such materials constitute prior art with respect to the present patent application.

Disclosure of Invention

According to exemplary embodiments, a variety of devices and associated methods for RF devices are contemplated. According to one exemplary embodiment, an apparatus comprises an apparatus comprising an RF receiver for receiving an RF signal. The RF receiver includes a plurality of Modulated Signal Detectors (MSDs) to generate a plurality of detected signals upon detection of a plurality of RF signals modulated using a plurality of modulation schemes. The RF receiver further includes a controller to cause reception of the plurality of RF signals in response to the plurality of detection signals.

According to another exemplary embodiment, an apparatus for communicating using RF signals includes a transmitter to transmit a modulated RF signal. The transmitted information is modulated onto the modulated RF signal using one of a variety of modulation schemes. The apparatus further includes a receiver for receiving packets from the received modulated RF signal. The receiver includes a multiple Modulation Scheme Detector (MSD) to generate a plurality of detected signals. The packet is received by configuring a receiver based on a detection signal of the plurality of detection signals. A detection signal is obtained from the packet.

According to another exemplary embodiment, a method of operating an RF receiver includes generating a plurality of detection signals by using a plurality of Modulation Signal Detectors (MSDs) when a plurality of RF signals modulated using a plurality of modulation schemes are detected. The method further includes causing reception of a plurality of RF signals in response to the plurality of detection signals.

Drawings

The drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the application or claimed subject matter. Those of ordinary skill in the art will appreciate that the disclosed concepts apply to other equally effective embodiments. In the drawings, the same numerical designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.

Fig. 1 shows a circuit arrangement for an RF receiver according to an exemplary embodiment.

Fig. 2 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 3 shows a frequency response diagram in an RF receiver according to an exemplary embodiment.

Fig. 4 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 5 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 6 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 7 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 8 shows a frequency response diagram in an RF receiver according to an exemplary embodiment.

Fig. 9 shows a circuit arrangement of a digital modem for an RF receiver according to an exemplary embodiment.

Fig. 10 shows scanning in a conventional receiver.

Fig. 11 shows a circuit arrangement for an RF receiver according to an exemplary embodiment.

Fig. 12 illustrates concurrent scanning in an RF receiver according to an exemplary embodiment.

Fig. 13 shows a worst case preamble arrival in an RF receiver according to an exemplary embodiment.

Fig. 14 shows a flow chart of coincidence detection in an RF receiver according to an example embodiment.

Fig. 15 illustrates channel filter bandwidth selection in an RF receiver according to an example embodiment.

Fig. 16 shows a circuit arrangement for an RF receiver according to an exemplary embodiment.

Fig. 17 shows a circuit arrangement for an RF receiver according to an exemplary embodiment.

Fig. 18 illustrates a network stack utilizing a shared Medium Access Control (MAC) in accordance with an example embodiment.

Fig. 19 shows a circuit arrangement of a network node according to an exemplary embodiment.

Fig. 20 shows a controller for an RF receiver according to an example embodiment.

Fig. 21 shows a control flow diagram of an RF receiver according to an exemplary embodiment.

Fig. 22 shows a control state diagram of an RF receiver according to an exemplary embodiment.

Fig. 23 shows a controller for an RF transmitter according to an exemplary embodiment.

Fig. 24 shows a control flow diagram of an RF transmitter according to an exemplary embodiment.

Fig. 25 shows a control state diagram of an RF transmitter according to an exemplary embodiment.

Fig. 26 illustrates a wireless communication system according to an example embodiment.

Fig. 27 shows a circuit arrangement of an IC including an RF receiver according to an exemplary embodiment.

Fig. 28 shows a circuit arrangement of an IC including an RF receiver and an RF transmitter according to an example embodiment.

Detailed Description

The present disclosure relates generally to communication devices and related methods. More particularly, the present disclosure relates to apparatus for communication devices, and more particularly, to apparatus for communication devices in which an RF receiver uses multiple modulation schemes, a transmitter is adapted to transmit RF signals to such a receiver, and associated methods.

An aspect of the present disclosure relates to an RF device including a receiver utilizing concurrent preamble detection (or concurrent detection), and an associated method. Some applications for short-range wireless communication, such as IoT applications, specify a receiver that can evaluate more than one frequency channel or physical layer (PHY) or PHY mode (e.g., Zigbee and bluetooth). In the context of the description, frequency channels may be overlapping or separated frequency channels or frequency ranges. Examples include asynchronous frequency hopping, network discovery (e.g., passive scanning in ieee 802.15.4), scanning Automatic Frequency Control (AFC), and Received Signal Strength Indication (RSSI) or energy detection scanning. For simplicity, the description refers to one or more frequency channels (multi-channel), but one of ordinary skill in the art will appreciate that the disclosed techniques and apparatus are applicable to multiple PHYs or PHY modes.

Such applications, such as transmission in the IoT application described above, may occur on more than one carrier frequency. Further, more than one modulation scheme or PHY mode may be used. In such applications, a System On Chip (SOC) that includes a radio (RX, TX, or both) typically has a packet handler and a protocol timer (implemented in hardware, software, firmware, or a combination thereof). In these cases, the RF receiver according to various embodiments avoids duplication of various parts or blocks of the RF receiver, such as packet handlers and protocol timers.

An RF receiver according to various embodiments avoids duplication of multiple digital processing functions when receiving multiple signals having different corresponding RF frequencies. Digital processing typically requires processing of several layers of the protocol stack (including PHY, Media Access Control (MAC), network layers). Typically, digital processing uses a variety of resources, such as hardware, memory, and software. The RF receiver avoids duplication of multiple digital processing functions by searching for features associated with multiple signals with multiple signal detectors and selecting a subset of the multiple signals for digital processing or concurrent digital processing. The features may be included in a preamble or sync word or PHY header or MAC header or a combination thereof. In some embodiments, the selection is based on a first successful detection (first come first serve) of the plurality of signal detectors, and subsequent detections are ignored when a subset of the plurality of signals are undergoing digital processing.

As described below, the signal detector may include various types of circuitry and detection techniques. The signal detector provides a signal quality metric (a metric that may indicate the likelihood that the received signal is a desired signal, e.g., has a frequency deviation within the limits of predetermined maximum and minimum deviation thresholds, and/or a correlation with a desired symbol sequence (preamble and/or sync word), and/or has a frequency error less than a predetermined frequency deviation threshold, and/or a signal-to-noise ratio (SNR) greater than a predetermined SNR threshold, etc.) for a baseband signal received from a frequency converter circuit that generates a frequency shifted frequency channel (e.g., by mixing) to produce the baseband signal. In an exemplary embodiment, the signal detector may constitute any one of a preamble detector, a sync word detector, an RSSI detector (i.e., providing an RSSI measurement for a received or provided signal), a signal arrival detector (e.g., as described in U.S. patent application No. 14/080,405 filed 11/14/2013, now U.S. patent No. 10,061,740), a cost function detector (e.g., as described in U.S. patent application No. 16/177,373 filed 10/31/2018), a correlator (e.g., as described in U.S. patent application No. 15/370,693 filed 6/2016, now U.S. patent No. US10,389,482), an amplitude detector, a phase detector, a differential phase detector, a phase click detector, a skew detector, or any combination of the foregoing. In general, any circuit or block that detects the presence of a desired or transmitted signal, such as an RF signal, in a frequency channel may be used. Further, it is noted that in an exemplary embodiment, a frequency scan for undesired signals may be performed, e.g., an RSSI scan may be performed to determine a "clean" channel. Once a "clean" channel is found, it can be used for transmission.

Some conventional approaches have been used in applications such as IoT applications. One approach is to evaluate one frequency at a time. This technique may be a relatively slow process because the receiver may repeat the evaluation multiple times. Furthermore, this solution requires the frequency synthesizer to jump from one frequency to the next, which increases the settling time for completing the evaluation. Longer evaluation times mean more energy consumption. A second approach is to implement multiple Intermediate Frequency (IF) paths, where each IF is followed by a corresponding demodulator. This approach has a relatively high power consumption for all demodulators. Furthermore, multiple demodulators can be costly in terms of die area, circuit complexity, and the like. Furthermore, demodulating multiple parallel channels requires running multiple frame controllers in parallel, which increases power consumption and cost, making this approach impractical for low-power, low-cost IoT applications.

An RF receiver according to various embodiments solves the above-mentioned problems. Other use cases also exist. For example, Z-Wave defines a single frequency at which the radio can receive frames while it scans other Z-Wave channels. According to various embodiments, a device that supports simultaneous signal detection will allow frames to be received without the additional delay and power consumption associated with receivers that evaluate one frequency at a time. In turn, this property allows the transmitting device to use very short preambles and payloads, thereby reducing the energy per Transmit (TX) frame. This approach would enable the use of an energy harvesting source that powers the transmitter.

Another example is asynchronous channel hopping, e.g. as inhttps://www.silabs.com/community/ wireless/proprietary/knowledge-base.entry.html/2019/06/20/channel scanning- 8x31As described in (1). The scheme provides that a node should be able to scan multiple channels for signals with limited preamble length. The specification leaves relatively few preamble symbols per channel to detect the preamble, which limits the time to reliably detect the signal. By receiving multiple channels simultaneously, an RF receiver according to various embodiments enables each channel to be receivedMore time is available. This time can be used to improve signal quality detection performance (e.g., reduce false positive detection), or to save power by going to sleep and becoming idle (e.g., in preamble detection mode). Another example is Bluetooth Low Energy (BLE). BLE specifies a relatively fast channel scan, for example during a search for advertisement packets. An RF receiver according to various embodiments may accommodate BLE fast channel scanning.

In an exemplary embodiment, the RF receiver is capable of detecting signals in multiple channels simultaneously without the overhead of multiple parallel demodulators. The RF receiver accomplishes this by using a relatively simple low power signal detector (one for each IF path) and at least one demodulator. In most IoT use cases, one demodulator is sufficient. The signal detector may have much lower complexity and lower power than conventional multi-demodulator solutions, thereby saving power and reducing complexity and/or cost. In an exemplary embodiment, a multi-channel RF receiver is used to receive at least one received signal of a plurality of channels. It does so by applying a frequency shift to the frequency channel using front end circuitry in the RF receiving circuitry to produce a plurality of filtered baseband signals. The signal detector is used to simultaneously measure the signal quality of each filtered baseband signal. The controller selects (at least) one filtered baseband signal for demodulation by the (at least one) demodulator.

RF receivers according to various embodiments take advantage of low duty cycle activity found in some applications, such as in IoT sensor networks. For example, a door sensor, light switch, motion sensor, or glass break detector may not be triggered 10 times per day. In other words, the RF receiver has a low duty cycle operation (e.g., at least partially, most of the time idle or sleep). In these low duty cycle use cases, it is more efficient to operate multiple signal detectors than to operate multiple demodulators. In most cases, one demodulator will suffice, which can reduce costs. For example, die area on a chip or IC may be reduced or saved. There may be no signal detector that detects a valid signal in any of the filtered baseband signals. In this case, one or more demodulators may remain in an inactive low power state. When the signal detector triggers at some later time, then the controller may wake up the demodulator and provide the associated filtered baseband signal to the demodulator for demodulation. For example, IF signal detector 1 triggers, the controller may provide filtered baseband signal 1 (provided by IF circuit 1) to the demodulator for demodulation.

Where multiple PHYs or multiple PHY modes are used, an RF receiver according to various embodiments may use multiple signal detectors (one for each PHY or PHY mode desired) on each filtered baseband signal over multiple frequency channels. If one signal detector triggers, the controller may select a demodulator suitable for demodulating the detected PHY (or PHY mode) and provide the associated filtered baseband signal to the demodulator. In other embodiments, rather than selecting a demodulator, a configurable demodulator may be configured to demodulate a detected PHY or PHY mode. If a certain channel is dedicated to a single PHY or PHY mode (e.g., known a priori, per debug), a single signal detector may be used for the associated filtered baseband signal. In other exemplary embodiments, when multiple signal detectors trigger, the controller may use the soft detection outputs of the signal detectors to select the filtered baseband signal based on maximum likelihood or maximum correlation. In other exemplary embodiments, the RF receiver applies a frequency shift to the multiple frequency channels using an analog down-converter (e.g., Low Noise Amplifier (LNA), in-phase-quadrature (IQ) mixer, Programmable Gain Amplifier (PGA)) for producing a combined analog IF signal.

An IF analog-to-digital converter (IF-ADC) converts the combined analog IF signal to produce a combined digital IF signal. The plurality of digital down converters apply a set of frequency shifts to the combined digital IF signal to produce a plurality of baseband signals. The plurality of channel filters may filter the plurality of baseband signals to produce a plurality of filtered basebands. Note that a single ADC and front-end circuitry (RF mixer, etc.) is used in conjunction with multiple IF path circuits or branches, thereby reducing complexity, cost, and power consumption or power consumption.

To allow for increased flexibility, a true IF-ADC (rather than a complex) is used in some embodiments. A true IF-ADC will deliver both positive and negative frequencies and thus can receive separate channels above and below the Local Oscillator (LO) frequency. The final frequency location of each individual channel is determined by its associated complex mixer and complex if filter stage. In this case, the IF-ADC bandwidth should accommodate the highest of the various IF paths (| IFx | +0.5BWx), as described below in connection with fig. 3, where | IFx | is equal to the absolute value of the RF receive frequency minus the LO frequency, and BWx is the appropriate or desired bandwidth for receiving the desired or transmitted signal (see fig. 3). In various embodiments, the RF receiver uses multiple digital mixer stages, where each digital mixer is driven by a combined digital IF signal and a Numerically Controlled Oscillator (NCO), each having its unique NCO frequency. The NCO frequency is equal to the IF frequency of the IF path or stage (IFx). Each digital mixer is followed by a filter stage. The filter stage may include a decimator, a Finite Impulse Response (FIR) filter, an Infinite Impulse Response (IIR) filter, a Direct Current (DC) filter, and so on, as will be understood by those of ordinary skill in the art.

In various embodiments, circuitry or hardware of the RF receiver may be saved or reduced by sharing functionality. For example, the second channel filter may share a multiplier with the first channel filter. As another example, a look-up table (LUT) for sine/cosine generation in an NCO may be shared among NCO's of a digital mixer. As described below, an RF receiver according to various embodiments includes an image reject calibration (IR-cal) circuit. The IR-cal stage may be shared or separate IR-cal circuits may be used. Due to frequency dependence in IQ errors, mismatches in actual implementation of various circuits or blocks, such as mixers, PGAs, etc., and/or self-mixing in mixer circuits, separate IR calibration stages or circuits may provide better image rejection, as will be understood by those of ordinary skill in the art. In contrast, as described above, sharing the IR-cal circuit allows saving hardware, cost, and the like. In an exemplary embodiment, the signal detector used in the RF receiver is a relatively simple signal detector. Examples include correlators, cost function detectors, Digital Signal Arrival (DSA) detectors, RSSI detectors, amplitude detectors, phase detectors, differential phase detectors, etc., as will be understood by those of ordinary skill in the art.

Fig. 1 shows a circuit arrangement for an RF receiver 5 according to an exemplary embodiment. The RF receiver 5 is coupled to an antenna 10 and receives RF signals through the antenna 10. The received RF signal is fed to the LNA 15, and the LNA 15 amplifies the received RF signal and provides the amplified RF signal to the mixer 20 (labeled "RFMIX"). Mixer 20 mixes the amplified RF signal with an LO signal provided by LO 25 to produce a mixed or downconverted signal. The mixed signal is provided to the PGA 30. The PGA 30 amplifies the mixed signal using a programmable gain to generate an amplified mixed signal.

The ADC 35 receives the amplified mixed signal, i.e., an analog signal, and converts it to a digital mixed signal. The ADC 35 provides the digital mixed signal to a digital MODEM (DIG _ MODEM)40, which the digital MODEM 40 may filter, decode, demodulate, etc. to extract and provide data at its output. Note that the digital modem 40 may perform various functions, such as channel filtering, signal detection, and modulation, as described below. Further note that although in some embodiments the transmit (modulation) function may be omitted, a short-word digital modem is still used for simplicity. In the exemplary embodiment, the front-end circuits, e.g., LNA 15, mixer 20, LO 25, PGA 30, and ADC 35, are shared by various IF branches or circuits in digital modem 40, as described above. The following description describes various digital modems 40 in accordance with an exemplary embodiment. Note that while the figures and accompanying description show two IF paths or circuits for simplicity and clarity, in various embodiments, more than two IF paths or circuits may be used, as will be understood by those of ordinary skill in the art.

Fig. 2 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The output signal of ADC 35 (see fig. 1) is provided to a decimator 55 (labeled "DEC 0"), decimator 55 decimates the signal and provides the decimated signal at its output. The output signal of the decimator 55 is fed to an input of a DC compensation circuit 60 (labeled "DC-comp"), the DC compensation circuit 60 removing or attenuating or compensating for any DC component present in the decimated signal. The output of the DC compensation circuit 60 drives two IF path circuits, as described below. In the first IF path circuit, the output of DC compensation circuit 60 drives the input of IR calibration circuit 65 (labeled "IR-cal _ a"), IR calibration circuit 65 performs IR calibration, as will be understood by those of ordinary skill in the art. The output of IR calibration circuit 65 drives an input of a digital mixer 75, which digital mixer 75 mixes the signal with the output signal of NCO 70 (labeled "NCO a") to generate a mixed digital signal at the output of digital mixer 75. A decimator 80 (labeled "DEC 1 a") receives and decimates the digital mixed signal and provides the resulting decimated signal to a channel filter 85 (labeled "CHFa"). The channel filter 85 filters (e.g., low-pass filters) the decimated signal and provides the resulting filtered signal to the DSA 90.

DSA 90 serves as a signal detector. Thus, the DSA 90 detects (or looks for or checks or waits for) the arrival of the desired or designated signal. If so detected, the DSA 90 provides a signal to the controller 105 to indicate signal arrival. In response, the controller 105 provides a selection signal to the Multiplexer (MUX)95 to cause the MUX 95 to provide the output of the channel filter 85 to the Digital Signal Processor (DSP)100, or generally to one or more demodulators. Thus, in various embodiments, reference to DSP 100 includes the use of one or more demodulators. The controller 105 also programs or configures or sets the DSP 100 for the detected signal type, PHY mode, etc. In response, the DSP 100 extracts data from packets in the output signal of the channel filter 85, which triggers the DSA 90 and provides the data at the output.

The second IF path circuit is similar to the first IF path circuit and operates in a similar manner. In contrast to "a" for the first IF path circuit, the individual blocks in the second IF path circuit use the symbol "b" in their label, e.g., "IR-cal _ b" instead of "IR-cal _ a" for the first IF path circuit. Thus, the second IF path circuitry includes IR calibration circuitry 135 (labeled "IR-cal _ b"), NCO 130 (labeled "NCO b"), decimator 120 (labeled "DEC 1 b"), channel filter 115 (labeled "CHFa"), and DSA 110 (labeled "DSAb"). IF the DSA 110 detects the arrival of the desired signal through the second IF path circuitry, i.e., in the output signal of the channel filter 115, it provides an indication of the signal arrival to the controller 105. In response, the controller 105 provides a select signal to the MUX 95 to cause the MUX 95 to provide the output of the channel filter 110 to the DSP 100.

The controller 105 also programs or configures or sets the DSP 100 for the detected signal type, PHY mode, etc. In response, the DSP 100 extracts data from packets in the output signal of the channel filter 115, which triggers the DSA 110 and provides the data at the output. Thus, the RF receiver is able to detect multiple PHYs or PHY modes or signals in multiple frequency channels simultaneously. Note that the NCO of the first and second IF path circuits have output frequencies corresponding to the two channels on which the respective IF path circuits operate. In an exemplary embodiment, controller 105 may set, program, or configure the output frequencies of NCO 70 and NCO 130. It is further noted that, as noted above, in some embodiments, more than two IF path circuits may be used, depending on the number of channels one wishes to scan simultaneously. Further, note that in some embodiments, DSA 90 and DSA 110 may be programmed to receive the same PHY or PHY mode, but at different frequencies as needed.

Fig. 3 shows a frequency response diagram in an RF receiver according to an example embodiment. More specifically, the figure shows the frequency response 150 of the decimator 55, the frequency channel 155 (formed by the frequency responses of the digital mixer 75, the decimator 80, and the channel filter 85) (labeled "BWa"). Channel 155 is on frequency (F)_LO-F_Ncoa) Is central, in which FLO and F_NcoaRepresenting the output frequencies of LO 25 and NCO 70, respectively. Similarly, fig. 3 shows a channel 160 (formed by the frequency response of the digital mixer 125, the decimator 120, and the channel filter 115) (labeled "BWb"). Channel 160 is at frequency (F)_LO+F_NCOb) Is a center, wherein F_LOAnd F_NCO0Representing the output frequencies of LO 25 and NCO 130, respectively. Note that this figure also shows twoThe IF frequency of the IF path circuit. They are respectively represented as IF_aAnd IF_b。

Fig. 4 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 4 is similar to that in fig. 2, except that the output of channel filter 85 drives the inputs of random access memory 180 (labeled "RAM a") and correlator 185 (labeled "COR a") and the output of channel filter 115 drives the inputs of RAM 195 (labeled "RAM b") and correlator 190 (labeled "COR b"). RAM 1 and RAM 2 represent memories that DSP 100 may use to perform its functions (e.g., demodulation), e.g., as scratchpad memories, etc.

The samples (IQ or phase or amplitude or combination) are stored in a circular buffer formed by RAM 180 and RAM 195. In this circuit, the RF receiver and correlator 190 can detect the correlation peak while processing the sync word of sync word a. DSP 100 may then "rewind" the data to the sync word using RAM 195 and apply Forward Error Correction (FEC) decoding followed by sync word demodulation (e.g., as in the PHY or PHY mode of BLE encoding). Note that a combination of the detector circuits shown in fig. 2 and 4 may be used. Thus, in some embodiments, one or more IF paths use one or more DSAs, while one or more IF paths use a combination of one or more RAMs and one or more correlators. Furthermore, in some embodiments, rather than using RAM 180 and RAM 195, a single RAM with dual ports may be used, in which case one port receives the output of channel filter 85 and the other port receives the output of channel filter 115.

Fig. 5 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 5 is similar to that in fig. 4, except that the output of channel filter 85 does not drive RAM 180 and correlator 185 but instead drives the input of IF processor circuit 205 (labeled "IF processor _ a"). The output of IF processor 205 drives the inputs of RAM 180 and correlator 185. Similarly, the output of channel filter 115 does not drive RAM 190 and correlator 190, but instead drives the input of IF processor circuit 210 (labeled "IF processor _ b"). The output of IF processor 210 drives the inputs of RAM 195 and correlator 190.

In an exemplary embodiment, IF processors 205 and 210 may each be a coordinate rotation digital computer (CORDIC) or any other cartesian to polar converter circuit. Each of IF processors 205 and 210 may also be constructed using a CORDIC followed by a phase differentiator, where the differentiation may be oversampled (multiple differentiations per symbol) or one differentiation per symbol may be used. IF processors 205 and 210 may also provide amplitude or log amplitude for Amplitude Shift Keying (ASK) or on-off keying (OOK) applications. In addition, IF processors 205 and 210 may be extended with slicers to slice the original amplitude, phase or differential phase to 1 or 0 values. Furthermore, a combination of the detector circuits shown in fig. 2 and 4 may be used. Thus, in some embodiments, one or more IF paths may use an IF processor, while one or more IF paths may use any of the signal detectors described above (e.g., DSA).

Fig. 6 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 6 is similar to that in fig. 2, except that the output of channel filter 85 drives the input of RSSI circuit 220 (labeled "RSSI a") and the output of channel filter 115 drives the input of RSSI circuit 225 (labeled "RSSI b"). The RSSI circuit in each IP path circuit extracts the signal level (RSSI, amplitude, Energy Detection (ED) or RMS level) from the respective channel filter output. By using multiple IF path circuits, the signal levels on multiple channels can be evaluated simultaneously, thereby speeding up the RSSI scan. The signal levels are transmitted to the controller 105 for processing. The controller 105 then controls the MUX 95 as described above in connection with fig. 2. In some embodiments, the controller 105 may include a memory that stores signal levels. Applications of the embodiment in fig. 6 include: frequency agile (link) signal level scanning, listen-before-talk, and fast spectrum analyzer.

Fig. 7 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 7 is similar to the embodiment shown in fig. 2, except that in the embodiment of fig. 7, the controller 105 drives the RF synthesizer. IF the number of frequencies that should or are desired to be swept is greater than the number of IF path circuits in the RF receiver, the RF synthesizer may alter the output frequency. For example, IF an RF receiver has two IF path circuits and requires 20 channels to perform RSSI evaluation, the RF synthesizer should be tuned on 10 frequencies. For example, fig. 8 shows 6 channels evaluated using three RF synthesizer (LO) frequencies. Note that the receiver in fig. 7 may also use any other detection architecture, such as those described above (e.g., DSA, IF processor, etc.). In embodiments where two DSAs or correlators are used and no signal is detected for a certain time window, the controller will change the LO frequency to the next frequency value to be evaluated again. Alternatively, the controller may change the frequency of the NCO. In such embodiments, scanning may be suspended once any DSA or correlator triggers, i.e., a signal is detected.

The first DSA or correlator triggered causes the controller 105 to select the MUX 95 to pass the associated channel filter output to the DSP 100 and configure the DSP 100 according to the detected signal, PHY or PHY mode, as described above. The DSP 100 extracts data from the DSA triggered packet. In the case where DSA or correlators trigger simultaneously, the highest correlation result may be used to select the channel from which DSP 100 extracts data. Alternatively, a priority scheme may be used so that when correlators or DSAs trigger simultaneously, a particular PHY will get priority to be demodulated first. In addition, DSA or TRECS (timing recovery system) can also extract residual frequency offset by adjusting LO or NCO frequency to improve alignment. Once the modulation is aligned in one of the channel filters, the bandwidth of that channel filter may be reduced to increase sensitivity, reduce noise, and increase channel selectivity. Those skilled in the art will appreciate that adding more IF path circuitry (while receiving channels) speeds up the scanning AFC system.

Fig. 8 shows a frequency response diagram in an RF receiver according to an exemplary embodiment using two IF path circuits. The LO may be driven from F when no valid signal is received_LO2To F_LO3To F_LO1To F_LO2And so on. When in channel F_LO3+F_NCO2The LO sweep will be at F when a valid signal is received_LO3Is stopped and DSP 100 will enable demodulation of the signal in the second IF path circuit. As described above, by using more IF path circuits, the scan time can be further reduced.

Fig. 9 shows a circuit arrangement of a digital modem 40 for an RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 9 is similar to the circuit arrangement in fig. 5, which uses IF processors 205 and 210, as described above, in fig. 5. In contrast to the embodiment in fig. 5, in the embodiment in fig. 9, the output of channel filter 85 drives the inputs of RAM 270 (labeled "RAM a") and TRCS 265 (labeled "TRECS a"). Similarly, the output of channel filter 115 drives the inputs of RAM 275 (labeled "RAM b") and TRECS 280 (labeled "TRECS b"). Each of TRECS 265 and 280 finds timing (on the preamble, sync word, or a combination of both). When timing is found in the IF path circuit, the corresponding TRECS also has an estimate of the frequency offset. The frequency offset estimate may be provided to a corresponding NCO in the IF path circuitry to align the modulated spectrum at the center of the channel filter bandwidth. The output of TRECS 265 forms an AFC loop in the first IF path circuit by providing a frequency offset signal to NCO 70. Similarly, the output of TRECS 280 forms an AFC loop in the second IF path circuit by providing a frequency offset signal to NCO 130. As described above, the frequency offset signal is used to trim or adjust or program or set or configure the respective frequencies of NCO 70 and NCO 130 to align the modulated signal at the center of the channel filter bandwidth.

Another aspect of the present disclosure relates to concurrent signal detection in an RF receiver by using multiple signal detectors. In general, an RF receiver according to various embodiments provides concurrent detection of patterns (or detection of patterns in a signal). The pattern may include a preamble, a sync word, or both. Thus, in various embodiments, concurrent mode detection constitutes concurrent preamble detection, concurrent sync word detection, and/or concurrent preamble and sync word detection. Without loss of generality, the following description may refer to preamble detection, sync word detection, or both. In other words, as noted, the pattern typically includes one or more preambles, one or more synchronization words, and/or both. Thus, as will be understood by those of ordinary skill in the art, reference in the description to preamble detection or a preamble detector may be generalized or generally applied to one or more modes or mode detections. Similarly, as will be understood by those of ordinary skill in the art, references in the description to sync word detection or sync words may be generalized or generally applied to one or more patterns or pattern detections.

Fig. 10 shows scanning in a conventional receiver. Scanning corresponds to Z-wave, which may have 3 PHY types: r1, R2 and R3 (e.g., in the Federal Communications Commission (FCC) region). R1 and R2 transmit at a frequency of about 908.4MHz, while R3 transmits at a different frequency, 916 MHz. Z-wave Specification (currently inhttps://www.itu.int/rec/T-REC- G.9959-201501-IAvailable) specifies three PHYs in clause 7.1.2.2: r1, R2 and R3. In channel configuration 2, all three PHYs may be used. The preambles of these PHYs are specified in clause 7.1.3.2, which states: the "preamble length should conform to tables 7-10. These values allow the receiver to scan all channels for the duration of the preamble and acquire synchronization on any channel. "when using channel configuration 2, the specification means sequential scanning of all three PHYs. The receiver faces the challenge of finding the preamble within the available preamble length for all three PHY possibilities.

The receiver may not have prior knowledge of which PHY type to transmit (to which PHY type the transmitted signal corresponds). Therefore, the receiver must scan three PHY types so that it can perform preamble detection during a single preamble transmission. The preamble length is just long enough to support this scheme while maintaining acceptable battery life. In fig. 10, the receiver performs a sequential loop scan loop, as shown. The preamble detection windows are approximately the same in terms of symbols to have balanced performance. As will be appreciated by one of ordinary skill in the art, a longer detection window will reduce false detections and improve detection sensitivity. In the receiver scan timing diagram shown in fig. 10, the scan period is proportional to the data rate (R1-9.6 kbps, R2-40 kbps, and R3-100 kbps), and is sequentially performed as described above.

In Z-wave, the specification requires preamble detection during the transmitted preamble duration. Therefore, the preamble is longer than a specific length to support the specification. The scan period typically constitutes a period in which the receiver is turned on (powered on) to detect a particular period. Typically, the scan period is the sum of an Automatic Gain Control (AGC) settling time, a group delay from the antenna to the preamble detector, a receiver settling time (e.g., AFC loop settling time), an asynchronous delay (the phase of the incoming preamble may be inverted to a correlator in the preamble detector), and a detection window (the evaluation time for the signal detector or the preamble detector to detect the PHY sequence). As understood by those of ordinary skill in the art, a relatively long detection window is desirable, however, the Scanning Period (SP) is limited by the preamble length. As described above, a Z-wave receiver operating according to the Z-wave specification scans multiple PHYs (scans received signals corresponding to the multiple PHYs), such as R1, R2, and R3. In terms of time, the preamble of the R2 PHY is the shortest. As mentioned above, conventional solutions configure the receiver to scan the preamble sequentially. The preambles of all PHYs are quite long, so sequential scanning receivers never lose packets. However, Z-wave provides for the introduction of an additional PHY for telecommunications. Scanning four PHYs can be problematic because the preamble length of a conventional PHY cannot be changed. Sequential scanning means speeding up the scanning period, which means that the length of the preamble correlator must be reduced. However, doing so results in a higher packet error rate, sensitivity loss, and reduced robustness to interference.

The RF receiver according to various embodiments supports concurrent signal detection, i.e., concurrent preamble detection, by using a plurality of signal detectors (e.g., preamble detectors). A typical application of such a receiver is a communication system using multiple PHYs, where the receiver does not have a priori knowledge of which PHY is transmitting. As mentioned above, Z-wave specifies this scheme. In an RF receiver according to various embodiments, in order to increase the communication range, an additional PHY is required to support remote applications (e.g., in a region or country complying with FCC regulations). Scanning four possible PHYs (signals transmitted by the corresponding PHY) is more challenging than scanning three PHYs. The RF receiver according to various embodiments utilizes the fact that R1 and R2 PHYs share the same channel to concurrently scan R1 and R2 PHYs (scan received RF signals corresponding to two respective PHYs). An RF receiver according to various embodiments features increased receive sensitivity, reduced packet error rate, and increased robustness to interference.

Although the following discussion refers to the use of receivers according to various embodiments in systems using Z-wave, the use of receivers according to various embodiments is contemplated and possible in systems having specifications other than Z-wave, with appropriate modifications, as will be appreciated by those of ordinary skill in the art. Accordingly, references to Z-wave, corresponding description, and receiver architecture and circuit arrangement are exemplary only, and not limiting. In various embodiments, a concurrent scanning RF receiver architecture or a partially concurrent and partially sequential scanning RF receiver architecture is used. In order to reduce the power consumption and cost of the receiver, the channel filter and all circuits in front of the channel filter (i.e. between the antenna interface and the channel filter, such as LNA, RF mixer, frequency synthesizer, PGA, ADC, AGC loop, decimator and digital mixer), are commonly referred to as front-end circuits, as will be described below. It should be noted that the embodiments depicted and described in the drawings are merely illustrative and exemplary, as will be understood by those of ordinary skill in the art. Other embodiments are contemplated and possible, as will be appreciated by one of ordinary skill in the art. For example, in some embodiments, the channel filters, digital mixers, and/or decimators may not be shared as desired.

In some embodiments, during concurrent preamble searching, a single channel filter is used for all PHYs that use concurrent preamble searching. In such embodiments, the channel filter bandwidth is configured (or set or programmed) to the bandwidth specification of the PHY with the highest bandwidth specified so that the channel filter can pass signals of all PHYs for concurrent preamble search. In some embodiments, the above scheme is extended and multiple preamble detectors are used to support concurrent preamble searches. Each preamble detector is configured as one of the PHYs for concurrent preamble search so that preamble detection can be linked to the PHY being received (i.e., the PHY to which the received RF signal corresponds). This scheme allows PHY-specific optimization in the receiver.

Examples of receiver optimization are: (1) AFC settings, (2) channel filter bandwidth, (3) sample rate converter ratio, (4) demodulator configuration, (5) decoder settings (e.g., manchester/non-return-to-zero (NRZ), de-interleaving, data de-whitening, and FEC engines), (6) additional preamble detection, and (7) sync word detection configuration. Each of the optimizations is described below, and one or more of the optimizations may be used with the exemplary receiver architecture shown in the figures and described in detail below.

(1) AFC setting: in order to minimize the delay, the frequency error is measured during the preamble search so that when the preamble is detected, the frequency error can be easily obtained. When one of the preamble detectors is looking for a preamble, frequency correction is applied to align the incoming signal close to the channel center frequency. Alignment may be accomplished by changing the RF local oscillator or the oscillator driving the digital mixer. The AFC may use a parameter (AFC limit) to adjust the maximum frequency offset compensation amount to prevent over-tuning due to measurement inaccuracies. Since different PHYs may have different AFC limits, performance may be optimized by adjusting the AFC limit according to the PHY found by the preamble detector (corresponding to the PHY that detected the received RF signal of the preamble).

(2) Channel filter bandwidth: since different PHYs may have different modulation bandwidths and frequency offset ranges, performance may be optimized by adjusting the channel filter bandwidth according to the PHY found by the preamble detector. After AFC is stabilized, a narrower bandwidth can be selected according to the PHY found by the preamble detector, which will improve the reception sensitivity and selectivity. The channel filter bandwidth is typically determined by the filter sampling rate and the channel filter coefficients. In some embodiments, the filter coefficients are changed so that the sampling rate used by subsequent or successive circuits remains unchanged.

(3) Sample rate converter ratio: after detecting the preamble of such a PHY (corresponding to the PHY that detected the received RF signal of the preamble), some PHYs may use the sample rate adjustment for further detection. Further detection may require detection of a preamble, a sync word, payload data, etc. (4) Demodulator configuration: the preamble detector may be a separate block without using a demodulator circuit, as needed. In such embodiments, the demodulator will be enabled or configured according to the PHY discovered by the corresponding preamble detector.

(5) The decoder sets up: to keep the cost low or reduce the cost (minimum or reduced die area), a single decoder may be used. To support such a configuration, the decoder may be adjusted according to the PHY discovered by the preamble detector. For example, decoding may require Manchester/NRZ decoding, de-interleaving, de-whitening, forward error correction, block decoding, and the like. (6) Additional preamble detection: after the preamble is initially detected, additional detection may be employed to improve the reliability of the overall preamble detection as part of the concurrent PHY detection. For example, the preamble detector may be configured according to the PHY discovered by the initial preamble detector. (7) Sync word detection configuration: if two or more PHYs share a sync word detection circuit, the circuit may be configured according to the PHY found by the preamble detector.

As noted above, in various embodiments, the above optimizations can be used individually, i.e., each optimization can be used individually, or multiple optimizations can be used together. Additionally or alternatively, in some embodiments, multi-channel reception may be supported or used. More specifically, by combining concurrent preamble detection with the above-described multi-channel reception technique (as detailed in the above-referenced priority U.S. patent application serial No. 16/668,834), as desired. More specifically, each IF path may have at least one detector to detect the preamble or sync word. If a preamble or sync word is detected, optimization can be performed in the same manner as described above. For example, in the IF path corresponding to detection, an oscillator driving a digital mixer may be tuned to compensate for frequency offset, and the channel filter bandwidth may be reduced to improve sensitivity and selectivity performance. In addition, one or more other IF paths may be shut down (or disabled or powered down) to reduce power consumption. All other optimizations described in this document can also be applied to the multi-channel configuration as needed.

The following description provides RF receiver architectures, flow diagrams, and related figures corresponding to concurrent detection in accordance with various embodiments. The RF receiver may use any of the optimizations described above. Further, the RF receiver may implement and use multi-channel reception using the above-described techniques as desired. As described above, the RF receiver uses some of the blocks or circuits (e.g., LNA 15, mixer 20, PGA 30, ADC 35, decimator 35, etc.) used in the previous figures (e.g., fig. 1-2, 4-7, and 9). The blocks or circuits provide similar functions and features to those described above in connection with fig. 1-9. Accordingly, the description of such blocks or circuits is not repeated below.

Fig. 11 shows a circuit arrangement for an RF receiver 5 according to an exemplary embodiment supporting concurrent detection. The RF receiver 5 includes a front-end circuit 277. In the illustrated embodiment, front-end circuit 277 includes LNA 15 (which receives gain-adjustment signal LNA _ gain from controller 105), mixer 20, RF frequency synthesizer (LO)25, PGA 30 (which receives gain-adjustment signal PGA _ gain from controller 105), ADC 35, decimator 55, DC compensation circuit 60, digital mixer 75, decimator 80, channel filter 85, and NCO 70. To reduce power consumption, cost, and complexity, certain blocks or circuits in the RF receiver 5 are shared among the various PHYs. In the figure, the shared block or circuitry (or hardware (which may include or use firmware or software) is labeled 280. accordingly, note that in addition to front-end circuitry 277, shared circuitry 280 includes frame controller circuitry (FRC) 315. the output of channel filter 85 is provided to demodulator 305 (labeled "Demod _ a, PHYa" and corresponding to a first PHY) and demodulator 310 (labeled "Demod _ b, PHYb" and corresponding to a first PHY). demodulator 305 and demodulator 310 are used for concurrent preamble and/or sync word detection for two respective PHYs.

Several techniques known to those of ordinary skill in the art may be used to detect the preamble and/or the synchronization word. A straightforward method of detecting the preamble and/or sync word may be by demodulating the signal and performing a binary comparison between the predefined sequence and the demodulated output. When a match occurs with no errors or relatively few errors, the sequence may be considered to have been detected. Examples of more complex Detection Methods are described in U.S. patent application No. 15/370,674 entitled "Radio Frequency Apparatus with Digital Signal Arrival Detection and Associated Methods" filed on 6.12.2016 and U.S. patent application No. 16/177,373 entitled "Apparatus with Radio Frequency Receiver with Improved Timing Recovery and Frequency Offset Estimation and Associated Methods" filed on 31.10.2018.

The demodulator 305 supplies the controller 105 with a signal FOEa (frequency offset estimation from Demod _ a corresponding to PHYa) and a PDa (preamble detection signal from Demod _ a). Similarly, demodulator 310 provides signals FOEb (frequency offset estimate from Demod _ b corresponding to PHYb) and PDb (preamble detection signal from Demod _ b) to controller 105. In response to the FOEa and FOEb signals, the controller 105 generates a frequency compensation signal (Freq _ comp) that is used to set the output frequency of the NCO 70 and/or the output frequency of the RF frequency synthesizer 25 depending on which demodulator detects the preamble (i.e., whether the demodulator 305 corresponding to FOEa or the demodulator 310 corresponding to FOEb detects the preamble). Signals PDa and PDb are used to represent preamble detection by demodulator 305 and demodulator 310, respectively.

The demodulator 305 also generates and provides an RSSIa signal to the controller 105 that is representative of the RSSI of the signal processed by the demodulator 305. Similarly, the demodulator 310 generates and provides to the controller 105 an RSSIb signal that represents the RSSI of the signal processed by the demodulator 310. The RSSIa and RSSIb signals are used to set the gain of the LNA 15 and PGA 30, respectively, depending on which demodulator detects the preamble (i.e., whether the demodulator 305 corresponding to RSSIa or the demodulator 310 corresponding to RSSIb detects the preamble). An RSSI (or power level) signal is typically obtained after the channel filter, which indicates the in-band power level. When RSSI exceeds a level that allows reliable detection, i.e., RSSI exceeds a detection level, then gain in front-end circuit 277 may be reduced while the goal is still to provide sufficient RSSI for reliable detection. In other words, the excess signal-to-noise ratio (SNR) at the input of the demodulator is compromised for improved linearity in front-end circuit 277 while maintaining relatively good demodulation performance. This scheme helps to improve receiver intermodulation tolerance. Various PHYs may have different detection levels, which require different AGC thresholds (the gain of front-end circuit 277 may decrease when RSSI crosses the AGC threshold). For example, if the signal PDa indicates that the PHYa is detected, the controller 105 may set the AGC threshold to a value corresponding to the detection level of the PHYa. Another example of RSSI-based gain control is described in U.S. patent No. 10,469,112 entitled "System, apparatus and method for performing automatic gain control in a receiver for packet-based protocols".

The demodulator 305 demodulates the signal corresponding to the PHYa to generate a data signal DATAa. The demodulator 310 demodulates a signal corresponding to PHYb to generate a data signal DATAb. The respective data signals (DATAa and DATAb) are fed to two inputs of the MUX 95. In response to control signal DATAa/DATAb from controller 105, MUX 95 provides either signal DATAa or signal DATAb to FRC 315. The controller 105 provides a bandwidth adjustment signal (CHF _ BW, which may include a plurality of bits) to the channel filter 85. The CHF _ BW signal is used to program the bandwidth of the channel filter 85. Alternatively, the CHF _ BW signal may be used to change the filter characteristic or the shape of the transfer function. For example, if a PHY is detected, the filter may be changed to provide a matched filter response, i.e., matched to the detected PHY, which may be beneficial for receive sensitivity.

As described above, the RF receiver in fig. 11 can concurrently scan R1 and R2. Fig. 12 shows details of the scanning procedure, while fig. 13 shows a worst case R2 preamble arrival for a communication system operating according to the Z-wave protocol. Referring again to fig. 12, concurrent scanning of the R1 and R2 PHYs (scanning the received RF signals corresponding to the respective two PHYs) reduces the scanning period. Concurrent scanning allows for a longer scanning period for the same preamble length, and therefore has less false preamble detections and higher receiver sensitivity. Note that the "R1 + R2 scan period" is specified by the R1 PHY, since the R1 PHY corresponds to a lower data rate. R2 detection may be enabled for the entire R1 Scan Period (SP). The R2 scan should be enabled for at least the "minimum R2 detection window" (labeled "minimum R2 detection window") length of time. However, enabling R2 scanning across the entire R1 SP allows for a longer R2 detection window.

Referring again to fig. 13, the point in time labeled 330 indicates that the R2 preamble arrives somewhat late, and thus the first preamble detection may fail. The point in time marked 332 indicates that the preamble is within R2 SP and can therefore be successfully detected. In addition to the concurrent preamble detection function, the RF receiver according to various embodiments has certain other features and attributes. As one example, FRC315 and various blocks in front-end circuit 277 (i.e., shared circuitry 280) may be shared among multiple PHYs. Furthermore, various optimizations may be performed depending on which preamble detector triggers (i.e., which preamble is detected first).

For example, in some embodiments, PHYa and PHYb may have different channel filter bandwidth specifications. Initially, the bandwidth of the channel filter 85 is set to the widest specified bandwidth capable of receiving two PHYs (receiving RF signals corresponding to the PHYs). Improved sensitivity and interference immunity is obtained by adapting the bandwidth of the channel filter 85 to the specified bandwidth of the PHY that detected the preamble. As another example of an optimization or feature, in some embodiments, different PHYs may have different maximum frequency offsets. Typically, the AFC range has a frequency adjustment limiting parameter. The parameter may be set based on which preamble detector is triggering (i.e., for which of the received RF signals corresponding to the respective PHYs, a preamble is detected). This limitation is used to contain the frequency adjustment within a specified range. Without this limitation, noise on the frequency offset estimate may cause the frequency adjustment to go outside of the effective range. As another example of an optimization or feature, in some embodiments, both RSSIa and RSSIb correspond to the same received signal prior to preamble detection, and thus the values of RSSIa and RSSIb signals will be substantially (or near or nearly) the same. After preamble detection, the bandwidth of the channel filter 85 may be changed and AFC may be adjusted. These events may affect the RSSI signal, so in some embodiments, the RSSI of the associated preamble detection is used for AGC purposes (i.e., alignment of the gains of LNA 15 and PGA 30).

As another example of optimization or features, in some embodiments FRC315 may include a variety of features. Such features may include, as desired: sync word timeout period, sync word detection, PHY header decoding, de-whitening, FEC decoder, address filtering, frame check sum sequence (FCS) check, etc. FRC315 may also handle some or all of the Media Access Control (MAC) functions such as frame control, MAC address filtering, PAN-ID filtering, security processing, processing of information elements, and the like. For an example of such functionality, see the ieee802.15.4-2015 standard for more detail. In various embodiments, FRC315 may be configured (e.g., using one or more control signals (not shown) provided by controller 105) to handle MAC functions. Using the control signal, the controller 105 may cause or control the enabling, disabling, or configuring of the MAC function based on the mode detection signal PDa and/or PDb. For example, in a multi-protocol receiver application, the MAC function may be selected based on the pattern detection signal PDa and/or PDb. As another example, the receiver may search for the Zigbee preamble and/or sync word, and the Bluetooth Low Energy (BLE) preamble/access address concurrently. If a Zigbee signal is detected, the controller 105 may configure the FRC315 to enable Zigbee MAC or Zigbee MAC functions. Conversely, if a BLE signal is detected, the controller 105 may configure the FRC315 to enable the BLE MAC or BLE MAC functionality. To support multi-protocol applications, the settings and state of the supported protocols may be retained in a memory, such as, for example, a non-volatile memory (not shown). Based on the pattern detection results, controller 105 may write the settings and state information from FRC315 to memory using a memory controller. Also, based on the pattern detection results, controller 105 may use the memory controller to read settings and state information back from memory into FRC 315. Examples of such setting and status signals include, but are not limited to: PAN ID, source and destination addresses, PHY capabilities supported, frame control fields, etc. For more settings and status information, see the IEEE802.15.4-2015 standard.

As another example of optimization or features, in some embodiments FRC315 may include a variety of features. Such features may include, as desired: sync word timeout period, sync word detection, PHY header decoding, de-whitening, FEC decoder, frame check sum sequence (FCS) check, etc.

Fig. 14 shows a flowchart 340 for coincidence detection in an RF receiver according to an example embodiment. This process may be implemented, for example, by the controller 105 as described above. Referring again to fig. 14, Demod _ a and Demod _ b are enabled at 343 (e.g., corresponding to demodulator 305 and demodulator 310, respectively). At 346, it is checked whether a preamble is detected. If not, the check for preamble detection continues at 346. However, if a preamble is detected, then at 349 the signals PDa and PDb are examined to determine which demodulator detected the preamble. If Demod _ a detects a preamble (as indicated by PDa), then AFC limit is set for PHYa at 352A, the Freq _ comp signal is based on FOEa, the channel filter bandwidth signal CHF _ BW is set based on the channel bandwidth specification of PHYa, and the LNA and PGA gains are set based on RSSIa. At 355A, the MUX 95 is controlled to provide the DATAa signal to the FRC315, and the settings of the FRC315 are adapted to the parameters of the PHYa (corresponding to the PHY of the received signal where the preamble was detected). At 358A, a PHYa frame is received or extracted. Conversely, if Demod _ B detects a preamble (as indicated by PDb), then AFC limit is set for PHYb at 352B, the Freq _ comp signal is set based on FOEb, the channel filter bandwidth signal CHF _ BW is set based on the channel bandwidth specification for PHYb, and the LNA and PGA gains are set based on RSSIb. At 355B, MUX 95 is controlled to provide a DATAb signal to FRC315, and the setting of FRC315 accommodates the parameters of PHYb. At 358B, a PHYb frame is received or extracted.

Fig. 15 illustrates how the bandwidth of the channel filter 85 is set in the RF receiver according to various embodiments. Waveform 361 corresponds to the modulation spectrum of the received RF signal corresponding to PHYa, while waveform 364 corresponds to the modulation spectrum of the received RF signal corresponding to PHYb. The waveform refers to the frequency at the output of the digital mixer 75. Note that in the illustrated example, both modulation spectra include worse case frequency offsets. Waveform 367 corresponds to the initial frequency response of channel filter 85. As described above, the bandwidth of the channel filter 85 is set so as to be adapted to the modulation spectrum of both PHYa and PHYb. In the illustrated example, waveform 370 shows the frequency response of channel filter 85 after a PDa trigger (i.e., detection of a preamble corresponding to PHYa). After AFC stabilization, waveform 361 is superimposed on waveform 370 to illustrate the programmed bandwidth of channel filter 85 compared to waveform 361 (the modulation spectrum of the received RF signal corresponding to PHYa). As shown, the bandwidth of the channel filter 85 is slightly greater than the maximum spectral width of the waveform 361 to properly fit the spectrum of the received RF signal corresponding to the PHYa.

Fig. 16 shows a circuit arrangement for the RF receiver 5 according to an exemplary embodiment. In this embodiment, the SUN PHY is used by way of example and not limitation. More specifically, in the Institute of Electrical and Electronics Engineers (IEEE) standard 802.15.4, several PHYs are specified, including SUN-FSK (frequency shift keying), SUN-OFDM (orthogonal frequency division multiplexing), and SUN-OQPSK (offset quadrature phase shift keying). In some applications, it may be desirable for a single device to support multiple SUN PHYs (e.g., Wi-SUN is considering adding SUN-OFDM, backwards compatible SUN-FSK). Fig. 16 shows an RF receiver that can support multiple SUN PHYs. For example, the transmitter may transmit a signal corresponding to SUN-FSK or SUN-OFDM. The receiver 5 has two demodulators 305 and 310, one for demodulating FSK (e.g., demodulator 305), which is a narrowband (as opposed to OFDM) signal, and the other for demodulating OFDM (e.g., demodulator 310), which is a wideband (as opposed to FSK) signal.

In this embodiment, demodulator 310 may use a long training field and short training field (LTF/STF) detector (similar to generating PDa as described above) for the OFDM received signal, as will be understood by those of ordinary skill in the art. Rather, as described above and as will be appreciated by one of ordinary skill in the art, the demodulator 305 may use a preamble detector and/or a sync word detector to generate the PDb signal. In this example, the spectrum corresponding to the SUN-OFDM PHY may be much wider than the corresponding spectrum of the SUN-FSK PHY. In the exemplary embodiment shown, separate decimators and channel filters are used to accommodate the spectral differences.

More specifically, in the signal path of the demodulator 305, the decimator 80 and the channel filter 85 are used. In contrast, in the signal path of demodulator 310, decimator 120 and channel filter 115 are used. Note that two separate control signals CHF _ BWa and CHF _ BWb are provided by controller 105 to program the bandwidths of channel filters 85 and 115, respectively. Note that a single decimator and a single channel filter may be used in some cases, depending on various factors, as will be understood by those of ordinary skill in the art. These factors include design specifications, performance specifications, cost, IC or device area, available technology (e.g., achievable bandwidth of the channel filter, semiconductor fabrication technology, etc.), target market, target end-user, etc., as will be understood by those of ordinary skill in the art.

Fig. 17 shows a circuit arrangement for the RF receiver 5 according to an exemplary embodiment. This embodiment provides for concurrent preamble detection on different frequency channels. More specifically, in Z-wave, the R1 PHY signal is transmitted at 908.40MHz, while the R3 PHY is transmitted at 916 MHz. As an alternative to increasing the preamble detection window, the arrival of the R1 and R3 signals may be detected concurrently. Fig. 16 provides an architecture for an RF receiver that performs concurrent detection. Note that the IF path is not limited to a single demodulator. Thus, as an example, IF path _ a may be used for R1 and R2 PHYs, while IF path _ b may be used for R3 PHYs. In this configuration, R1, R2, and R3 PHYs may be searched concurrently. Because the transmit signals corresponding to R1 and R3 use different frequencies, two NCO's are used: NCO 80 for one PHY (e.g., R1) and NCO 130 for another PHY (e.g., R3). Similar to the embodiment in fig. 16, separate decimators and channel filters are used for the receive signal paths corresponding to the two PHYs. More specifically, the decimator 80 and the channel filter 85 are for a receive signal path corresponding to one PHY (e.g., R1), while the decimator 120 and the channel filter 115 are for a receive signal path corresponding to another PHY (e.g., R3).

Controller 105 generates signals Freq _ comp _ a and Freq _ comp _ b, which are used to set the output frequencies of NCO 80 and NCO 130, respectively. In addition, signals Freq _ comp _ a and Freq _ comp _ b are provided as input signals to MUX 375. In response to a selection signal provided by controller 105 (PDa/PDb, i.e., which of demodulators 305 and 310 detected the preamble), MUX 375 provides Freq _ comp _ a or Freq _ comp _ b to RF frequency synthesizer 25. RF frequency synthesizer 25 uses the output signal of MUX 375 to set its output frequency (the LO signal used by mixer 20). Note that in the exemplary embodiment shown above, a receiver for concurrently detecting two preambles (e.g., an RF receiver including two demodulators 305 and 310, respectively) is shown. However, one of ordinary skill in the art will appreciate that an RF receiver according to other embodiments may concurrently detect more than two preambles by making appropriate modifications (e.g., using more than two demodulators, decimators, channel filters, etc.) as desired. As will be appreciated by one of ordinary skill in the art, the selection of the number of concurrently detected preambles depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technologies, such as semiconductor manufacturing technology, target market, target end-user, and the like.

The network may use one PHY to initiate a handoff to another PHY. For example, in BLE, the PHY is set after connection by checking the functions and configurations of two devices in a procedure called PHY update procedure. For more details, see bluetooth specification version 5.0, section B, section 5.1.10 of volume 6. Concurrent PHY detection capabilities according to various embodiments will make the PHY update procedure unnecessary. This attribute will reduce latency and power consumption associated with the overhead of the PHY update procedure. For example, a node may immediately decide to transmit using a higher rate PHY if link quality allows, and a receiver incorporating concurrent detection according to various embodiments will be able to receive the higher rate PHY. To support concurrent detection, a node may share concurrent detection capabilities with other nodes by transmitting a PHY capability field so that the other nodes may utilize the concurrent detection capabilities. Further, the PHY as part of the concurrency detection may be included in the shared PHY capability field. In the IEEE802.15.4 standard, the PHY capability IE may be used to convey concurrency detection capabilities (see, e.g., IEEE802.15.4-2015, clause 7.4.4.10). Further, the PHY capability IE may include a PHY as part of a concurrency detection scheme or arrangement. By sharing concurrency detection capabilities, the network may have a migration path from traditional PHY switching methods (e.g., PHY update procedure in BLE) to more favorable concurrency detection methods.

Note that in some embodiments, the controller 105 may provide fewer control signals than shown in the figures as needed, as will be understood by one of ordinary skill in the art. For example, as described above, in some embodiments, the controller 105 may provide a single control signal, i.e., a bandwidth adjustment signal, i.e., a CHF _ BW signal (which may include multiple bits, or provide CHF _ BWa and CHF _ BWb signals if two or more channel filters are used, etc.). In some embodiments, controller 105 may provide other control signals in addition to the one or more bandwidth adjustment signals, i.e., one or more of the PGA _ gain signal, LNA _ gain signal, one or more control signals, etc., provided to FRC315, as will be understood by those of ordinary skill in the art. As will be appreciated by one of ordinary skill in the art, the selection of the type and number of control signals depends on various factors. These factors include design specifications, performance specifications, cost, IC or device area, available technology, target market, target end-user, etc., as will be understood by those of ordinary skill in the art.

One aspect of the present disclosure relates to an RF communication system supporting multiple modulation schemes. A modulation scheme is a process of converting data into an electrical signal suitable for transmission over a medium. Different modulation schemes are characterized by different processes or process sequences. A communication device according to an example embodiment includes a node that may communicate with other nodes in a system, as described below. The node may have Receive (RX) and Transmit (TX) capabilities, i.e., transceiver capabilities, as needed, as described below. By way of example, and not limitation, a node, receiver, and transmitter according to various embodiments (such as the exemplary embodiments described herein) may use one or more of the following modulation schemes: frequency Shift Keying (FSK), M-ary FSK, M-ary PSK, on-off keying (OOK), Amplitude Shift Keying (ASK), Quadrature Phase Shift Keying (QPSK), offset quadrature phase shift keying (O-QPSK), Binary Phase Shift Keying (BPSK), 1/4pi QPSK, Quadrature Amplitude Modulation (QAM), Orthogonal Frequency Division Multiplexing (OFDM), and Chirp Spread Spectrum (CSS). As will be appreciated by one of ordinary skill in the art, the choice of modulation scheme used depends on a variety of factors, such as design and performance specifications, use case scenarios, cost, complexity, available technology, and so forth.

Emerging network protocols, such as Wi-SUN and Amazon Sidewalk, use nodes that seek to communicate under a relatively wide range of path loss and interference/multipath conditions. To support reliable communications, multiple modulation schemes may be used, each of which is optimized for a particular use case. For example, the FSK modulation scheme may be used for relatively long-range communications, while the OFDM modulation scheme may be used for relatively high-throughput communications. Generally, a high throughput modulation scheme is desirable because it favors battery life or has lower power consumption, as well as network service capacity (short medium occupancy time). In contrast, long-range transmissions typically use modulation schemes optimized for lower data rates.

Various use cases, such as in the IoT domain, use dedicated and optimized modulation schemes. The various use cases are the result of different cost structures in the nodes and communication conditions. For example, the cost structure may depend on the application and various factors, such as whether the node serves a gateway device or a terminal device, whether it is powered by a button cell, a lithium thionyl chloride battery, or a mains power supply. Communication conditions may include relatively long distance communications, relatively high throughput, relatively severe multipath, or interference. For example, it is well known that OFDM-based modulation schemes are suitable for relatively high throughput, relatively severe multipath, while FSK modulation schemes are suitable for relatively low cost/low power and relatively long range communications. The modulation scheme is characterized by having or using unique modulation, e.g., FSK, OFDM, O-QPSK, Chirp Spread Spectrum (CSS) are examples of modulation schemes according to the application. Note that OFDM with different Modulation and Coding Schemes (MCS) are not generally considered to be different modulation schemes, and O-QPSK or CSS with two different spreading factors are not considered to be different modulation schemes either.

The conventional method takes a relatively large amount of time and effort to facilitate the transition from one data rate to another, i.e., the transition from one modulation scheme to another. Thus, a trade-off is made between RX sensitivity, which is a trade-off with transmission range, and latency, which is a trade-off with throughput, power consumption and network capacity.

The illustrative embodiments use apparatus, and an associated method, for transmitting and receiving packets between a plurality of nodes using a plurality of modulation schemes for a plurality of data rates in an RF communication system. An RF receiver in a node receives packets without prior knowledge of which modulation scheme to use to transmit the packets (e.g., by other nodes in the system). The illustrative embodiments reduce cost and overhead in networks with multiple PHYs. In addition, they simplify the communication protocol. These attributes benefit energy consumption, network service capacity, range, and throughput.

The disclosed concepts aim to reduce costs and overhead in networks with multiple PHYs. In addition, they simplify the communication protocol. These attributes benefit energy consumption, network service capacity, range, and throughput. In an exemplary embodiment, overhead is reduced by taking advantage of advances in receiver detection techniques. These detection techniques allow a cost-effective solution to detect more than one modulation scheme simultaneously. Thus, the modulation scheme may be optimized for a given or desired use case. Furthermore, the modulation scheme and SHR (synchronization field) can be optimized independently to best serve a given or desired use case. For example, a relatively long range PHY with a relatively low rate may be implemented based on an O-QPSK PHY with Direct Sequence Spread Spectrum (DSSS), where the SHR is long enough to obtain optimal sensitivity. Such SHR can limit the throughput of relatively high data rate modulation schemes. However, in an exemplary embodiment, a relatively high throughput SHR may be optimized separately. As just one example, the OFDM modulation scheme may be used for relatively high throughput use cases, where the SHR (or STF + LTF, synchronization field for SUN OFDM) may have a shorter duration than a relatively long range SHR, such that throughput is optimized.

A disadvantage of OFDM is the use of a non-constant envelope. The information in an OFDM signal is embedded in both phase and amplitude. Therefore, the use of a linear power amplifier has sufficient linearity, but the power consumption is high. O-QPSK (sinusoidal), CSS and FSK, on the other hand, have a constant envelope, which allows the use of non-linear power amplifiers. The non-linear power amplifier may have higher power efficiency than the linear power amplifier. In general, when low power consumption in the transmit mode is required, a modulation scheme with a constant envelope is preferred. Battery powered devices may have a relatively limited power budget. Constant envelope modulation schemes are capable of producing higher output power than non-constant envelope modulation schemes. This property is desirable when relatively long distance communication is required. As used in the exemplary embodiments, the disclosed technology recognizes that different modulation types have respective advantages and disadvantages. The apparatus and methods according to various embodiments allow for improved efficiency and higher figure of merit by allowing for the use of different modulation schemes without using a priori knowledge of the modulation scheme used, as described further below.

Continuing with the example above, by using a concurrency detection technique, the receiving node, or the RF receiver in the node, will be able to scan both modulation schemes without knowing in advance which modulation scheme to use to transmit the RF signal that the receiver is receiving, as described above. In other words, the RF receiver will find the modulation scheme by searching two SHR concurrently. From the transmitting node (or RF transmitter) perspective, once it has an indication of link quality, it can decide to select the appropriate modulation scheme without first transmitting a mode switch packet or processing the PHY negotiation protocol. In this way, a relatively high throughput PHY is not compromised by a PHY that also supports relatively long distances. Conversely, the receive sensitivity of the long-range PHY is not compromised by PHYs that also support relatively high throughput.

In some embodiments, simplification may be achieved by not allowing a node to receive more than one packet at a time. When a node is allowed to receive multiple packets simultaneously, the responses (e.g., acknowledgements) to the packets may be relatively complex. For example, if a packet is received, it may defer its transmission response because it may disrupt the reception of another packet that is still being received. Nodes waiting for a response may listen for a longer time because the response is deferred. The waiting period will be a function of the lowest data rate and the longest packet length. By not allowing a node to receive no more than one packet at a time, the response may be well defined, which will save power on the node that expects to respond.

In some embodiments, further simplification may be made by sharing the Medium Access Control (MAC) format between modulation schemes. This can simplify the MAC protocol, reduce cost, and improve coexistence. The hardware and software or firmware for one MAC may be more compact than if multiple MACs were used. In other words, sharing a MAC results in the use of less hardware resources and less storage and processing power, thereby reducing overall cost. Packet Traffic Arbitration (PTA) may be an integral part of a MAC to address conventional bandwidth contention issues among multiple MACs, and a PTA may not have all available data to make optimization decisions on transmission priority. In other words, in conventional approaches, the number of successful and unsuccessful transmissions using the first MAC may not be available in the second MAC. These data can be provided relatively easily in a single shared MAC, which facilitates priority calls.

Some embodiments may be used in conjunction with conventional methods, as desired. For example, the SUN-OQPSK PHY may be combined with the SUN-OFDM PHY. In this case, the nodes may be configured such that they search for SUN-OQPSK SHR and SUN-OFDM SHR concurrently. Once one of these SHR is detected, the node relies on a conventional scheme that adjusts by using the PHR, e.g., the spreading factor in the case of SUN-OQPSK, or the MCS in the case of SUN-OFDM. The PHR is a PHY header and is typically transmitted after the SHR. The PHR contains PHY information about the packet, such as packet length, rate mode or spreading factor, MCS, data whitening enable/disable, Frame Check Sum (FCS) length, etc.

In some embodiments, nodes may transmit packets that include their PHY capability Information Elements (IEs). A node may use an IE to communicate which PHYs it may receive concurrently. The IE may also indicate that it can act on mode switch packets or PHY negotiation protocols. By communicating the PHY capabilities of a node, other nodes may select the modulation scheme switching methods supported by the node. For example, a conventional device that does not support concurrent detection may support a conventional approach. In the same network, a receiver with the above-described concurrency detection techniques may be used to add more advanced nodes in accordance with the exemplary embodiments. The disclosed concept can be used to upgrade a network by signaling one or more modulation scheme switching methods in the PHY capability IE.

The illustrative embodiments support various use cases using different modulation schemes. For example, in one use case, O-QPSK and OFDM, or FSK, O-QPSK and OFDM modulation schemes may be supported. In the initial communication, the node may use a modulation scheme that supports relatively long-range communication, such as O-QPSK. Once the initial connection is established, the node may collect signal quality metrics such as packet success rate, RSSI, signal-to-noise ratio, EVM (error vector magnitude), link margin, etc. Based on the signal quality metric, the node may decide to change the modulation scheme, e.g., the node may change to a modulation scheme with a relatively higher throughput or data rate, such as OFDM, when the signal quality allows it. A higher data rate allows for a shorter transmission time, given a certain amount of payload data. Shorter transmission times may save energy and increase network capacity. Conversely, when the packet success rate falls below a threshold, the node may decide to change to a modulation scheme with a relatively longer distance, such as O-QPSK. Doing so may help to maintain communication even when conditions deteriorate, for example, when mobility increases in range or is causing congestion. Note that switching to a new modulation scheme does not inform the RF receiver in advance. This approach allows for an optimized SHR and STF/LTF design that supports a relatively high figure of merit for all supported data rates. Note that in this use case, as described above, simplification can be achieved by prohibiting more than one packet from being received at a time, thereby allowing a single protocol stack or MAC to support multiple modulation schemes.

It is further noted that the figure of merit is related to the following efficiency goals: higher network capacity, lower energy or power consumption, and higher data throughput. Efficient networks use most of the energy for transmitting data Payloads (PSDUs). A relatively small portion of the total power should be spent on overhead data such as synchronization and PHY headers. Conventional nodes spend a relatively long time on overhead data, e.g., by transmitting a mode switch packet followed by a settling delay. The settling delay is used to allow the receiver node time to process the mode switch packet and prepare for the new modulation scheme. The actual data transmission is contained in the PSDU. In an exemplary embodiment, the use of a mode switch PPDU or PHY negotiation procedure is eliminated. Packets with the new modulation scheme may be transmitted without the energy, time, and spectrum spent for mode switch PPDU or PHY negotiation transactions. This attribute translates into longer battery life (or lower power or energy consumption), higher effective throughput, reduced latency, and higher network capacity. Furthermore, PSDUs typically contain addressing and are protected by encryption, thereby enhancing network security. A node according to an exemplary embodiment spends relatively little time on overhead data and more time on PSDU transmission. This property results in higher throughput, less energy waste on overhead data, and higher network capacity.

In some embodiments, the use case described above may be extended with an OFDM PHY that supports MCS switching similar to the SUN OFDM modulation scheme. The relatively long-range modulation scheme may still be a different modulation scheme, e.g., O-QPSK. In such embodiments, there is no need to support long ranges in OFDM modulation schemes. This property allows for skipping lower data rates in OFDM modulation schemes and optimizing STF/LTF and PHR without using a relatively long range scheme. Such embodiments may provide shorter STF, LTF, and PHR durations and higher figures of merit while still having the benefit of further increasing the data rate. Such an embodiment may be further extended by adding a rate switch similar to the SUN O-QPSK modulation scheme, e.g., for relatively long distance modulation schemes. Such embodiments may be considered hybrid, where the advantages from the use case described above are combined with the advantages of rate mode switching and/or MCS switching.

In a third use case, in some embodiments, a single shared MAC may be used instead of multiple MACs, as described above. Fig. 18 illustrates a network or protocol stack 400 with a shared Medium Access Control (MAC) according to these embodiments. The remainder of the protocol stack is well known to those of ordinary skill in the art and will not be described in detail. In the illustrated example, the shared MAC (labeled "IEEE 802.15.4MAC layer") allows for reduced device complexity, improved coexistence, and reduced maintenance costs (i.e., repair of errors or failures in a single stack, rather than scheduling multiple MACs). In the illustrated example, the protocol stack supports four modulation schemes by using four corresponding PHYs: FSK, O-QPSK, OFDM, and CSS. Other protocol stacks supporting other modulation schemes are contemplated and may be used as desired with appropriate modifications, as will be appreciated by those of ordinary skill in the art.

Further details regarding the operation of nodes and related methods according to exemplary embodiments are provided below. Typically, a packet contains a preamble, a synchronization frame delimiter (SFD, also known as a sync word), a PHY Header (PHR), and a PHY payload. Some modulation schemes may omit SFD, for example in CSS/LoRa. In OFDM, the preamble and SFD are typically replaced by a Short Training Field (STF) and a Long Training Field (LTF). A network using nodes according to example embodiments may employ more than one of the above modulation schemes. For example, one node may be capable of transmitting FSK RF signals while another node may be capable of transmitting OFDM RF signals, or one node may be capable of transmitting FSK signals while another node may be capable of transmitting FSK RF signals or OFDM RF signals. To this end, the node may have an FSK modulator or an OFDM modulator, or both. The above examples are provided for illustration only, and other possibilities are contemplated and exist. Thus, the node may also be able to use other modulation schemes (e.g., O-QPSK, BPSK, OOK, ASK, QAM, etc.). Generally, a network using a node according to an exemplary embodiment uses at least two modulation schemes, and the node should be able to transmit at least one modulation scheme. If a node is capable of transmitting more than one modulation scheme, a transmit controller (e.g., a finite state machine (TX-FSM)) may be used to select an appropriate or desired modulation scheme. The selection may be based on previous transmissions. For example, the technique described in the IEEE 802.15.4-2020 standard is referred to as the link margin (obtained from a previous transmission) Information Element (IE). As an example, packet success rate, RSSI, etc. may be used as desired.

The RF receiver according to an exemplary embodiment uses a Modulation Scheme Detector (MSD), as described in detail below. The fields listed above have different characteristics when modulated using one of a plurality of modulation schemes, which are determined by their phase, amplitude and bit sequence. The MSD uses these attributes to detect the modulation scheme with relatively few false detections used in the multiple modulation schemes. In various embodiments, an FSM (RX-FSM) or controller controls state transitions, configuration of receiving nodes (RF receivers in the nodes), and reception of packets.

Fig. 19 shows a circuit arrangement of a network node 520 according to an exemplary embodiment. The network node 520 comprises an RX (via the RF receiver circuit 5) and a TX (via the transmitter circuit 515), i.e. it constitutes an RF transceiver. Similarly, the numbered blocks/circuits/elements in fig. 19 operate similarly and/or analogously to their counterparts described above (e.g., in conjunction with fig. 17 or other figures). In the embodiment shown in fig. 19, the demodulator 305 demodulates a received signal modulated using FSK modulation. Similarly, the demodulator 310 demodulates a received signal modulated using OFDM modulation. However, as will be appreciated by those of ordinary skill in the art, FSK and OFDM constitute examples only, and other modulation schemes are possible and contemplated, e.g., as described above. Fig. 19 also includes two MSDs: MSD _ FSK 403 and MSD _ OFDM 406. MSD _ FSK 403 detects the FSK modulated signal and provides an indication of the detection via signal MSD _ FSK, which is provided to controller 105. Similarly, MSD _ OFDM 406 detects a signal modulated with OFDM and provides an indication of the detection via the signal MSD _ OFDM, which is provided to the controller 105.

In an exemplary embodiment, MSD such as MSD _ FSK 403 and MSD _ OFDM 406 constitute a signal detector, and may be implemented using the signal detector in various ways as described above (e.g., DSA 90), as will be understood by those of ordinary skill in the art. There may be one MSD per filtered baseband (i.e., the output of the channel filter). Typically, each MSD is configured to detect the presence of a desired, specific, different modulation scheme in the signal received at the input. When a packet has been successfully received, FRC315 (RX FRC)315 provides an output signal of "received packet" to controller 105. The controller 105 uses the memory 409 to perform its functions (e.g., program storage, work storage, saving network information, network status, etc.). The controller 105 provides an enable signal (RX _ enable) to enable the receiver 5 and an RX configuration signal (RX _ config) to configure the RF receiver 5.

The controller 105 provides a TX _ enable signal to enable the transmitter or transmitter circuit 515. The controller 105 also provides a TX configuration signal (TX _ config) to configure the transmitter 515. The TX-FRC 412 is a transmitter frame controller. It performs processing on the PSDU (i.e., the TX _ PSDU received from controller 105), such as Sync Header (SHR) insertion, block coding, forward error correction, frame checksum generation, data whitening, etc., to generate a TX _ PPDU signal that is provided to modulator 415. The modulator 415 modulates the TX _ PPDU signal using a desired modulation scheme. Note that for FSK, there are alternative modulation schemes that use LO 25 as needed. LO 25 provides a TX _ LO signal to DAC 418. The DAC 418 converts the modulated output of the modulator 415 into an analog signal, which is provided to a Power Amplifier (PA) 421. The PA 421 amplifies the signal from the DAC 418 and transmits the amplified signal via the RF switch 11 and the antenna 10. In response to a control signal (e.g., from the controller 105), the RF switch 11 couples the antenna 10 to the RF receiver 5 for RF receiving operations or to the RF transmitter 515 for RF transmitting operations.

Fig. 20 shows a controller 105R for the RF receiver 5 of fig. 19. In various embodiments, the controller 105R is part of the controller 105 (see fig. 19), but it may be implemented separately as desired. Referring again to fig. 20, the controller 105R includes an application processor 430, the application processor 430 running at least a portion of the protocol stack and at least a portion of the application layer. The application processor receives events such as sensor inputs, processes the events (e.g., by running an application) and provides control outputs such as actuator signals. The application processor may initiate reception through the MAC interface, e.g., after a packet transmission, the node may initiate reception to receive an acknowledgement packet to indicate a successful transmission. In an exemplary embodiment, the application processor 430 may load configuration data for the RF receiver 5 into hardware registers, namely shift registers 434 and 436. Alternatively, the application processor 430 may provide the configuration data directly to the hardware, however, to support fast configuration, the application processor 430 may load the configuration data stored in the memory 409 (e.g., non-volatile memory) to the controller 105 at power-up or startup. Then, when the configuration data is to be used, the controller 105 can load the configuration data from the registers in the controller 105 into the shift registers 434 and 436 relatively quickly. Fast configuration is required to reduce latency to support relatively fast turnaround times between transmission and reception, and vice versa.

The application processor 430 interfaces with the MAC processor 428 via a "MAC interface". The MAC processor 428 processes the MAC payload and provides it to the application processor. The MAC processor 428 provides a TX _ PSDU signal (to the controller 105 to provide to the transmitter circuit 515 for transmission as an RF signal, see fig. 19 and 23) and receives an RX _ PSDU signal from the receive circuit 5. MAC processor 428 provides a receiver enable signal to receive FSM (RX _ FSM) 425. The RX _ FSM 425 receives the "received packets," "MSD _ FSK," and "MSD _ OFDM" signals described above from circuitry in the controller 105. The RX _ FSM 425 works in conjunction with the timer 423 via an output signal "timer start" (to indicate a waiting period for packet reception) and an input signal "timeout" (to indicate no packet reception within a specified period of time counted by the timer 423). The RX _ FSM 428 provides a state output signal (labeled "state Sx") to several other blocks or circuits. These states are described in detail below. The state output signals S0 and S1 are provided to latch 432. Latch 432 latches one or more enable signals from RX _ FSM 425. State output signal S0 resets latch 432, which places receiver 5 in an idle state (not enabled), i.e., signal RX _ enable has a binary 0 value. The status output signal S1 sets the latch, which enables the receiver 5, i.e. the signal RX _ enable has a binary 1 value. The status output signal S2 enables the shift register 434, the shift register 434 containing the setting or configuration data for FSK reception (provided by the "configuration data" input to the shift register 434). The status output signal S3 enables the shift register 436, the shift register 436 containing settings or configuration data for OFDM reception (provided by "configuration data" input to the shift register 434). Status output signal S6 provides a "packet ready" signal to MAC processor 428 and application processor 430 so that they can process the received packets.

The state output signal S2/S3 (i.e., whether S2 is active or S3 is active) is used as a select signal for the MUX 438. In response to the selection signal, the MUX 438 provides either the output of the shift register 434 or the output of the shift register 436 as its output as the "RX _ config" signal. The RX _ config signal configures the receiver to support the detected modulation scheme (FSK and OFDM in the example in question). Such configurations may include, but are not limited to, channel filter bandwidth, the location of MUX 95 (see fig. 19), demodulator settings (e.g., if one demodulator is used that can be configured to support multiple modulation schemes), settings for automatic gain control circuitry (AGC) (see fig. 19) (e.g., more margin is left for non-constant envelope modulation (e.g., OFDM) when an OFDM modulation scheme is detected), settings for Automatic Frequency Control (AFC) (e.g., frequency offset estimates associated with the detected modulation scheme are used to provide frequency feedback (see fig. 19) to, for example, NCOa or NCOb to compensate for frequency offset), and/or settings for FRC315 (e.g., to activate a certain block decoding scheme, forward error correction scheme, frame checksum polynomial, data de-whitening, etc.).

Fig. 21 shows a control flow diagram of the RF receiver 5 in the exemplary embodiment shown in fig. 19 and 20. The "Sx" symbol next to the parenthesis (where "x" denotes a state number, e.g., S0 for state 0) indicates which portions of the flowchart correspond to a given state (see fig. 20 and 22). For example, state S0 corresponds to 440 and 441 in the flowchart. At 440, the receiver is idle. At 441, the receiver is enabled, which enables a signal detector (MSD). At 442, it is checked whether a signal is detected. If not, control returns to 442. Otherwise (i.e., a signal is detected), the detected modulation scheme is checked at 443. If the modulation scheme is FSK (MSD _ FSK ═ 1), control passes to 444. If the modulation scheme is OFDM (MSD _ OFDM ═ 1), then control passes to 448. In the case of FSK modulation, a timer is started at 444 (see fig. 20). At 445, the receiver is configured for FSK packet reception. At 446, an FSK packet is received (or attempted to be received). At 447, a timeout check is made. If there is no timeout, control returns to 446, and when a packet is received, control passes to 452 to process the PSDU (e.g., by the MAC processor (see FIG. 20)). Otherwise, control returns to 442 to check for signal detection. As described above, if the modulation scheme is OFDM (MSD _ OFDM ═ 1), control passes to 448 where a timer is started (see fig. 20). At 449, the receiver is configured for OFDM packet reception. At 450, an OFDM packet is received (or attempted to be received). At 451, a timeout check is performed. If there is no timeout, control returns to 450 and when a packet is received, control passes to 452 to process the PSDU (e.g., by the MAC processor (see FIG. 20)). Otherwise, control returns to 442 to check for signal detection.

Fig. 22 shows a control state diagram of the RX _ FSM 425 (see fig. 20) according to an exemplary embodiment. In other words, RX _ FSM 425 is implemented (e.g., using flip-flops, latches, gates, etc., as will be understood by one of ordinary skill in the art) to implement the functions shown in fig. 22. The states have state output signals shown in fig. 20. Referring again to fig. 22, operation begins at state S0 (idle). When the receiver is enabled, the state transitions to S1. As long as MSD _ FSK _ OFDM is 0 (no signal detected), control remains at S1. If MSD _ FSK is 1 (FSK signal detected), the state transitions from S1 to S2, where a timer (see fig. 20) is started and configuration is performed, as described above. When the Config _ done signal is asserted, indicating that the configuration is complete (see above), the state transitions from S2 to S4. If no packet is received and there is no timeout, control remains at S4. If a timeout occurs before the packet is received, control will transition from S4 to S1. However, once the packet is received, control transfers from S4 to S6. At state S6, the processor (see fig. 20) is notified of the receipt of a packet (by using the "packet ready" signal). As described above, the processor may process the packet. Receiving OFDM packets follows a similar scheme. More specifically, if MSD _ OFDM ═ 1 (an OFDM signal is detected), the state transitions from S1 to S3, where a timer (see fig. 20) is started and configuration is performed, as described above. When the Config _ done signal is set, the state transitions from S3 to S5. If no packet is received and there is no timeout, control remains at S5. If a timeout occurs before the packet is received, control will transition from S4 to S1. However, once the packet is received, control transfers from S5 to S6.

Fig. 23 shows a controller 105T for an RF transmitter according to an example embodiment. In various embodiments, the controller 105T is part of the controller 105 (see fig. 19), but it may be implemented separately as desired. Referring again to fig. 23, controller 105T includes an application processor 430 (which may be shared with the RX application processor in fig. 20) that runs at least a portion of the protocol stack and at least a portion of the application layer. The application processor receives events such as sensor inputs, processes the events (e.g., by running an application program), and provides control outputs such as actuator signals. The application processor may also respond to previously received packets, e.g., to prepare to transmit an acknowledgement. The modulation scheme and turnaround time (the time between the end of a received packet and the start of a response packet) may be based on the detected modulation scheme of a previously received packet. In an exemplary embodiment, the application processor 430 may load configuration data for the RF transmitter 515 into hardware registers, namely shift registers 459 and 461. Alternatively, the application processor 430 may provide the configuration data directly to the hardware, however, to support fast configuration, the application processor 430 may load the configuration data stored in the memory 409 (e.g., non-volatile memory) to the controller 105 at power-up or startup. Then, when the configuration data is to be used, the controller 105 can relatively quickly load the configuration data from the registers in the controller 105 into the shift registers 459 and 461. Fast configuration is required to reduce latency to support relatively fast turnaround times between transmission and reception, and vice versa.

The application processor 430 interfaces with the MAC processor 428 via a "MAC interface". The application processor processes the MAC payload and provides it to the MAC processor 428. The MAC processor 428 provides the TX _ PSDU signal (to the controller 105 to provide to the transmitter for transmission as an RF signal). The MAC processor 428 provides a transmitter enable signal to the transmit FSM (TX _ FSM) 457. TX _ FSM 457 receives the output of comparator 455 (labeled "C)_out"). The comparator 455 compares the Link quality (labeled "Link Margin") provided by the application processor with a threshold (labeled "TH"). The TX _ FSM 457 provides a state output signal (labeled "state Sx") to several other blocks or circuits. These states are described in detail below. The status output signal S2 enables the shift register 459, which contains setting or configuration data for FSK transmission (provided by "configuration data" input to the shift register 434). The status output signal S3 enables the shift register 461, the shift register 436 containing setup or configuration data for OFDM transmission (provided by "configuration data" input to the shift register 461). Status output signal S4 drives enable circuit 463, which enables circuit 463 to enable transmitter 515 (see fig. 19) using signal TX _ enable to transmit a modulated RF signal, as described above.

The state output signal S2/S3 (i.e., whether S2 is active or S3 is active) is used as a select signal for the MUX 465. In response to the selection signal, the MUX465 provides as its output either the output of the shift register 459 or the output of the shift register 461 a "TX _ config" signal. The TX _ config signal configures the transmitter to support modulation schemes (FSK and OFDM in the example under discussion). Such configurations may include, but are not limited to, symbol shaping (e.g., shapes such as sine, raised cosine, gaussian, etc.) in modulator 415 (see fig. 19), setting the bandwidth of DAC 418 (see fig. 19), in the case of DAC-based IQ modulators, the bandwidth of frequency synthesizer (LO)25 (see fig. 19), e.g., if FSK modulation at a relatively high data rate is used, setting of modulator 415 (e.g., if one modulator is used that may be configured to support multiple modulation schemes), and/or setting of FRC412 (see fig. 19) (e.g., activating a certain block decoding scheme, forward error correction scheme, frame checksum polynomial, data de-whitening, etc.).

Fig. 24 shows a control flow diagram of the RF transmitter 515 in the exemplary embodiment shown in fig. 19 and 23. The "Sx" symbol next to the parenthesis (where "x" denotes a state number, e.g., S0 for state 0) indicates which portions of the flowchart correspond to a given state (see fig. 23 and 25). For example, state S0 corresponds to 465 in the flowchart. At 465, the transmitter is idle. After enabling the transmitter, it is checked at 467 whether the link margin is greater than a threshold TH, as described above. If not, an FSK modulation scheme is selected at 469 and an RF signal modulated using FSK is transmitted at 471. However, if the link margin is greater than the threshold, then an OFDM modulation scheme is selected at 473 and an RF signal modulated using OFDM is transmitted at 471.

Fig. 25 illustrates a control state diagram of the TX _ FSM 457 (see fig. 23) according to an exemplary embodiment. In other words, TX _ FSM 457 is implemented (e.g., using flip-flops, latches, gates, etc., as will be understood by one of ordinary skill in the art) to implement the functions shown in fig. 25. The state has the state output signal shown in fig. 23. Referring again to fig. 25, S0 constitutes an idle state and the transmitter is not enabled. The application processor 428 may issue a "transmitter enable" signal over the MAC interface (see fig. 23) based on one or more sensor inputs, one or more timers (not shown), one or more events, or a combination thereof, as desired, to transition from S0 to S1. At S1, the output of the comparator (see FIG. 23), i.e., C_outIs read. When C is_outWhen 0, the state transitions to S2; otherwise, the state transitions to S3. At S2, the configuration data stored in the shift register 459 is loaded into the transmitter circuit to support the FSK modulation scheme. After configuration is complete, a transition from S2 to state S4 will occur. In contrast, at S3, the configuration data stored in the shift register 461 is loaded into the transmitter circuit to support the OFDM modulation scheme. After configuration is complete, a transition from S3 to S4 will occur. In state S4, the transmitter 515 (see fig. 19) is enabled by asserting the TX _ enable signal (see fig. 19 and 23), the PSDU (TX _ PSDU, see fig. 19) is provided to the transmitter 515 from the controller 105, and the packet is transmitted using the selected modulation scheme. After the transmission is completed, a transition is made to state S0.

Note that the MAC functions may be handled by hardware (e.g., by MAC processor 428 in fig. 20 and 23) as well as software or firmware as desired. In some embodiments, the application processor 430 may handle link layer functions, network layer functions, MAC layer functions, or a combination thereof, in addition to running a desired application. In some embodiments, at least some MAC functions may be shared between supported modulation schemes, as described above. For example, both SUN-FSK and SUN-OFDM use IEEE802.15.4 MAC, which may be shared. In some embodiments, a dedicated MAC function (e.g., MAC processor) dedicated to the supported modulation scheme is used. For example, when the Zigbee modulation scheme (OQPSK) is used, IEEE802.15.4 MAC may be used, and when the bluetooth modulation scheme (GFSK) is used, bluetooth MAC may be used.

Receivers and transmitters in accordance with the exemplary embodiments can be used in various communication arrangements, systems, subsystems, networks, and the like, as desired. Fig. 26 illustrates a wireless communication system 500 according to an example embodiment. As mentioned above, the system comprises an RF receiver 5. The system 500 includes a transmitter 515 coupled to the antenna 10A. Via antenna 10A, transmitter 515 transmits RF signals. The receiver 5 may receive the RF signal via the antenna 10B. Additionally or alternatively, node or transceiver 520A and/or node or transceiver 520B may receive the transmitted RF signals (via receiver 5).

In addition to receiving capabilities, node or transceiver 520A and node transceiver 520B may also transmit RF signals. The transmitted RF signal may be received by the receiver 5 either in a separate receiver or via a receiver circuit of the non-transmitting node or transceiver. Other systems or subsystems having different configurations and/or capabilities are also contemplated. For example, in some example embodiments, two or more nodes or transceivers (e.g., node 520A and node 520B) may form a network, such as an ad hoc network. As another example, in some demonstrative embodiments, nodes 520A and 520B may form part of a network, e.g., in conjunction with transmitter 515.

An RF receiver, such as RF receiver 5 described above, may be used for various circuits, blocks, subsystems, and/or systems. For example, in some embodiments, such an RF receiver may be integrated in an IC, such as a microcontroller unit (MCU). Fig. 27 shows a block diagram of IC 550, IC 550 including RF receiver 5, according to an example embodiment. Fig. 28 is similar to the embodiment of fig. 27 and shows an IC 550 that includes an RF transmitter 515 in addition to the RF receiver 5. Thus, the embodiment in fig. 28 has RF transceiver capabilities and can be used as a node.

Referring to fig. 27, IC 550 constitutes or includes an MCU. IC 550 includes a plurality of blocks (e.g., one or more processors 565, data converter 605, I/O circuitry 585, etc.) that communicate with each other using link 560. In an exemplary embodiment, the link 560 may constitute a coupling mechanism, such as a bus, a set of conductors or semiconductor elements (e.g., traces, devices, etc.) for communicating information, such as data, commands, status information, and the like. IC 550 may include a link 560 coupled to one or more processors 565, clock circuits 575, and power management circuits or Power Management Units (PMUs) 580. In some embodiments, the one or more processors 565 may include circuitry or blocks to provide information processing (or data processing or computation) functions, such as a Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), or the like. In some embodiments, processor 565 may include one or more DSPs in addition to or in the alternative. The DSP may provide various signal processing functions, such as arithmetic functions, filtering, delay blocks, etc., as desired. Clock circuit 575 may generate one or more clock signals that facilitate or control the timing of the operation of one or more blocks in IC 550. Clock circuit 575 may also control the timing of operations using link 560 as needed. In some embodiments, clock circuit 575 may provide one or more clock signals to other blocks in IC 550 via link 560. In some embodiments, PMU 580 may reduce a clock speed of a device (e.g., IC 550), turn off a clock, reduce power, turn off a power supply, disable (or power down or put in a lower power consumption or sleep or inactive or idle state), enable (or power up or put in a higher power consumption or normal or active state), or any combination of the preceding, relative to a portion of a circuit or all components of a circuit, such as one or more blocks in IC 550. Further, in response to a transition from an inactive state to an active state (including, but not limited to, when one or more processors 565 transition from a low power or idle or sleep state to a normal operating state), PMU 580 may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the preceding.

Link 560 may be coupled to one or more circuits 600 through a serial interface 595. One or more circuits or blocks coupled to link 560 may communicate with circuit 600 through serial interface 595. As will be appreciated by one of ordinary skill in the art, the circuit 600 may use one or more serial protocols, e.g., SMBUS, I²C. SPI, etc. Link 560 may be coupled to one or more peripheral devices 590 through I/O circuitry 585. Through the I/O circuitry 585, one or more peripheral devices 590 may be coupled to the link 560, and thus may communicate with one or more blocks coupled to the link 560, e.g., one or more processors 565, memory circuitry 625, etc. In an exemplary embodiment, peripheral devices 590 may include various circuits, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.). Note that in some embodiments, some of peripherals 590 may be external to IC 550. Examples include a keypad, a speaker, etc. In some embodiments, for some peripherals, I/O circuitry 585 may be bypassed. In such embodiments, some peripheral devices 590 may couple to link 560 and communicate with link 560 without the use of I/O circuitry 585. As noted above, in some embodiments, such peripheral devices may be external to IC 550. Link 560 may be coupled to analog circuitry 620 via one or more data converters 605. The data converter 605 may include one or more ADCs 605A and/or one or more DACs 605B. ADC 605A receives one or more analog signals from analog circuit 620 and willOne or more analog signals are converted to a digital format, which conveys the signals in the digital format to one or more blocks coupled to link 560. Instead, DAC 605B receives one or more digital signals from one or more blocks coupled to link 560 and converts the digital signals to an analog format, which they pass to analog circuit 620. Analog circuitry 620 may include a variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as will be understood by one of ordinary skill in the art. In some embodiments, analog circuitry 620 may communicate with circuitry external to IC 550 as needed to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks.

Control circuitry 570 is coupled to link 560. Accordingly, control circuitry 570 may communicate with and/or control the operation of various blocks coupled to link 560 by providing control information or signals. In some embodiments, control circuitry 570 also receives status information or signals from various blocks coupled to link 560. Further, in some embodiments, control circuitry 570 facilitates (or controls or oversees) communication or cooperation between various blocks coupled to link 560. In some embodiments, the control circuit 570 may initiate or respond to a reset operation or signal. As one of ordinary skill in the art will appreciate, the reset operation may cause a reset of one or more blocks, ICs 550, etc. coupled to link 560. For example, the control circuitry 570 may reset the PMU 580 and circuitry, such as the RF receiver 5 or various blocks, circuits, or components thereof, to an initial or known state. In an exemplary embodiment, the control circuit 570 may include various types and circuit blocks. In some embodiments, the control circuitry 570 may include logic circuitry, a Finite State Machine (FSM), or other circuitry to perform operations such as those described above. Communication circuit 640 is coupled to link 560 and is also coupled to a circuit or block (not shown) external to IC 550. Through communication circuitry 640, the various blocks coupled to link 560 (or IC 550, generally) may communicate with external circuitry or blocks (not shown) via one or more communication protocols. Examples of communications include USB, ethernet, etc. In an exemplary embodiment, other communication protocols may be used, depending on factors such as the design or performance specifications of a given application, as will be appreciated by those of ordinary skill in the art.

As described above, the memory circuit 625 is coupled to the link 560. Thus, the memory circuit 625 may communicate with one or more blocks coupled to the link 560, such as one or more processors 565, control circuits 570, I/O circuits 585, and so on. Memory circuit 625 provides storage for various information or data in IC 550, such as operands, tags, data, instructions, and so forth, as will be understood by those of ordinary skill in the art. The memory circuit 625 may support various protocols as needed, such as Double Data Rate (DDR), DDR2, DDR3, DDR4, and so on. In some embodiments, memory read and/or write operations of memory circuit 625 involve the use of one or more blocks of IC 550, such as one or more processors 565. In some cases, a Direct Memory Access (DMA) arrangement (not shown) allows for improved performance of memory operations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between a source or destination of data and the memory circuit 625, rather than through blocks such as one or more processors 565. The memory circuit 625 may include a variety of memory circuits or blocks. In the illustrated embodiment, the memory circuit 625 includes non-volatile (NV) memory 635. Additionally or alternatively, the memory circuit 625 may include volatile memory (not shown), such as Random Access Memory (RAM). NV memory 635 may be used to store information related to the performance, control, or configuration of one or more blocks in IC 550. For example, NV memory 635 may store configuration information related to the operation of RF receiver 5 (and/or transmitter 515 in fig. 28), such as configuration information for various blocks, circuits, components, etc. of RF receiver 5 (and/or transmitter 515 in fig. 28).

The various circuits and blocks used in the exemplary embodiments, including the digital and/or mixed signal circuits described above, may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, the digital and/or mixed signal blocks, elements, components or circuits shown in fig. 19, 20, 23 and 26-28 may generally be implemented using digital circuitry (or at least in part in the case of mixed signal blocks). The digital circuit may include circuit elements or blocks such as gates, digital Multiplexers (MUXs), latches, flip-flops, registers, Finite State Machines (FSMs), processors, programmable logic (e.g., Field Programmable Gate Arrays (FPGAs) or other types of programmable logic), Arithmetic Logic Units (ALUs), standard cells, custom analog cells, and so forth, as desired, as will be understood by those of ordinary skill in the art. Further, analog circuits or mixed signal circuits or both, e.g., power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.), etc., may be included as desired. The analog circuitry may include biasing circuitry, decoupling circuitry, coupling circuitry, power supply circuitry, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuitry (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog multiplexers, etc., as desired, as will be understood by one of ordinary skill in the art. As described above, the mixed signal circuit may include an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), etc., in addition to analog and digital circuits, as will be understood by those of ordinary skill in the art. As one of ordinary skill in the art will appreciate, the choice of circuitry for a given implementation depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technologies, such as semiconductor manufacturing technology, target market, target end-user, and the like.

The various circuits and blocks that comprise the analog circuits described above and are used in the exemplary embodiments may be implemented in a variety of ways and using a variety of circuit elements or blocks. For example, LNA 15, mixer 20, and PGA 30 may generally be implemented using analog circuitry. The analog circuitry may include biasing circuitry, decoupling circuitry, coupling circuitry, power supply circuitry, current mirrors, current and/or voltage sources, filters, amplifiers, converters, signal processing circuitry (e.g., multipliers), sensors or detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog multiplexers, and so forth, as desired, as will be understood by those of ordinary skill in the art. Further, digital circuitry or mixed signal circuitry or both may be included. As needed and as will be understood by one of ordinary skill in the art, a digital circuit may include circuit elements or blocks, such as gates, digital Multiplexers (MUXs), latches, flip-flops, registers, Finite State Machines (FSMs), processors, programmable logic (e.g., Field Programmable Gate Arrays (FPGAs) or other types of programmable logic), Arithmetic Logic Units (ALUs), standard cells, custom analog cells, and so forth. As described above, the mixed signal circuit may include an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), etc., in addition to analog and digital circuits, as will be understood by those of ordinary skill in the art. As one of ordinary skill in the art will appreciate, the choice of circuitry for a given implementation depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technologies, such as semiconductor manufacturing technology, target market, target end-user, and the like.

Referring to the drawings, those of ordinary skill in the art will note that the various blocks shown may primarily depict conceptual functions and signal flow. An actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the specific circuitry shown. For example, the functions of the various blocks may be combined into one circuit block as desired. Further, the functions of a single block may be implemented in multiple circuit blocks as desired. The choice of circuit implementation depends on various factors, such as the particular design and performance specifications of a given implementation. Other modifications and alternative embodiments in addition to those disclosed will be apparent to those of ordinary skill in the art. Accordingly, this disclosure teaches those skilled in the art the manner of carrying out the disclosed concepts in accordance with the exemplary embodiments and should be construed as illustrative only. Where applicable, the figures may or may not be drawn to scale, as will be appreciated by those of ordinary skill in the art.

The specific forms and embodiments shown and described constitute only exemplary embodiments. Various changes in the shape, size and arrangement of parts may be made by those skilled in the art without departing from the scope of the disclosure. For example, persons skilled in the art may substitute equivalent elements for the elements shown and described. Moreover, one skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the present disclosure.

Claims (20)

1. An apparatus, comprising:

a Radio Frequency (RF) receiver for receiving RF signals, the RF receiver comprising:

a plurality of Modulation Signal Detectors (MSDs) for generating a plurality of detection signals when a plurality of RF signals modulated using a plurality of modulation schemes are detected; and

a controller that causes reception of the plurality of RF signals in response to the plurality of detection signals.

2. The apparatus of claim 1, wherein the plurality of MSDs comprise a plurality of preamble detectors.

3. The apparatus of claim 1, in which the plurality of MSDs comprise a plurality of sync word detectors.

4. The apparatus of claim 1, wherein the plurality of MSDs operate concurrently to detect a plurality of different physical layers (PHYs).

5. The apparatus of claim 1, wherein the plurality of MSDs operate concurrently to detect the plurality of RF signals modulated using a plurality of modulation schemes.

6. The apparatus of claim 1, wherein the controller causes reception of the plurality of RF signals using a plurality of demodulators.

7. The apparatus of claim 1, wherein the controller configures the RF receiver based on the plurality of detection signals.

8. The apparatus of claim 1, wherein the controller comprises a Media Access Controller (MAC) processor shared to receive the plurality of RF signals modulated using the plurality of modulation schemes.

9. The apparatus of claim 1, wherein the plurality of modulation schemes comprise at least one of: frequency shift keying, i.e., FSK, M-ary PSK, on-off keying, i.e., OOK, amplitude shift keying, i.e., ASK, quadrature phase shift keying, i.e., QPSK, offset quadrature phase shift keying, i.e., O-QPSK, binary phase shift keying, i.e., BPSK, 1/4pi QPSK, quadrature amplitude modulation, i.e., QAM, orthogonal frequency division multiplexing, i.e., OFDM, and chirp spread, i.e., CSS.

10. An apparatus for communicating using RF signals, the apparatus comprising:

a transmitter that transmits a modulated RF signal, wherein the transmitted information is modulated onto the modulated RF signal using one of a plurality of modulation schemes; and

a receiver that receives packets from a received modulated RF signal, the receiver comprising a plurality of Modulation Scheme Detectors (MSDs) to generate a plurality of detection signals, wherein a packet is received by configuring the receiver based on a detection signal of the plurality of detection signals, wherein the detection signal is obtained from the packet.

11. The apparatus of claim 10, comprising a controller to configure the receiver to receive signals modulated using the plurality of modulation schemes based on the plurality of detection signals.

12. The apparatus of claim 10, wherein the plurality of MSDs detect the modulation scheme of the received modulated RF signal during a preamble, a synchronization field, a Start of Frame Delimiter (SFD), a Short Training Field (STF), or a Long Training Field (LTF), or a combination thereof.

13. The apparatus of claim 10, further comprising a Media Access Controller (MAC) processor to process a shared MAC function to receive packets from a received modulated RF signal.

14. The apparatus of claim 10, wherein the plurality of modulation schemes comprise at least one of: frequency shift keying, i.e., FSK, M-ary PSK, on-off keying, i.e., OOK, amplitude shift keying, i.e., ASK, quadrature phase shift keying, i.e., QPSK, offset quadrature phase shift keying, i.e., O-QPSK, binary phase shift keying, i.e., BPSK, 1/4pi QPSK, quadrature amplitude modulation, i.e., QAM, orthogonal frequency division multiplexing, i.e., OFDM, and chirp spread, i.e., CSS.

15. A method of operating a Radio Frequency (RF) receiver to receive an RF signal, the method comprising:

generating a plurality of detection signals by using a plurality of modulation signal detectors, i.e., a plurality of MSDs, when a plurality of RF signals modulated using a plurality of modulation schemes are detected; and

causing reception of the plurality of RF signals in response to the plurality of detection signals.

16. The method of claim 15, wherein using multiple MSDs comprises using multiple preamble detectors or multiple sync word detectors.

17. The method of claim 15, comprising operating the plurality of MSDs concurrently to detect a plurality of different physical layers (PHYs).

18. The method of claim 15, comprising operating the plurality of MSDs concurrently to detect the plurality of RF signals modulated using a plurality of modulation schemes.

19. The method of claim 15, comprising configuring the RF receiver to receive an RF signal of the plurality of RF signals based on a modulation scheme used to modulate the RF signal.

20. The method of claim 15, wherein a Media Access Controller (MAC) processor is shared to receive the plurality of RF signals modulated using the plurality of modulation schemes.

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