CN112751581A

CN112751581A - Apparatus, and associated method, for radio frequency receiver with reduced power consumption and delay

Info

Publication number: CN112751581A
Application number: CN202011178980.6A
Authority: CN
Inventors: H·D·瑞杰特
Original assignee: Silicon Laboratories Inc
Current assignee: Silicon Laboratories Inc
Priority date: 2019-10-30
Filing date: 2020-10-29
Publication date: 2021-05-04

Abstract

Apparatus, and an associated method, for a radio frequency receiver with reduced power consumption and delay. An apparatus includes a Radio Frequency (RF) receiver for receiving a received signal. The RF receiver includes a plurality of Intermediate Frequency (IF) path circuits to generate a plurality of filtered baseband signals. The plurality of IF path circuits includes a respective plurality of signal detectors that detect receipt of a received signal from a respective plurality of filtered baseband signals. The RF receiver further includes a controller that selects at least one filtered baseband signal, and at least one demodulator that demodulates the selected at least one filtered baseband signal.

Description

Apparatus, and associated method, for radio frequency receiver with reduced power consumption and delay

Technical Field

The present invention relates generally to communication devices and related methods. More particularly, the present invention relates to apparatus, and an associated method, for a multi-channel Radio Frequency (RF) receiver having improved power consumption and delay.

Background

As technology advances, more and more circuit elements have been integrated into devices, such as Integrated Circuits (ICs). In addition, more and more devices (e.g., ICs or subsystems) have been integrated into products. This trend is expected to continue with advances such as the internet of things (IoT).

As the number of circuit elements, devices, subsystems, etc. continues to increase, the amount of power consumption of products including these elements also increases accordingly. In certain applications, such as battery powered, mobile, or portable products, the amount of power or energy available is limited. Given the relatively small amount of power or energy available in these applications, the reduced power consumption of a component or product provides advantages or benefits, such as, for example, increased battery life, increased "uptime" or active time of the system, and the like.

Even in a non-portable environment, increased power consumption always results in the generation of a large amount of heat, since electrical energy is not used 100% efficiently. Thus, reducing power consumption of a component or product provides advantages or benefits, such as reducing heat, reducing power costs, and the like.

The statements in this section and any corresponding figure(s) are included as background information material. The materials in this section should not be construed as an admission that these materials constitute prior art to the present patent application.

Disclosure of Invention

In accordance with exemplary embodiments, various apparatus, and associated methods, are contemplated for a multi-channel RF receiver. According to one exemplary embodiment, an apparatus includes an RF receiver for receiving a received signal. The RF receiver includes a plurality of Intermediate Frequency (IF) path circuits that generate a plurality of filtered baseband signals. The plurality of IF path circuits includes a respective plurality of signal detectors that detect receipt of a received signal from a respective plurality of filtered baseband signals. The RF receiver further includes a controller that selects at least one filtered baseband signal, and at least one demodulator that demodulates the selected at least one filtered baseband signal.

According to another exemplary embodiment, an apparatus includes an RF receiver for receiving a received signal. The RF receiver includes a plurality of IF path circuits that generate a plurality of filtered baseband signals. The plurality of IF path circuits includes a respective plurality of signal detectors that detect receipt of a received signal from a respective plurality of filtered baseband signals. The RF receiver further includes a respective plurality of Received Signal Strength Indication (RSSI) detectors that provide a respective plurality of RSSI metrics for the plurality of filtered baseband signals. The RF receiver further includes a controller to select at least one filtered baseband signal based on a respective RSSI metric of the plurality of RSSI metrics, and at least one demodulator to demodulate the selected at least one filtered baseband signal.

According to another exemplary embodiment, a method of receiving a received signal in an RF receiver, the method includes: the method includes generating a plurality of filtered baseband signals using a plurality of Intermediate Frequency (IF) path circuits, and detecting reception of a received signal from a corresponding plurality of filtered baseband signals using a corresponding plurality of signal detectors in the plurality of IF path circuits. The method further includes selecting at least one filtered baseband signal and demodulating the selected at least one filtered baseband signal using at least one demodulator.

Drawings

The drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the application or claimed subject matter. Those of ordinary skill in the art will appreciate that the disclosed concepts lend themselves to other equivalent embodiments. In the drawings, the same numerical designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.

Fig. 1 shows a circuit arrangement of an RF receiver according to an exemplary embodiment.

Fig. 2 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 3 shows a diagram of a frequency response in an RF receiver according to an exemplary embodiment.

Fig. 4 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 5 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 6 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 7 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 8 shows a diagram of a frequency response in an RF receiver according to an exemplary embodiment.

Fig. 9 shows a circuit arrangement of a digital modem of an RF receiver according to an exemplary embodiment.

Fig. 10 illustrates a wireless communication system according to an example embodiment.

Fig. 11 shows a circuit arrangement of an IC comprising an RF receiver according to an exemplary embodiment.

Fig. 12 shows a circuit arrangement of an IC comprising an RF receiver and an RF transmitter according to an exemplary embodiment.

Detailed Description

The present invention relates to communication devices and related methods. More particularly, the present invention relates to apparatus, and an associated method, for a multi-channel receiver having improved power consumption and delay. In particular, an RF Receiver (RX) apparatus and associated method in accordance with the present invention are directed to reducing energy consumption and delay in frequency scanning applications while also seeking to reduce cost and complexity.

Some applications for short-range wireless communication, such as internet of things applications, specify receivers that are capable of evaluating more than one frequency channel or physical layer (PHY) or PHY mode (e.g., Zigbee and bluetooth). In the context of the specification, a frequency channel may be a frequency overlapping or frequency separated channel or frequency range. Examples include asynchronous frequency hopping, network discovery (e.g., passive scanning in IEEE 802.15.4), scanning Automatic Frequency Control (AFC), and Received Signal Strength Indication (RSSI) or energy detection scanning. For simplicity, this specification refers to one or more frequency channels (multi-channel), but as will be appreciated by those of ordinary skill in the art, the disclosed techniques and apparatus may also be applied to multiple PHYs or PHY modes.

Transmissions in such applications, such as the internet of things application described above, may be made on more than one carrier frequency. In addition, more than one modulation scheme or PHY mode may be used. In such applications, a System On Chip (SOC) that includes wireless (receive, transmit, or both) typically has a packet handler and a protocol timer (implemented on hardware, software, firmware, or a combination thereof). In these cases, the RF receiver according to various embodiments avoids duplication of various parts or blocks of the RF receiver, such as packet handlers and protocol timers.

An RF receiver according to various embodiments avoids duplication of several digital processing functions when receiving multiple signals having different corresponding RF frequencies. Digital processing typically requires processing of several layers of the protocol stack (including PHY, Media Access Control (MAC), network layers). Typically, digital processing uses various resources, such as hardware, memory, and software. The RF receiver avoids repetition of several signal processing functions and selects a subset of the plurality of signals for digital processing or concurrent digital processing by searching for characteristics associated with the plurality of signals using the plurality of signal detectors. These characteristics may be contained in the preamble or sync word, or PHY header, or MAC header, or a combination thereof. In some embodiments, the selection is based on a first successful detection (first come first serve) in the plurality of signal detectors, and subsequent detections are ignored when a subset of the plurality of signals are being digitally processed.

The signal detector may include various types of circuitry and detection techniques, as described below. The signal detectors provide signal quality metrics (metrics that may indicate the likelihood that the received signal is a desired signal, e.g., having a frequency deviation within predetermined maximum and minimum deviation threshold limits, and/or correlation with a desired symbol sequence (preamble and or sync word), and/or having a frequency error less than a predetermined frequency offset threshold, and/or a signal-to-noise ratio (SNR) greater than a predetermined signal-to-noise ratio threshold, etc.) for baseband signals they receive from a frequency converter circuit that generates frequency shifted frequency channels (e.g., by mixing) to generate baseband signals. In an exemplary embodiment, the signal detector may constitute any one of a preamble detector, a sync word detector, an RSSI detector (i.e., providing an RSSI measurement for a received or provided signal), a signal arrival detector (e.g., as described in U.S. patent application No. 14/080405 filed on 14/11/2013, U.S. patent No. 10061740 now), a cost function detector (e.g., as described in U.S. patent application No. 16/177373 filed on 31/10/2018), a correlator (e.g., as described in U.S. patent application No. 15/370693 filed on 12/2016, U.S. patent No. 10389482 now), an amplitude detector, a phase detector, a differential phase detector, a phase click detector, a skew detector, or any combination thereof. In general, any circuit or block that detects the presence of a desired or transmitted signal (e.g., an RF signal) in a frequency channel may be used. Additionally, note that in an exemplary embodiment, a frequency scan of the undesired signals may be performed, e.g., an RSSI scan may be performed to determine a "clean" channel. Once a "clean" channel is found, this channel can be used for transmission.

Some conventional approaches have been used in applications such as internet of things applications. One approach is to evaluate a frequency over time. This technique can be a relatively slow process because the receiver may repeat the evaluation multiple times. Furthermore, this solution requires the frequency synthesizer to jump from one frequency to the next, which increases the solution time to complete the evaluation. The longer the evaluation time, the greater the energy consumption.

A second approach is to implement multiple Intermediate Frequency (IF) paths, where each IF is followed by a respective demodulator. This approach has a relatively high power consumption for all demodulators. Furthermore, multiple demodulators are expensive in terms of die area, circuit complexity, etc. Furthermore, the need to run multiple frame controllers in parallel to demodulate multiple parallel channels increases power consumption and cost, making this approach generally impractical for low power, low cost internet of things applications.

An RF receiver according to various embodiments addresses the above-mentioned issues. Other use cases also exist. For example, Z-Wave defines a single frequency at which the radio can receive frames while also scanning other Z-Wave channels. According to various embodiments, a device that supports simultaneous signal detection will allow frames to be received without the additional delay and power consumption associated with a receiver that evaluates one frequency at a time. This property, in turn, allows the transmitting device to use very short preambles and payloads, thereby reducing the energy per Transmission (TX) frame. This approach would enable the use of an energy harvesting source that powers the transmitter.

Another example is asynchronous channel hopping, https:// www.silabs.com/unity/wireless/prepractic/knowledge-base. entry. html/2019/06/20/channel _ scanning-8x31 as described in the following links. The scheme provides that a node should be able to scan several channels for signals with a limited preamble length. The present specification leaves relatively few preamble symbols for each channel to detect the preamble, which limits the time to reliably detect the signal. By receiving multiple channels simultaneously, an RF receiver according to various embodiments allows more time to be available per channel. This time may be used to improve signal quality detection performance (e.g., less false positive detection), or to save power by entering a sleep state or becoming idle (e.g., in a preamble sensing mode).

Yet another example is Bluetooth Low Energy (BLE). For example, BLE specifies a relatively fast channel scan during a search for advertisement packets. An RF receiver according to various embodiments may accommodate BLE fast channel scanning.

In an exemplary embodiment, the RF receiver is capable of detecting signals in multiple channels simultaneously without the overhead of multiple parallel demodulators. The RF receiver accomplishes this by using a relatively simple and low power signal detector (one for each IF path) and at least one demodulator. In most internet of things use cases, one demodulator is sufficient. The signal detector may have much lower complexity and lower power consumption than conventional multi-demodulator solutions, thereby saving power and reducing complexity and/or cost.

In an exemplary embodiment, a multi-frequency channel RF receiver is used to receive at least one received signal in a plurality of frequency channels. This is accomplished by using front-end circuitry in the RF receiving circuitry to frequency shift the channel to produce a plurality of filtered baseband signals. The signal detector is used to simultaneously measure the signal quality of each filtered baseband signal. The controller selects (at least) one of the filtered baseband signals for demodulation by the (at least one) demodulator.

RF receivers according to various embodiments take advantage of low duty cycle activity found in some applications, such as internet of things sensor networks. For example, a door sensor, light switch, motion sensor, or glass break detector may trigger less than 10 times per day. In other words, the RF receiver has a low duty cycle of operation (e.g., is at least partially in an idle or sleep state for a majority of the time). In these low duty cycle use cases, it is more efficient to operate multiple signal detectors than to operate multiple demodulators. In most cases, one demodulator will suffice, thereby reducing costs. For example, die area on a chip or IC may be reduced or saved.

The signal detector may not detect any valid signal in the filtered baseband signal. In this case, the demodulator(s) may remain in an inactive low power consumption state. When the signal detector triggers after a certain time, the controller may wake up the demodulator and provide the demodulator with the associated filtered baseband signal for demodulation. For example, IF signal detector 1 triggers, the controller may provide filtered baseband signal 1 (provided by IF circuit 1) to the demodulator for demodulation.

Where multiple PHYs or multiple PHY modes are used, an RF receiver according to various embodiments may use multiple signal detectors (one per PHY or PHY mode is contemplated) on each filtered baseband signal over multiple frequency channels. If one of the signal detectors triggers, the controller may select a demodulator suitable for demodulating the detected PHY (or PHY mode) and provide the associated filtered baseband signal to that demodulator. In other embodiments, rather than selecting a demodulator, a configurable demodulator may be configured to demodulate a detected PHY or PHY mode. If a certain channel is dedicated to a single PHY or PHY mode (e.g., a priori known per debug), a single signal detector may be used on the associated filtered baseband signal.

In other exemplary embodiments, when multiple signal detectors trigger, the controller may use the soft detection outputs of the signal detectors to select the filtered baseband signal based on maximum likelihood or maximum correlation. In other exemplary embodiments, the RF receiver applies a frequency shift to the multiple frequency channels using an analog down-converter (e.g., Low Noise Amplifier (LNA), in-phase-quadrature (IQ) mixer, Programmable Gain Amplifier (PGA)) to produce a combined analog IF signal.

An IF analog-to-digital converter (IF-ADC) converts the combined analog IF signal to produce a combined digital IF signal. The plurality of digital down converters apply a set of frequency shifts to the combined digital IF signal to produce a plurality of baseband signals. The plurality of channel filters may filter the plurality of baseband signals to produce a plurality of filtered basebands. Note that a single ADC and front-end circuitry (RF mixer, etc.) is used in conjunction with multiple IF path circuits or branches, thereby reducing complexity, cost, and energy or power consumption.

To allow for increased flexibility, in some embodiments, a real IF-ADC (corresponding to a complex number) is used. A real IF-ADC will deliver positive and negative frequencies so that separate channels can be received above and below the Local Oscillator (LO) frequency. The final frequency location of each individual channel is determined by its associated complex mixer and complex IF filter stage. In this case, the IF-ADC bandwidth should be adapted to the highest of the various IF paths (| IFx | +0.5BWx), as described below in connection with fig. 3, where | IFx | is equal to the absolute value of the RF receive frequency minus the local oscillator frequency, and BWx is the appropriate or required bandwidth to receive the desired or transmitted signal (see fig. 3).

In various embodiments, the RF receiver uses multiple digital mixer stages, where each digital mixer is driven by a combined digital IF signal and a Numerically Controlled Oscillator (NCO), each numerically controlled oscillator having its unique NCO frequency. The NCO frequency is equal to the IF frequency of the IF path or stage (IFx). Each digital mixer is followed by a filter stage. As will be appreciated by those of ordinary skill in the art, the filter stages may include decimators, Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, Direct Current (DC) filters, and the like.

In various embodiments, the circuitry or hardware of the RF receiver may be saved or reduced by sharing functionality. For example, the second channel filter may share a multiplier with the first channel filter. As another example, a look-up table (LUT) for sine/cosine generation in the NCO may be shared among the NCO's of the digital mixer.

As described below, an RF receiver according to various embodiments includes image reject calibration (IR-cal) circuitry. The IR-cal stages may be shared or separate IR-cal circuits may be used. As will be appreciated by those of ordinary skill in the art, the IR-cal stage or circuit alone may provide better image rejection due to frequency dependence in IQ errors caused by mismatches in the actual implementation of the various circuits or blocks, such as the mixer, PGA, etc., and/or self-mixing in the mixer circuit. In contrast, sharing the IR-cal circuitry may save hardware, cost, and the like, as described above.

In an exemplary embodiment, the signal detector used in the RF receiver is a relatively simple signal detector. Examples include correlators, cost function detectors, Digital Signal Arrival (DSA) detectors, RSSI detectors, amplitude detectors, phase detectors, differential phase detectors, etc., as will be appreciated by one of ordinary skill in the art.

Fig. 1 shows a circuit arrangement of an RF receiver 5 according to an exemplary embodiment. The RF receiver 5 is coupled to an antenna 10, and the RF receiver 5 receives RF signals through the antenna 10. The received RF signal is fed to the LNA 15, and the LNA 15 amplifies the received RF signal and provides the amplified RF signal to the mixer 20 (labeled "RFMIX"). Mixer 20 mixes the amplified RF signal with an LO signal provided by LO 25 to produce a mixed or downconverted signal. The mixed signal is provided to the PGA 30. PGA30 amplifies the mixed signal using a programmable gain to produce an amplified mixed signal.

The ADC 35 receives the amplified mixed signal (analog signal) and converts it into a digital mixed signal. The ADC 35 provides the digital mixed signal to the digital modem 40, and the digital modem 40 may filter, decode, demodulate, etc., the digital mixed signal to extract the data and provide the data at its output. Note that the digital modem 40 may perform various functions such as channel filtering, signal detection, and modulation, as described below. Further, note that although in some embodiments the transmit (modulation) function may be omitted, for simplicity of representation, a short-word digital modem is still used.

In the exemplary embodiment, the various IF branches or circuits in digital modem 40 share front-end circuitry, such as LNA 15, mixer 20, LO 25, PGA30, and ADC 35, as described above. The following description describes various digital modems 40 according to an exemplary embodiment. Note that although the figures and accompanying description show two IF paths or circuits for simplicity and clarity of presentation, in various embodiments, more than two IF paths or circuits may be used, as will be appreciated by those of ordinary skill in the art.

Fig. 2 shows a circuit arrangement of a digital modem 40 of an RF receiver according to an exemplary embodiment. The output signal of ADC 35 (see fig. 1) is provided to decimator 55 (labeled "DEC 0"), decimator 55 decimates the signal and provides a decimated signal at its output. The output signal of the decimator 55 is fed to the input of a DC compensation circuit 60 (labeled "DC-comp"), which DC compensation circuit 60 removes or attenuates or compensates for any DC component present in the decimated signal. The output of the DC compensation circuit 60 drives two IF path circuits, as described below.

As will be appreciated by those of ordinary skill in the art, in the first IF path circuit, the output of the DC compensation circuit 60 drives the input of an IR calibration circuit 65 (labeled "IR-cal _ a"), which IR calibration circuit 65 performs IR calibration. The output of IR calibration circuit 65 drives an input of a digital mixer 75, which digital mixer 75 mixes the output of IR calibration circuit 65 with the output signal of NCO 70 (labeled "NCO a") to generate a mixed digital signal at the output of digital mixer 75. A decimator 80 (labeled "DEC 1 a") receives and decimates the digital mixed signal and provides the resulting decimated signal to a channel filter 85 (labeled "CHFa"). The channel filter 85 filters (e.g., low-pass filters) the decimated signal and provides the resulting filtered signal to the DSA 90.

DSA 90 serves as a signal detector. Thus, the DSA 90 detects (or looks for or checks or waits for) the arrival of the desired or designated signal. If so detected, DSA 90 provides a signal to controller 105 to indicate signal arrival. In response, the controller 105 provides a select signal to the Multiplexer (MUX)95 to cause the MUX 95 to provide the output of the channel filter 85 to the Digital Signal Processor (DSP)100, or generally to one or more demodulators.

Thus, in various embodiments, reference to DSP 100 includes the use of one or more demodulators. The controller 105 also programs or configures or sets the DSP 100 for the detected signal type, PHY mode, etc. In response, the DSP 100 extracts data from packets in the output signal of the channel filter 85 that triggers the DSA 90 and provides the data at an output.

The second IF path circuit is similar to the first IF path circuit and operates in a similar manner. The various blocks in the second IF path circuit use the notation "b" in their label, rather than "a" in the first IF path circuit (e.g., the first IF path is "IR-cal _ b" rather than "IR-cal _ a". accordingly, the second IF path circuit includes an IR calibration circuit 135 (labeled "IR-cal _ b"), an NCO 130 (labeled "NCO b"), a decimator 120 (labeled "DEC 1 b"), a channel filter 115 (labeled "CHFb"), and a DSA 110 (labeled "DSAb").

IF the DSA 110 detects the arrival of the desired signal or signals through the second IF path circuitry, i.e., in the output signal of the channel filter 115, the DSA 110 provides an indication of the arrival of the signals to the controller 105. In response, the controller 105 provides a select signal to the MUX 95 to cause the MUX 95 to provide the output of the channel filter 110 to the DSP 100.

The controller 105 also programs or configures or sets the DSP 100 for the detected signal type, PHY mode, etc. In response, the DSP 100 extracts data from packets in the output signal of the channel filter 115 that triggers the DSA 110 and provides the data at an output. Thus, the RF receiver is able to detect multiple PHYs or PHY modes or signals in multiple frequency channels simultaneously.

Note that the NCO of the first and second IF path circuits have output frequencies corresponding to the two channels on which the respective IF path circuits operate. In an exemplary embodiment, controller 105 may set, program, or configure the output frequencies of NCO 70 and NCO 130. It is further noted that, as noted above, in some embodiments, more than two IF path circuits may be used, depending on the number of channels desired to be scanned simultaneously. Additionally, note that in some embodiments, DSA 90 and DSA 110 may be programmed to receive the same PHY or PHY mode, but at different frequencies, as needed.

Fig. 3 shows a diagram of a frequency response in an RF receiver according to an exemplary embodiment. In particular, the figure shows the frequency response 150 of decimator 55, channel 155 (formed by the frequency responses of digital mixer 75, decimator 80, and channel filter 85) (labeled "BWa"). Channel 155 is on frequency (F)_LO-F_NCOa) Is a center, wherein F_LOAnd F_NCOaRepresenting the output frequencies of LO 25 and NCO 70, respectively.

Similarly, fig. 3 shows a channel 160 (formed by the frequency response of the digital mixer 125, the decimator 120, and the channel filter 115) (labeled "BWb"). Channel 160 is at frequency (F)_LO+F_NCOb) Is a center, wherein F_LOAnd F_NCO0Representing the output frequencies of LO 25 and NCO 130, respectively. Note that the figure also shows the IF frequencies of the two IF path circuits. They are respectively represented as IF_aAnd IF_b。

Fig. 4 shows a circuit arrangement of the digital modem 40 of the RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 4 is similar to that in fig. 2, except that the output of channel filter 85 drives the inputs of random access memory 180 (labeled "RAMa") and correlator 185 (labeled "COR a") and the output of channel filter 115 drives the inputs of RAM195 (labeled "RAMb") and correlator 190 (labeled "COR b"). RAM1 and RAM2 represent memory that DSP 100 may use to perform its functions (e.g., demodulation), e.g., as a scratch pad or the like.

The samples (IQ or phase or amplitude or combination) are stored in a circular buffer formed by RAM 180 and RAM 195. In this circuit, the RF receiver, correlator 190, can detect the correlation peak when processing the sync (sync) word for sync word a. DSP 100 may then use RAM195 to "rewind" the data through the data to the sync word and apply Forward Error Correction (FEC) decoding followed by sync word demodulation (e.g., as in the PHY or PHY mode of BLE encoding).

Note that a combination of the detector circuits shown in fig. 2 and fig. 4 may be used. Thus, in some embodiments, one or more IF paths use DSA(s), while one or more IF paths use a combination of RAM(s) and correlator(s). Furthermore, instead of using RAM 180 and RAM195, a single RAM with dual ports may be used in some embodiments, in which case one port receives the output of channel filter 85 and the other port receives the output of channel filter 115.

Fig. 5 shows a circuit arrangement of the digital modem 40 of the RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 5 is similar to that in fig. 4, except that the output of channel filter 85 does not drive RAM 180 and correlator 185 but instead drives the input of IF Processor circuit 205 (labeled "IF Processor _ a"). The output of IF processor 205 drives the inputs of RAM 180 and correlator 185. Similarly, the output of channel filter 115 does not drive RAM 190 and correlator 190, but instead drives the input of IF Processor circuit 210 (labeled "IF Processor _ b"). The output of IF processor 210 drives the inputs of RAM195 and correlator 190.

In an exemplary embodiment, IF

processors

205 and 210 may each be a coordinate rotation digital computer (CORDIC) or any other cartesian-polar transformation circuit. Each of

IF processors

205 and 210 may also be constructed using CORDIC followed by a phase differentiator, where the differentiation may be oversampled (multiple differentiations per symbol) or one differentiation per symbol may be used. IF

processors

205 and 210 may also provide amplitude or log amplitude for Amplitude Shift Keying (ASK) or on-off keying (OOK) applications.

In addition, IF

processors

205 and 210 may be extended with a clipper to limit the original amplitude, phase or differential phase to 1 or 0 values. Furthermore, a combination of the detector circuits shown in fig. 2 and 4 may be used. Thus, in some embodiments, one or more IF paths may use an IF processor, while one or more IF paths may use any of the signal detectors described above (e.g., DSA).

Fig. 6 shows a circuit arrangement of the digital modem 40 of the RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 6 is similar to that in fig. 2, except that the output of channel filter 85 drives the input of RSSI circuit 220 (labeled "RSSI a") and the output of channel filter 115 drives the input of RSSI circuit 225 (labeled "RSSI b"). The RSSI circuit in each IP path circuit extracts the signal level (RSSI, amplitude, Energy Detection (ED) or RMS level) from the respective channel filter output.

By using multiple IF path circuits, the signal level can be evaluated on multiple channels simultaneously, thereby speeding up the RSSI scan. The signal levels are transmitted to the controller 105 for processing. The controller 105 then controls the MUX 95 as described above in connection with fig. 2. In some embodiments, the controller 105 may include a memory that stores signal levels. Applications of the embodiment of fig. 6 include: frequency agile (link) signal level sweep, listen before talk, and fast spectrum analyzer.

Fig. 7 shows a circuit arrangement of the digital modem 40 of the RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 7 is similar to the embodiment shown in fig. 2, except that in the embodiment of fig. 7, the controller 105 drives the RF synthesizer. IF the number of frequencies that should be scanned or desired to be scanned is greater than the number of IF path circuits in the RF receiver, the RF synthesizer changes the output frequency. For example, IF the RF receiver has two IF path circuits and 20 channels are required to perform RSSI evaluation, the RF synthesizer should be tuned on 10 frequencies. As an example, fig. 8 shows 6 channels evaluated using three RF synthesizer (LO) frequencies.

Note that the receiver in fig. 7 may also use any other detection architectures such as those described above (e.g., DSA, IF processor, etc.). In embodiments where two DSAs or correlators are used and no signal is detected by either of them for a certain time window, the controller will change the LO frequency to the next frequency value to be evaluated again. Alternatively, the controller may change the frequency of the NCO. In such embodiments, scanning may be suspended whenever either the DSA or the correlator triggers (i.e., a signal is detected).

The first triggered DSA or correlator causes the controller 105 to select MUX 95 to pass the relevant channel filter output to DSP 100 and configure DSP 100 according to the detected signal, PHY or PHY mode as described above. The DSP 100 extracts data from the packet at the DSA trigger. In the case where two DSAs or correlators trigger simultaneously, the highest correlation result may be used to select the channel from which DSP 100 extracts data. Alternatively, a priority scheme may be used such that whenever two correlators or DSAs trigger simultaneously, a particular PHY will get priority to be demodulated first. In addition, DSA or TRECS (timing recovery system) can also extract residual frequency offset by adjusting LO or NCO frequency to improve alignment.

Once the modulation is aligned in one channel filter, the bandwidth of the channel filter can be reduced to obtain sensitivity, reduce noise, and improve channel selectivity. As will be appreciated by those of ordinary skill in the art, adding more IF path circuitry (while receiving channels) speeds up the scanning AFC system.

Fig. 8 shows a graph of frequency response in an RF receiver according to an exemplary embodiment using two IF path circuits. The LO may be from F when no valid signal is received_LO2Scan to F_LO3From F_LO3Scan to F_LO1From F_LO1Scan to F_LO2And the like. When in channel F_LO3+F_NCO2The LO sweep will be at F when a valid signal is received_LO3Stops and DSP 100 will begin demodulating signals in the second IF path circuit. As described above, the scanning time can be further shortened by using more IF path circuits.

Fig. 9 shows a circuit arrangement of the digital modem 40 of the RF receiver according to an exemplary embodiment. The circuit arrangement in fig. 9 is similar to the circuit arrangement in fig. 5 in that IF

processors

205 and 210 are used, as described above. In contrast to the embodiment in fig. 5, in the embodiment of fig. 9, the output of channel filter 85 drives the inputs of RAM 270 (labeled "RAM a") and TRECS 265 (labeled "TRECS a"). Similarly, the output of channel filter 115 drives the input of RAM 275 (labeled "RAM b") and TRECS 280 (labeled "TRECS b").

Each of

TRECS

265 and 280 finds the timing (on the preamble, sync word, or a combination of both). When the timing is found in the IF path circuit, the corresponding TRECS also has an estimate of the frequency shift. The frequency offset estimate may be provided to each NCO in the IF path circuitry to align the modulated spectrum at the center of the channel filter bandwidth. The output of TRECS 265 forms an AFC loop in the first IF-path circuit by providing a frequency-offset signal to NCO 70.

Similarly, the output of TRECS 280 forms an AFC loop in the second IF-path circuit by providing a frequency-offset signal to NCO 130. As described above, the frequency offset signal is used to fine tune or adjust or program or set or configure the respective frequencies of NCO 70 and NCO 130 to align the modulated signal at the center of the channel filter bandwidth.

Receivers according to exemplary embodiments may be used in various communication arrangements, systems, subsystems, networks, etc., as desired. Fig. 10 shows a system 500 for radio communication according to an example embodiment. As mentioned above, the system comprises an RF receiver 5.

System 500 includes a transmitter 515 coupled to antenna 10A. Via antenna 10A, transmitter 515 transmits RF signals. The receiver 5 may receive the RF signal via the antenna 10B. Additionally or alternatively, transceiver 520A and/or transceiver 520B may receive the transmitted RF signals (via receiver 5).

In addition to receiving capabilities, transceiver 520A and transceiver 520B may also transmit RF signals. The receiver 5 may receive the transmitted RF signal in a stand-alone receiver or through a receiver circuit of a non-transmitting transceiver.

Other systems or subsystems having varying configurations and/or capabilities are also contemplated. For example, in some example embodiments, two or more transceivers (e.g., transceiver 520A and transceiver 520B) may form a network, such as an ad-hoc network. As another example, in some demonstrative embodiments,

transceivers

520A and 520B may form part of a network, e.g., along with transmitter 515.

An RF receiver, such as RF receiver 5 described above, may be used in various circuits, blocks, subsystems and/or systems. For example, in some embodiments, such an RF receiver may be integrated in an IC such as a microcontroller unit (MCU). Fig. 11 shows a block diagram of IC550 according to an example embodiment. Fig. 12 is similar to the embodiment of fig. 11 and shows an IC550, which IC550 comprises an RF transmitter 515 in addition to the RF receiver 5. Thus, the embodiment in fig. 12 has RF transceiver capability.

Referring to fig. 11, IC550 constitutes or includes an MCU. IC550 includes a plurality of blocks (e.g., processor(s) 565, data converter 605, I/O circuitry 585, etc.) that communicate with each other using link 560. In an exemplary embodiment, link 560 may constitute a coupling mechanism, such as a bus, a set of conductors, or semiconductor elements (e.g., traces, devices, etc.) for communicating information (e.g., data, commands, status information, etc.).

IC550 may include a link 560 coupled to one or more processors 565, clock circuits 575, and power management circuits or Power Management Units (PMUs) 580. In some embodiments, processor(s) 565 may include circuitry or blocks to provide information processing (or data processing or computation) functions, such as a Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), and so forth. Additionally or alternatively, in some embodiments, processor(s) 565 may include one or more DSPs. The DSP may provide various signal processing functions, such as arithmetic functions, filtering, delay blocks, etc., as desired.

Clock circuit 575 may generate one or more clock signals that facilitate or control the timing of the operation of one or more blocks in IC 550. Clock circuit 575 may also control the timing of operations using link 560 as desired. In some embodiments, clock circuit 575 may provide one or more clock signals to other blocks in IC550 via link 560.

In some embodiments, the PMU 580 may reduce the clock speed of a device (e.g., IC 550), shut down the clock, reduce power, shut down the power supply, disable (or power down or placed in lower power consumption or sleep or inactive or idle state), enable (or power up or placed in higher power consumption or normal or active state), or any combination of the preceding, for a portion of a circuit or all components of a circuit (e.g., one or more blocks in the IC 550). Further, in response to a transition from an inactive state to an active state (including, but not limited to, when processor(s) 565 transition from a low power consumption or idle or sleep state to a normal operating state), PMU 580 may turn on a clock, increase a clock rate, turn on power, increase power, or any combination of the preceding.

Link 560 may be coupled to one or more circuits 600 through a serial interface 595. One or more circuits or blocks coupled to link 560 may communicate with circuit 600 through serial interface 595. The circuit 600 may communicate using one or more serial protocols, as will be appreciated by those of ordinary skill in the art, e.g., SMBUS, I²C, SPI, etc.

Link 560 may be coupled to one or more peripheral devices 590 through I/O circuitry 585. Through the I/O circuitry 585, one or more peripheral devices 590 may be coupled to the link 560 and may thus communicate with one or more blocks coupled to the link 560 (e.g., processor(s) 565, storage circuitry 625, etc.).

In an exemplary embodiment, peripheral devices 590 may include various circuits, blocks, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, sensors, etc.). Note that in some embodiments, some of peripherals 590 may be external to IC 550. Examples include a keypad, a speaker, etc.

In some embodiments, I/O circuitry 585 may be bypassed with respect to some peripherals. In such embodiments, some peripheral devices 590 may couple to and communicate with link 560 without the use of I/O circuitry 585. In some embodiments, such peripheral devices may be external to IC550, as described above.

Link 560 may be coupled to analog circuitry 620 via data converter(s) 605. Data converter(s) 605 may include one or more ADCs 605A and/or one or more DACs 605B.

ADC(s) 605A receives analog signal(s) from analog circuitry 620 and converts the analog signal(s) to a digital format, which communicates with one or more blocks coupled to link 560. Instead, DAC(s) 605B receive digital signal(s) from one or more blocks coupled to link 560 and convert the digital signal(s) to analog format, which communicates with analog circuitry 620.

Analog circuitry 620 may include a variety of circuitry that provides and/or receives analog signals. Examples include sensors, transducers, and the like, as will be understood by one of ordinary skill in the art. In some embodiments, analog circuitry 620 may communicate with circuitry external to IC550 as needed to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks.

Control circuitry 570 is coupled to link 560. Control circuitry 570 may, therefore, communicate with various modules coupled to link 560 and/or control the operation of various modules coupled to link 560 by providing control information or signals. In some embodiments, control circuitry 570 also receives status information or signals from various blocks coupled to link 560. Additionally, in some embodiments, control circuitry 570 facilitates (or controls or oversees) communication or cooperation between the various blocks coupled to link 560.

In some embodiments, the control circuit 570 may initiate or respond to a reset operation or signal. As will be appreciated by one of ordinary skill in the art, a reset operation may result in a reset of one or more blocks of link 560, etc., coupled to IC 550. For example, control circuitry 570 may reset PMU 580 and circuitry, such as RF receiver 5, or various blocks, circuits, or components thereof, to an initial or known state.

In an exemplary embodiment, the control circuit 570 may include various types of circuits and circuit blocks. In some embodiments, control circuitry 570 may include logic circuitry, a Finite State Machine (FSM), or other circuitry to perform operations such as those described above.

Communication circuit 640 is coupled to link 560 and is also coupled to a circuit or block (not shown) external to IC 550. Various blocks coupled to link 560 (or IC550 in general) by communication circuit 640 may communicate with external circuits or blocks (not shown) via one or more communication protocols. Examples of communications include USB, ethernet, etc. As will be appreciated by one of ordinary skill in the art, in the exemplary embodiment, other communication protocols may be used, depending on factors such as the design or performance specifications of a given application.

Memory circuit 625 is coupled to link 560 as previously described. Thus, the storage circuitry 625 may communicate with one or more blocks coupled to the link 560, e.g., the processor(s) 565, the control circuitry 570, the I/O circuitry 585, etc.

As will be appreciated by those of ordinary skill in the art, storage circuitry 625 provides storage for various information or data in IC550, such as operands, flags, data, instructions, and so forth. The memory circuit 625 may support various protocols such as Double Data Rate (DDR), DDR2, DDR3, DDR4, etc., as desired.

In some embodiments, memory read and/or write operations of storage circuit 625 involve the use of one or more blocks in IC550, such as processor(s) 565. A Direct Memory Access (DMA) arrangement (not shown) allows for improved performance of memory operations in certain situations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between a source or destination of data and memory circuit 625, rather than through a block such as processor(s) 565.

The memory circuit 625 may include various memory circuits or blocks. In the illustrated embodiment, the storage circuit 625 includes non-volatile (NV) memory 635. Additionally, or alternatively, the storage circuit 625 may include volatile memory (not shown), such as Random Access Memory (RAM). NV memory 635 may be used to store information related to the performance, control, or configuration of one or more blocks in IC 550. For example, the NV memory 635 may store configuration information related to the operation of the RF receiver 5, such as configuration information for various blocks, circuits, components, etc., of the RF receiver 5.

Referring to the drawings, those skilled in the art will note that the various blocks shown may primarily describe conceptual functions and signal flow. An actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the specific circuitry shown. For example, the functions of the various blocks may be combined into one circuit block as desired. Furthermore, the functionality of individual blocks within several circuit blocks may be implemented as desired. The choice of circuit implementation depends on various factors such as the particular design and performance specifications of a given implementation. Other modifications and alternative embodiments in addition to those in the present invention will be apparent to those of ordinary skill in the art. Accordingly, this disclosure teaches those skilled in the art the manner of carrying out the disclosed concepts in accordance with the exemplary embodiments and is to be construed as illustrative only. As will be appreciated by those of ordinary skill in the art, the drawings may or may not be to scale, where appropriate.

The specific forms and embodiments shown and described constitute only exemplary embodiments. Various changes in the shape, size and arrangement of parts may be made by those skilled in the art without departing from the scope of the invention. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the invention.

Claims

1. An apparatus, comprising:

radio Frequency (RF) receiver for receiving a received signal, the RF receiver comprising:

a plurality of intermediate frequency path circuits (IF path circuits) that generate a plurality of filtered baseband signals, the plurality of IF path circuits including a corresponding plurality of signal detectors that detect receipt of received signals from the corresponding plurality of filtered baseband signals;

a controller that selects at least one filtered baseband signal; and

at least one demodulator that demodulates the selected at least one filtered baseband signal.

2. The apparatus of claim 1, wherein the RF receiver comprises a multichannel receiver.

3. The apparatus of claim 2, wherein the RF receiver receives the received signal in any one of a plurality of frequency channels.

4. The apparatus of claim 1, further comprising a receive path circuit to receive an RF signal and to derive a digital signal, wherein the receive path circuit provides the digital signal to the plurality of IF path circuits.

5. The apparatus of claim 4, wherein the receive path circuitry comprises:

a low noise amplifier that amplifies the RF signal to generate a first amplified signal;

a mixer that mixes the first amplified signal with a Local Oscillator (LO) signal to generate a mixed signal;

a Programmable Gain Amplifier (PGA) that amplifies the mixed signal to generate a second amplified signal; and

an analog-to-digital converter that converts the second amplified signal to the digital signal and provides the digital signal to the plurality of IF path circuits.

6. The apparatus of claim 4, wherein the plurality of IF path circuits apply a corresponding plurality of frequency shifts to a plurality of frequency channels comprising the receive signal to generate a corresponding plurality of baseband signals.

7. The apparatus of claim 6, wherein the plurality of IF path circuits filter the plurality of baseband signals to generate the plurality of filtered baseband signals.

8. The apparatus of claim 1, wherein the plurality of detectors comprise a preamble detector, a sync word detector, an RSSI detector, a signal arrival detector, a cost function detector, a correlator, an amplitude detector, a phase detector, a differential phase detector, a phase click detector, a skew detector, or a combination of any of the foregoing.

9. The apparatus of claim 1, wherein the plurality of signal detectors in the plurality of IF path circuits simultaneously detect receipt of the receive signal.

10. An apparatus, comprising:

a multi-channel Radio Frequency (RF) receiver for receiving at least one received signal in any one of a plurality of frequency channels, said multi-channel RF receiver comprising:

a plurality of intermediate frequency path circuits (IF path circuits) that generate a plurality of filtered baseband signals, the plurality of IF path circuits including a respective plurality of received signal strength indication detectors (RSSI detectors) that provide a respective plurality of RSSI metrics for the plurality of filtered baseband signals;

a controller that selects at least one filtered baseband signal based on a respective RSSI metric of the plurality of RSSI metrics; and

11. The apparatus of claim 10, further comprising receive path circuitry to receive an RF signal comprising the plurality of channels and to derive a digital signal, wherein the receive path circuitry provides the digital signal to the plurality of IF path circuitry.

12. The apparatus of claim 11, wherein the receive path circuitry comprises:

13. The apparatus of claim 11, wherein each IF path circuit in the plurality of IF path circuits comprises:

an image reject calibration circuit that processes a signal derived from the digital signal and provides a first output signal;

a digital mixer to mix the first output signal with an output signal of a digitally controlled oscillator to generate a second output signal;

a decimator that decimates the second output signal to generate a baseband signal;

a channel filter that filters the baseband signals to generate respective filtered baseband signals for respective IF path circuits.

14. The apparatus of claim 11, further comprising a Multiplexer (MUX) that selects the at least one filtered baseband signal, wherein the controller provides a select signal to the MUX.

15. A method of receiving a received signal in a Radio Frequency (RF) receiver, the method comprising:

using a plurality of intermediate frequency path circuits, i.e., a plurality of IF path circuits, to generate a plurality of filtered baseband signals;

using a respective plurality of signal detectors in the plurality of IF path circuits to detect receipt of the receive signal from the respective plurality of filtered baseband signals;

selecting at least one filtered baseband signal; and

using at least one demodulator to demodulate the selected at least one filtered baseband signal.

16. The method of claim 15, wherein the RF receiver comprises a multi-channel receiver, and wherein the RF receiver receives the received signal in any one of a plurality of frequency channels.

17. The method of claim 15, further comprising:

deriving a digital signal from the received RF signal; and

providing the digital signal to the plurality of IF path circuits.

18. The method of claim 17, further comprising:

applying, using the plurality of IF path circuits, a corresponding plurality of frequency shifts to a plurality of frequency channels comprising the received signal to generate a corresponding plurality of baseband signals; and

filtering the plurality of baseband signals to generate the plurality of filtered baseband signals.

19. The method of claim 15, wherein the plurality of detectors comprise a preamble detector, a sync word detector, an RSSI detector, a signal arrival detector, a cost function detector, a correlator, an amplitude detector, a phase detector, a differential phase detector, a phase click detector, a skew detector, or a combination of any of the foregoing.

20. The method of claim 15, wherein the plurality of signal detectors in the plurality of IF path circuits simultaneously detect receipt of the receive signal.