CN114696835A - Manchester coding signal bit synchronization method, device and storage medium - Google Patents
Manchester coding signal bit synchronization method, device and storage medium Download PDFInfo
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Abstract
The invention carries out oversampling on two continuous digital bits and estimates the initial time of the digital bits by combining the characteristic of Manchester coding, thereby giving the synchronous adjustment direction of the digital bits, and finally achieving the synchronization of the sampling clock and the digital bits under the condition of gradually reducing the adjustment step length. Thus, under the condition that the sampling clock is synchronous with the digital bit, the logic level of the signal can be reduced by counting the high-low level pulse after oversampling for the whole digital bit instead of a part of one digital bit, thereby improving the receiving sensitivity.
Description
Technical Field
The present invention relates to the field of digital communication technologies, and in particular, to a manchester encoded signal bit synchronization method, apparatus, device, and computer storage medium.
Background
In digital communication, after a baseband signal is amplified and shaped, although the signal amplitude reaches the full power swing, the signal waveform may be subjected to glitch or multiple inversions at the high-low level cut-off point because noise or interference is also amplified, as shown in fig. 1. These two phenomena are severe near the receiver sensitivity, and these glitches and multiple flips affect the bit synchronization of the receiver digital signal. When the receiving circuit adopts an edge identification method to carry out bit synchronization, in a digital circuit of the receiver, one form adopts an edge triggering form, a burr has an edge, and thus, after the circuit is triggered, a false edge moment can be generated; if there are multiple flips, it indicates that the noise or interference near the edge is large, and the first flip may be earlier than the true edge timing, resulting in the time length change of the two bits before and after no longer being the desired 50% duty cycle.
A common method for solving the glitch and multiple flips problem is to deduce that the signal in a certain time interval should be high level or low level according to the count of high and low pulses in the time interval, so as to summarize the glitch or multiple flips in the time interval into a single level, thereby eliminating the effect of the glitch and multiple flips on the subsequent digital signal processing. For example, in a certain time interval, the signal to be processed is oversampled, and the high level of the sampling is recorded as logic 1, and the low level of the sampling is recorded as logic 0. After the time interval is over, the number of points sampled to be logic 1 is N1The number of points sampled as logic 0 is N0. If N is present1>N0The signal during this time is classified as high, otherwise as low.
If the original signal is Manchester encoded, its pulse width has only two values, and one is twice the other. After the level determination is performed on the time interval, it can be determined whether the pulse width of the formed signal is consistent with the width required by the original signal. If so, the resulting signal is a valid Manchester encoded signal; otherwise the resulting signal is an erroneous signal, as shown in fig. 2. If the formed signal is valid, it can be sent to the next module for further processing. The disadvantage of this method is that the length of the selected time interval is directly equal to the error of the digital bit start time, and the duty ratio of the processed signal increases with the increase of the time interval in consideration of the phenomenon of multiple inversions near the rising edge and the falling edge of the signal. Another point is that when a small segment of the signal is corrupted by a glitch or multiple flips, the entire digital bit is determined to be corrupted.
The key to this approach is that no bit synchronization of the digital signal is performed, so that no statistical evaluation can be performed over the entire digital bit, evaluating whether the digital bit is a logic 1 or a logic 0. This would give the correct logic level by making a statistical estimate over the entire digital bit, which would be judged as erroneous, with the immediate consequence of reduced receive sensitivity.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the problems of logic level judgment error and low receiving sensitivity caused by no bit synchronization of digital signals in the prior art.
In order to solve the above technical problem, the present invention provides a manchester encoded signal bit synchronization method, apparatus, device and computer storage medium, comprising:
counting within two continuous data bit widths, and listing all digital signal combinations conforming to the Manchester encoding rule;
analyzing counting results of a logic 1 point number and a logic 0 point number in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling initial point relative positions, and summarizing the counting results to obtain a plurality of counting result conditional expressions;
listing counting result conditional expressions in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling starting point relative positions, and combining the combinations with consistent results to obtain the relative relation between the sampling starting point relative positions and the counting results;
obtaining a judgment process of the relative position of the sampling starting point according to the relative relation;
judging whether the relative position of the sampling starting point of the digital signal to be processed has the phenomenon of repeated jump in advance and behind by utilizing the judging process according to the counting result expression of the digital signal to be processed in the bit width of two continuous data;
if the sampling starting point is close to the boundary, adjusting the sampling starting point by half bit width to reach the vicinity of synchronization;
and if the phenomenon of repeated jump between the leading and the lagging does not occur, adjusting the sampling starting point to reach the vicinity of synchronization by utilizing a dichotomy.
Preferably, after the initial synchronization of the sampling start point and the digital bit edge is completed, the sampling start point is continuously fine-tuned so that the probability of the occurrence of the lead and lag is respectively half to further optimize the relative position of the sampling start point.
Preferably, the analyzing the counting results of the number of logic 1 points and the number of logic 0 points in the first bit width and the second bit width of each combination under the condition that the relative position of the sampling starting point is advanced and delayed comprises the following steps of:
sampling digital signals in a period of time, counting the number of logic 1 points and the number of logic 0 points in each counting interval by taking one data bit width as the counting interval, and selecting the maximum value N of the number of the logic 1 points1-maxAnd a logical 0 point number maximum N0-max。
Preferably, the analyzing the counting results of the number of logic 1 points and the number of logic 0 points in the first bit width and the second bit width of each combination under the condition that the relative position of the sampling starting point is advanced and delayed, and inducing the counting results to obtain a plurality of counting result conditional expressions includes:
when the time period with logic 1 is equal to the time length of one bit width, the counting result is summarized into a first conditional expression
Time period when logic is 0, etcWhen the time length of one bit width is long, the counting result is summarized into a second conditional expression
When the time period with the logic 1 is greater than the time length of half bit width, the counting result is summarized as a third conditional expression:
when the time period of the logic 0 is longer than the time length of half bit width, the counting result is summarized as a fourth conditional expression:
when the time period of logic 1 is the same as the time period of logic 0 in the two data bit widths, the counting result is summarized as the total counting result of the two bit widths:
wherein N is1And N0Representing a number of logical 1 points and a number of logical 0 points in one bit width,
representing all number of sample points within bit width, N1,bit1And N0,bit1Representing the number of logical 1 points and logical 0 points, N, within the first bit width1,bit2And N0,bit2Indicating the number of logic 1 points and the number of logic 0 points within the second bit width.
Preferably, the determining process includes:
when the counting result in two continuous bit widths is expressed as
If so, the inference result is invalid, otherwise, the judgment is madeThe process is continued;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the temperature of the water is higher than the set temperature,when the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is less than the threshold value, the judgment result is advanced, and when the second bit width counting result expression is
The determination result is hysteresis.
Preferably, the shifting the sampling start point, and the determining whether the sampling start point is near the boundary or near the synchronization by the shifted relative position includes:
shifting the sampling starting point by a quarter of the number of sampling points to the left, if the relative position becomes lag, the sampling starting point is near the boundary, otherwise, the sampling starting point is near the synchronization;
shifting the sampling start point by a quarter number of sampling points to the right, if the relative position becomes advanced, the sampling start point is near the boundary, otherwise near the synchronization.
Preferably, the adjusting the sampling start point to be near synchronization by using bisection includes:
a. marking the position of the current sampling start point as delta Na＝0；
b. Determining whether the current sample start point is a leading or lagging data bit edge;
c. if the sampling is lagging, the current sampling starting point is made to be far away from the reference position
If the current sampling starting point is an advanced one, the current sampling starting point is enabled to be a remote parameterExamination position
d. Calculating the relative position of the next sampling starting point according to the far-end reference position of the current sampling starting point
e. Determining whether the next sample start point relative position is an early or late data bit edge;
f. if the relative position of the next sampling starting point is the same as the relative position of the last sampling starting point, updating the relative position of the current sampling starting point to be the relative position delta N of the next sampling starting pointa＝ΔNm(ii) a Otherwise, updating the far-end reference position of the current sampling starting point to be the relative position delta N of the next sampling starting pointb＝ΔNm；
g. Repeating steps d), e) and f) until | Δ Na-ΔNb| is less than a given threshold;
h. at this time, the relative position of the final sampling start point is
i. Adjusting relative position delta N according to sampling starting pointadjust＝-ΔNmThe sampling start point position is adjusted to achieve bit synchronization.
The invention also provides a device for synchronizing Manchester coding signal bits, which comprises:
the combination enumerating module is used for counting within two continuous data bit widths and enumerating all digital signal combinations conforming to the Manchester encoding rule;
the counting result induction module is used for analyzing the counting results of the number of the logic 1 points and the number of the logic 0 points in the first bit width and the second bit width under the two conditions of leading and lagging of the relative position of the sampling starting point of each combination, and inducing the counting results to obtain a plurality of counting result conditional expressions;
the relative relation building module is used for listing counting result conditional expressions in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling starting point relative positions, and combining the combinations with consistent results to obtain the relative relation between the sampling starting point relative positions and the counting results;
the judgment flow construction module is used for obtaining a judgment flow of the relative position of the sampling starting point according to the relative relation;
the repeated jump judging module is used for judging whether the relative position of the sampling starting point of the digital signal to be processed has the phenomenon of repeated jump in advance and behind according to the counting result expression of the digital signal to be processed in the bit width of two continuous data by utilizing the judging flow;
the boundary sampling starting point synchronization module is used for shifting the sampling starting point if the phenomenon of repeated jump of leading and lagging occurs, judging whether the sampling starting point is near the boundary or near the synchronization according to the relative position after the shifting, and if the sampling starting point is near the boundary, adjusting the sampling starting point by half bit width so as to reach the near synchronization;
and the dichotomy synchronization module is used for adjusting the sampling starting point to reach the vicinity of synchronization by using a dichotomy if the phenomenon of repeated jump in advance and behind does not occur.
The invention also provides a device for synchronizing Manchester coding signal bits, which comprises:
a memory for storing a computer program; and the processor is used for realizing the step of bit synchronization of the Manchester coded signal when the computer program is executed.
The present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method of bit synchronization of a manchester encoded signal as described above.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention provides a Manchester coding signal bit synchronization method which can solve the defects of the prior art. Counting in two continuous data bit widths, listing all digital signal combinations conforming to the Manchester coding rule, analyzing the counting results in the first bit width and the second bit width under the two conditions of leading and lagging of each combination, summarizing the counting results to obtain a plurality of counting result conditional expressions, summarizing and listing a relative relation table, and generating a judgment flow chart; therefore, the judgment flow chart can be used for deducing whether the sampling starting point has the phenomenon of repeated jump before and after the relative position of the digital signal to be processed, if so, the sampling starting point is shifted, whether the sampling starting point is near the boundary or near the synchronization is judged according to the shifted relative position, if so, the sampling starting point is adjusted by half bit width to reach the vicinity of the synchronization, and if the phenomenon of repeated jump before and after does not occur, the sampling starting point is adjusted by a bisection method to reach the vicinity of the synchronization. The invention carries out oversampling on two continuous digital bits and estimates the initial time of the digital bits by combining the characteristic of Manchester coding, thereby giving the synchronous adjustment direction of the digital bits, and finally achieving the synchronization of the sampling clock and the digital bits under the condition of gradually reducing the adjustment step length. Thus, under the condition that the sampling clock is synchronous with the digital bit, the logic level of the signal can be reduced by counting the high-low level pulse after oversampling for the whole digital bit instead of a part of one digital bit, thereby improving the receiving sensitivity.
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In order that the present disclosure may be more readily and clearly understood, reference is now made to the following detailed description of the present disclosure taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a diagram illustrating glitches and multiple flip phenomena in a baseband signal;
FIG. 2 is a schematic view of a prior art deburring process;
FIG. 3 is a flow chart of an implementation of bit synchronization of the Manchester encoded signal of the present invention;
FIG. 4 is a Manchester encoding schematic;
FIG. 5 is a schematic diagram of a sample start point leading a digital bit edge;
FIG. 6 is a schematic diagram of the alignment of the sampling start point and the digital edge after bit synchronization;
FIG. 7 is a schematic diagram of two consecutive digital bits with the sample start point leading the digital bit edge;
FIG. 8 is a schematic diagram of two consecutive digital bits with sampling start points lagging digital bit edges;
FIG. 9 is a flow chart of the relative location determination of a sampling start point according to the present invention;
FIG. 10 is a schematic diagram of sample start point boundary conditions and synchronization conditions;
FIG. 11 is a graphical representation of 12/13 combined sample point counts;
FIG. 12 is a schematic view of 2/3 combined sample point counts;
FIG. 13 is a block diagram of an apparatus for bit synchronizing a Manchester encoded signal.
Detailed Description
The core of the invention is to provide a method, a device, equipment and a computer storage medium for synchronizing Manchester coding signal bits, which synchronize a sampling starting point and a digital bit, so that the logic level of a signal can be summarized by counting high and low level pulses after oversampling the whole digital bit, and the receiving sensitivity is further improved.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 3, fig. 3 is a flow chart of implementing manchester encoded signal bit synchronization according to the present invention; the specific operation steps are as follows:
manchester encoding is the representation of 0 and 1 by the high and low changes of the signal. For example, in IEEE 802.3, the encoding mode is that a transition from high level to low level of a signal represents 0, and a transition from low level to high level represents 1, as shown in fig. 4, and a data Bit width is defined in fig. 4 to refer to a width of one Bit (Bit) of the encoded signal; the data Bit edge refers to the time starting point of one Bit (Bit) of the encoded signal, and it is noted that in the manchester-encoded signal sequence, the probability that two bits (Bit) continuously have high-level logic 1 is 1/4; the probability that two bits (Bit) consecutively appear as high-level logic 0 is also 1/4.
The receiver samples the received signal at a fixed sampling rate, the range of the separation Δ T between the start of sampling and the edge of the digital bit being
Wherein, TbIs the time length of the digital bit width, and the range is also the adjustment range of the sampling start point in the bit synchronization process, that is, the adjustable range of the sampling start point is half the digital bit width. "-" indicates the sample start point is advanced to the left, and "+" indicates the sample start point is retarded to the right.
Suppose NTbIs the number of sampling points in a digital bit width, and the interval between the sampling initial point and the digital bit edge is expressed by the number of the sampling points delta N, so as to obtain the sampling point
The two ways Δ T and Δ N of the interval representation of the sampling start point and the digital bit edge are as follows:
where the function Round () performs a rounding operation.
As an example, the case where the sampling start point leads the digital bit edge is shown in fig. 5, and when the bit synchronization is completed, the sampling start point is aligned with the digital bit edge as shown in fig. 6.
S301, counting in two continuous data bit widths, and listing all digital signal combinations conforming to the Manchester encoding rule;
counting operations are performed on two consecutive digital bit widths, and assuming Δ N is the number of spaced points between the sampling start point and the data bit edge, all 10 combinations that may comply with the manchester encoding rules are shown in fig. 7 and 8. Fig. 7 and 8 are for the case of sampling start points leading and lagging digital bit edges, respectively.
S302, analyzing counting results of a logic 1 point and a logic 0 point in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling initial point relative positions, and summarizing the counting results to obtain a plurality of counting result conditional expressions;
when the input signal has a glitch or is turned over for many times, the counting result has an error. We define a number of points N that count to logic 1 within one bit width over a period of time1Maximum value of (1) is N1-max(ii) a Number of points N counted as logic 0 in one bit width0Maximum value of (1) is N0-maxLet Bit be 1, the probability of "1" obtained by sampling is r1(ii) a When Bit is 0, the probability of "0" obtained by sampling is r0If the number of sampling points in one bit width is equal to
In the case of bit synchronization, there is the following relationship:
at a period of time M.TbInternally sampling the digital signal by a data bit width TbCounting the number N of logic 1 points in each counting interval for the counting interval1i(i ═ 1, 2.. multidot., M) and the number N of logical 0 points0i(i ═ 1, 2.. times, M), and choose the maximum N of the logical 1 point numbers1-maxAnd a logical 0 point number maximum N0-max：
In the signal sequence subjected to manchester encoding, the probability that two bits (bits) continuously appear high-level logic 1 is 1/4; the probability that two bits (Bit) consecutively appear as high-level logic 0 is also 1/4. This ensures that the actual maximum value N can be measured even if M is chosen large enough without bit synchronization1-maxAnd N0-max。
The steps of calculating the number of sampling points are as follows:
(1) defining an input signal by using a first bit width to obtain an input signal segment with a time width of one bit width;
(2) the length of the time segment with logic 1 in this segment is determined, denoted t1；
(3) Assume a bit width inner sampling point number of
In the absence of noise or interference, the number of sampling points with logic 1 is
(4) In the case of noise or interference, it is assumed that the sample points are sampled with a probability r during a time period of logic 11 Taking 1, the number of sampling points with logic 1 obtained by actual sampling is
(5) Similarly, assume that the sample points are sampled with probability r during a time period of logic 00 Taking 0, the sampling point number of logic 0 obtained by sampling is
(6) Repeating steps 1) -5) for the second bit width to obtain the number of sampling points with logic 1 and 0 respectively.
After analysis, the counting result within one bit width can be summarized into 4 types:
when the time period with logic 1 is equal to the time length of one bit width, the counting result is summarized into a first conditional expression
When the time period of logic 0 is equal to the time length of one bit width, the counting result is reduced to a second conditional expression
When the time period with the logic 1 is greater than the time length of half bit width, the counting result is summarized as a third conditional expression:
when the time period of the logic 0 is longer than the time length of half bit width, the counting result is summarized as a fourth conditional expression:
in some cases, because of symmetry, the same length of time period occupied by logic 1 and logic 0 of the two bit width defined input signal segments cannot be used for judging the relative position of the sampling starting point, so when the time period of logic 1 is the same as the time period of logic 0 in the two data bit widths, the counting result is summarized as the total counting result of the two bit widths:
wherein N is1And N0Representing a number of logical 1 points and a number of logical 0 points in one bit width,
representing all number of sample points within bit width, N1,bit1And N0,bit1Representing the number of logical 1 points and logical 0 points, N, within the first bit width1,bit2And N0,bit2Indicating the number of logic 1 points and the number of logic 0 points in the second bit width.
S303, listing counting result conditional expressions in the first bit width and the second bit width of each combination under the two conditions of leading and lagging of the relative position of the sampling starting point, and combining the combinations with consistent results to obtain the relative relationship between the relative position of the sampling starting point and the counting result;
the relative relationship between the relative position of the sampling start point and the counting result is shown in table 1:
TABLE 1 relative relationship table of sampling start point relative position and counting result
The combinations denoted by x in table 1 are combinations that do not comply with the manchester encoding rules and ideally do not occur. From table 1, the relative position of the sampling start point with respect to the digital bit edge, i.e. whether it is leading or lagging, can be deduced from the counting result. The combination marked in table 1 is a combination which does not comply with the manchester coding rule and ideally does not occur, but the presence thereof in table 1 does not affect the determination of the relative position of the sampling start point. That is, table 1 contains all possible combinations in practical cases, so that the method of the present invention is complete.
S304, obtaining a judgment process of the relative position of the sampling starting point according to the relative relation;
the counting results 5 and 6 in table 1 are the same as the counting results in the case of bit synchronization, and cannot be used to determine the relative position of the sampling start point with respect to the digital bit edge, and are ignored in the process of adjusting the sampling start point in bit synchronization.
The counting results 7a and 7b in table 1 are identical and it is not possible to distinguish whether the sampling start point is a leading or lagging digital bit edge. The counting results 7c and 7d are identical and it is not possible to distinguish whether the sampling start point is a leading or lagging digital bit edge. The counting results 7a-7d are thus written collectively as counting result 7 and ignored during the bit sync adjustment sampling start point.
The counting results 1 to 4 in table 1 are mutually exclusive for the cases of leading and lagging, and whether the sampling start point is a leading or lagging digital bit edge can be uniquely determined from the counting results.
The flow chart of the judgment of the relative position of the sampling starting point is shown in fig. 9:
when the counting result in two continuous bit widths is expressed as
If so, the inference result is invalid, otherwise, the judgment is continued;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
The judgment result is lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is less than the threshold value, the judgment result is advanced, and when the second bit width counting result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is less than the threshold value, the judgment result is advanced, and when the second bit width counting result expression is
The determination result is hysteresis.
S305, judging whether the relative position of the sampling starting point of the digital signal to be processed has the phenomenon of repeated jump in advance and behind by utilizing the judging process according to the counting result expression of the digital signal to be processed in two continuous data bit widths;
s306, if the sampling is near, shifting the sampling starting point, judging whether the sampling starting point is near the boundary or near the synchronization according to the relative position after the shifting, and if the sampling starting point is near the boundary, adjusting the sampling starting point by half bit width to reach the vicinity of the synchronization;
and S307, if the phenomenon of repeated jump in advance and behind does not occur, adjusting the sampling starting point to reach the vicinity of synchronization by using a dichotomy.
The invention carries out oversampling on two continuous digital bits and estimates the initial time of the digital bits by combining the characteristic of Manchester coding, thereby giving the synchronous adjustment direction of the digital bits, and finally achieving the synchronization of the sampling clock and the digital bits under the condition of gradually reducing the adjustment step length. Thus, under the condition that the sampling clock is synchronous with the digital bit, the logic level of the signal can be reduced by counting the high-low level pulse after oversampling for the whole digital bit instead of a part of one digital bit, thereby improving the receiving sensitivity.
Based on the above embodiment, step S303 is further described in detail as follows:
as shown in fig. 10, taking the 12/13 th combination as an example,
in the first bit width, i.e. in the a-segment, the sampled points are ideally all 1, but because of the influence of noise and interference, the sampled points have a probability r1Take 1, therefore
In the second bit wide B section, the sampling point has the probability r1Take 1, therefore
N1B＝r1ΔN(Ea2)
The other sampling points are taken as 0
N0B＝ΔN-N1B＝(1-r1)ΔN(Ea3)
In the second positionWide C section, sampling point with probability r0Get 0, therefore
The other sampling points are 1, have
At the second bit width, combining (Ea2) and (Ea5), the number of sampling points is 1
In the above formula, Δ N is relative to N1Is a linear increasing relationship, such that
Let r be1＝r0，
At the second bit width, combining (Ea3) and (Ea4), the number of sampling points taken to be 0 is
In the above formula,. DELTA.N for N0Is a linear decreasing relationship, such that
Let r be1＝r0，
Let Δ N be 0, by (Ea9),
binding (Ea8), (Ea11) and (Ea12),
i.e., row number 1 as listed in table 1.
In fig. 11, the following derivation can be obtained by exchanging the above subscript "1" with "0" in the case of 2/3 combination:
in the first bit width, i.e. in section a, the sampled points are ideally all 0, but because of the influence of noise and interference, the sampled points have a probability r0Get 0, therefore
In the second bit wide B section, the sampling point has the probability r0Take 0, therefore
N0B＝r0ΔN(Eb2)
The rest sampling point is 1, have
N1B＝ΔN-N0B＝(1-r0)ΔN(Eb3)
In the second bit wide C section, the sampling point has the probability r1Take 1, therefore
The other sampling points are taken as 0
At the second bit width, combining (Eb2) and (Eb5), the number of sampling points taken to be 0 is
In the above formula, Δ N is relative to N0Is a linear increasing relationship, such that
Let r be1＝r0，
At the second bit width, combining (Eb3) and (Eb4), the number of sampling points 1 is taken as
In the above formula, Δ N is relative to N1Is a linear decreasing relationship, such that
Suppose r1＝r0，
Let Δ N be 0, by (Eb9),
combined with (Eb8), (Eb11) and (Eb12),
i.e., row number 2 as listed in table 1.
Based on the above embodiments, the present embodiment further describes steps S305 to S306 in detail as follows:
when the sampling start point is spaced from the edge of the digital bit
Then, due to the influence of noise and interference, the relative position of the sampling start point deduced from the counting result repeatedly jumps in the lead and lag as shown in fig. 12, and it can be seen that when the sampling start point is located at the leading and lagging positions
The phenomenon of repeated jumps of the leading and lagging digital bit edges relative to the position of the start point of the time sample is similar to the situation after the bit synchronization is completed. To distinguish between these two states, the sample start point is shifted to the left by a quarter number of sample points, if the relative position becomes lagging, the sample start point is near the boundary, otherwise near the synchronization; shifting the sampling start point by a quarter of the number of sampling points to the right, if the relative position becomes advanced, the sampling start point is near the boundary, otherwise near the synchronization. As shown in table 2:
TABLE 2 determination of boundary conditions for relative positions of sampling start points
If the sampling start point is at the boundary, adjusting the sampling start point to the left or the right
The sampling start point is then synchronized with the digital bit edge. After the condition that the sampling start point is at the boundary is processed, the condition that the advance and the lag jump repeatedly can be used as the convergence condition of the bit synchronization. That is, when the leading and lagging repeated jumps occur with respect to the sampling start point position, it can be considered that the bit synchronization has been completed.
Based on the above embodiments, this embodiment further describes step S307 in detail, specifically as follows:
a. marking the position of the current sampling start point as delta Na＝0；
b. Determining whether the current sample start point is a leading or lagging data bit edge;
c. if the sampling is lagging, the current sampling starting point is made to be far away from the reference position
If the sampling is advanced, the far-end reference position of the current sampling starting point is enabled
d. Calculating the relative position of the next sampling starting point according to the far-end reference position of the current sampling starting point
e. Determining whether the next sample start point relative position is an early or late data bit edge;
f. if the relative position of the next sampling starting point is the same as that of the previous sampling starting point, the current sampling is carried outUpdating the relative position of the sample starting point to be the relative position delta N of the next sampling starting pointa＝ΔNm(ii) a Otherwise, updating the far-end reference position of the current sampling starting point to be the relative position delta N of the next sampling starting pointb＝ΔNm；
g. Repeating steps d), e) and f) until | Δ Na-ΔNb| is less than a given threshold;
h. at this time, the relative position of the final sampling start point is
i. Adjusting relative position delta N according to sampling starting pointadjust＝-ΔNmThe sampling start point position is adjusted to achieve bit synchronization.
After the above adjustment is completed, it can be checked whether the phenomenon that the sampling start point jumps back and forth repeatedly occurs to confirm that the bit synchronization is achieved.
In practice, the relative timing of the data bit edges may change slowly due to phase perturbations of the data clock, as well as small deviations in the frequency of the data clock. Continuously fine-tuning the sampling starting point after the sampling starting point and the digital bit edge reach initial synchronization, so that the probability of occurrence of lead and lag is respectively half to further optimize the relative position of the sampling starting point; so that the sampling start point can keep synchronization even under the condition that the data bit edge changes slowly.
The invention relates to a Manchester coding signal bit synchronization method, which comprises the following steps:
referring to fig. 13, fig. 13 is a block diagram illustrating a structure of a device for bit synchronization of a manchester encoded signal according to an embodiment of the present invention; the specific device may include:
a combination enumerating module 100, configured to count within two consecutive data bit widths, and enumerate all digital signal combinations that comply with the manchester encoding rule;
a counting result induction module 200, configured to analyze counting results of a logical 1 point and a logical 0 point in the first bit width and the second bit width of each combination under two conditions, namely, an advance condition and a retard condition of the relative position of the sampling start point, and induce the counting results to obtain multiple conditional expressions of the counting results;
a relative relationship establishing module 300, configured to list conditional expressions of the counting results in the first bit width and the second bit width for each combination under two conditions, namely, an advance condition and a retard condition, of the relative position of the sampling start point, and merge the combinations with consistent results to obtain a relative relationship between the relative position of the sampling start point and the counting results;
the judgment flow construction module 400 is used for obtaining a judgment flow of the relative position of the sampling starting point according to the relative relationship;
the repeated jump judging module 500 is configured to judge, according to a count result expression of the to-be-processed digital signal within two consecutive data bit widths, whether a phenomenon of repeated jump in advance and behind occurs at a relative position of a sampling start point of the to-be-processed digital signal by using the judging process;
a boundary sampling starting point synchronization module 600, configured to shift a sampling starting point if a phenomenon of repeated jump between leading and trailing occurs, determine, according to a relative position after the shift, whether the sampling starting point is near a boundary or near synchronization, and adjust the sampling starting point by a half bit width to reach near synchronization if the sampling starting point is near the boundary;
and a bisection synchronization module 700, configured to adjust the sampling starting point to be close to synchronization by using a bisection method if a phenomenon of repeated jump between leading and lagging does not occur.
The manchester encoded signal bit synchronization apparatus provided in this embodiment is used for implementing the manchester encoded signal bit synchronization method, and thus the specific implementation manner in the manchester encoded signal bit synchronization apparatus can be seen in the foregoing embodiments of the manchester encoded signal bit synchronization method, for example, the combination listing module 100, the counting result summarizing module 200, the relative relationship building module 300, the judgment flow building module 400, the repeated jump judging module 500, the boundary sampling starting point synchronization module 600, and the bisection synchronization module 700 are respectively used for implementing steps S101, S102, S103, S104, S105, S106, and S107 in the manchester encoded signal bit synchronization method, so that the specific implementation manner thereof can refer to the description of the corresponding respective embodiments, and will not be repeated herein.
The specific embodiment of the present invention further provides a device for synchronizing manchester encoded signal bits, including: a memory for storing a computer program; a processor for implementing the steps of one of the manchester encoded signal bit synchronization methods described above when executing the computer program.
The specific embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the manchester encoded signal bit synchronization method are implemented.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A method for synchronizing manchester encoded bits of a signal, comprising:
counting within two continuous data bit widths, and listing all digital signal combinations conforming to the Manchester encoding rule;
analyzing counting results of a logic 1 point number and a logic 0 point number in a first bit width and a second bit width of each combination under the condition that the relative position of a sampling starting point is advanced and lagged, and inducing the counting results to obtain a plurality of counting result conditional expressions;
listing counting result conditional expressions in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling starting point relative positions, and combining the combinations with consistent results to obtain the relative relation between the sampling starting point relative positions and the counting results;
obtaining a judgment process of the relative position of the sampling starting point according to the relative relation;
judging whether the relative position of the sampling starting point of the digital signal to be processed has the phenomenon of repeated jump in advance and behind by utilizing the judging process according to the counting result expression of the digital signal to be processed in the bit width of two continuous data;
if the sampling starting point is close to the boundary, adjusting the sampling starting point by half bit width to reach the vicinity of synchronization;
and if the phenomenon of repeated jump between the leading and the lagging does not occur, adjusting the sampling starting point to reach the vicinity of synchronization by utilizing a dichotomy.
2. The manchester encoded signal bit synchronization method of claim 1 wherein said achieving the vicinity of synchronization comprises:
and after the initial synchronization of the sampling starting point and the digital bit edge is completed, continuously fine-tuning the sampling starting point to ensure that the occurrence probability of the lead and the lag is respectively half to further optimize the relative position of the sampling starting point.
3. The manchester encoded signal bit synchronization method of claim 1, wherein analyzing the count results of the number of logic 1 points and the number of logic 0 points in the first bit width and the second bit width for each combination in both the early and late sample start point relative positions and generalizing the count results to obtain a plurality of count result conditional expressions comprises:
sampling digital signals in a period of time, counting the number of logic 1 points and the number of logic 0 points in each counting interval by taking one data bit width as the counting interval, and selecting the maximum value N of the number of the logic 1 points1-maxAnd a logical 0 point number maximum N0-max。
4. The manchester encoded signal bit synchronization method of claim 3 wherein analyzing the count results for the number of logic 1 points and the number of logic 0 points in the first bit width and in the second bit width for each combination with both an early and a late sample start point relative position and generalizing the count results to obtain a plurality of count result conditional expressions comprises:
when the time period with logic 1 is equal to the time length of one bit width, the counting result is summarized into a first conditional expression
When the time period of logic 0 is equal to the time length of one bit width, the counting result is reduced to a second conditional expression
When the time period with the logic 1 is greater than the time length of half bit width, the counting result is summarized as a third conditional expression:
when the time period of the logic 0 is longer than the time length of half bit width, the counting result is summarized as a fourth conditional expression:
when the time period of logic 1 is the same as the time period of logic 0 in the two data bit widths, the counting result is summarized as the total counting result of the two bit widths:
wherein, N1And N0Representing a number of logical 1 points and a number of logical 0 points in one bit width,
representing all number of sample points within bit width, N1，bit1And N0，bit1Representing the number of logical 1 points and logical 0 points, N, within the first bit width1，bit2And N0，bit2Indicating the number of logic 1 points and the number of logic 0 points within the second bit width.
5. The manchester encoded signal bit synchronization method of claim 4, wherein the determining step comprises:
when the count result in two consecutive bit widths is expressed as
If so, the inference result is invalid, otherwise, the judgment is continued;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is not valid, the second bit width counting result expression is
When the result is determined to be advanced, the second bit width count result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is less than the threshold value, the judgment result is advanced, and when the second bit width counting result expression is
Judging the result to be lag;
the first bit width counting result expression is
When the second bit width count result expression is
When the bit width is less than the threshold value, the judgment result is advanced, and when the second bit width counting result expression is
The determination result is hysteresis.
6. The manchester-encoded signal bit synchronization method of claim 1 wherein shifting the sampling start point and determining whether the sampling start point is near the boundary or near the sync by the relative position after shifting comprises:
shifting the sampling starting point by a quarter of the number of sampling points to the left, if the relative position becomes lag, the sampling starting point is near the boundary, otherwise, the sampling starting point is near the synchronization;
shifting the sampling start point by a quarter number of sampling points to the right, if the relative position becomes advanced, the sampling start point is near the boundary, otherwise near the synchronization.
7. The manchester encoded signal bit synchronization method of claim 1 wherein said adjusting the sampling start point to near synchronization with bisection comprises:
a) marking the position of the current sampling start point as delta Na＝0；
b) Determining whether the current sample start point is a leading or lagging data bit edge;
c) if the sampling is lagging, the current sampling starting point is made to be far away from the reference position
If the sampling is advanced, the far-end reference position of the current sampling starting point is enabled
d) Calculating the relative position of the next sampling starting point according to the far-end reference position of the current sampling starting point
e) Determining whether the next sample start point relative position is an early or late data bit edge;
f) if the relative position of the next sampling starting point is the same as the relative position of the last sampling starting point, updating the relative position of the current sampling starting point to be the relative position delta N of the next sampling starting pointa＝ΔNm(ii) a Otherwise, updating the far-end reference position of the current sampling starting point to be the relative position delta N of the next sampling starting pointb＝ΔNm；
g) Repeating steps d), e) and f) until | Δ Na-ΔNb| is less than a given threshold;
h) at this time, the relative position of the final sampling start point is
i) Adjusting relative position delta N according to sampling starting pointadjust＝-ΔNmThe sampling start point position is adjusted to achieve bit synchronization.
8. An apparatus for bit synchronizing a manchester encoded signal, comprising:
the combination enumerating module is used for counting within two continuous data bit widths and enumerating all digital signal combinations conforming to the Manchester encoding rule;
the counting result induction module is used for analyzing the counting results of the number of the logic 1 points and the number of the logic 0 points in the first bit width and the second bit width under the two conditions of leading and lagging of the relative position of the sampling starting point of each combination, and inducing the counting results to obtain a plurality of counting result conditional expressions;
the relative relation building module is used for listing counting result conditional expressions in a first bit width and a second bit width of each combination under the two conditions of leading and lagging sampling starting point relative positions, and combining the combinations with consistent results to obtain the relative relation between the sampling starting point relative positions and the counting results;
the judgment flow construction module is used for obtaining a judgment flow of the relative position of the sampling starting point according to the relative relation;
the repeated jump judging module judges whether the relative position of the sampling starting point of the digital signal to be processed has the phenomenon of repeated jump in advance and behind according to the counting result expression of the digital signal to be processed in two continuous data bit widths by utilizing the judging flow;
the boundary sampling starting point synchronization module is used for shifting the sampling starting point if the phenomenon of repeated jump of leading and lagging occurs, judging whether the sampling starting point is near the boundary or near the synchronization according to the relative position after the shifting, and if the sampling starting point is near the boundary, adjusting the sampling starting point by half bit width so as to reach the near synchronization;
and the dichotomy synchronization module is used for adjusting the sampling starting point to reach the vicinity of synchronization by using a dichotomy if the phenomenon of repeated jump in advance and behind does not occur.
9. An apparatus for bit synchronizing a manchester encoded signal, comprising:
a memory for storing a computer program;
a processor for implementing the steps of a method of bit synchronization of a manchester encoded signal according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of a method of bit synchronizing a manchester encoded signal according to any one of claims 1 to 7.
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| CN114422062A (en) * | 2021-11-30 | 2022-04-29 | 中国电子科技集团公司第五十三研究所 | Communication synchronization method and device of FPGA-based inter-satellite laser communication system |
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| US4984249A (en) * | 1989-05-26 | 1991-01-08 | First Pacific Networks | Method and apparatus for synchronizing digital data symbols |
| US20160056829A1 (en) * | 2014-08-22 | 2016-02-25 | Analog Devices Global | Isolator system supporting multiple adcs via a single isolator channel |
| CN109412601A (en) * | 2018-10-17 | 2019-03-01 | 西安微电子技术研究所 | A kind of regeneration of high speed manchester encoded signals and drive control method |
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