CN114696711A - Motor position signal distribution system and method - Google Patents

Abstract

The invention discloses a motor position signal distribution system and a method, which comprises the following steps: the system comprises an absolute encoder and a Field Programmable Gate Array (FPGA), wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. According to the technical scheme, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to a control system for controlling the outside through the FPGA, the distribution of the position signal of the motor is realized, and the application range and the application scene of the absolute encoder are enlarged.

Description

Motor position signal distribution system and method

Technical Field

The embodiment of the invention relates to the technical field of motors, in particular to a motor position signal distribution system and a motor position signal distribution method.

Background

The requirements of modern processing technology on processing precision and processing efficiency have prompted the birth of servo motor control systems. In order to ensure accurate positioning of the operation object, the servo motor control system needs to acquire accurate position information of the motor.

In the prior art, an encoder can be used to obtain the position information of a single machine. However, the incremental encoder cannot directly know the current actual position of the motor after being powered on, and the current position of the motor can be correctly captured only after the motor moves to an electric phase to trigger the limit sensor to acquire the 0 bit; the absolute encoder can acquire the current actual position of the motor after being electrified, the position is not required to be calibrated through a limit sensor, but the absolute encoder is usually communicated through a synchronous/asynchronous protocol, and one-to-many signals are relatively difficult. Meanwhile, the commercial motor driving module usually does not disclose an internal structure to the outside, so that the position signal cannot be output in real time to an upper control system by changing internal hardware or software architecture.

Therefore, a need exists for a motor position signal distribution system that enables the acquisition of a position signal of a motor and that can upload the position signal to a control system.

Disclosure of Invention

The invention provides a motor position signal distribution system and a motor position signal distribution method, which are used for acquiring a position signal of a motor and uploading the position signal to a control system.

In a first aspect, an embodiment of the present invention provides a motor position signal distribution system, including: an absolute encoder and an FPGA (field programmable gate array),

when the absolute encoder receives a clock signal, a position signal is sent to the FPGA;

and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal.

Further, the system further comprises: the motor driver PA is provided with a motor driver,

the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

Further, the system further comprises a first single-to-single-ended chip, a second single-to-single-ended chip, a first single-to-differential chip, a second single-to-differential chip, a third single-to-differential chip and a fourth single-to-differential chip,

a clock signal received by the absolute encoder is a first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

the absolute encoder, upon receiving the first clock signal,

sending a first position signal to the PA through the second single-ended to single-ended conversion chip and the third single-ended to differential conversion chip, so that the PA determines the current position information of the motor based on the first position information;

and the first position signal is sent to the FPGA through the second single-end-to-single-end conversion chip and the fourth single-end-to-differential chip.

Further, the FPGA includes a first decoder and a first enhanced encoder emulator,

the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder;

correspondingly, the absolute encoder sends a second position signal to the first enhanced encoder emulator through the first decoder when receiving the second clock signal.

Further, the operation of the FPGA on the second position signal includes:

sending, by the first decoder, the second position signal to the first incremental encoder emulator;

and coding the second position signal through the first incremental encoder simulator to obtain an incremental encoded second position signal, and then sending the incremental encoded second position signal to the PA, so that the PA determines the current position information of the motor based on the incremental encoded second position signal.

Further, the step of the FPGA coding the second position signal through the first incremental encoder simulator to obtain an incrementally coded second position signal includes:

the FPGA determines a preset bit of the second position signal as a criterion bit through the first incremental encoder simulator;

and the FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

Further, the FPGA includes a second decoder and an encoder emulator,

the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through a second decoder;

and when receiving the third clock signal, the absolute encoder sends the third position signal to the encoder emulator through the second decoder.

Further, the operation of the third position signal by the FPGA includes:

sending, by the second decoder, the third position signal to the encoder emulator;

encoding the third position signal through the encoder simulator to obtain an encoded third position signal;

and when a fourth clock signal sent by the PA is received through the encoder simulator, the encoded third position signal is sent to the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain a third encoded position signal, including:

the absolute type encoder simulator encodes the third position signal to obtain an absolute type encoded third position signal;

and the second incremental coding simulator codes the third position signal to obtain an incremental coding third position signal.

In a second aspect, an embodiment of the present invention further provides a motor position signal distribution method, which is applied to the motor position signal distribution system in the first aspect, and the method includes:

when receiving a clock signal, the absolute encoder sends a position signal to the FPGA;

and the FPGA sends the position signal to a control system so that the control system determines the position information of the motor according to the position signal.

The embodiment of the invention provides a motor position signal distribution system, which comprises: the system comprises an absolute encoder and a Field Programmable Gate Array (FPGA), wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. According to the technical scheme, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to a control system for controlling the outside through the FPGA, the distribution of the position signal of the motor is realized, and the application range and the application scene of the absolute encoder are enlarged.

Drawings

Fig. 1 is a structural diagram of a motor position signal distribution system according to an embodiment of the present invention;

fig. 2 is a structural diagram of a motor position signal distribution system according to a second embodiment of the present invention;

fig. 3 is a structural diagram of a motor position signal distribution system according to a third embodiment of the present invention;

fig. 4 is a schematic diagram of output signals of a first incremental encoder emulator according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram of an output signal of a first incremental encoder emulator according to a third embodiment of the present invention;

fig. 6 is a structural diagram of a motor position signal distribution system according to a fourth embodiment of the present invention;

fig. 7 is a flowchart of a motor position signal distribution method according to a fifth embodiment of the present invention;

fig. 8 is a schematic structural diagram of a motor system according to a sixth embodiment of the present invention.

Reference numerals:

the chip comprises a first single-to-single-ended chip-210, a second single-to-single-ended chip-220, a first single-to-differential chip-230, a second single-to-differential chip-240, a third single-to-differential chip-250 and a fourth single-to-differential chip-260.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings, not all of them.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but could have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like. In addition, the embodiments and features of the embodiments in the present invention may be combined with each other without conflict.

Example one

Fig. 1 is a structural diagram of a motor position signal distribution system according to an embodiment of the present invention, where the embodiment is applicable to a situation where a motor position signal needs to be uploaded to a control system, and the system includes: the system comprises an absolute encoder and an FPGA, wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal.

An encoder is a device that compiles, converts, and/or otherwise encodes signals or data into a form of signals that may be communicated, transmitted, and stored. Encoders convert angular or linear displacements, called codewheels, into electrical signals, called coderulers. Each position of the absolute encoder corresponds to a certain digital code, so that its representation is only dependent on the start and end positions of the measurement, and not on the intermediate course of the measurement.

The FPGA belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array, and can effectively solve the problem of less gate circuits of the original device.

Specifically, when receiving a clock signal, the absolute encoder may send a position signal of the motor to an external control system through the FPGA. The control system may store and process the position signals in the host computer.

It will be appreciated that the transmission protocols for the clock signal and the location signal may include synchronous simplex protocols, asynchronous simplex protocols and half-duplex protocols.

When the transmission protocol is a synchronous simplex protocol, the absolute encoder can send the position signal to the FPGA through the second channel when receiving the clock signal through the first channel, and after the FPGA receives the position signal, the absolute encoder continues to send the position signal to the FPGA; when the transmission protocol is an asynchronous simplex protocol, the absolute encoder can continuously send the position signal to the FPGA through the second channel when receiving the clock signal through the first channel; when the transmission protocol is a half-duplex protocol, the absolute encoder can send the position signal to the FPGA through the third channel after receiving the clock signal through the third channel.

Further, the system further comprises: and the motor driver PA is used for receiving the position signal sent by the absolute type encoder when receiving the clock signal.

Different PAs can receive position signals of different protocols, and FPGA or external chips can be adopted to convert the protocol types of the different PAs correspondingly.

The motor driver, also known as a servo driver, a servo controller and a servo amplifier, can be used for controlling a servo motor, has the action similar to that of a frequency converter acting on a common alternating current motor, belongs to a part of a servo system, and is mainly applied to a high-precision positioning system. The servo motor is generally controlled by three modes of position, speed and moment, so that the high-precision positioning of a transmission system is realized, and the servo motor is a high-end product of a transmission technology at present.

According to the technical scheme of the embodiment, the motor position signal distribution system comprises an absolute encoder and an FPGA (field programmable gate array), wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. According to the technical scheme, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to a control system for controlling the outside through the FPGA. Further, the system further comprises: and the motor driver PA receives the position signal sent by the absolute type encoder when receiving the clock signal. The position signal is sent to the PA and the control system, the distribution of the position signal of the motor is further realized, and the application range and the application scene of the absolute encoder are enlarged.

Example two

Fig. 2 is a structural diagram of a motor position signal distribution system according to a second embodiment of the present invention, which is embodied on the basis of the second embodiment. In this embodiment, the system may further include: the system comprises an absolute encoder, a Field Programmable Gate Array (FPGA) and a motor driver PA, wherein the absolute encoder sends a first position signal to the FPGA when receiving a first clock signal; and the FPGA sends the first position signal to an external control system so that the control system determines the current position information of the motor according to the first position signal. The PA receives a first position signal sent by the absolute encoder when receiving a first clock signal.

As described in the first embodiment, the absolute encoder may send the first position signal to the PA and the control system, respectively, so that the position signal of the motor is distributed, and the application range and the application scenario of the absolute encoder are expanded.

In this embodiment, the first clock signal and the first position signal may be transmitted by using a synchronous simplex transmission protocol.

Further, the system further includes a first single-to-single-ended conversion chip 210, a second single-to-single-ended conversion chip 220, a first single-to-differential conversion chip 230, a second single-to-differential conversion chip 240, a third single-to-differential conversion chip 250, and a fourth single-to-differential conversion chip 260; the clock signal received by the absolute encoder is a first clock signal sent by the PA through the first differential-to-single-ended chip 210 and the first single-ended-to-differential chip 230; the absolute encoder is specifically configured to: when the first clock signal is received, sending a first position signal to the PA through the second single-to-single-ended chip 220 and the third single-to-differential chip 250, so that the PA determines current position information of the motor based on the first position information; the first position signal is sent to the FPGA through the second single-to-single-ended chip 220 and the fourth single-to-differential chip 260.

In addition, the PA may also send the first clock signal to the FPGA through the second single-ended to differential chip 240.

The differential-to-single-ended chip is also called an encoder signal conversion module and can be used for solving the problem of interface conversion between a rotary encoder and a differential mode output of a grating ruler and a single chip microcomputer and a PLC controller. The pulse shaping circuit can overcome strong interference in a complex field environment of an industrial control system, eliminate electrical interference of a strong electric field, a strong magnetic field and the like, effectively protect sensitive circuits, has a pulse shaping function, effectively improves the anti-interference performance between systems, and provides a safe interface.

The differential signal has stronger common-mode interference resistance and is suitable for long-distance transmission, and the single-ended signal does not have the function. The single-ended to differential chip is also called a single-ended to differential converter.

In this embodiment, the PA may be responsible for outputting the first clock signal as the master and receiving the first position signal from the absolute encoder, the absolute encoder may be responsible for receiving the first clock signal from the PA as the slave and outputting the first position signal synchronized with the first clock signal, and the FPGA may be responsible for receiving the first position signal from the absolute encoder and also receiving the synchronized first clock signal from the PA as the slave.

Specifically, when the PA sends out a synchronous first clock signal, the clock +, clock-is converted from a differential signal to a single-ended signal at the first differential-to-single-ended chip 210, and then divided into two paths: the signal is converted into a clock 1+ and a clock 1-at the first single-ended to differential chip 230 and sent to the absolute encoder; converted to clock 2+, clock 2-at the second single-ended to differential chip 240, and sent to the FPGA chip. When the absolute encoder receives a first clock signal from the PA, the absolute encoder starts to output a first position signal, and data + and data-are converted from differential signals into single-ended signals at a 220 second differential-to-single-ended chip, and then are divided into two paths: converted to data 1+, data 1-at the third single-ended to differential chip 250 and sent to PA; converted to data 2+, data 2-at the fourth single-ended to differential chip 260, and sent to the FPGA chip. After receiving the clock 2+, the clock 2-, the data 2+ and the data 2-, the FPGA processes the data through an internal encoder signal monitoring code, converts the data into a first position signal and uploads the first position signal to an upper control system.

It should be noted that, when monitoring the rising edge of the first position signal, the FPGA starts receiving the first position signal, and sends the first position signal to the control system after receiving the first position signal.

Specifically, taking the biss-c protocol as an example, first, a clock falling edge is monitored to determine whether a PA clock signal starts; when the PA clock starts, starting to monitor the rising edge of the signal output of the encoder to judge whether the signal conversion of the encoder is finished; and starting a signal receiving process when the signal conversion is finished.

The motor position signal distribution system provided by the embodiment of the invention comprises an absolute encoder, an FPGA and a motor driver PA, wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal; the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

In addition, when the absolute encoder receives a clock signal through the differential-to-single-ended chip and the single-ended-to-differential chip, the position signal of the motor can be uploaded to a control system for controlling the outside through the differential-to-single-ended chip, the single-ended-to-differential chip and the FPGA, and the position signal can be sent to the PA through the differential-to-single-ended chip and the single-ended-to-differential chip, so that one-to-two of the position signal of the motor is realized, and the application range and the application scene of the absolute encoder are expanded.

EXAMPLE III

Fig. 3 is a structural diagram of a motor position signal distribution system according to a third embodiment of the present invention, which is embodied on the basis of the above-mentioned embodiments. In this embodiment, the system may further include: the system comprises an absolute encoder, a Field Programmable Gate Array (FPGA) and a motor driver PA, wherein the absolute encoder sends a second position signal to the FPGA when receiving a second clock signal; and the FPGA sends the second position signal to an external control system so that the control system can determine the current position information of the motor according to the second position signal. The PA receives a second position signal sent by the absolute encoder when receiving a second clock signal.

As described in the first embodiment, the absolute encoder may send the second position signal to the PA and the control system, respectively, so that the position signal of the motor is distributed, and the application range and the application scenario of the absolute encoder are expanded.

In this embodiment, the second clock signal and the second position signal may be transmitted by using a synchronous simplex, an asynchronous simplex, or a half-duplex transmission protocol.

Further, the FPGA includes a first decoder and a first enhanced encoder emulator; the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder; accordingly, the absolute encoder is specifically configured to: upon receiving the second clock signal, sending a second position signal through the first decoder to the first enhanced encoder emulator.

In particular, the first decoder may send the second clock signal to the absolute encoder, and the absolute encoder may send the second position signal to the first decoder upon receiving the second clock signal, and may further send the second position signal to the first enhanced encoder emulator. The first enhanced encoder simulator can recode the second position signal, so that the second position signal obtained by recoding meets the transmission requirement of the current PA, and the second position signal is conveniently conveyed to the current PA and further used for controlling the current motor.

Further, the operation of the FPGA on the second position signal includes: sending, by the first decoder, the second position signal to the first incremental encoder emulator; and coding the second position signal through the first incremental encoder simulator to obtain an incremental encoded second position signal, and then sending the incremental encoded second position signal to the PA so that the PA determines the current position information of the motor based on the incremental encoded second position signal.

The enhanced encoder simulator may be located inside the FPGA, and configured to re-encode the second position signal sent by the absolute encoder to obtain an enhanced encoded second position signal, and may match the enhanced encoded second position signal with a corresponding PA to output the second position signal.

Specifically, a first decoder of the FPGA may receive the second position signal and send the second position signal to the first incremental encoder emulator.

Further, the step of the FPGA coding the second position signal through the first incremental encoder simulator to obtain an incrementally coded second position signal includes:

and the FPGA determines the preset bit of the second position signal as a criterion bit through the first incremental encoder simulator.

And the FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

Fig. 4 is a schematic diagram of output signals of a first incremental encoder emulator according to a third embodiment of the present invention; if 3 and 4 bits of the absolute encoder are taken as the criterion bits of the incremental encoder, the corresponding A, B-phase signal is output, and the 4 th bit signal is taken as the a-phase signal, and the xor operation is performed on the 3 and 4-bit codes to obtain the B-phase signal corresponding to the incremental encoder, as shown in fig. 4.

Fig. 5 is a schematic diagram of an output signal of another first incremental encoder emulator according to a third embodiment of the present invention, as shown in fig. 5, if 3 and 4 bits of an absolute encoder are taken as criterion bits of the incremental encoder, a complete period of a corresponding phase a or B is 10000 (binary) count bits of the absolute encoder, and considering that the incremental encoder usually needs to perform a quadruple operation, a corresponding incremental encoder signal 1count (C) is obtained_I) Absolute encoder signal count (C) equal to 100 (binary) times_A) And the decimal conversion is as follows:

C_I＝(2^2)*C_A

the accuracy of the incremental second position signal converted by the absolute encoder is directly related to the decoding period of the absolute encoder and the speed at which the motor moves. If the absolute encoder 1count ═ C_A50nm, decoding period T_dWhen the maximum moving speed V of the motor is 100mm/s at 20us, the maximum variation of the absolute signals of two adjacent periods is (T)_d*V)/C_A40 count. If the converted incremental second position signal is to be guaranteed to be authentic, the incremental encoder 1count must be guaranteed to be C_I＝(2^n)*C_A>2*40*C_A4um, i.e. the lower bits n used for decision in the absolute encoder signal must be guaranteed (2^ n)>And 40 x 2 is 80, and the corresponding n is more than or equal to 7, so that the minimum judgment bits of the absolute encoder are 8 and 7.

The minimum resolution of the incremental second position signals output by the FPGA in different operating environments can be determined according to the above algorithm.

The absolute conversion increment scheme of the position signal mainly aims at synchronous simplex, asynchronous simplex or half-duplex encoder protocols, and bidirectional signal communication is arranged between an absolute encoder and a PA (power amplifier) of the protocols, so that one-to-two of a front end is difficult to realize. By the method, one-to-two of the second position signal can be realized, and the requirement of one-to-many of the second position signal can be met.

In this embodiment, the FPGA may be responsible for outputting the second clock signal and receiving the second position signal from the absolute encoder as the master, and the absolute encoder may be responsible for receiving the second clock signal from the FPGA as the slave and outputting the second position signal synchronized with the second clock signal at the same time. The FPGA may also upload the second position signal to the control system.

In the embodiment, the requirement of dividing the position signal into two parts can be realized only by the FPGA and the PA without a front-end hardware architecture.

The motor position signal distribution system provided by the embodiment of the invention comprises an absolute encoder, an FPGA and a motor driver PA, wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal; the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

In addition, when receiving a second clock signal sent by the first decoder, the absolute encoder sends a second position signal to the first decoder, and the first decoder uploads the second position signal to the control system and sends the second position signal to the first incremental encoder simulator. And the first incremental encoder simulator encodes the second position signal to obtain an incremental encoded second position signal, and then sends the incremental encoded second position signal to the PA, so that the PA determines the current position information of the motor based on the incremental encoded second position signal. The position signal of the motor is divided into two, and the application range and the application scene of the absolute encoder are enlarged.

Example four

Fig. 6 is a structural diagram of a motor position signal distribution system according to a fourth embodiment of the present invention, which is embodied on the basis of the foregoing embodiments. In this embodiment, the system may further include: the system comprises an absolute encoder, a Field Programmable Gate Array (FPGA) and a motor driver PA, wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. The PA receives a position signal sent by the absolute encoder when receiving a clock signal.

As described in the first embodiment, the absolute encoder may send the first position signal to the PA and the control system, respectively, so that the position signal of the motor is distributed, and the application range and the application scenario of the absolute encoder are expanded.

In this embodiment, the third clock signal and the third position signal may be transmitted by using a synchronous simplex, an asynchronous simplex, or a half-duplex transmission protocol.

Further, the FPGA comprises a second decoder and an encoder emulator; the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through a second decoder; the absolute encoder is specifically configured to: upon receiving the third clock signal, sending, by the second decoder, the third position signal to the encoder emulator.

Specifically, the second decoder may send the third clock signal to the absolute encoder, and the absolute encoder may send the third position signal to the second decoder when receiving the third clock signal, and further may send the third position signal to the encoder emulator. The encoder simulator can recode the second position signal, so that the recoded third position signal meets the transmission requirement of the current PA, and the third position signal is conveniently conveyed to the current PA and further used for controlling the current motor.

Further, the operation of the third position signal by the FPGA includes: sending, by the second decoder, the third position signal to the encoder emulator; encoding the third position signal through the encoder simulator to obtain an encoded third position signal; and when a fourth clock signal sent by the PA is received through the encoder simulator, the encoded third position signal is sent to the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

The encoder simulator can be located inside the FPGA and used for recoding the third position signal sent by the absolute encoder to obtain a coded third position signal, and the coded third position signal can be matched with the corresponding PA to output the third position signal.

Specifically, the PA may send the fourth clock signal to the encoder emulator, and the encoder emulator may send an encoded third bit signal obtained by encoding completion to the PA when receiving the fourth clock signal.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain a third encoded position signal, including: the absolute type encoder simulator encodes the third position signal to obtain an absolute type encoded third position signal; and the second incremental coding simulator codes the third position signal to obtain an incremental coding third position signal.

In this embodiment, the encoder emulator may include an absolute encoder emulator and a second incremental encoder emulator. It is understood that when the position signal is divided into two or more parts, different encoder emulators can be used for the PAs of different transmission protocols to facilitate the transmission of the position signal.

The motor position signal distribution system provided by the embodiment of the invention comprises an absolute encoder, an FPGA and a motor driver PA, wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal; the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

In addition, when receiving a third clock signal sent by the second decoder, the absolute encoder sends a third position signal to the second decoder, and the second decoder uploads the third position signal to the control system and sends the third position signal to the encoder emulator. The encoder emulator encodes the third position signal to obtain an encoded third position signal. The encoder emulator, upon receiving the fourth clock signal sent by the PA, may send an encoded third position signal to the PA to cause the PA to make a determination of the current position information of the motor based on the incrementally encoded second position signal. The position signal of the motor is divided into two, and the application range and the application scene of the absolute encoder are enlarged.

EXAMPLE five

Fig. 7 is a flowchart of a motor position signal distribution method according to a fifth embodiment of the present invention, where the motor position signal distribution method according to the present embodiment is applied to the motor position signal distribution system according to any one of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, and the method includes:

and step 710, when the absolute encoder receives the clock signal, the absolute encoder sends a position signal to the FPGA.

And 720, the FPGA sends the position signal to a control system, so that the control system determines the position information of the motor according to the position signal.

Further, the method also includes:

step 730, the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

According to the technical scheme provided by the embodiment of the invention, when the absolute encoder receives a clock signal, a position signal is sent to the FPGA; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. According to the technical scheme, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to a control system for controlling the outside through the FPGA. Further, the method further comprises: the PA receives a position signal sent by the absolute encoder when receiving a clock signal. The position signal is sent to the PA and the control system, the distribution of the position signal of the motor is further realized, and the application range and the application scene of the absolute encoder are enlarged.

On the basis of the above technical solution, the clock signal received by the absolute encoder is a first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

the absolute encoder, upon receiving the first clock signal,

sending a first position signal to the PA through the second single-ended to single-ended conversion chip and the third single-ended to differential conversion chip, so that the PA determines the current position information of the motor based on the first position information;

and the first position signal is sent to the FPGA through the second single-end-to-single-end conversion chip and the fourth single-end-to-differential chip.

On the basis of the technical scheme, the FPGA comprises a first decoder and a first enhanced encoder simulator,

the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder;

correspondingly, the absolute encoder sends a second position signal to the first enhanced encoder emulator through the first decoder when receiving the second clock signal.

The operation of the FPGA on the second position signal comprises the following steps:

sending, by the first decoder, the second position signal to the first incremental encoder emulator;

and coding the second position signal through the first incremental encoder simulator to obtain an incremental encoded second position signal, and then sending the incremental encoded second position signal to the PA, so that the PA determines the current position information of the motor based on the incremental encoded second position signal.

Further, the step of the FPGA coding the second position signal through the first incremental encoder simulator to obtain an incrementally coded second position signal includes:

the FPGA determines a preset bit of the second position signal as a criterion bit through the first incremental encoder simulator;

and the FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

On the basis of the technical scheme, the FPGA comprises a second decoder and an encoder simulator,

the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through a second decoder;

and when receiving the third clock signal, the absolute encoder sends the third position signal to the encoder emulator through the second decoder.

On the basis of the above technical solution, the operation step of the FPGA on the third position signal includes:

sending, by the second decoder, the third position signal to the encoder emulator;

encoding the third position signal through the encoder simulator to obtain an encoded third position signal;

and when a fourth clock signal sent by the PA is received through the encoder simulator, the encoded third position signal is sent to the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain a third encoded position signal, including:

the absolute type encoder simulator encodes the third position signal to obtain an absolute type encoded third position signal;

and the second incremental coding simulator codes the third position signal to obtain an incremental coding third position signal.

The motor position signal distribution method provided by the embodiment of the invention can be applied to the motor position signal distribution system provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the system.

EXAMPLE six

Fig. 8 is a schematic structural diagram of a motor system according to a sixth embodiment of the present invention, and as shown in fig. 8, the motor system includes a motor system and a motor; the servo motor can be used for controlling the speed, the position precision of the servo motor is very accurate, and a voltage signal can be converted into torque and rotating speed to drive a control object; the motor system is used for determining a position signal of the motor.

The motor system provided by the embodiment of the invention can comprise the motor position signal distribution system provided by the embodiment, and has corresponding functions and beneficial effects.

From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.

It should be noted that, in the embodiment of the motor position signal distribution system, the units and modules included in the embodiment are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A motor position signal distribution system, comprising: an absolute encoder and a field programmable gate array FPGA,

when the absolute encoder receives a clock signal, a position signal is sent to the FPGA;

and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal.

2. The motor position signal distribution system of claim 1, further comprising: the motor driver PA is provided with a motor driver,

the PA receives a position signal sent by the absolute encoder when receiving a clock signal.

3. The motor position signal distribution system of claim 2, further comprising a first single-to-single-ended chip, a second single-to-single-ended chip, a first single-to-differential chip, a second single-to-differential chip, a third single-to-differential chip, and a fourth single-to-differential chip,

a clock signal received by the absolute encoder is a first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

the absolute encoder, upon receiving the first clock signal,

sending a first position signal to the PA through the second single-ended to single-ended conversion chip and the third single-ended to differential conversion chip, so that the PA determines the current position information of the motor based on the first position information;

and sending the first position signal to the FPGA through the second single-end-to-single-end chip and the fourth single-end-to-differential chip.

4. The motor position signal distribution system of claim 2, wherein the FPGA includes a first decoder and a first enhanced encoder emulator,

the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder;

correspondingly, the absolute encoder sends a second position signal to the first enhanced encoder emulator through the first decoder when receiving the second clock signal.

5. The motor position signal distribution system of claim 4, wherein the step of operating the second position signal by the FPGA comprises:

sending, by the first decoder, the second position signal to the first incremental encoder emulator;

and coding the second position signal through the first incremental encoder simulator to obtain an incremental encoded second position signal, and then sending the incremental encoded second position signal to the PA, so that the PA determines the current position information of the motor based on the incremental encoded second position signal.

6. The motor position signal distribution system of claim 5, wherein the FPGA encodes the second position signal via the first incremental encoder emulator, and wherein the step of incrementally encoding the second position signal comprises:

the FPGA determines a preset bit of the second position signal as a criterion bit through the first incremental encoder simulator;

and the FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

7. The motor position signal distribution system of claim 2, wherein the FPGA includes a second decoder and an encoder emulator,

the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through a second decoder;

and when receiving the third clock signal, the absolute encoder sends the third position signal to the encoder emulator through the second decoder.

8. The motor position signal distribution system of claim 7, wherein the step of operating the third position signal by the FPGA comprises:

sending, by the second decoder, the third position signal to the encoder emulator;

encoding the third position signal through the encoder simulator to obtain an encoded third position signal;

and when a fourth clock signal sent by the PA is received through the encoder simulator, the encoded third position signal is sent to the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

9. The motor position signal distribution system of claim 8, wherein the encoder emulator includes an absolute encoder emulator and a second incremental encoder emulator, the encoder emulator encoding the third position signal resulting in the step of encoding a third position signal comprising:

the absolute type encoder simulator encodes the third position signal to obtain an absolute type encoded third position signal;

and the second incremental coding simulator codes the third position signal to obtain an incremental coding third position signal.

10. A motor position signal distribution method applied to the motor position signal distribution system according to any one of claims 1 to 9, characterized by comprising:

when receiving a clock signal, the absolute encoder sends a position signal to the FPGA;

and the FPGA sends the position signal to a control system so that the control system determines the position information of the motor according to the position signal.

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