CN114696711A - Motor position signal distribution system and method - Google Patents

Abstract

The invention discloses a motor position signal distribution system and a method, which comprises the following steps: the system comprises an absolute encoder and a Field Programmable Gate Array (FPGA), wherein the absolute encoder sends a position signal to the FPGA when receiving a clock signal; and the FPGA sends the position signal to an external control system so that the control system determines the current position information of the motor according to the position signal. According to the technical scheme, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to a control system for controlling the outside through the FPGA, the distribution of the position signal of the motor is realized, and the application range and the application scene of the absolute encoder are enlarged.

Description

A motor position signal distribution system and method

technical field

Embodiments of the present invention relate to the technical field of motors, and in particular, to a system and method for distributing motor position signals.

Background technique

The requirements of modern processing technology for processing accuracy and processing efficiency have given birth to the birth of servo motor control system. In order to ensure the precise positioning of the operating object, the servo motor control system needs to obtain the precise position information of the motor.

In the prior art, an encoder can be used to obtain the position information of a single machine. However, the incremental encoder cannot directly know the current actual position of the motor after it is powered on. It needs to move the motor to the point where the electrical phase triggers the limit sensor to obtain 0 bits to correctly capture the current position of the motor; the absolute encoder can be powered on. To obtain the actual position of the current motor, it is not necessary to calibrate the position through the limit sensor, but the absolute encoder usually communicates through the synchronous/asynchronous protocol, and it is relatively difficult to divide the signal. At the same time, commercial motor drive modules usually do not disclose the internal structure to the outside world, so it is impossible to output position signals in real time to the upper control system by changing their internal hardware or software structure.

Therefore, there is an urgent need for a motor position signal distribution system, which can obtain the position signal of the motor and upload the position signal to the control system.

SUMMARY OF THE INVENTION

The present invention provides a motor position signal distribution system and method, so as to obtain the position signal of the motor and upload the position signal to the control system.

In a first aspect, an embodiment of the present invention provides a motor position signal distribution system, including: an absolute encoder and an FPGA,

When the absolute encoder receives the clock signal, it sends the position signal to the FPGA;

The FPGA sends the position signal to an external control system, so that the control system determines the current position information of the motor according to the position signal.

Further, the system further includes: a motor driver PA,

The PA receives the position signal sent by the absolute encoder when the clock signal is received.

Further, the system further includes a first differential-to-single-ended chip, a second differential-to-single-ended chip, a first single-ended-to-differential chip, a second single-ended-to-differential chip, a third single-ended-to-differential chip, and a fourth Single-ended to differential chip,

The clock signal received by the absolute encoder is the first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

When the absolute encoder receives the first clock signal,

A first position signal is sent to the PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the PA determines the current position information of the motor based on the first position information ;

The first position signal is sent to the FPGA through the second differential-to-single-ended chip and the fourth single-ended-to-differential chip.

Further, the FPGA includes a first decoder and a first enhanced encoder emulator,

The clock signal received by the absolute encoder is the second clock signal sent by the FPGA through the first decoder;

Correspondingly, when the absolute encoder receives the second clock signal, the second position signal is sent to the first enhanced encoder emulator through the first decoder.

Further, the operation steps of the FPGA on the second position signal include:

sending the second position signal to the first incremental encoder emulator through the first decoder;

The second position signal is encoded by the first incremental encoder simulator, and after the incrementally encoded second position signal is obtained, the incrementally encoded second position signal is sent to the PA, so that the PA determines the current position information of the motor based on the incrementally encoded second position signal.

Further, the FPGA encodes the second position signal through the first incremental encoder simulator, and the step of obtaining the incrementally encoded second position signal includes:

The FPGA determines the preset position of the second position signal as a criterion position through the first incremental encoder simulator;

The FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

Further, the FPGA includes a second decoder and an encoder emulator,

The clock signal received by the absolute encoder is the third clock signal sent by the FPGA through the second decoder;

When the absolute encoder receives the third clock signal, the third position signal is sent to the encoder emulator through the second decoder.

Further, the operation steps of the FPGA on the third position signal include:

sending the third position signal to the encoder emulator through the second decoder;

Encoding the third position signal by the encoder simulator to obtain an encoded third position signal;

When receiving the fourth clock signal sent by the PA, the encoder emulator sends the encoded third position signal to the PA, so that the PA performs motor motor based on the encoded third position signal Determination of current location information.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain an encoded third position signal. steps, including:

The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal;

The second incremental encoding simulator encodes the third position signal to obtain an incrementally encoded third position signal.

In a second aspect, an embodiment of the present invention further provides a motor position signal distribution method, which is applied to the motor position signal distribution system described in the first aspect, and the method includes:

When the absolute encoder receives the clock signal, it sends the position signal to the FPGA;

The FPGA sends the position signal to the control system, so that the control system determines the position information of the motor according to the position signal.

An embodiment of the present invention provides a motor position signal distribution system, including: an absolute encoder and a field programmable logic gate array FPGA, where the absolute encoder sends a position signal to the FPGA when receiving a clock signal ; The FPGA sends the position signal to an external control system, so that the control system determines the current position information of the motor according to the position signal. In the above technical solution, when the absolute encoder receives the clock signal, it can upload the position signal of the motor to the control system that controls the outside world through the FPGA, which realizes the distribution of the position signal of the motor and expands the application range and application of the absolute encoder. Scenes.

Description of drawings

1 is a structural diagram of a motor position signal distribution system according to Embodiment 1 of the present invention;

2 is a structural diagram of a motor position signal distribution system according to Embodiment 2 of the present invention;

3 is a structural diagram of a motor position signal distribution system according to Embodiment 3 of the present invention;

4 is a schematic diagram of an output signal of a first incremental encoder simulator provided in Embodiment 3 of the present invention;

5 is a schematic diagram of an output signal of another first incremental encoder simulator provided in Embodiment 3 of the present invention;

6 is a structural diagram of a motor position signal distribution system according to Embodiment 4 of the present invention;

7 is a flowchart of a method for distributing a motor position signal according to Embodiment 5 of the present invention;

FIG. 8 is a schematic structural diagram of a motor system according to Embodiment 6 of the present invention.

Reference number:

The first differential-to-single-ended chip-210, the second differential-to-single-ended chip-220, the first single-ended-to-differential chip-230, the second single-ended-to-differential chip-240, the third single-ended-to-differential chip-250 and The fourth single-ended to differential chip-260.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

Before discussing the exemplary embodiments in greater detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts various operations (or steps) as a sequential process, many of the operations may be performed in parallel, concurrently, or concurrently. Additionally, the order of operations can be rearranged. The process may be terminated when its operation is complete, but may also have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, subroutines, and the like. Furthermore, the embodiments of the invention and the features of the embodiments may be combined with each other without conflict.

Example 1

FIG. 1 is a structural diagram of a motor position signal distribution system provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation where the motor position signal needs to be uploaded to a control system. The system includes: an absolute encoder and an FPGA, When the absolute encoder receives a clock signal, it sends a position signal to the FPGA; the FPGA sends the position signal to an external control system, so that the control system determines the motor according to the position signal current location information.

Among them, the encoder is a device that compiles and converts signals or data into signals that can be used for communication, transmission and storage. The encoder converts angular displacement or linear displacement into electrical signals, the former is called a code wheel, and the latter is called a code ruler. Each position of the absolute encoder corresponds to a certain digital code, so its indication is only related to the starting and ending positions of the measurement, and has nothing to do with the intermediate process of the measurement.

FPGA belongs to a kind of semi-custom circuit in the application-specific integrated circuit. It is a programmable logic array, which can effectively solve the problem that the number of original device gate circuits is small.

Specifically, when the absolute encoder receives the clock signal, the position signal of the motor can be sent to the external control system through the FPGA. The control system can store and process the position signal in the host computer.

It can be known that the transmission protocol of the clock signal and the position signal may include a synchronous simplex protocol, an asynchronous simplex protocol and a half-duplex protocol.

When the transmission protocol is a synchronous simplex protocol, when the absolute encoder receives the clock signal through the first channel, it can send the position signal to the FPGA through the second channel. After the FPGA receives the position signal, the absolute encoder continues to send Position signal to FPGA; when the transmission protocol is asynchronous simplex protocol, when the absolute encoder receives the clock signal through the first channel, it can continuously send the position signal to the FPGA through the second channel; when the transmission protocol is half-duplex During the protocol, after receiving the clock signal through the third channel, the absolute encoder can send the position signal to the FPGA through the third channel.

Further, the system further includes: a motor driver PA, the PA is configured to receive the position signal sent by the absolute encoder when the clock signal is received.

Among them, different PAs can receive position signals of different protocols, and corresponding to different PAs, FPGA or an external chip can be used to convert their protocol types.

Motor driver, also known as servo driver, servo controller and servo amplifier, can be used to control servo motors. Its function is similar to that of frequency converters acting on ordinary AC motors. It is part of the servo system and is mainly used in high-precision positioning systems. Generally, the servo motor is controlled by three methods of position, speed and torque to achieve high-precision positioning of the transmission system. It is currently a high-end product of transmission technology.

In the technical solution of this embodiment, the motor position signal distribution system includes an absolute encoder and an FPGA, the absolute encoder sends a position signal to the FPGA when receiving a clock signal; the FPGA sends the position signal It is sent to an external control system, so that the control system determines the current position information of the motor according to the position signal. In the above technical solution, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to the external control system through the FPGA. Further, the system further includes: a motor driver PA, and the PA receives the position signal sent by the absolute encoder when the clock signal is received. It realizes sending the position signal to the PA and control system, further realizes the distribution of the position signal of the motor, and expands the application scope and application scenarios of the absolute encoder.

Embodiment 2

FIG. 2 is a structural diagram of a motor position signal distribution system according to Embodiment 2 of the present invention. This embodiment is embodied on the basis of the foregoing embodiment. In this embodiment, the system may further include: an absolute encoder, a field programmable logic gate array FPGA and a motor driver PA, the absolute encoder sends the first position signal when receiving the first clock signal to the FPGA; the FPGA sends the first position signal to an external control system, so that the control system determines the current position information of the motor according to the first position signal. The PA receives the first position signal sent by the absolute encoder upon receiving the first clock signal.

As described in the first embodiment, the absolute encoder can send the first position signal to the PA and the control system respectively, which realizes the distribution of the position signal of the motor and expands the application scope and application scenarios of the absolute encoder.

In this embodiment, the first clock signal and the first position signal may be transmitted using a synchronous simplex transmission protocol.

Further, the system further includes a first differential-to-single-ended chip 210, a second differential-to-single-ended chip 220, a first single-ended-to-differential chip 230, a second single-ended-to-differential chip 240, and a third single-ended-to-differential chip. chip 250 and a fourth single-ended-to-differential chip 260; the clock signal received by the absolute encoder is sent by the PA through the first differential-to-single-ended chip 210 and the first single-ended-to-differential chip 230 The first clock signal; the absolute encoder is specifically used for: when receiving the first clock signal, through the second differential to single-ended chip 220 and the third single-ended to differential chip 250 A position signal is sent to the PA, so that the PA determines the current position information of the motor based on the first position information; through the second differential-to-single-ended chip 220 and the fourth single-ended-to-differential chip 260 sends the first position signal to the FPGA.

In addition, the PA can also send the first clock signal to the FPGA through the second single-ended to differential chip 240 .

Among them, the differential to single-ended chip is also called the encoder signal conversion module, which can be used to solve the conversion interface between the rotary encoder, the differential mode output of the grating scale, the single-chip microcomputer, and the PLC controller. It can overcome the strong interference in the complex field environment of the industrial control system, eliminate the electrical interference such as strong electric field and strong magnetic field, and can effectively protect the more sensitive circuits. a secure interface.

Differential signals have strong anti-common mode interference ability and are suitable for long-distance transmission, while single-ended signals do not have this function. Single-ended to differential chips are also called single-ended-to-differential converters.

In this embodiment, the PA can act as the master station to output the first clock signal and receive the first position signal from the absolute encoder, and the absolute encoder can act as the slave station to receive the first clock signal from the PA, and simultaneously output and For the first position signal synchronized by the first clock signal, the FPGA, as a slave station, receives the first position signal from the absolute encoder and also receives the synchronized first clock signal from the PA.

Specifically, when the PA sends a synchronous first clock signal, the clock+ and clock- are converted from differential signals to single-ended signals at the first differential-to-single-ended chip 210, and then divided into two channels: the first single-ended to differential signals The chip 230 is converted into clock 1+ and clock 1-, and sent to the absolute encoder; at the second single-ended to differential chip 240, it is converted into clock 2+ and clock 2-, and sent to the FPGA chip. When the absolute encoder receives the first clock signal from the PA, the absolute encoder starts to output the first position signal, and the data + and data - are converted from differential signals to single-ended signals at the 220 second differential to single-ended chip. , and then divided into two channels: at the third single-ended to differential chip 250, it is converted into data 1+ and data 1-, and sent to the PA; at the fourth single-ended to differential chip 260, it is converted into data 2+ and data 2- , sent to the FPGA chip. After receiving the clock 2+, clock 2-, data 2+, and data 2-, the FPGA processes the data through the internal encoder signal monitoring code, converts it into a first position signal, and uploads it to the upper-level control system.

It should be noted that the FPGA starts to receive the first position signal when monitoring the rising edge of the first position signal, and sends the first position signal to the control system after receiving the first position signal.

Specifically, taking the biss-c protocol as an example, first monitor the falling edge of the clock to determine whether the PA clock signal starts; when the PA clock starts, start monitoring the rising edge of the encoder signal output to determine whether the encoder signal conversion is complete; When the signal conversion is completed, the signal reception process starts.

The motor position signal distribution system provided by the embodiment of the present invention includes an absolute encoder, an FPGA, and a motor driver PA. When receiving a clock signal, the absolute encoder sends a position signal to the FPGA; the FPGA sends all the signals to the FPGA. The position signal is sent to an external control system, so that the control system determines the current position information of the motor according to the position signal; the PA receives the position signal sent by the absolute encoder when the clock signal is received.

In addition, when the absolute encoder receives the clock signal through the differential to single-ended chip and the single-ended to differential chip, the position signal of the motor can be uploaded to the external controller through the differential to single-ended chip, the single-ended to differential chip and the FPGA. The control system can also send the position signal to the PA through the differential-to-single-end chip and the single-end-to-differential chip, which realizes one-half of the motor's position signal and expands the application scope and application scenarios of the absolute encoder.

Embodiment 3

FIG. 3 is a structural diagram of a motor position signal distribution system according to Embodiment 3 of the present invention. This embodiment is embodied on the basis of the foregoing embodiment. In this embodiment, the system may further include: an absolute encoder, a field programmable logic gate array FPGA and a motor driver PA, the absolute encoder sends the second position signal when receiving the second clock signal to the FPGA; the FPGA sends the second position signal to an external control system, so that the control system determines the current position information of the motor according to the second position signal. The PA receives the second position signal sent by the absolute encoder when the second clock signal is received.

As described in the first embodiment, the absolute encoder can send the second position signal to the PA and the control system respectively, which realizes the distribution of the position signal of the motor and expands the application scope and application scenarios of the absolute encoder.

In this embodiment, the second clock signal and the second position signal may be transmitted using a synchronous simplex, asynchronous simplex or half-duplex transmission protocol.

Further, the FPGA includes a first decoder and a first enhanced encoder emulator; the clock signal received by the absolute encoder is a second clock signal sent by the FPGA through the first decoder; corresponding The absolute encoder is specifically configured to: when receiving the second clock signal, send a second position signal to the first enhanced encoder emulator through the first decoder.

Specifically, the first decoder can send the second clock signal to the absolute encoder, and when the absolute encoder receives the second clock signal, it can send the second position signal to the first decoder, and further can also send the second position signal to the first decoder. The second position signal is sent to the first enhanced encoder emulator. The first enhanced encoder simulator can re-encode the second position signal, so that the re-encoded second position signal meets the transmission requirements of the current PA, so that the second position signal can be transmitted to the current PA, and then used to control the current motor .

Further, the operation steps of the FPGA on the second position signal include: sending the second position signal to the first incremental encoder simulator through the first decoder; An incremental encoder simulator encodes the second position signal, and after obtaining the incrementally encoded second position signal, sends the incrementally encoded second position signal to the PA, so that the The PA determines the current position information of the motor based on the incrementally encoded second position signal.

The enhanced encoder simulator can be located inside the FPGA to re-encode the second position signal sent by the absolute encoder to obtain the enhanced encoded second position signal, which can be matched with the corresponding PA to output the second position Signal.

Specifically, the first decoder of the FPGA may receive the second position signal, and send the second position signal to the first incremental encoder simulator.

Further, the FPGA encodes the second position signal through the first incremental encoder simulator, and the step of obtaining the incrementally encoded second position signal includes:

The FPGA determines the preset bit of the second position signal as a criterion bit through the first incremental encoder simulator.

The FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

FIG. 4 is a schematic diagram of an output signal of a first incremental encoder simulator provided in Embodiment 3 of the present invention; as shown in FIG. 4 , if bits 3 and 4 of the absolute encoder are taken as the Criterion bit, then the corresponding A, B-phase signal output is shown in Figure 4, take the 4th bit signal as the A-phase signal, and perform XOR operation on the 3rd and 4th bit codes to obtain the corresponding incremental coding The B-phase signal of the device.

FIG. 5 is a schematic diagram of the output signal of another first incremental encoder simulator provided in Embodiment 3 of the present invention. As shown in FIG. 5 , if bits 3 and 4 of the absolute encoder are taken as the incremental encoder , then the length of a complete cycle of the corresponding A or B phase is 10000 (binary) count bits of the absolute encoder. Considering that the incremental encoder usually needs to perform quadruple frequency operation, the corresponding incremental The encoder signal 1count(C _I ) of the formula encoder is equal to the absolute encoder signal count(C _A ) which is 100 (binary) times. Converted to decimal, it is:

C _I =(2^2)*C _A

The accuracy of the incremental second position signal converted by the absolute encoder is directly related to the decoding cycle of the absolute encoder and the speed of the motor moving. If the absolute encoder 1count=C _A =50nm, the decoding period T _d =20us, and the maximum moving speed of the motor V=100mm/s, the maximum change of the absolute signal in two adjacent periods is (T _d *V)/ CA ₌ 40 counts. In order to ensure the real reliability of the converted incremental second position signal, it must be ensured that the incremental encoder 1count=C _I =(2^n)*C _A >2*40*C _A =4um, that is to say , the low-order n used for judgment in the absolute encoder signal must ensure that (2^n)>40*2=80, and the corresponding n≥7, the minimum judgment bits of the absolute encoder are 8 and 7 bits.

According to the above algorithm, the minimum resolution of the incremental second position signal output by the FPGA under different working environments can be determined.

The absolute rotation incremental scheme of the position signal is mainly aimed at the encoder protocol of synchronous simplex, asynchronous simplex or half-duplex. The absolute encoder of this protocol has two-way signal communication with the PA, so it is difficult to achieve a front-end one. Divide into two. Through the above method, not only can the second position signal be divided into two, but also the one-to-many requirement of the second position signal can be satisfied.

In this embodiment, the FPGA can act as the master station to output the second clock signal and receive the second position signal from the absolute encoder, and the absolute encoder can act as the slave station to receive the second clock signal from the FPGA, and simultaneously output and The second position signal is synchronized with the second clock signal. The FPGA can also upload the second position signal to the control system.

This embodiment does not require a front-end hardware architecture, and only needs an FPGA and a PA to achieve the requirement of dividing the position signal into two.

The motor position signal distribution system provided by the embodiment of the present invention includes an absolute encoder, an FPGA, and a motor driver PA. When receiving a clock signal, the absolute encoder sends a position signal to the FPGA; the FPGA sends all the signals to the FPGA. The position signal is sent to an external control system, so that the control system determines the current position information of the motor according to the position signal; the PA receives the position signal sent by the absolute encoder when the clock signal is received.

In addition, when the absolute encoder receives the second clock signal sent by the first decoder, it sends the second position signal to the first decoder, and the first decoder further uploads the second position signal to the control system, and sends the second position signal to the control system. The first incremental encoder simulator. The first incremental encoder emulator encodes the second position signal, and after obtaining the incrementally encoded second position signal, sends the incrementally encoded second position signal to the PA to obtain the incrementally encoded second position signal. The PA is caused to determine the current position information of the motor based on the incrementally encoded second position signal. The position signal of the motor is divided into two, and the application scope and application scenarios of the absolute encoder are expanded.

Embodiment 4

FIG. 6 is a structural diagram of a motor position signal distribution system according to Embodiment 4 of the present invention. This embodiment is embodied on the basis of the foregoing embodiment. In this embodiment, the system may further include: an absolute encoder, a field programmable logic gate array FPGA, and a motor driver PA, and the absolute encoder sends a position signal to the FPGA when receiving a clock signal ; The FPGA sends the position signal to an external control system, so that the control system determines the current position information of the motor according to the position signal. The PA receives the position signal sent by the absolute encoder when the clock signal is received.

As described in the first embodiment, the absolute encoder can send the first position signal to the PA and the control system respectively, which realizes the distribution of the position signal of the motor and expands the application scope and application scenarios of the absolute encoder.

In this embodiment, the third clock signal and the third position signal may be transmitted using a synchronous simplex, asynchronous simplex or half-duplex transmission protocol.

Further, the FPGA includes a second decoder and an encoder emulator; the clock signal received by the absolute encoder is a third clock signal sent by the FPGA through the second decoder; the absolute encoder specifically for: sending the third position signal to the encoder emulator through the second decoder when the third clock signal is received.

Specifically, the second decoder can send the third clock signal to the absolute encoder, and when the absolute encoder receives the third clock signal, it can send the third position signal to the second decoder, and further can also send the third position signal to the second decoder. The third position signal is sent to the encoder emulator. The encoder simulator can re-encode the second position signal, so that the re-encoded third position signal meets the transmission requirements of the current PA, so that the third position signal can be transmitted to the current PA, and then used to control the current motor.

Further, the operation steps of the FPGA on the third position signal include: sending the third position signal to the encoder simulator through the second decoder; The third position signal is encoded to obtain the encoded third position signal; when the encoder emulator receives the fourth clock signal sent by the PA, the encoded third position signal is sent to the PA, so that the PA determines the current position information of the motor based on the encoded third position signal.

The encoder simulator can be located inside the FPGA, and is used to re-encode the third position signal sent by the absolute encoder to obtain the encoded third position signal, which can be matched with the corresponding PA to output the third position signal.

Specifically, the PA may send the fourth clock signal to the encoder emulator, and when receiving the fourth clock signal, the encoder emulator may send the encoded third position signal obtained after encoding to the PA.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain an encoded third position signal. The steps include: the absolute encoder emulator encodes the third position signal to obtain an absolute encoded third position signal; the second incremental encoder emulator encodes the third position signal , to obtain the incrementally encoded third position signal.

In this embodiment, the encoder simulator may include an absolute encoder simulator and a second incremental encoder simulator. It can be known that when the position signal is divided into two or more than one, different encoder emulators can be used for PAs with different transmission protocols, which is convenient for the transmission of the position signal.

The motor position signal distribution system provided by the embodiment of the present invention includes an absolute encoder, an FPGA, and a motor driver PA. When receiving a clock signal, the absolute encoder sends a position signal to the FPGA; the FPGA sends all the signals to the FPGA. The position signal is sent to an external control system, so that the control system determines the current position information of the motor according to the position signal; the PA receives the position signal sent by the absolute encoder when the clock signal is received.

In addition, when the absolute encoder receives the third clock signal sent by the second decoder, it sends the third position signal to the second decoder, and the second decoder further uploads the third position signal to the control system, and sends the third position signal to the control system. Encoder emulator. The encoder simulator encodes the third position signal to obtain the encoded third position signal. When receiving the fourth clock signal sent by the PA, the encoder simulator may send the encoded third position signal to the PA, so that the PA determines the current position information of the motor based on the incrementally encoded second position signal . The position signal of the motor is divided into two, and the application scope and application scenarios of the absolute encoder are expanded.

Embodiment 5

7 is a flowchart of a method for distributing a motor position signal according to Embodiment 5 of the present invention. The method for distributing a motor position signal adopted in this embodiment is applied to any one of Embodiment 1, Embodiment 2, Embodiment 3 and Embodiment 4 In the motor position signal distribution system, the method includes:

Step 710: When the absolute encoder receives the clock signal, it sends the position signal to the FPGA.

Step 720: The FPGA sends the position signal to the control system, so that the control system determines the position information of the motor according to the position signal.

Further, the method also includes:

Step 730: The PA receives the position signal sent by the absolute encoder when the clock signal is received.

According to the technical solution provided by the embodiment of the present invention, when the absolute encoder receives a clock signal, it sends a position signal to the FPGA; the FPGA sends the position signal to an external control system, so that the The control system determines the current position information of the motor according to the position signal. In the above technical solution, when the absolute encoder receives the clock signal, the position signal of the motor can be uploaded to the external control system through the FPGA. Further, the method further includes: receiving, by the PA, a position signal sent by the absolute encoder when the clock signal is received. It realizes sending the position signal to the PA and control system, further realizes the distribution of the position signal of the motor, and expands the application scope and application scenarios of the absolute encoder.

Based on the above technical solution, the clock signal received by the absolute encoder is the first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip;

When the absolute encoder receives the first clock signal,

A first position signal is sent to the PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the PA determines the current position information of the motor based on the first position information ;

The first position signal is sent to the FPGA through the second differential-to-single-ended chip and the fourth single-ended-to-differential chip.

On the basis of the above technical solution, the FPGA includes a first decoder and a first enhanced encoder emulator,

The clock signal received by the absolute encoder is the second clock signal sent by the FPGA through the first decoder;

Correspondingly, when the absolute encoder receives the second clock signal, the second position signal is sent to the first enhanced encoder emulator through the first decoder.

The operation steps of the FPGA on the second position signal include:

sending the second position signal to the first incremental encoder emulator through the first decoder;

The second position signal is encoded by the first incremental encoder simulator, and after the incrementally encoded second position signal is obtained, the incrementally encoded second position signal is sent to the PA, so that the PA determines the current position information of the motor based on the incrementally encoded second position signal.

Further, the FPGA encodes the second position signal through the first incremental encoder simulator, and the step of obtaining the incrementally encoded second position signal includes:

The FPGA determines the preset position of the second position signal as a criterion position through the first incremental encoder simulator;

The FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator.

On the basis of the above technical solution, the FPGA includes a second decoder and an encoder simulator,

The clock signal received by the absolute encoder is the third clock signal sent by the FPGA through the second decoder;

When the absolute encoder receives the third clock signal, the third position signal is sent to the encoder emulator through the second decoder.

On the basis of the above technical solution, the operation steps of the FPGA on the third position signal include:

sending the third position signal to the encoder emulator through the second decoder;

Encoding the third position signal by the encoder simulator to obtain an encoded third position signal;

When receiving the fourth clock signal sent by the PA, the encoder emulator sends the encoded third position signal to the PA, so that the PA performs motor motor based on the encoded third position signal Determination of current location information.

Further, the encoder simulator includes an absolute encoder simulator and a second incremental encoder simulator, and the encoder simulator encodes the third position signal to obtain an encoded third position signal. steps, including:

The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal;

The second incremental encoding simulator encodes the third position signal to obtain an incrementally encoded third position signal.

The motor position signal distribution method provided by the embodiment of the present invention can be applied to the motor position signal distribution system provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects of the above system.

Embodiment 6

FIG. 8 is a schematic structural diagram of a motor system according to Embodiment 6 of the present invention. As shown in FIG. 8 , the system includes a motor system and a motor; the servo motor can be used to control the speed, and its position accuracy is very accurate, and the voltage can be The signal is converted into torque and speed to drive the control object; the motor system is used to determine the position signal of the motor.

The motor system provided by the embodiment of the present invention may include the motor position signal distribution system provided by the above embodiment, and has corresponding functions and beneficial effects.

From the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be realized by software and necessary general-purpose hardware, and of course can also be realized by hardware, but in many cases the former is a better embodiment . Based on such understanding, the technical solutions of the present invention can be embodied in the form of software products in essence or the parts that make contributions to the prior art, and the computer software products can be stored in a computer-readable storage medium, such as a floppy disk of a computer , read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), flash memory (FLASH), hard disk or CD, etc., including several instructions to make a computer device (which can be a personal computer, A server, or a network device, etc.) executes the methods described in the various embodiments of the present invention.

It is worth noting that, in the above-mentioned embodiment of the motor position signal distribution system, the units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; , the specific names of the functional units are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present invention.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention. The scope is determined by the scope of the appended claims.

Claims (10)

1. a motor position signal distribution system, is characterized in that, comprises: absolute encoder and field programmable logic gate array FPGA, When the absolute encoder receives the clock signal, it sends the position signal to the FPGA; The FPGA sends the position signal to an external control system, so that the control system determines the current position information of the motor according to the position signal. 2. The motor position signal distribution system according to claim 1, wherein the system further comprises: a motor driver PA, The PA receives the position signal sent by the absolute encoder when the clock signal is received. 3. The motor position signal distribution system according to claim 2, wherein the system further comprises a first differential-to-single-ended chip, a second differential-to-single-ended chip, a first single-ended-to-differential chip, a second differential-to-single-ended chip, Single-ended to differential chip, third single-ended to differential chip and fourth single-ended to differential chip, The clock signal received by the absolute encoder is the first clock signal sent by the PA through the first differential-to-single-ended chip and the first single-ended-to-differential chip; When the absolute encoder receives the first clock signal, A first position signal is sent to the PA through the second differential-to-single-ended chip and the third single-ended-to-differential chip, so that the PA determines the current position information of the motor based on the first position information ; The first position signal is sent to the FPGA through the second differential-to-single-ended chip and the fourth single-ended-to-differential chip. 4. The motor position signal distribution system according to claim 2, wherein the FPGA comprises a first decoder and a first enhanced encoder emulator, The clock signal received by the absolute encoder is the second clock signal sent by the FPGA through the first decoder; Correspondingly, when the absolute encoder receives the second clock signal, the second position signal is sent to the first enhanced encoder emulator through the first decoder. 5. The motor position signal distribution system according to claim 4, wherein the operation step of the FPGA on the second position signal comprises: sending the second position signal to the first incremental encoder emulator through the first decoder; The second position signal is encoded by the first incremental encoder simulator, and after the incrementally encoded second position signal is obtained, the incrementally encoded second position signal is sent to the PA, so that the PA determines the current position information of the motor based on the incrementally encoded second position signal. 6 . The motor position signal distribution system according to claim 5 , wherein the FPGA encodes the second position signal through the first incremental encoder simulator to obtain the incrementally encoded first position signal. 7 . The steps of the two-position signal include: The FPGA determines the preset position of the second position signal as a criterion position through the first incremental encoder simulator; The FPGA determines the incremental second position signal according to the criterion bit through the first incremental encoder simulator. 7. The motor position signal distribution system according to claim 2, wherein the FPGA comprises a second decoder and an encoder simulator, The clock signal received by the absolute encoder is the third clock signal sent by the FPGA through the second decoder; When the absolute encoder receives the third clock signal, the third position signal is sent to the encoder emulator through the second decoder. 8. The motor position signal distribution system according to claim 7, wherein the operation step of the FPGA on the third position signal comprises: sending the third position signal to the encoder emulator through the second decoder; Encoding the third position signal by the encoder simulator to obtain an encoded third position signal; When receiving the fourth clock signal sent by the PA, the encoder emulator sends the encoded third position signal to the PA, so that the PA performs motor motor based on the encoded third position signal Determination of current location information. 9. The motor position signal distribution system according to claim 8, wherein the encoder emulator comprises an absolute encoder emulator and a second incremental encoder emulator, and the encoder emulator The third position signal is encoded to obtain the step of encoding the third position signal, including: The absolute encoder simulator encodes the third position signal to obtain an absolute encoded third position signal; The second incremental encoding simulator encodes the third position signal to obtain an incrementally encoded third position signal. 10. A method for distributing a motor position signal, applied to the motor position signal distribution system according to any one of claims 1-9, wherein the method comprises: When the absolute encoder receives the clock signal, it sends the position signal to the FPGA; The FPGA sends the position signal to the control system, so that the control system determines the position information of the motor according to the position signal.

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