CN114695224A - 芯片键合对准结构与键合芯片结构及其制作方法 - Google Patents

芯片键合对准结构与键合芯片结构及其制作方法 Download PDF

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CN114695224A
CN114695224A CN202011589292.9A CN202011589292A CN114695224A CN 114695224 A CN114695224 A CN 114695224A CN 202011589292 A CN202011589292 A CN 202011589292A CN 114695224 A CN114695224 A CN 114695224A
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metal
etch stop
chip
bonding surface
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杨晋嘉
蔡馥郁
林大钧
蔡滨祥
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United Microelectronics Corp
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Abstract

本发明公开一种芯片键合对准结构与键合芯片结构及其制作方法，其中该芯片键合对准结构包括:半导体芯片、金属层、蚀刻停止层、至少一个金属凸丘、介电阻障层、硅氧化物层以及碳氮化硅层。金属层位于半导体芯片的键合表面，具有一个金属对准图案。蚀刻停止层覆盖于键合表面和该金属层上。金属凸丘由金属层向上延伸穿过蚀刻停止层，介电阻障层覆盖于蚀刻停止层和金属凸丘上。硅氧化物层覆盖于介电阻障层上。碳氮化硅层覆盖于硅氧化物层上。

Description

芯片键合对准结构与键合芯片结构及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，特别是涉及一种半导体芯片键合技术的键合对准结构以及应用此键合对准结构所制作而成的键合芯片结构及其制作方法。
背景技术
芯片键合技术是指将两片半导体芯片(例如，晶片)经清洗后贴合在一起，再经过高温退火处理，在二者的介面形成化学键的连接。目前已成为制备复合材料及实现微机械加工的重要手段，且广泛应用于半导体制作工艺应用，包括基板工程、集成电路制造、微机电系统(MEMS)和封装等技术之中。
典型的芯片键合技术，会在两片半导体芯片的键合表面上分别形成包含有介电缓冲层和键合材料层(通常为碳氮化硅层)的键合中间层(inter-bonding layer，IBL)。再通过热和压力使两片半导体芯片的键合材料层表面原子产生共价键合，当键合能(bondingenergy)达到一定强度，即可在不使用黏接媒介物的状况下结成为一体。为了使这两片半导体芯片精准对位，一般会在其中一个半导体芯片中，最靠近其键合表面的金属层上形成对准标记；再采用图像辨识的方式来识别对此一对准标记，将两片半导体芯片面对面精准贴合。
然而，由于对准标记受到介电缓冲层和键合材料层的覆盖，可能导致对准标记清晰度欠佳，识别不易，进而降低两片半导体芯片键合的对位精度。再加上，对准标记通常为铜质金属图案，在芯片键合之前，容易受到其他热制作工艺(例如热退火制作工艺)的影响而形成铜凸起缺陷(Cu hillock)，并突穿覆盖于其上的介电缓冲层和/或键合材料层，导致铜离子扩散到介电缓冲层和/或键合材料层或其他后续行程的材料层中，可能影响键合后半导体芯片的效能和可靠度。
因此，有需要提供一种先进的芯片键合对准结构与键合芯片结构及其制作方法，来解决现有技术所面临的问题。
发明内容
本说明书的一实施例揭露一种芯片键合对准结构，此芯片键合对准结构包括:半导体芯片、金属层、蚀刻停止层、至少一个金属凸丘、介电阻障(dielectric barrier)层、硅氧化物层以及碳氮化硅层。金属层位于半导体芯片的键合表面上，具有一个金属对准图案。蚀刻停止层覆盖于键合表面和该金属层上。金属凸丘由金属层向上延伸穿过蚀刻停止层，介电阻障层覆盖于蚀刻停止层和金属凸丘上。硅氧化物层覆盖于介电阻障层。碳氮化硅层覆盖于硅氧化物层上。
本说明书的另一实施例揭露一种芯片键合对准结构的制作方法，此方法包括下述步骤:首先，于半导体芯片的键合表面形成一个金属层，使其具有一个金属对准图案。然后，形成蚀刻停止层，覆盖键合表面和金属层；再进行高压退火(high pressure anneal，HPA)制作工艺，以形成至少一个金属凸丘，由金属层向上延伸穿过蚀刻停止层。接着，形成一个介电阻障层，覆盖于蚀刻停止层和金属凸丘；形成一个硅氧化物层覆盖介电阻障层；以及形成一个碳氮化硅层覆盖硅氧化物层。
本说明书的又一实施例揭露一种键合芯片结构，此键合芯片结构包括:第一半导体芯片、第二半导体芯片以及介层插塞。第一半导体芯片，具有第一键合表面，并包括:金属层、至少一个金属凸丘、蚀刻停止层、硅氧化物层以及碳氮化硅层。金属层位于第一键合表面上，且具有一个金属对准图案。蚀刻停止层覆盖于键合表面和该金属层上。金属凸丘由金属层向上延伸穿过蚀刻停止层。介电阻障层覆盖于蚀刻停止层和金属凸丘上。硅氧化物层覆盖于介电阻障层上。碳氮化硅层覆盖于硅氧化物层上。第二半导体芯片具有第二金属导线层以及面对第一键合表面的第二键合表面。介层插塞电连接第一半导体芯片中的第一金属导线层和第二半导体芯片中的第二金属导线层。
本说明书的再一实施例揭露一种键合芯片结构的制作方法，此方法包括下述步骤:首先，于第一半导体芯片的第一键合表面形成一个金属层，使其具有一个金属对准图案。然后，形成蚀刻停止层覆盖于第一键合表面和金属层上；再进行高压退火制作工艺，以形成至少一个金属凸丘，由金属层向上延伸穿过蚀刻停止层。之后，形成介电阻障层覆盖于蚀刻停止层和金属凸丘上；形成硅氧化物层覆盖于介电阻障层上；形成碳氮化硅层覆盖于硅氧化物层上。后续，将第二半导体芯片的第二键合表面与第一键合表面面对面键合；再形成介层插塞，电连接第一半导体芯片中的第一金属导线层和第二半导体芯片中的第二金属导线层。
根据上述实施例，本说明书是在提供一种芯片键合对准结构与键合芯片结构及其制作方法。是先在所欲键合的两个半导体芯片其中一者的键合表面上形成具有对金属准图案的金属层。并将修补半导体芯片元件的金属导线层所使用的高压退火步骤延后，先在金属层上形成一个蚀刻停止层，之后再实施高压退火。用于在金属层中生成金属凸丘(例如，铜凸起缺陷(Cu hillock))，并突破蚀刻停止层。之后，再于蚀刻停止层上形成介电阻障层，覆盖金属凸丘；并在介电阻障层上依序形成包含硅氧化物层和碳氮化硅层的键合中间层，以形成芯片键合对准结构。后续，再采用芯片键合对准结构进行对位，将两个半导体芯片的键合表面面对面键合，形成键合芯片结构。
由于，金属凸丘的生成可以增加金属层中金属对准图案的清晰度，有利于芯片键合的精确对位。另外，通过介电阻障层的覆盖，可以防止金属凸丘中的金属离子扩散至后续形成的键合中间层，避免键合中间层发生破裂，维持键合中间层的平整。故而，可以在提高芯片键合制作工艺的对位精度的同时，增进键合芯片结构的制作工艺良率和品质。
附图说明
为了对本说明书的上述及其他方面有更佳的了解，下文特举实施例，并配合所附的附图详细说明如下：
图1A至图1F为本说明书的一实施例，绘示制作半导体键合芯片结构10的一系列制作工艺结构剖面示意图。
符号说明
10:键合芯片结构
11:第一半导体芯片
11a:第一键合表面
12:第二半导体芯片
12a:第二键合表面
100:芯片键合对准结构
101:元件基材
101a:元件基材的前侧表面
102:层间介电层
102a:层间介电层的顶部表面
103:金属导线层
104:蚀刻停止层
105:高压退火制作工艺
106a:金属凸丘
106b:金属凸丘
107:介电阻障层
108:硅氧化物层
108a:硅氧化物层的上表面
109:碳氮化硅层
110:金属层
110p:金属对准图案
121:元件基材
121a:元件基材的前侧表面
122:层间介电层
122a:层间介电层的顶部表面
123:金属导线层
124:蚀刻停止层
128:硅氧化物层
129:碳氮化硅层
具体实施方式
本说明书是提供一种芯片键合对准结构与键合芯片结构及其制作方法，可在提高芯片键合制作工艺对位精度的同时，增进键合芯片结构的制作工艺良率和品质。为了对本说明书的上述实施例及其他目的、特征和优点能更明显易懂，下文特举多个实施例，并配合所附的附图作详细说明。
但必须注意的是，这些特定的实施案例与方法，并非用以限定本发明。本发明仍可采用其他特征、元件、方法及参数来加以实施。优选实施例的提出，仅用以例示本发明的技术特征，并非用以限定本发明的申请专利范围。该技术领域中具有通常知识者，将可根据以下说明书的描述，在不脱离本发明的精神范围内，作均等的修饰与变化。在不同实施例与附图之中，相同的元件，将以相同的元件符号加以表示。
请参照图1A至图1F，图1A至图1F是根据本说明书的一实施例，绘示制作键合芯片结构10的一系列制作工艺结构剖面示意图。键合芯片结构10的制作方法包括下述步骤：首先，提供一个第一半导体芯片11，并于第一半导体芯片11的第一键合表面11a形成一个金属层110，使其具有一个金属对准图案110p(如图1A所绘示)。
形成第一半导体芯片11的步骤，包括:在一个元件基材101的前侧表面101a上进行后端布线制作工艺(Back-End-Of-Line，BEOL)(未绘示)，在前侧表面101a上形成一个层间介电层(Interlayer Dielectric，ILD)102和多层金属导线层103。
在本说明书的一些实施例中，元件基材101可以是由半导体材质，例如硅(silicon，Si)、锗(germanium，Ge)，或化合半导体材质，例如砷化镓(gallium arsenide，GaAs)，所构成。但在另一些实施例中，元件基材101。也可以是一种绝缘层上覆硅(Siliconon Insulator，SOI)基板。在本实施例之中，元件基材101较佳是一种硅基材，例如是硅晶片。金属导线层103包括至少一个半导体元件(未绘示)，例如晶体管、电容器，电阻器其他主动(有源)/被动(无源)元件、微电子/微机械结构(未绘示)或上述的任意组合。
在本说明书的一些实施例中，金属层110可以是包埋于层间介电层102中的多层金属导线层103中的最上方一层金属层。层间介电层102的顶部表面102a可以被视为是第一半导体芯片11的第一键合表面11a。在本实施例中，金属层110(金属导线层103)是采用铜制作工艺所形成的图案化铜质层，金属对准图案110p可以是一种铜质对准图案，并且位于元件基材101的边缘区域。
然后如图1B所绘示，形成蚀刻停止层104覆盖于第一键合表面(层间介电层102的顶部表面102a)和金属层110上。在本说明书的一些实施例中，蚀刻停止层104的材质可以包括一种介电材料，例如碳氮化硅、氮化硅及上述成分的组合。
进行高压退火制作工艺105，增加金属表面粗糙度，并于金属层110中形成至少一个金属凸丘(例如、金属凸丘106a和106b)，由金属层110向上延伸穿过蚀刻停止层104(如图1C所绘示)。在本实施例中，由于金属层110为铜质层，因此所形成的金属凸丘106a和106b可以是一种铜凸起缺陷(Cu hillock)。其中，金属凸丘106a可以由金属对准图案110p向上延伸穿过蚀刻停止层104；金属凸丘106b可以由金属层110的其他部位向上延伸穿过蚀刻停止层104。
但值得注意的是图1C所绘示的金属凸丘106a和106b仅是例示；在其他实施例中，金属凸丘的数目、形状、尺寸和形成的位置并未限定。例如，在一些实施例中，在进行高压退火制作工艺105之后，金属对准图案110p上可以不生成金属凸丘106a。在另一些实施例中，可以生成更多的金属凸丘(未绘示)由金属层110的任何其他位置向上延伸穿过蚀刻停止层104。
之后，采用多个沉积制作工艺，例如聚焦离子束(Focused Ion Beam，FIB)沉积制作工艺，依序形成介电阻障层107覆盖于蚀刻停止层104和金属凸丘106上；形成硅氧化物层108覆盖于介电阻障层107上；形成碳氮化硅层109覆盖于硅氧化物层108上，完成如图1D所绘示的芯片键合对准结构100的制备。其中，构成介电阻障层107的材料可以是选自于由碳氮化硅、碳化硅、氮化硅、含氧碳化硅及上述的任意组合所组成的一族群。
在本实施例中，在形成碳氮化硅层109之前，会对硅氧化物层108进行平坦化步骤(未绘示)，例如以化学机械研磨(Chemical-Mechanical Planarization，CMP)技术，移除一部分硅氧化物层108，以提供一个实质上平坦的上表面108a，再以沉积制作工艺于硅氧化物层108的上表面108a上形成碳氮化硅层109。
其中，芯片键合对准结构100可以包括:半导体芯片11、金属层110、蚀刻停止层104、至少一个金属凸丘106、介电阻障层107、硅氧化物层108以及碳氮化硅层109。金属层110位于第一半导体芯片11的第一键合表面11a上，具有一个金属对准图案110p。蚀刻停止层104覆盖于键合表面和该金属层107上。金属凸丘106由金属层110的金属对准图案110p或其他位置向上延伸穿过蚀刻停止层104，介电阻障层107覆盖于蚀刻停止层104和金属凸丘106上。硅氧化物层108覆盖于介电阻障层107。碳氮化硅层109覆盖于硅氧化物层108上。
后续，提供第二半导体芯片12，并且使第一半导体芯片11与第二半导体芯片12面对面键合(如图1E所绘示)。例如在本实施例中，第二半导体芯片12的形成包括下述步骤:先在元件基材121的前侧表面121a上形成层间介电层122和至少一层金属导线层123，用于在元件基材121的前侧表面121a上形成至少一个半导体元件。之后，采用多个沉积制作工艺，在层间介电层122上方依序形成蚀刻停止层124、硅氧化物层128和碳氮化硅层129。在本实施例中，层间介电层122的顶部表面122a，可以视为第二半导体芯片12具有键合表面12a。
第一半导体芯片11与第二半导体芯片12的键合步骤，包括:将第二半导体芯片12翻转，使位于第二半导体芯片12的键合表面12a上方的碳氮化硅层129，与位于第一半导体芯片11的第一键合表面11a上方的碳氮化硅层109面对面接触。再通过热和压力使碳氮化硅层109和129的表面原子产生共价键合，使第一半导体芯片11与第二半导体芯片122紧密贴合。
之后，再形成介层插塞13，连接第一半导体芯片11中的金属导线层103和第二半导体芯片12中的金属导线层123。在本实施中，形成介层插塞13的步骤，包括以蚀刻停止层104为停止层进行蚀刻制作工艺，移除一部分元件基材121、层间介电层122、蚀刻停止层124、硅氧化物层128、碳氮化硅层129、碳氮化硅层109、硅氧化物层108、介电阻障层107和蚀刻停止层104，以形成一个开口，将一部分金属导线层103暴露出来。在以导电材料填充此一开口。后续，在通过一系列后段制作工艺，例如金属镶嵌制作工艺(metal damascene process)(未绘示)，形成如图1F所绘示的半导体键合芯片结构10。
根据上述实施例，本说明书是在提供一种芯片键合对准结构100与键合芯片结构10及其制作方法。是先在所欲键合的两个半导体芯片(第一半导体芯片11和第二半导体芯片12)其中一者(第一半导体芯片11)的键合表面(第一键合表面11a)上形成具有对金属准图案110p的金属层110。并将用于修补半导体芯片元件(第一半导体芯片11)的金属导线层(金属导线层103)所使用的高压退火步骤105延后，先在金属层110上形成一个蚀刻停止层104，之后再实施高压退火步骤105。使金属层110中生成金属凸起缺陷(例如，铜凸起缺陷(Cu hillock)，并突破蚀刻停止层104。在高压退火步骤105之后，再于蚀刻停止层104上形成介电阻障层107，覆盖金属凸丘106；并在介电阻障层107上依序形成包括硅氧化物层108和碳氮化硅层109的键合中间层，以形成芯片键合对准结构。后续，再采用芯片键合对准结构100进行对位，将两个半导体芯片(第一半导体芯片11和第二半导体芯片12)加以键合，形成键合芯片结构10。
由于，在进行高压退火步骤105之前，先于金属层110上形成蚀刻停止层104，不但可以增加金属层110中金属对准图案110p的清晰度，有利于芯片键合的精确对位，而且通过介电阻障层107的覆盖，可以防止金属凸丘106中的金属离子扩散至键合中间层(包括硅氧化物层108和碳氮化硅层109)，影响键合芯片结构10或后续形成的其他元件的效能和可靠度。故而，可以在提高芯片键合制作工艺对位精度的同时，增进键合芯片结构10的制作工艺良率和品质。
虽然结合以上优选实施例公开了本发明，然而其并非用以限定本发明，任何该技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，因此本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (10)

1.一种芯片键合对准结构，其特征在于，包括:
半导体芯片，具有键合表面；
金属层，位于该键合表面，具有金属对准图案；
蚀刻停止层，覆盖于该键合表面和该金属层上；
至少一金属凸丘，由该金属层向上延伸穿过该蚀刻停止层；
介电阻障层，覆盖于该蚀刻停止层和该至少一金属凸丘上；
硅氧化物层，覆盖于该介电阻障层上；以及
碳氮化硅层，覆盖于该硅氧化物层上。
2.如权利要求1所述的芯片键合对准结构，其中该金属对准图案，为铜质对准图案；该金属凸丘为铜质凸丘。
3.如权利要求1所述的芯片键合对准结构，其中该介电阻障层包括介电材料，选自于由碳氮化硅、碳化硅、氮化硅、含氧碳化硅及上述的任意组合所组成的族群。
4.如权利要求1所述的芯片键合对准结构，其中该蚀刻停止层包括介电材料，选自于由碳氮化硅、氮化硅及上述组合所组成的族群。
5.一种芯片键合对准结构的制作方法，包括:
于半导体芯片的键合表面形成金属层，使其具有金属对准图案；
形成蚀刻停止层，覆盖该键合表面和该金属层；
进行高压退火制作工艺，以形成至少一金属凸丘，由该金属层向上延伸穿过该蚀刻停止层；
形成介电阻障层，覆盖该蚀刻停止层和该至少一金属凸丘；
形成硅氧化物层，覆盖该介电阻障层；以及
形成碳氮化硅层，覆盖该硅氧化物层。
6.如权利要求5所述的芯片键合对准结构的制作方法，其中形成该金属层的步骤，包括铜制作工艺。
7.一种键合芯片结构，包括:
第一半导体芯片，具有第一键合表面，包括:
金属层，位于该第一键合表面上，且具有金属对准图案；
蚀刻停止层，覆盖于该键合表面和该金属层上；
至少一金属凸丘，由该金属层向上延伸穿过该蚀刻停止层；
介电阻障层，覆盖于该蚀刻停止层和该至少一金属凸丘上；
硅氧化物层，覆盖于该介电阻障层上；以及
碳氮化硅层，覆盖于该硅氧化物层上；
第二半导体芯片，具有面对该第一键合表面的第二键合表面；以及
介层插塞，电连接该第一半导体芯片中的第一金属导线层和该第二半导体芯片中的第二金属导线层。
8.如权利要求7所述的键合芯片结构，其中该金属对准图案，为铜质对准图案，该金属凸丘为铜质凸丘。
9.如权利要求7所述的键合芯片结构，其中该金属层为该第一金属导线层的一部分。
10.一种键合芯片结构的制作方法，包括:
于第一半导体芯片的第一键合表面形成金属层，使其具有金属对准图案；
形成蚀刻停止层，覆盖于该第一键合表面和该金属层上；
进行高压退火制作工艺，以形成至少一金属凸丘，由该金属层向上延伸穿过该蚀刻停止层；
形成介电阻障层，覆盖于该蚀刻停止层和该至少一金属凸丘；
形成硅氧化物层，覆盖于该介电阻障层；
形成碳氮化硅层，覆盖于该硅氧化物层；
将第二半导体芯片的第二键合表面与该第一键合表面面对面键合；以及
形成介层插塞，电连接该第一半导体芯片中的第一金属导线层和该第二半导体芯片中的第二金属导线层。
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