CN114695086A - Etching method for forming semiconductor device structure and semiconductor device structure - Google Patents
Etching method for forming semiconductor device structure and semiconductor device structure Download PDFInfo
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- 238000005530 etching Methods 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000007789 gas Substances 0.000 claims description 83
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 42
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 16
- 239000011261 inert gas Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 13
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 13
- 229910052731 fluorine Inorganic materials 0.000 claims description 13
- 239000011737 fluorine Substances 0.000 claims description 13
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 239000004215 Carbon black (E152) Substances 0.000 claims description 10
- 229930195733 hydrocarbon Natural products 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- -1 hydrocarbon small molecule Chemical class 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 239000004341 Octafluorocyclobutane Substances 0.000 claims description 3
- 229910018503 SF6 Inorganic materials 0.000 claims description 3
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 claims description 3
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 claims description 3
- 235000019407 octafluorocyclobutane Nutrition 0.000 claims description 3
- QYSGYZVSCZSLHT-UHFFFAOYSA-N octafluoropropane Chemical compound FC(F)(F)C(F)(F)C(F)(F)F QYSGYZVSCZSLHT-UHFFFAOYSA-N 0.000 claims description 3
- DAFIBNSJXIGBQB-UHFFFAOYSA-N perfluoroisobutene Chemical group FC(F)=C(C(F)(F)F)C(F)(F)F DAFIBNSJXIGBQB-UHFFFAOYSA-N 0.000 claims description 3
- 229960004065 perflutren Drugs 0.000 claims description 3
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 130
- 229920000642 polymer Polymers 0.000 description 14
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002430 hydrocarbons Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000004811 fluoropolymer Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
The invention discloses an etching method for forming a semiconductor device structure and the semiconductor device structure, comprising the following steps: providing a substrate, wherein a layer to be etched is arranged on the substrate, a patterned graph layer is arranged on the layer to be etched, and the ratio of the thickness of the layer to be etched to the thickness of the graph layer is more than 5; and introducing a first gas to the surface of the figure layer, wherein the first gas comprises: h2And CHyFz, y is more than or equal to 0 and less than or equal to 3 and 0<z is less than or equal to 4; CHyFz and H2The flow ratio of (3): 1-1: 3; forming a hardening layer by the first gas and the top of the pattern layer; and after the hardened layer is formed, taking the pattern layer and the hardened layer as masks, introducing second gas, etching the layer to be etched until the top surface of the substrate is exposed, and forming a groove in the layer to be etched. The invention protects the pattern layer through the hardening layer and improves the selection ratio of the layer to be etched to the pattern layerThe mask can be effectively masked during deep etching, and the etching requirement is met.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an etching method for forming a semiconductor device structure and the semiconductor device structure.
Background
Under the continuous push of moore's law, the technology node of the semiconductor rapidly advances to a node below 10 nm. In general, in the fabrication of integrated circuit semiconductor devices, it is necessary to form a predetermined material structure on a substrate. The formation of the predetermined material structure includes depositing a layer to be etched on the substrate, and disposing the patterned pattern layer as a mask on the layer to be etched. The plasma etching process is one of important technical links that restrict the development of the plasma etching process, wherein Photoresist (PR) is used as a material for etching polysilicon (polysilicon), silicon dioxide, silicon nitride (SiN) and the like below a film plate to form a Complementary Metal Oxide Semiconductor (CMOS), a through hole (Via), a Trench (Trench) and the like, which is one of important steps.
When the thickness of the layer to be etched is very thick and the mask is relatively thin, the etching process requires a very high selection ratio of the mask. Some mask materials, particularly photoresist, have too low a selectivity ratio during etching, cannot be effectively masked during etching, and cannot meet the etching requirements.
Disclosure of Invention
The invention provides a method for improving the etching selection ratio of a mask aiming at the condition that a material to be etched is thick and the upper mask is relatively thin, so as to accurately transfer a pattern.
In order to achieve the above object, the present invention provides an etching method for forming a semiconductor device structure, comprising: providing a substrate, wherein a layer to be etched is arranged on the substrate, a patterned graph layer is arranged on the layer to be etched, and the ratio of the thickness of the layer to be etched to the thickness of the graph layer is more than 5; and introducing a first gas to the surface of the figure layer, wherein the first gas comprises: h2And CHyFz, y is more than or equal to 0 and less than or equal to 3, 0<z is less than or equal to 4; CHyFz and H2The flow ratio of (3): 1-1: 3; forming a hardening layer by the first gas and the top of the pattern layer; after the hardened layer is formed, the graphic layer and the hardened layer are used as masks,and introducing a second gas, etching the layer to be etched until the top surface of the substrate is exposed, and forming a groove in the layer to be etched.
Alternatively, the CHyFz selects: tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Or CH3F.
Alternatively, CHyFz selects CF4Wherein, CF4And H2The gas flow ratio of (2: 1) to (1: 2).
Optionally, the first gas further comprises: c1～C5At least one of hydrocarbon small molecule gases.
Optionally, the hydrocarbon small molecule gas is CH4、C2H6Or C2H4At least one of (1).
Optionally, the first gas further comprises: an inert gas.
Optionally, the flow rate of the inert gas is 100sccm to 500 sccm.
Optionally, the second gas comprises: fluorine-containing gas and O2。
Optionally, the fluorine-containing gas comprises: nitrogen trifluoride (NF)3) Sulfur hexafluoride (SF)6) Hexafluoroethane (C)2F6) Tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Octafluoropropane (C)3F8) Octafluorocyclobutane (C)4F8) Or octafluoroisobutylene (C)4F8) Or fluorine gas (F)2)、C4F6At least one of (1).
Optionally, the second gas further comprises: an inert gas.
Optionally, the inert gas comprises argon or helium.
Optionally, the pattern layer is a photoresist layer.
Optionally, the material of the layer to be etched includes: silicon dioxide, silicon nitride or polysilicon.
Optionally, the process conditions for forming the hardened layer include: the pressure is 40 mT-60 mT, the radio frequency is 60Mhz, 900W-1200W, and/or 2MHz, 200W-2500W.
The invention also provides a semiconductor device structure formed by adopting the method, which comprises the following steps: the etching device comprises a substrate, a first etching layer and a second etching layer, wherein the substrate is provided with a layer to be etched, and the layer to be etched is provided with a patterned graph layer; the hardening layer is positioned on the top surface of the graphic layer; and the groove is positioned in the layer to be etched and between the adjacent pattern layers, and the top surface of the substrate is exposed.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the first gas is introduced to the surface of the patterned graph layer to form the hardened layer on the top of the graph layer, the graph layer and the hardened layer are used as masks, and when the second gas is introduced for etching, the selection ratio of the layer to be etched to the graph layer is improved through the hardened layer, so that when the ratio of the thickness of the layer to be etched to the thickness of the graph layer is more than 5, the masks can be effectively masked, and the etching requirement is met.
Drawings
FIG. 1 is a flow chart of an etching method for forming a semiconductor device structure according to the present invention.
Fig. 2 is a schematic diagram of an etched structure.
FIG. 3 is a schematic view of a PR surface with a hardened layer formed thereon.
FIG. 4 shows different CF4/H2Different etching modes are achieved by the gas proportion.
Fig. 5 is a diagram of the results of further controlling the PR processing process.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "top", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, the etching method for forming a semiconductor device structure provided by the present invention comprises the following steps:
step S1, providing a substrate, wherein a layer to be etched is arranged on the substrate, a patterned graphic layer is arranged on the layer to be etched, and the ratio of the thickness of the layer to be etched to the thickness of the graphic layer is more than 5;
step S2, introducing a first gas to the surface of the patterned layer, the first gas including: h2And CHyFz, y is more than or equal to 0 and less than or equal to 3 and 0<z is less than or equal to 4; CHyFz and H2The flow ratio of (A) to (B) is: 3: 1-1: 3, forming a hardening layer by the first gas and the top of the pattern layer;
and step S3, after the hardened layer is formed, introducing a second gas by taking the pattern layer and the hardened layer as masks, etching the layer to be etched until the top surface of the substrate is exposed, and forming a groove in the layer to be etched.
The invention comprises H2And the gases of CHyFz, hydrogen, carbon, and fluorine readily produce hydrocarbon fluorine-based polymers (polymers) that deposit on the surface of the patterned layer to form a hardened layer. And taking the graph layer and the hardened layer as masks, then introducing second gas for etching, and slowing down or blocking the etching of the plasma on the graph layer by using the hardened layer, thereby improving the selection ratio of the layer to be etched to the upper mask. When the ratio of the thickness of the layer to be etched to the thickness of the pattern layer is larger than 5, the upper mask cannot be completely etched, and a preset material structure can be obtained after etching is finished.
CHyFz can be selected from tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Or CH3F. CHyFz and H2The flow ratio of (A) to (B) is: 3: 1-1: if CHyFz and H2The proportion is too large, the hardened layer is too thin or difficult to form, and the protective effect on the graphic layer is very small or no protective effect is realized; if the ratio is too small, i.e., the H content is increased, it is a very big challenge for the upper electrode material because the more H, the damage to the electrode is a process of becoming qualitative. When CHyFz selects CF4In one embodiment, CF4And H2The gas flow ratio of (2: 1) to (1: 2).
In some embodiments, the patterning layer is a photoresist layer. Photoresist is one of the key materials for fine pattern processing in microelectronics technologies. The applied photoresist may be exposed to form a photoresist pattern and the material may be etched into a predetermined material structure using the photoresist pattern as an etching mask. The photoresist has poor etching resistance, and the etching selection ratio between the photoresist layer and the layer to be etched can be effectively improved by the method. In some embodiments, the first gas further comprises: c1～C5At least one of hydrocarbon small molecule gases. In some embodiments, the hydrocarbon small molecule gas is CH4，C2H6Or C2H4. The hydrocarbon small molecule gas can be used as deposition gas to provide hydrocarbon free radicals to help form polymer deposition, thereby increasing the polymer content of the PR surface and improving the selectivity of the layer to be etched to PR.
The first gas further comprises: an inert gas such as argon (Ar) or helium (He). The inert gas serves on the one hand as a diluent gas for adjusting the concentration of the main gas. The bombardment effect of the plasma can be improved by adding the inert gas with proper amount, and the bombardment effect of the plasma is not strong due to too small amount of the inert gas. Inert gases are also used to adjust the polymer deposition uniformity. Too much inert gas is added to excessively dilute the main gas concentration, resulting in less polymer formation. Argon gas produces positive Ar ions that are directional and promote faster deposition of compounds in small-scale structures.
In some embodiments, the second gas comprises: fluorine-containing gas and O2. For etching SiO2When the materials are equalThe fluorine-containing gas may provide a source of F for etching, O2The etching speed can be accelerated. After a hardening layer is formed on the top of the graph layer, the layer to be etched can be quickly etched by the introduced second gas. The hardening layer protects the pattern layer, and deviation of a device structure caused by loss of the pattern layer is avoided. In some embodiments, the fluorine-containing gas comprises: nitrogen trifluoride (NF)3) Sulfur hexafluoride (SF)6) Hexafluoroethane (C)2F6) Tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Octafluoropropane (C)3F8) Octafluorocyclobutane (C)4F8) Or octafluoroisobutylene (C)4F8) Or fluorine gas (F)2) At least one of (1).
In some embodiments, the second gas further comprises: an inert gas such as argon (Ar) or helium (He).
The second gas can also be other suitable gases to etch the layer to be etched. For example, some combinations of gases that can form small deposits, continuously compensate for the loss of the overlying mask and continuously etch the underlying layer to be etched during the etch.
The etching method of the invention can adopt a Plasma etching method and is applied to a Plasma etching process cavity, and Inductively Coupled Plasma (ICP) and the like can be selected, but not limited to Capacitively Coupled Plasma (CCP).
When a device structure such as a Complementary Metal Oxide Semiconductor (CMOS) is formed, a material such as polysilicon (polysilicon), silicon dioxide, silicon nitride (SiN), etc. may be disposed under the mask.
As shown in fig. 2 (a), a semiconductor device structure includes an etch stop layer 10, an oxide layer 20, and a photoresist layer 30, which are sequentially disposed. A substrate, a dielectric layer, etc. may be disposed under the etch stop layer 10.
The etch stop layer 10 may be a single layer or a multilayer, and may be made of silicon oxide, silicon carbide (SiC), silicon nitride, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbide nitride (SiOCN), or other suitable materials. The oxide layer 20 serves as a dielectric layer, and the structure thereof may be a single layer or multiple layers, such as a single layer of silicon oxide, a double layer of silicon oxide/silicon nitride, a multiple layer of silicon oxide/silicon nitride/silicon oxide, and the like. The material of the oxide layer 20 in this embodiment is silicon dioxide. The oxide layer 20 serves as the layer to be etched. And covering photoresist on the layer to be etched, and forming a photoresist pattern as a patterned pattern layer through exposure. The ratio of the thickness of the oxide layer 20 to the photoresist layer 30 is greater than 5.
Since the thickness ratio of silicon dioxide to photoresist is too large, when silicon dioxide is etched using the photoresist layer 30 as a mask, the photoresist has poor etching resistance, and common processes such as CHF3/O2/CF4Or C4F8/O2The selection ratio of silicon dioxide/photoresist of the gas combination of/Ar does not meet the requirement, and the silicon dioxide can not be effectively masked during the deep etching of the silicon dioxide, so that the etching requirement can not be met.
By introducing a first gas, CF, to the surface of the photoresist layer 304/H2The process window of the combination of/Ar is as follows:
1. pressure: 40 mT-60 mT;
2. radio Frequency (RF) Frequency: 60Mhz, 900W to 1200W, 2MHz, 200W to 2500W;
3.CF4/H2the proportion of (A): 2:1>x>1:2；
Ar flow rate: 100sccm to 500 sccm.
As shown in fig. 3, using CF4/H2The gas combination/Ar readily results in a deposited hydrocarbon fluoropolymer on the freshly made photoresist layer 30, thereby forming a hardened layer 40(Harden PR) on the PR.
After passing the first gas, H2Can provide H free radicals to react with PR surface and can react with CF4Forming a C-H structure to further form longer carbon chains; CF4Providing a source of C helps form a polymer deposit. The reaction mechanism is as follows:
H2reaction with PR: (CHO) x + H → CH4↑+OH*
CH4Further chain extension reactions occur:
(1)CH4→CH3*+H*
(2)2CH3*→C2H6
(3)C2H6+CH3*→C2H5*+CH4
(4)C2H5*→C2H4+H*
(5)C2H6+H*→C2H5*+H2
(6)2C2H5*→C2H6+C2H4
chain extension reactions may also include other reactions that form longer chains.
The deposited polymer can harden the (harden) PR surface structure during etching, acting to protect the PR and thus increasing the silicon dioxide/photoresist selectivity. After the hardened layer is formed, the photoresist layer and the hardened layer are used as masks, and second gas C is introduced4F6/O2and/Ar, etching the layer to be etched until the top surface of the etching stop layer is exposed to form a groove.
In the polymer deposition process, the formed plasma also has the etching effect on the layer to be etched, and CF4Providing a C source to aid in polymer deposition, and providing a F source to etch the underlying silicon dioxide, CF4Reaction with silica: CFx + SiO2→SiF4+CO2+ CO, and Ar as a diluent gas to adjust the concentration of the main gas and provide Ar+And etching is carried out. But by mixing CF4And H2The flow ratio of (3: 1) to (1: 3) is controlled, and the polymer can be continuously deposited, thereby forming the hardened layer 40.
After the etching is performed by introducing the second gas, as shown in fig. 2 (B), a deep groove can be obtained in the oxide layer 20.
By adjusting CF4/H2The adjustment and control process of the gas ratio performs PR processing on the semiconductor device structure shown in fig. 2 (a), and the process conditions are as follows:
60mT,900/200(H/L),300CF4/xH2400 Ar; H/L refers to High frequency (High frequency) and Low frequency (Low frequency), respectively.
It was found that CF is not present in any proportion4/H2Can form the hardened layer, FIG. 4 provides different CF4/H2Different etching (etch) patterns achieved by the gas ratio (ratio). Using H2The etch rate can be adjusted. When CF4/H2Gas ratio from 6:1 to 1:2, i.e. 300CF4/xH2From 300CF4/50H2To 300CF4/600H2The PR process is changed from the etch mode (tch mode) to the deposition mode (dep mode) to the etch mode (tch mode). The depth of the groove is 6:1
The groove depth is 3:1
Thus CF4/H2The gas ratio is from 6:1 to 3:1, the gas has high fluorine content and H2The content is less, so that the etching is facilitated, and meanwhile, the thickness of the upper layer mask with the ratio of 3:1 is slightly larger than that of the upper layer mask with the ratio of 6: 1. When CF4/H2Gas ratio of 3:1 to 1:1 (groove depth of 1: 1)
) Turning to deposition mode, at this time H2The content is increased, the etching rate is reduced, the formation of polymer is facilitated, the upper mask is thicker, namely a thicker hardened layer is obtained, but the gas still has a certain etching effect on the lower layer to be etched. When CF4/H2At a gas ratio of less than 1:1 (e.g., a groove depth of 1: 2)
) Turning to the etch mode, at this time H2Greater content of H2Also used as an etching gas to etch the device structureAnd (5) etching. In a gas ratio of 1:2, the upper mask is thicker, i.e. the layer to be etched has better etching performance, and meanwhile, a thicker hardened layer can still be obtained. The results in FIG. 4 show that CF4/H2Controlling the gas ratio to be 2: 1-1: 2, the hardened layer formed by PR treatment is thicker at this time, and CF4、H2The layer to be etched also has better etching performance.
At CF4/H2When the gas ratio is close to 3:1 or close to 1:3, the gas has an etching effect, but the surface of the device structure can still form polymers, namely the reaction process is that the polymer deposition of the upper mask and the plasma etching of the lower layer to be etched are carried out simultaneously.
After PR treatment, forming a hardening layer with enough thickness above PR, and the etching of the silicon dioxide below is not finished because the required etching depth is deeper (the thickness of the silicon dioxide/photoresist is more than 5), and then further etching the silicon dioxide, wherein the process conditions are as follows:
35mT,500/1200(H/L),9C4F6/7O2/600Ar；
introducing C during silicon dioxide etching4F6/O2the/Ar gas combination is used as the second gas, so that the layer to be etched can be quickly etched, and clean grooves can be obtained.
Further regulating and controlling the PR treatment process, wherein the adopted process conditions are as follows:
60mT,1200/2500(H/L),200CF4/400H2/300Ar。
fig. 5 is a diagram showing the result of further controlling the PR treatment process. In FIG. 5, the initial PR thickness (h1) was 3.7 μm. The PR surface was treated to a total thickness (h2) of 3.9 μm, including about 2.6 μm for the underlying PR (h3) and about 1 μm for the case of the surface-formed hardened layer (h 4).
By carrying out PR processing, the thickness of the original PR is increased, the PR is protected in the following etching process, and the loss of the PR is reduced.
In summary, in the invention, the first gas is introduced to the surface of the patterned pattern layer to form the hardened layer, and the patterned layer and the hardened layer are used as masks, so that after the second gas for etching is introduced, the patterned layer can be protected by the hardened layer when the layer to be etched is very thick and the patterned layer above the layer to be etched is relatively thin, the selection ratio of the layer to be etched to the patterned layer is improved, the mask can be effectively masked during etching, and the etching requirement is met.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (15)
1. An etching method for forming a semiconductor device structure is characterized by comprising the following steps:
providing a substrate, wherein a layer to be etched is arranged on the substrate, a patterned graph layer is arranged on the layer to be etched, and the ratio of the thickness of the layer to be etched to the thickness of the graph layer is more than 5;
introducing a first gas to the surface of the figure layer, wherein the first gas comprises: h2And CHyFz, y is more than or equal to 0 and less than or equal to 3, 0<z is less than or equal to 4; CHyFz and H2The flow ratio of (3): 1-1: 3; forming a hardening layer on the first gas and the top of the pattern layer;
and after the hardened layer is formed, introducing second gas by taking the pattern layer and the hardened layer as masks, etching the layer to be etched until the top surface of the substrate is exposed, and forming a groove in the layer to be etched.
2. The etching method for forming a semiconductor device structure according to claim 1, wherein the CHyFz selects: tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Or CH3And F.
3. The etching method for forming a semiconductor device structure according to claim 2, wherein CHyFz selects CF4Wherein, CF4And H2The gas flow ratio of (2: 1) to (1: 2).
4. The etching method for forming a semiconductor device structure according to claim 1, wherein the first gas further comprises: c1～C5At least one of hydrocarbon small molecule gases.
5. The etching method for forming the structure of the semiconductor device as claimed in claim 4, wherein the hydrocarbon small molecule gas is CH4、C2H6Or C2H4At least one of (1).
6. The etching method for forming a semiconductor device structure according to claim 1, wherein the first gas further comprises: an inert gas.
7. The etching method for forming a semiconductor device structure according to claim 6, wherein a flow rate of the inert gas is 100sccm to 500 sccm.
8. The etching method for forming the semiconductor device structure according to claim 1, wherein the second gas comprises: fluorine-containing gas and O2。
9. The etching method for forming the semiconductor device structure according to claim 8, wherein the fluorine-containing gas comprises: nitrogen trifluoride (NF)3) Sulfur hexafluoride (SF)6) Hexafluoroethane (C)2F6) Tetrafluoromethane (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Octafluoropropane (C)3F8) Octafluorocyclobutane (C)4F8) Or octafluoroisobutylene (C)4F8) Or fluorine gas (F)2) Or C4F6At least one of (1).
10. The etching method for forming a semiconductor device structure according to claim 8, wherein the second gas further comprises: an inert gas.
11. The etching method for forming a semiconductor device structure according to claim 6 or 10, wherein the inert gas comprises argon or helium.
12. The etching method for forming the semiconductor device structure according to claim 1, wherein the pattern layer is a photoresist layer.
13. The etching method for forming the semiconductor device structure according to claim 1, wherein the material of the layer to be etched comprises: silicon dioxide, silicon nitride or polysilicon.
14. The etching method for forming the semiconductor device structure according to claim 1, wherein the process conditions for forming the hardened layer include: the pressure is 40 mT-60 mT, the radio frequency is 60Mhz, 900W-1200W, and/or 2MHz, 200W-2500W.
15. A semiconductor device structure formed by the method of any of claims 1 to 14, comprising:
the etching device comprises a substrate, a first etching layer and a second etching layer, wherein the substrate is provided with a layer to be etched, and the layer to be etched is provided with a patterned graphic layer;
the hardening layer is positioned on the top surface of the graphic layer;
and the groove is positioned in the layer to be etched and between the adjacent pattern layers, and the top surface of the substrate is exposed.
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