CN114692542B - Simulation circuit reliability simulation method based on dynamic step length - Google Patents
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Abstract
The invention discloses a simulation circuit reliability simulation method based on dynamic step length, which mainly solves the problems that the prior art cannot be attached to the actual degradation condition of a device and the simulation precision and the speed cannot be considered. The implementation scheme is as follows: reading the set degradation time T and s step sizes from a circuit simulation input file; calculating an initial step time T 0 = T/s, and assigning the initial step time T 0 = T/s to each step; inputting a device degradation model function, and calculating a degradation rate function f (t) of the device degradation model function along with time; scaling calculation is carried out on s step sizes with the value of t 0 according to degradation rates f (t) of the device degradation function at different moments, so that a group of dynamic step sizes are obtained; and performing circuit reliability simulation by using the dynamic step length to obtain a degradation result of the circuit characteristic index. The invention improves the reliability simulation precision, and the reliability simulation time becomes budget controllable by setting the step number of the simulation, so that the invention can be used for predicting the degradation relation of the circuit performance along with time and the service life of the circuit.
Description
Technical Field
The invention belongs to the technical field of computer simulation, and particularly relates to a circuit reliability simulation method which can be used for predicting the degradation relation of circuit performance along with time and the service life of a circuit.
Background
With the development of moore's law, the current device size is smaller and the circuit scale is larger, which brings more serious non-ideal effects, such as hot carrier injection effect HCI, bias temperature instability BTI, and the like, and these non-ideal effects can cause certain important parameters of the device, such as threshold voltage, to be continuously degraded with time, so that the service life of the circuit is reduced. Currently, in order to consider the life problem of a circuit, each large EDA manufacturer and some universities begin to pay attention to the reliability simulation problem of the circuit, and the degradation relation of the circuit performance with time and the life of the circuit are obtained through the circuit reliability simulation. The third party model interface TMI for the commercial simulation tool developed by the accumulation electric company has one function for importing the degradation model, so that the degradation model can be called in the circuit simulation process to perform reliability simulation.
In circuit reliability simulation, when it is desired to calculate the degradation of a parameter of a certain device in the circuit, such as the threshold voltage degradation, it is necessary to include the actual time-varying stress present at the circuit node. To this end, most reliability simulators include methods in which some commercial reliability tools employ performing transient simulations and calculating the aging of the circuit over a short time span, such as a transient simulation time, and then extrapolating the results to a set aging time T age. However, the circuit bias condition may be changed to bring a larger simulation error due to degradation of the transistor performance caused by aging, so in order to consider the change of the bias condition caused by aging, the set aging time T age may be divided into a plurality of step time h for calculation, so that a more accurate calculation of the circuit degradation amount can be realized by updating the circuit bias condition once through each step simulation.
As shown in fig. 1, the initial reliability simulation method is to read parameters used in simulation through a circuit netlist file netlist, calculate degradation parameters of a transient device during transient simulation, extrapolate once to obtain degradation parameters of a predetermined time T age, and finally map the degradation parameters back into a circuit to perform post-circuit simulation to obtain degradation of a circuit characteristic index at T age. The flow method causes the circuit bias to change due to the interaction of the aging of the device and the response of the circuit to the device, thereby influencing the aging of the device, and if one-step extrapolation calculation is adopted, the degradation of the intermediate process can be ignored, thereby bringing larger simulation errors.
As shown in fig. 2, considering the change of bias conditions caused by device degradation, the predetermined degradation time T age is divided into a plurality of identical time steps h for simulation, namely, firstly, parameters used for simulation are read from a circuit netlist file netlist, transient simulation is performed to obtain transient degradation parameters, then the transient degradation parameters are extrapolated to the first step time to obtain degradation parameters of the step time, the degradation parameters are mapped into a circuit, the transient simulation of the next step is added and extrapolated until all the steps are simulated to obtain degradation parameters of T age, then the degradation parameters are mapped into the circuit, and the circuit is simulated to obtain degradation of circuit characteristic indexes at T age. Although this solution takes into account the bias condition changes caused by the aging of the circuit, the step h separated by the predetermined time T age is a fixed step, which causes two problems:
firstly, the theory of the current degradation model proves that the degradation amount of device parameters in a degradation circuit gradually tends to be saturated along with the lengthening of degradation time, so if the set step length is too small, the degradation energy in the early stage can obtain a relatively accurate result, but the degradation gradually tends to be saturated in the later stage, meaningless simulation is brought, and the simulation time is too long.
If the set step length is too large, simulation errors caused by bias condition change caused by degradation still can be caused when the early degradation speed is higher, and the reliability simulation accuracy is insufficient.
Some scholars have also proposed methods of adapting the step size, i.e. setting the step size to be an adaptive step size that varies continuously with the variation of the circuit performance through some calculation according to the degradation amount of the circuit performance, but these methods still have some problems: firstly, the circuit performance change may not have a direct relation with the degradation of devices in the circuit, and some devices are very little degraded, but the circuit performance is greatly degraded, so that even if the step length is reduced, the circuit simulation is not more accurate; secondly, the number of steps of the adaptive step-size method is uncertain, which may be tens of steps or hundreds of steps, which may cause the calculation time of circuit simulation to become unacceptable.
Disclosure of Invention
The invention aims to solve the problems brought by the prior art, and provides a circuit reliability simulation method based on dynamic step length, so that the simulation step length changes along with the degradation rate of a device, the reliability simulation precision is improved, and the reliability simulation time becomes budget controllable by setting the number of the simulation step length.
In order to achieve the above purpose, the technical scheme of the invention comprises the following steps:
(1) Reading the set degradation time T age and s step sizes h 1,h2,…,hi,…,hs from a circuit simulation input file;
(2) Calculating an initial step time: t 0 = T/s and assigning it to the steps such that each step h i＝t0;
(3) Input device degradation model function: Δvth (T) =a (Vg, vd, T, L …) T n, and calculates a degradation rate function of the degradation model function over time:
f(t)＝A(Vg,Vd,T,L…)*n*tn-1
Wherein ΔVth is a device degradation parameter, T is degradation time, n is a fitting parameter, and A (Vg, vd, T, L …) is a function of device stress and parameters required by reliability simulation; vg is the gate voltage born by the device, vd is the drain voltage born by the device, T is the simulation temperature, and L is the groove length of the device;
(4) Scaling calculation is carried out on s step sizes h 1,h2,…,hs with the value of t 0 according to degradation rates of a device degradation function at different moments, so that a group of dynamic step sizes w 1,w2,…,wi,…,ws is obtained:
w1＝2t0*([f(s*t0)]2/([f(s*t0)]2+[f(1*t0)]2))
w2＝2t0*([f((s-1)*t0)]2/([f((s-1)*t0)]2+[f(2*t0)]2))
...
wi＝2t0*([f((s-i+1)*t0)]2/([f((s-i+1)*t0)]2+[f(i*t0)]2))
...
ws＝2t0*([f((s-s+1)*t0)]2/([f((s-s+1)*t0)]2+[f(s*t0)]2));
(5) Performing circuit reliability simulation:
(5a) Performing transient simulation on a target circuit by using a reliability simulation tool to obtain data of stress borne by a device in the circuit, reading model parameters from the stress data and a circuit netlist, calculating to obtain device degradation parameters at a first step length w 1 time by a device degradation model function delta Vth (t), and feeding back the device degradation parameters to the circuit netlist file to obtain a once-updated circuit netlist file;
(5b) Performing a second step transient simulation by using the new circuit netlist file to obtain data of stress on a device in a circuit, calculating to obtain device degradation parameters of the first two step (w 1+w2) time by the stress data and model parameters read from the circuit netlist, and feeding back the device degradation parameters to the circuit netlist file to obtain a second updated circuit netlist file;
(5c) And so on, repeating the reliability simulation process, and calculating to obtain the first s step lengths The degradation parameters of the device are fed back to the circuit netlist file to obtain an s-time updated circuit netlist file;
(5d) Performing post-simulation on the target circuit by using the updated circuit netlist file for s times to obtain The amount of degradation in circuit performance over time, from which a prediction is made of the reliability of the circuit.
Compared with the prior art, the invention has the following advantages:
1) According to the degradation model theory that the degradation rate of the degradation model function is continuously reduced along with time, the invention reduces the original fixed step length with the value of t 0 when the degradation speed of the degradation parameter of the device is high in the early stage by correlating the step length with the degradation rate, thereby increasing the reliability simulation times and improving the simulation precision; when the later degradation rate is slow, the step length is amplified, so that the simulation times in the later period can be reduced while the precision is ensured.
2) According to the invention, a group of new dynamic step sizes is obtained after the dynamic scaling calculation is carried out on s step sizes with the value of t 0, so that the situation of actual degradation of a device can be attached, the number of the dynamic step sizes is ensured to be fixed s, the number of reliability simulation times is determined in advance, and the problem that the number of simulation times of a simulation tool exceeds the simulation time budget due to the fact that the number of the step sizes of the existing self-adaptive step sizes is not fixed is solved.
3) The invention can be applied to a commercial reliable circuit simulation tool, brings higher simulation precision under the condition of the same simulation times, and meets the requirements of the simulation speed and the precision of the commercial simulation tool.
Drawings
FIG. 1 is a flow chart of an implementation of a reliability simulation without adding a step size in the prior art;
FIG. 2 is a flow chart of an implementation of a prior art reliability simulation using a fixed step size;
FIG. 3 is a flow chart of a dynamic step implementation of the present invention;
Fig. 4 is a graph of device parameter degradation over time for reliability simulation of an inverter using a fixed step size in the prior art.
Fig. 5 is a graph of device parameter degradation over time for reliability simulation of an inverter using the dynamic step sizes of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 3, the specific implementation steps of this example are as follows:
and step 1, reading a circuit netlist and calculating to obtain an initial step size.
1.1 Setting a circuit structure, a model library file, simulation conditions and reliability simulation parameters of the inverter to form an inverter circuit netlist file which is used as an input file required by the reliability simulation of the subsequent inverter;
1.2 Reading parameters required by reliability simulation from the inverter circuit netlist, degradation time T age =2e8seconds, step size s=20;
1.3 20 fixed step sizes h 1,h2,…,hi,…,h20 with the value of 1E7 seconds are calculated according to the step size number,
Wherein, the time interval of h 1 is [0,1E7], the time interval of h 2 is [1E7,2E7], the time interval of … and h 20 is [1.9E8,2E8].
And 2, setting a degradation model and calculating the degradation rate of the degradation function.
2.1 Setting the degradation model used as the bias temperature instability BTI degradation model:
Wherein A is a model degradation constant, G is a grid voltage calculation factor parameter, C is a drain voltage calculation factor parameter, M is a ditch length dependence coefficient, EA is an activation energy fitting parameter, n is a time correlation coefficient, k is a Boltzmann constant, T is a simulation temperature, L is a device ditch length, vgs and Vds are grid voltage and drain voltage born by the device, and T age is degradation time;
setting but not limited to a=0.056, g=5.0, c= -2.0, m=3.0, ea=0.15, n=0.5, t=100k, l=90 nm, vgs inputs a square wave voltage with a high level of 1.5v, vds=1.8v;
2.2 Time derivative of the degradation model function to obtain a degradation rate function f (t) with respect to time:
And 3, scaling and calculating the fixed step length to obtain a dynamic step length.
3.1 Calculating the degradation rate of the moment by using the end point value of the time interval of each fixed step length through a degradation rate function f (t), so as to calculate the degradation rate of 20 step lengths, wherein if the degradation rate of the moment of the step length h 1 is f (1E 7), the degradation rate of the moment of the step length … and the moment of the step length h i is f (i 1E 7), and the degradation rate of the moment of the step length … and the step length h 20 is f (2E 8);
3.2 20 fixed steps h 1,h2,…,hi,…,h20 with a value of 1E7 seconds are grouped in pairs according to a given law: i.e. h 1 and h 20,h2 and h 19,h3 and h 18,h4 and h 17,h5 and h 16,h6 and h 15,h7 and h 14,h8 and h 13,h9 and h 12,h10 and h 11 are each a group, resulting in 10 packets;
3.3 The fixed step sizes of each group are dynamically scaled according to the square ratio of the degradation rate at the moment of each group of fixed step sizes, so that the proportional relation of 10 groups of scaled dynamic step sizes and the sum of the step size values of 10 groups of dynamic step sizes are obtained:
w1/w20＝[f(2E8)]2/[f(1E7)]2,w1+w20＝h1+h20＝2E7 Second, wherein the second is;
w2/w19＝[f(1.9E8)]2/[f(2E7)]2,w2+w19＝h2+h19＝2E7 Second, wherein the second is;
w3/w18＝[f(1.8E8)]2/[f(3E7)]2,w3+w18＝h3+h19＝2E7 Second, wherein the second is;
w4/w17＝[f(1.7E8)]2/[f(4E7)]2,w4+w17＝h4+h17＝2E7 Second, wherein the second is;
w5/w16＝[f(1.6E8)]2/[f(5E7)]2,w5+w16＝h5+h16＝2E7 Second, wherein the second is;
w6/w15＝[f(1.5E8)]2/[f(6E7)]2,w6+w15＝h6+h15＝2E7 Second, wherein the second is;
w7/w14＝[f(1.4E8)]2/[f(7E7)]2,w7+w14＝h7+h14＝2E7 Second, wherein the second is;
w8/w13＝[f(1.3E8)]2/[f(8E7)]2,w8+w13＝h8+h13＝2E7 Second, wherein the second is;
w9/w12＝[f(1.2E8)]2/[f(9E7)]2,w9+w12＝h9+h12＝2E7 Second, wherein the second is;
w10/w11＝[f(1.1E8)]2/[f(10E7)]2,w10+w11＝h10+h11＝2E7 Second, wherein the second is;
3.4 Calculating 20 dynamic step sizes according to the proportional relation of each group of dynamic step sizes and the sum of each group of dynamic step sizes:
w1＝2t0*([f(20*t0)]2/([f(20*t0)]2+[f(1*t0)]2))
w2＝2t0*([f(19*t0)]2/([f(19*t0)]2+[f(2*t0)]2))
...
wi＝2t0*([f((20-i+1)*t0)]2/([f((20-i+1)*t0)]2+[f(i*t0)]2))
...
w20＝2t0*([f(1*t0)]2/([f(1*t0)]2+[f(20*t0)]2));
Wherein t 0 is 1E7 seconds in this example;
3.5 A set of dynamic steps of this example is obtained by the above calculation, the values of which are as follows:
w1＝221134 w2＝660481 w3＝1274134 w4＝2048845
w5＝2974272 w6＝4038081 w7＝5224077 w8＝6511526
w9＝7875254 w10＝9286389 w11＝10713611 w12＝12124746
w13＝13488474 w14＝14775923 w15＝15961919 w16＝17025728
w17＝17951155 w18＝18725866 w19＝19339519 w20＝19778866
and 4, performing circuit reliability simulation by using the dynamic step length.
4.1 Performing transient simulation on the inverter circuit to obtain data of stress of a device in the circuit, reading model parameters from the stress data and the inverter circuit netlist, calculating device degradation parameters of a first step length w 1 = 221134 seconds through a device degradation model function delta Vth (t), and feeding back the device degradation parameters to the circuit netlist file to obtain a once-updated circuit netlist file;
4.2 Performing a second step transient simulation by using the new circuit netlist file to obtain data of stress on a device in the inverter circuit, calculating to obtain device degradation parameters of the first two step (w 1+w2) time by the stress data and model parameters read from the circuit netlist, and feeding back the device degradation parameters to the inverter circuit netlist file to obtain a secondarily updated inverter circuit netlist file;
4.3 Analogize sequentially, repeat the above-mentioned reliability simulation process, calculate and get 20 step time The degradation parameters are fed back to the inverter circuit netlist file to obtain an inverter circuit netlist file updated for 20 times;
4.4 Using the updated circuit netlist file for 20 times, performing the last simulation on the inverter circuit to obtain a history The delay degradation amount of the inverter after time operation; wherein/>
The advantages of the invention can be further illustrated by the following simulation results:
First, simulation conditions
Using the existing degradation model DeltaVth BTI (T), setting a model degradation constant A=0.056A, a grid voltage calculation factor parameter G=5.0, a drain voltage calculation factor parameter C= -2.0, a ditch length dependence coefficient M=3.0, an activation energy fitting parameter EA=0.15, a time correlation coefficient n=0.5, a simulation temperature T of 100k, a device ditch length L of 90nm, a grid voltage Vgs of square wave voltage with an input high level of 1.5v, and a drain voltage Vds=1.8v;
Second, simulation content
Simulation 1, under the above simulation conditions, according to the flow of the prior method shown in fig. 2, reliability simulation is performed on the inverter circuit by using 20 fixed steps with a value of 1E7 seconds, so as to obtain a graph of degradation of the device threshold voltage parameter in the inverter with time, as shown in fig. 4.
Simulation 2, under the above simulation conditions, performing reliability simulation on the inverter circuit by using the 20 dynamic step sizes w 1,w2,…,wi,…,w20 obtained by the method to obtain a graph of time degradation of the device threshold voltage parameter in the inverter, as shown in fig. 5;
Third, description of results
As can be seen from fig. 4, the parameter degradation amount for the first several step times is large with respect to the parameter degradation amount for the total time T age; the degradation amount of the threshold voltage of the device in the subsequent step length time is smaller and smaller along with the time, particularly, the degradation amount between two adjacent step lengths is closer and closer to each other in the later simulation time, so that the original step length simulation is reused at the moment, the precision improvement caused by the simulation is not obvious, and the meaning of inserting step length is lost; therefore, the fixed step simulation is used, the problem of insufficient reliability simulation precision is brought, and meanwhile, unnecessary simulation time waste is brought.
As can be seen from fig. 5, the reliability simulation is performed by using the dynamic step length, so that the degradation amount of the threshold voltage parameter of the device in the inverter is distributed more uniformly, and the reliability simulation by using the dynamic step length can be better attached to the actual degradation situation of the device, so that compared with the fixed step length method, the reliability simulation is performed by using 20 step lengths, and the accuracy of the dynamic step length simulation is higher.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (4)
1. The simulation method for the reliability of the analog circuit based on the dynamic step length is characterized by comprising the following steps of:
(1) Reading the set degradation time T age and s step sizes h 1,h2,…,hi,…,hs from a circuit simulation input file;
(2) Calculating an initial step time: t 0 = T/s and assigning it to the steps such that each step h i＝t0;
(3) And inputting a degradation model function of the device, and calculating a degradation rate function of the degradation model function along with time, wherein the implementation is as follows:
3.1 Setting the degradation model used as the bias temperature instability BTI degradation model:
Wherein A is a model degradation constant, G is a grid voltage calculation factor parameter, C is a drain voltage calculation factor parameter, M is a ditch length dependence coefficient, EA is an activation energy fitting parameter, n is a time correlation coefficient, k is a Boltzmann constant, T is a simulation temperature, L is a device ditch length, vgs and Vds are grid voltage and drain voltage born by the device, and T age is degradation time;
3.2 Time derivative of the degradation model function to obtain a degradation rate function f (t) with respect to time:
(4) Scaling calculation is carried out on s step sizes h 1,h2,…,hs with the value of t 0 according to degradation rates of a device degradation function at different moments, so that a group of dynamic step sizes w 1,w2,…,wi,…,ws is obtained:
w1＝2t0*([f(s*t0)]2/([f(s*t0)]2+[f(1*t0)]2))
w2＝2t0*([f((s-1)*t0)]2/([f((s-1)*t0)]2+[f(2*t0)]2))
...
wi＝2t0*([f((s-i+1)*t0)]2/([f((s-i+1)*t0)]2+[f(i*t0)]2))
...
ws＝2t0*([f((s-s+1)*t0)]2/([f((s-s+1)*t0)]2+[f(s*t0)]2));
(5) Performing an analog circuit reliability simulation:
(5a) Performing transient simulation on the simulation circuit by using a reliability simulation tool to obtain data of stress borne by a device in the circuit, reading model parameters from the stress data and a circuit netlist, calculating to obtain device degradation parameters at a first step length w 1 time by a device degradation model function delta Vth (t), and feeding back the device degradation parameters to the circuit netlist file to obtain a once-updated circuit netlist file;
(5b) Performing a second step transient simulation by using the new circuit netlist file to obtain data of stress on a device in a circuit, calculating to obtain device degradation parameters of the first two step (w 1+w2) time by the stress data and model parameters read from the circuit netlist, and feeding back the device degradation parameters to the circuit netlist file to obtain a second updated circuit netlist file;
(5c) And so on, repeating the reliability simulation process, and calculating to obtain the first s step lengths The degradation parameters of the device are fed back to the circuit netlist file to obtain an s-time updated circuit netlist file;
(5d) Performing the last simulation on the simulation circuit by using the updated circuit netlist file for s times to obtain The amount of degradation in circuit performance over time, from which a prediction is made of the reliability of the circuit.
2. The method of claim 1, wherein the step number s in (1) is a fixed parameter determined in the simulation input file that is not increased or decreased by a step algorithm as a number of subsequent reliability transient simulation executions.
3. The method of claim 1, wherein the circuit netlist file in (5 a) is an input file required for circuit simulation, and comprises a circuit structure of a target simulation circuit, a model library, simulation conditions and reliability simulation parameters.
4. The method of claim 1, wherein the sum of the times of the s dynamic steps calculated in (5 c)Its value corresponds to the input degradation time T age.
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