CN114678057A - Memory test repair circuit, memory device and memory test repair method - Google Patents
Memory test repair circuit, memory device and memory test repair method Download PDFInfo
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- CN114678057A CN114678057A CN202210310832.8A CN202210310832A CN114678057A CN 114678057 A CN114678057 A CN 114678057A CN 202210310832 A CN202210310832 A CN 202210310832A CN 114678057 A CN114678057 A CN 114678057A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
Abstract
The present disclosure provides a memory test repair circuit, a memory device, and a memory test repair method. The memory test repair circuit comprises an error checking and correcting circuit, a storage circuit and a built-in self-repair circuit. The output end of the error checking and correcting circuit is connected with each memory chip to be tested and is used for writing test data into the memory chip to be tested, reading out the stored data from the memory chip to be tested after preset time, and outputting the address code of inconsistent data when the stored data is inconsistent with the test data. The storage circuit is connected with the output end of the error checking and correcting circuit and is used for storing the address code of the inconsistent data output by the error checking and correcting circuit. The built-in self-repairing circuit is used for repairing the memory to be tested according to the address code of the inconsistent data. The method and the device can enrich the built-in self-test function of the memory and improve the built-in self-test effect of the memory.
Description
Technical Field
The present disclosure relates to memory test technologies, and in particular, to a memory test repair circuit, a memory device, and a memory test repair method.
Background
In the production of memories, such as Dynamic Random Access Memories (DRAMs), it is necessary to test the memories. When testing a memory, generally, test data of multi-bit bits are input into the memory, after a period of time, storage data is read from the memory, and the written test data and the read storage data are compared to judge which memory cells in the memory are abnormal.
The most common method for testing a Memory is Memory built-In Self Test (MBIST), which means that Test data of the Memory is not generated by an external tester (ATE), but is automatically generated by an internal Memory Test logic (logic chip), and the logic chip compares results. An MBIST circuit for use with memory built-in self-test includes an MBIST control circuit, an address vector generator, a test data generator, and a response analyzer. The MBIST control circuit is used for controlling data writing or data reading in the memory to be tested, the address vector generator is used for defining data writing positions, the test data generator is used for generating test data, and the response analyzer is used for comparing the read data with the written data.
However, the conventional MBIST circuit can only determine whether the read data is correct, and the function is too single, so how to expand the function of the MBIST circuit and improve the effect of built-in self-test of the memory still needs to be solved urgently.
Disclosure of Invention
The invention provides a memory test repair circuit, a memory device and a memory test repair method, which are used for expanding the function of an MBIST circuit and improving the built-in self-test effect of a memory.
In one aspect, the present disclosure provides a memory test repair circuit for repairing a memory to be tested, where the memory to be tested includes at least one memory chip to be tested, and the memory test repair circuit includes:
the output end of the error checking and correcting circuit is connected with each memory chip to be tested and is used for writing test data into the memory chip to be tested and reading out the stored data from the memory chip to be tested after preset time, and outputting the address code of inconsistent data when the stored data is inconsistent with the test data;
the storage circuit is connected with the output end of the error checking and correcting circuit and is used for storing the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit is used for repairing the memory to be tested according to the address code of the inconsistent data.
In an optional embodiment, further comprising:
and the output end of the test data writing circuit is connected with the input end of the error checking and correcting circuit and is used for generating the test data and the address vector of the test data.
In an optional embodiment, further comprising:
the built-in self-test control circuit is connected with the input end of the test data writing circuit and the output end of the storage circuit and is used for controlling the test data writing circuit to generate address vectors of the test data and reading out the address codes of the inconsistent data from the storage circuit;
the built-in self-repairing circuit is connected with the built-in self-testing control circuit and the memory chip to be tested and is used for repairing the memory to be tested under the control of the built-in self-testing control circuit.
In an optional embodiment, each memory chip to be tested is provided with a parameter setting circuit, the parameter setting circuit is configured to set an operating parameter of the memory chip to be tested, and the memory test repair circuit further includes:
and the chip parameter configuration circuit is connected with the parameter setting circuit and is used for inputting parameter codes to the parameter setting circuit so as to enable the parameter setting circuit to set the operating parameters of the storage chip to be tested according to the parameter codes.
In an optional embodiment, the parameter encoding includes parameter name encoding and parameter value encoding.
In an optional embodiment, the test data is encoded by the error checking and correcting circuit and then written into the memory chip to be tested, the error checking and correcting circuit is further configured to write the check data generated by the error checking and correcting circuit into the memory chip to be tested, and the test data and the check data are written into the memory chip to be tested at different positions.
In an alternative embodiment, the memory under test includes a plurality of memory chips under test arranged in a stacked manner.
In another aspect, the present disclosure provides a storage device comprising:
the memory to be tested comprises at least one memory chip to be tested and an error checking and correcting circuit, wherein the output end of the error checking and correcting circuit is connected with each memory chip to be tested, the error checking and correcting circuit is used for writing test data into the memory chip to be tested and reading out the stored data from the memory chip to be tested after preset time, and when the stored data is inconsistent with the test data, outputting the address code of the inconsistent data;
and the memory test repair circuit is connected with the input end and the output end of the error checking and correcting circuit and is used for inputting the test data and the address vector of the test data into the error checking and correcting circuit and repairing the memory to be tested according to the address code of the inconsistent data.
In an alternative embodiment, the memory test repair circuit includes:
the storage circuit is connected with the output end of the error checking and correcting circuit and is used for storing the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit is used for repairing the memory to be tested according to the address code of the inconsistent data.
In an optional embodiment, the memory test repair circuit further comprises:
and the output end of the test data writing circuit is connected with the input end of the error checking and correcting circuit and is used for generating the test data and the address vector of the test data.
In an optional embodiment, the memory test repair circuit further comprises:
the built-in self-test control circuit is connected with the input end of the test data writing circuit and the storage circuit and is used for controlling the test data writing circuit to generate the test data and the address vector and reading the address code of the inconsistent data from the storage circuit;
the built-in self-repairing circuit is connected with the built-in self-testing control circuit and the memory chip to be tested and is used for repairing the memory to be tested under the control of the built-in self-testing control circuit.
In an optional embodiment, each of the memory chips to be tested is provided with a parameter setting circuit, the parameter setting circuit is configured to set an operation parameter of the memory chip to be tested, and the memory test repair circuit further includes:
and the chip parameter configuration circuit is connected with the parameter setting circuit and is used for inputting parameter codes to the parameter setting circuit so as to enable the parameter setting circuit to set the operating parameters of the storage chip to be tested according to the parameter codes.
In an optional embodiment, the parameter encoding includes parameter name encoding and parameter value encoding.
In an optional embodiment, the test data is encoded by the error checking and correcting circuit and then written into the memory chip to be tested, the error checking and correcting circuit is further configured to write the check data generated by the error checking and correcting circuit into the memory chip to be tested, and the test data and the check data are written into the memory chip to be tested at different positions.
In an alternative embodiment, the memory under test includes a plurality of memory chips under test arranged in a stacked manner.
In another aspect, the present disclosure provides a memory test repair method applied to the memory test repair circuit provided in any one of the above embodiments, the method including:
controlling a test data writing circuit to input test data and address vectors of the test data to an error checking and correcting circuit;
the error checking and correcting circuit writes the coded test data into a to-be-tested memory chip of a to-be-tested memory according to the address vector of the test data;
after the preset time length, the error checking and correcting circuit reads out the storage data from the storage chip to be tested, and compares the test data with the storage data; when the test data is inconsistent with the stored data, outputting the address code of the inconsistent data;
the storage circuit stores the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit repairs the memory to be tested according to the address code of the inconsistent data.
In an alternative embodiment, the controlling the test data writing circuit to input the test data and the address vector of the test data to the error checking and correcting circuit includes:
after the built-in self-test control circuit receives a data writing instruction, the built-in self-test control circuit controls the test data writing circuit to input test data and address vectors of the test data to the error checking and correcting circuit;
the step of repairing the memory to be tested by the built-in self-repairing circuit according to the address code of the inconsistent data comprises the following steps:
when the built-in self-test control circuit detects that the address code is stored in the storage circuit, the address code of the inconsistent data is sent to the built-in self-repair circuit, and the built-in self-repair circuit repairs the memory to be tested according to the address code of the inconsistent data.
In an optional embodiment, when a parameter setting circuit is disposed on each of the memory chips to be tested, and the memory test repair circuit is disposed with a chip parameter configuration circuit, before the built-in self-test control circuit controls the test data write circuit to input test data and address vectors of the test data to the error check and correction circuit, the method further includes:
the chip parameter configuration circuit inputs parameter codes to the parameter setting circuit, so that the parameter setting circuit sets the operating parameters of the memory chip to be tested according to the parameter codes.
In an optional embodiment, further comprising:
and the error checking and correcting circuit generates checking data and writes the checking data into the appointed storage bit in the memory chip to be detected.
In an optional embodiment, the test data and the check data are written into the memory chip to be tested at the same time.
The memory test repair circuit provided by the embodiment of the disclosure comprises an error checking and correcting circuit, a test data writing circuit, a storage circuit, a built-in self-test control circuit and a built-in self-repair circuit. The error checking and correcting circuit is used for outputting the address code of the inconsistent data, namely the code of the storage bit with a problem (namely the storage error) in the storage chip to be tested. The memory circuit is used for storing the address code of the inconsistent data, and the built-in self-test control circuit controls the built-in self-repair circuit to repair the memory chip to be tested with the problem in the memory to be tested according to the address code of the inconsistent data. In addition, the memory chip to be tested can be set to be tested in a specific environment, and the purpose of personalized testing is achieved. Therefore, the memory test repair circuit provided by the embodiment of the disclosure can not only confirm the abnormal storage bit, but also repair the chip and the memory where the abnormal storage bit is located, has various functions, and improves the effect of built-in self test of the memory.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a built-in self test circuit used in the prior art provided by the present disclosure;
FIG. 2 is a schematic structural diagram of a memory test repair circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a memory test repair circuit for writing test data and reading stored data according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another structure of a memory test repair circuit according to another embodiment of the disclosure;
FIG. 5 is a schematic diagram of another structure of a memory test repair circuit according to another embodiment of the disclosure;
fig. 6 is a schematic diagram of parameter coding provided by an embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating an operation of a chip parameter configuration circuit according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram illustrating an operation of a chip parameter configuration circuit according to another embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a memory device provided by one embodiment of the present disclosure;
FIG. 10 is a schematic diagram of a memory device provided by another embodiment of the present disclosure;
fig. 11 is a flowchart illustrating a method for testing and repairing a memory according to an embodiment of the disclosure.
The reference numbers illustrate:
memory test repair circuit 10
Test data write circuit 400
Built-in self-test control circuit 500
Chip parameter configuration circuit 600
Memory test repair circuit 40
Built-in self-repair circuit 42
Test data write circuit 43
Built-in self test control circuit 44
Chip parameter configuration circuit 45
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. The drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the disclosure, as detailed in the appended claims.
In the production of memories, such as Dynamic Random Access Memories (DRAMs), testing of the memories is required. When testing a memory, generally, test data of multi-bit bits are input into the memory, after a period of time, storage data is read from the memory, and the written test data and the read storage data are compared to judge which memory cells in the memory are abnormal. The most common method for testing a Memory is Memory built-In Self Test (MBIST), which means that Test data of the Memory is not generated by an external tester (ATE), but is automatically generated by an internal Memory Test logic (logic chip), and the logic chip compares results.
FIG. 1 is a schematic diagram of a prior art MBIST circuit used in performing memory built-in self-tests. An MBIST circuit for use with memory built-in self-test includes an MBIST control circuit, an address vector generator, a test data generator, and a response analyzer. The MBIST control circuit is used for controlling data writing or data reading in the memory to be tested, the address vector generator is used for defining data writing positions, the test data generator is used for generating test data, and the response analyzer is used for comparing the read data with the written data.
The present disclosure provides a memory test repair circuit, a memory device, and a memory test repair method. The Memory test Repair circuit comprises an Error correction Code (ECC circuit for short), a Memory circuit (RAM for short) and a Built-In Self-Repair circuit (BISR circuit for short). The ECC circuit writes test data into the memory chip to be tested and reads out the stored data from the memory chip to be tested after preset time length, and when the stored data is inconsistent with the test data, the ECC circuit outputs address codes of inconsistent data. The storage circuit stores the address code of the inconsistent data output by the error checking and correcting circuit. The BISR circuit repairs the memory to be tested according to the address code of the inconsistent data.
When the memory test repair circuit provided by the embodiment of the disclosure is used for testing a memory, not only can the address of an abnormal memory cell (a memory cell causing inconsistency between write data and read data) be tested, but also the address code of the inconsistency between the write data and the read data can be stored, and the memory can be repaired. Therefore, the built-in self-test function of the memory is enriched, and the built-in self-test effect of the memory is improved.
Referring to fig. 2, an embodiment of the present disclosure provides a memory test repair circuit 10 for repairing a memory 20 to be tested, where the memory 20 to be tested includes at least one memory chip 21 to be tested, and fig. 2 shows that the memory 20 to be tested includes a plurality of memory chips 21 to be tested, but the number of the memory chips 21 to be tested in the memory 20 to be tested is not limited.
In an alternative embodiment, as shown in fig. 2, the memory 20 to be tested includes a plurality of memory chips 21 to be tested, which are stacked, and the stacking manner may be set according to actual needs, which is not limited in this embodiment.
The memory test repair circuit 10 includes an error checking and correcting circuit (ECC circuit) 100, a memory circuit 200, and a built-in self-repair circuit (BISR circuit) 300. For clarity, the ECC circuit 100 is used to represent the error checking and correcting circuit 100, and the BISR circuit 300 is used to represent the built-in self-repairing circuit 300.
The output terminal of the ECC circuit 100 is connected to each of the memory chips 21 to be tested. The connection of the ECC circuit 100 to the memory chip 21 under test refers to a signal connection or may also include an electrical connection. The ECC circuit 100 is used to write test data into the memory chip 21 to be tested, and read out the memory data from the memory chip 21 to be tested after a preset time period. The ECC circuit 100 is further configured to output an address code of the inconsistent data when the stored data is inconsistent with the test data.
In a digital circuit, the smallest unit of data is "bit", also called data "bit", which is also the smallest unit in a memory, and it represents a data high level signal by "1" and a data low level signal by "0". In a digital circuit, generally 8 consecutive bits (data bits) constitute a byte (byte), and the test data written by the ECC circuit 100 into the memory chip 21 to be tested is data including at least one byte.
The test data is encoded by the ECC circuit 100 and written into the memory chip 21 to be tested. The ECC circuit 100 is also configured to write the check data generated by itself to the memory chip 21 under test at the same time, but the test data and the check data are written to the memory chip 21 under test at different locations. As shown in fig. 3(a), the Data to memory (test Data) and Check bits (Check Data, which may also be understood as Check bits) are written into the memory chip 21 to be tested. That is, the ECC circuit 100 encodes test data by adding check bits (i.e., check data) to data bits in the test data.
If the data bits in the test data are 8 bits, then 5 check bits need to be added for ECC error checking and correction. For each doubling of data bits, the ECC circuit 100 adds only one check bit during encoding of test data, that is, when the data bits in the test data are 16 bits, the additional check bits are 6 bits, when the data bits in the test data are 32 bits, the additional check bits are 7 bits, and when the data bits in the test data are 64 bits, the additional check bits are 8 bits. And so on, the added check bit is increased by only one bit when the data bit is doubled. When the ECC has more check bits, the fault-tolerant capability is stronger.
In addition, when the ECC circuit 100 writes test data into the memory chip 21 to be tested, the test data is written based on an address vector of the test data, which defines a memory bit to which the test data is to be written. Similarly, the parity bits have predetermined locations when written. Each memory bit has an address code. If a storage error occurs in a certain bit of the test data, the ECC circuit 100 will read out the storage data from the memory chip 21 to be tested after a preset time period, and will generate fail bit, which is different from the written test data. At this time, the ECC circuit 100 outputs an address code of the inconsistent data (i.e., the inconsistent data bit fail bit). Similarly, when the written check data does not match the read check data, the ECC circuit 100 outputs an address code of the mismatch data. The address code refers to the address code of the memory location where the inconsistent data is stored.
Referring to fig. 2 and fig. 3(b), the memory circuit 200 is connected to the output terminal of the ECC circuit 100, and the memory circuit 200 is used for storing a Fail bit address (Fail bit address) of the inconsistent data output by the ECC circuit 100. When the ECC circuit 100 does not output the address code of the inconsistent data, the memory circuit 200 does not need to have a memory operation. The storage circuit 200 may automatically store the address code of the inconsistent data, or may complete the storage of the address code of the inconsistent data under the control of other circuits, such as the built-in self-test control circuit 500 described below.
The BISR circuit 300 is used for repairing the memory 20 according to the address code of the inconsistent data. The BISR circuit 300 includes a repair algorithm for determining whether a failed memory cell in the memory 20 under test is repairable and performing a logical repair by software. In an alternative embodiment, after receiving the address code of the inconsistent data, the BISR circuit 300 determines the failed memory location in the memory under test 20 according to the address code of the inconsistent data, and then starts the repair algorithm to determine whether the failed memory location is repairable, and if the failed memory location is repairable, the execution logic performs repair.
Thus, the memory test repair circuit 10 provided by the present embodiment includes the ECC circuit 100, the memory circuit 200, and the BISR circuit 300. The ECC circuit 100 is configured to output an address code of inconsistent data, which is a code of a storage bit in the memory chip 21 to be tested where a problem (i.e., a storage error) occurs. The storage circuit 200 is used for storing the address code of the inconsistent data, and the BISR circuit 300 is used for repairing the memory 20 to be tested according to the address code of the inconsistent data.
The memory test repair circuit 10 provided in this embodiment can not only detect the address of an abnormal memory cell (a memory cell causing inconsistency between write data and read data) when testing the memory, but also store the address code of the inconsistency between the write data and the read data, and repair the memory. Compared with the MBIST circuit used in the memory built-in self-test in the prior art, the memory test repair circuit 10 provided by the embodiment enriches at least the function of the memory built-in self-test, and improves the effect of the memory built-in self-test.
Referring to fig. 4, in yet another embodiment provided by the present disclosure, the memory test repair circuit 10 is further described on the basis of the first embodiment. In this embodiment, the memory test repair circuit 10 further includes a test Data writing circuit 400(Address/Data Generator), an output terminal of the test Data writing circuit 400 is connected to an input terminal of the ECC circuit 100, and is used for generating the test Data and an Address vector of the test Data. In an alternative embodiment, the Memory Test repair circuit 10 further includes a built-In Self-Test control circuit 500 (MBIST circuit), and the built-In Self-Test control circuit 500 is connected to the input terminal of the Test data writing circuit 400 and the output terminal of the Memory circuit 200. The built-in self-test control circuit 500 is used to control the test data write circuit 400 to generate address vectors of the test data and the test data, and address codes for reading the inconsistent data from the memory circuit 200.
A worker can control the testing of the memory device under test 20 by controlling the built-in self-test control circuit 500. For example, a test command may be issued from the tool to the built-in self-test control circuit 500 through the JTAG standard interface. After receiving the test command, the built-in self-test control circuit 500 controls the test data write circuit 400 to generate the test data and the address vector of the test data. When the address code of the inconsistent data is stored in the memory circuit 200, the built-in self-test control circuit 500 reads the address code of the inconsistent data from the memory circuit 200. The built-in self-test control circuit 500 then controls the BISR circuit 300 to repair the memory under test 20 according to the address code of the inconsistent data.
The BISR circuit 300 is connected to the built-in self-test control circuit 500 and connected to the memory chip under test 21 for repairing the memory under test 20 under the control of the built-in self-test control circuit 500. Specifically, the BISR circuit 300 is in signal connection with the built-in self-test control circuit 500, and can repair the memory 20 to be tested by using the address code of the inconsistent data.
The memory test repair circuit 10 provided in the present embodiment includes the ECC circuit 100, the memory circuit 200, the BISR circuit 300, the test data write circuit 400, and the built-in self-test control circuit 500. The ECC circuit 100 is configured to output an address code of inconsistent data, which is a code of a storage bit in the memory chip 21 to be tested where a problem (i.e., a storage error) occurs. The memory circuit 200 is used for storing the address code of the inconsistent data, and the built-in self-test control circuit 500 controls the BISR circuit 300 to repair the memory chip 21 to be tested having a problem in the memory 20 to be tested according to the address code of the inconsistent data. Therefore, the memory test repair circuit 10 provided by the embodiment of the disclosure can not only confirm the abnormal storage bit, but also repair the chip and the memory where the abnormal storage bit is located, so that the memory test repair circuit has various functions, and the effect of built-in self test of the memory is improved.
Referring to fig. 5, the present disclosure provides another embodiment, and the memory test repair circuit 10 is further described on the basis of any one of the above embodiments. In this embodiment, each memory chip 21 to be tested is further provided with a parameter setting circuit 22, and the parameter setting circuit 22 is configured to set an operation parameter of the memory chip 21 to be tested. The parameter setting circuit 22 is, For example, a circuit having a dft (design For test) function For realizing a specific auxiliary design.
Correspondingly, the memory test repair circuit 10 further includes a chip parameter configuration circuit 600. The chip parameter configuration circuit 600 is connected to the parameter setting circuit 22, and is configured to input a parameter code (CMD code) to the parameter setting circuit 22, so that the parameter setting circuit 22 sets an operating parameter of the memory chip 21 according to the parameter code.
The parameter codes include parameter name codes for defining what the operating parameters of the memory chip 21 to be tested have and parameter value codes for defining the values of the operating parameters of the memory chip 21 to be tested. For example, fig. 6 is a schematic diagram of parameter coding, in which P4 to P0 are used to define what the operating parameters of the memory chip 21 to be tested have, and D4 to D0 are used to define the values of the operating parameters of the memory chip 21 to be tested. The parametric code may also include a CLK clock that defines the frequency and time period of the parameter change. It should be noted that the parameter code is only valid when the memory chip 21 to be tested is in the high state. The length of the parameter coding may be set according to actual needs, and this embodiment is not limited. The parameter coding may be set according to actual needs, and this embodiment is not limited.
For example, as shown in fig. 7, the chip parameter configuration circuit 600 may simultaneously set the operating parameters of all the memory chips 21 to be tested in the memory 20 to be tested through the parameter setting circuit 22 set on the memory chips 21 to be tested. For example, as shown in fig. 8, the operation parameters may be set individually for any one of the memory chips 21 to be tested.
By setting the operation parameters of the memory chip 21 to be tested, the memory chip 21 to be tested can be in a specific operation environment, and the purpose of testing the memory chip 21 to be tested in the specific operation environment is achieved. For example, one memory chip 21 to be tested may be in the state of the maximum voltage, and the one memory chip 21 to be tested is tested again in the state of the maximum voltage to determine whether there is an abnormal storage bit, and if there is an abnormal storage bit, the ECC circuit 100 may output the address code of the inconsistent data.
In this embodiment, the setting of the operation parameters of the memory chip 21 to be tested through the parameter code may be performed before the testing of the memory chip 21 to be tested, or may be performed in the testing of the memory chip 21 to be tested. Preferably, before testing the memory chip 21 to be tested, the operating parameters of the memory chip 21 to be tested are set.
The operation parameters of the memory chip 21 to be tested are set through the parameter codes, so that the memory chip 21 to be tested is in a preset operation environment, and the operation condition of the memory chip 21 to be tested in the preset operation environment can be tested in a more targeted manner.
Referring to fig. 9 and 10, another embodiment of the present disclosure provides a memory device 30, where the memory device 30 includes a memory 20 to be tested and a memory test repair circuit 40.
The memory under test 20 includes at least one memory chip under test 21 and an error checking and correcting circuit (ECC circuit) 23. The ECC circuit 23 is disposed in the memory 20 to be tested, and an output end of the ECC circuit 23 is connected to each of the memory chips 21 to be tested. The ECC circuit 23 is configured to write test data into the memory chip 21 to be tested and read out the stored data from the memory chip 21 to be tested after a preset time period, and output an address code of inconsistent data when the stored data is inconsistent with the test data. The test data is encoded by the ECC circuit 23 and then written into the memory chip 21 to be tested, and the ECC circuit 23 is further configured to write the check data generated by the ECC circuit 23 into the memory chip 21 to be tested, where the test data and the check data are written into the memory chip 21 to be tested at different positions.
Optionally, the memory under test 20 includes a plurality of memory chips under test 21 stacked in a stacked manner.
The memory test repair circuit 40 is connected to the input end and the output end of the ECC circuit 23, and is configured to input the test data and the address vector of the test data to the ECC circuit 23, and repair the memory 20 to be tested according to the address coding of the inconsistent data.
In an alternative embodiment, the memory test repair circuit 40 includes a memory circuit 41 and a built-in self repair circuit 42. The storage circuit 41 is connected to the output terminal of the ECC circuit 23, and is used for storing the address code of the inconsistent data output by the ECC circuit 23. The built-in self-repair circuit 42 is used for repairing the memory under test 20 according to the address code of the inconsistent data.
For the related description of the ECC circuit 23, the memory circuit 41 and the self-repair circuit 42, reference may be made to the related description of the ECC circuit 100, the memory circuit 200 and the BISR circuit 300 in any of the above embodiments, and the description thereof is omitted here.
In an alternative embodiment, the memory test repair circuit 40 further includes a test data write circuit 43. An output terminal of the test data writing circuit 43 is connected to an input terminal of the ECC circuit 23 for generating the test data and an address vector of the test data.
In an alternative embodiment, the memory test repair circuit 40 also includes a built-in self-test control circuit 44. The built-in self test control circuit 44 is connected to an input of the test data write circuit 43 and the memory circuit 41 for controlling the test data write circuit to generate the test data and the address vector, and for reading the address code of the inconsistent data from the memory circuit. The built-in self-repair circuit 42 is connected to the built-in self-test control circuit 44 and connected to the memory chip 21 to be tested, and is used for repairing the memory 20 to be tested under the control of the built-in self-test control circuit 44.
For the description of the test data writing circuit 43 and the built-in self-test control circuit 44, reference may be made to the description of the test data writing circuit 400 and the built-in self-test control circuit 500 in any of the above embodiments, and the description thereof is omitted here.
In an alternative embodiment, each memory chip 21 under test is provided with a parameter setting circuit 22, and the parameter setting circuit 22 is configured to set an operating parameter of the memory chip 21 under test. Correspondingly, the memory test repair circuit 40 further includes a chip parameter configuration circuit 45. The chip parameter configuration circuit 45 is connected to the parameter setting circuit 22, and is configured to input a parameter code to the parameter setting circuit 22, so that the parameter setting circuit 22 sets an operating parameter of the memory chip 21 to be tested according to the parameter code. The parameter coding comprises parameter name coding and parameter value coding.
For the description of the parameter setting circuit 22, the chip parameter configuration circuit 45, the parameter code, and the operation parameter of the memory chip 21 to be tested, reference may be made to the description of the parameter setting circuit 22, the chip parameter configuration circuit 600, the parameter code, and the operation parameter of the memory chip 21 to be tested in any of the above embodiments, and details are not repeated here.
In the memory device 30 provided by the embodiment, the ECC circuit 23 is disposed in the memory 20 to be tested, so that the interaction time between the ECC circuit 23 and the memory chip 21 to be tested is shorter. In addition, the storage device 30 provided in this embodiment can detect the address of an abnormal storage unit (a storage unit causing inconsistency between the write data and the read data) in the memory 20 to be tested, store the address code of the inconsistency between the write data and the read data, and repair the memory. The storage device 30 provided in this embodiment can also set the operating environment of the memory chip 21 to be tested according to actual needs, so that the test of the memory chip 21 to be tested has more pertinence and practicability. Therefore, the memory device 30 provided by the embodiment enriches the function of the memory built-in self-test, and improves the effect of the memory built-in self-test.
Referring to fig. 11, another embodiment of the present disclosure provides a memory test repair method, which is applied to the memory test repair circuit 10 provided in any one of the above embodiments.
The memory test repair method comprises the following steps:
s1101, the test data write circuit is controlled to input the test data and the address vector of the test data to the error check and correction circuit.
In a digital circuit, the smallest data unit is "bit", also called data "bit", which is also the smallest unit in a memory, and it represents a data high level signal by "1" and a data low level signal by "0". In a digital circuit, generally 8 consecutive bits (data bits) constitute one byte (byte), and the test data written by the ECC circuit 100 into the memory chip 21 to be tested is data including at least one byte.
The test data input from the test data writing circuit 400 to the ECC circuit 100 (i.e., the error checking and correcting circuit 100) is data including a plurality of bytes, and the address vector is used to locate the memory bit to which the data is to be stored.
Alternatively, after receiving the data write command, the built-in self-test control circuit 500 controls the test data write circuit to input the test data and the address vector of the test data to the ECC circuit 100.
And S1102, the error checking and correcting circuit writes the coded test data into a memory chip to be tested of the memory to be tested according to the address vector of the test data.
The test data is encoded by the ECC circuit 100 and written into the memory chip 21 to be tested.
The ECC circuit 100 is also configured to generate check data and write the check data to a specified storage bit in the memory chip 21 to be tested. The test data and the check data are written into the memory chip 21 to be tested at the same time, but the test data and the check data are written into the memory chip 21 to be tested at different positions. The Data to memory (test Data) and Check bits (Check Data, which may also be understood as Check bits) are written into the memory chip 21 to be tested. That is, the ECC circuit 100 encodes test data by adding check bits (i.e., check data) to data bits in the test data.
If the data bits in the test data are 8 bits, then 5 check bits need to be added for ECC error checking and correction. For each doubling of data bits, the ECC circuit 100 adds only one check bit during encoding of test data, that is, when the data bits in the test data are 16 bits, the additional check bits are 6 bits, when the data bits in the test data are 32 bits, the additional check bits are 7 bits, and when the data bits in the test data are 64 bits, the additional check bits are 8 bits. And so on, the added check bit is increased by only one bit when the data bit is doubled. When the ECC has more check bits, the fault-tolerant capability is stronger.
In addition, when the ECC circuit 100 writes test data into the memory chip 21 to be tested, the test data is written based on an address vector of the test data, which defines a memory bit to which the test data is to be written. Similarly, the parity bits have predetermined locations when written. Each memory bit has an address code.
S1103, after the preset duration, the error checking and correcting circuit reads out the storage data from the memory chip to be tested, and compares the test data with the storage data; and when the test data is inconsistent with the stored data, outputting the address code of the inconsistent data.
If a storage error occurs in a certain bit of the test data, the ECC circuit 100 will read out the storage data from the memory chip 21 to be tested after a preset time period, and will generate fail bit, which is different from the written test data. At this time, the ECC circuit 100 outputs an address code of the inconsistent data (i.e., the inconsistent data bit fail bit). Similarly, when the written check data does not match the read check data, the ECC circuit 100 outputs an address code of the mismatch data. The address code refers to the address code of the memory location where the inconsistent data is stored.
S1104, the storage circuit stores the address code of the inconsistent data output by the error checking and correcting circuit.
When the ECC circuit 100 does not output the address code of the inconsistent data, the memory circuit 200 does not need to have a memory operation. The storage circuit 200 may automatically store the address code of the inconsistent data, or may complete the storage of the address code of the inconsistent data under the control of other circuits, such as the built-in self-test control circuit 500 described below.
S1105, the built-in self-repair circuit repairs the memory to be tested according to the address code of the inconsistent data.
The BISR circuit 300 (i.e., the built-in self-repair circuit 300) is used for repairing the memory under test 20 according to the address coding of the inconsistent data. The BISR circuit 300 includes a repair algorithm for determining whether a failed memory cell in the memory 20 under test is repairable and performing a logical repair by software. In an alternative embodiment, after receiving the address code of the inconsistent data, the BISR circuit 300 determines the failed memory location in the memory under test 20 according to the address code of the inconsistent data, and then starts the repair algorithm to determine whether the failed memory location is repairable, and if the failed memory location is repairable, the execution logic performs repair.
Optionally, when the built-in self-test control circuit 500 detects that the address code is stored in the memory circuit 200, the address code of the inconsistent data is sent to the BISR circuit 300, and the BIST circuit 300 repairs the memory 20 to be tested according to the address code of the inconsistent data.
In an alternative embodiment, when each memory chip 21 to be tested is provided with the parameter setting circuit 22 and the memory test repair circuit is provided with the chip parameter configuration circuit 600, the chip parameter configuration circuit 600 inputs a parameter code to the parameter setting circuit 22, so that the parameter setting circuit 22 sets the operating parameter of the memory chip 21 to be tested according to the parameter code.
The memory test repair method provided in this embodiment describes a specific implementation manner of the memory test repair circuit 10 when testing the memory 20 to be tested. When the memory is tested, the memory test repair circuit can not only test the address of an abnormal memory cell (a memory cell causing inconsistency between write data and read data), but also store the address code of the inconsistency between the write data and the read data, and repair the memory. The operation environment of the memory chip 21 to be tested can be set according to actual needs, so that the test of the memory chip 21 to be tested has pertinence and practicability. Therefore, the memory test repair method provided by the embodiment enriches at least the function of the built-in self-test of the memory, and improves the effect of the built-in self-test of the memory.
The above embodiments are merely examples of the present disclosure, and not intended to limit the scope of the present disclosure, and all equivalent structures or equivalent processes that may be modified from the disclosure and drawings, or directly or indirectly applied to other related technical fields, are also included in the scope of the present disclosure.
Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (20)
1. The utility model provides a memory test repair circuit, is used for restoreing the memory that awaits measuring, the memory that awaits measuring includes at least one memory chip that awaits measuring, memory test repair circuit includes:
the output end of the error checking and correcting circuit is connected with each memory chip to be tested and is used for writing test data into the memory chip to be tested and reading out the stored data from the memory chip to be tested after preset time, and outputting the address code of inconsistent data when the stored data is inconsistent with the test data;
the storage circuit is connected with the output end of the error checking and correcting circuit and is used for storing the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit is used for repairing the memory to be tested according to the address code of the inconsistent data.
2. The memory test repair circuit of claim 1, further comprising:
and the output end of the test data writing circuit is connected with the input end of the error checking and correcting circuit and is used for generating the test data and the address vector of the test data.
3. The memory test repair circuit of claim 2, further comprising:
the built-in self-test control circuit is connected with the input end of the test data writing circuit and the output end of the storage circuit and is used for controlling the test data writing circuit to generate address vectors of the test data and reading out the address codes of the inconsistent data from the storage circuit;
the built-in self-repairing circuit is connected with the built-in self-testing control circuit and the memory chip to be tested and is used for repairing the memory to be tested under the control of the built-in self-testing control circuit.
4. The memory test repair circuit according to any one of claims 1 to 3, wherein a parameter setting circuit is disposed on each of the memory chips to be tested, the parameter setting circuit being configured to set an operating parameter of the memory chip to be tested, the memory test repair circuit further comprising:
and the chip parameter configuration circuit is connected with the parameter setting circuit and is used for inputting parameter codes to the parameter setting circuit so as to enable the parameter setting circuit to set the operating parameters of the storage chip to be tested according to the parameter codes.
5. The memory test repair circuit of claim 4, wherein the parameter encoding comprises a parameter name encoding and a parameter value encoding.
6. The memory test repair circuit of any one of claims 1 to 3, wherein the test data is encoded by the error checking and correcting circuit and then written into the memory chip under test, the error checking and correcting circuit is further configured to write check data generated by the error checking and correcting circuit into the memory chip under test, and the test data and the check data are written into the memory chip under test at different locations.
7. The memory test repair circuit according to any one of claims 1 to 3, wherein the memory under test includes a plurality of memory chips under test arranged in a stack.
8. A memory device, comprising:
the memory to be tested comprises at least one memory chip to be tested and an error checking and correcting circuit, wherein the output end of the error checking and correcting circuit is connected with each memory chip to be tested, the error checking and correcting circuit is used for writing test data into the memory chip to be tested and reading out the stored data from the memory chip to be tested after preset time, and when the stored data is inconsistent with the test data, outputting the address code of the inconsistent data;
and the memory test repair circuit is connected with the input end and the output end of the error checking and correcting circuit and is used for inputting the test data and the address vector of the test data into the error checking and correcting circuit and repairing the memory to be tested according to the address code of the inconsistent data.
9. The memory device according to claim 8, wherein the memory test repair circuit comprises:
the storage circuit is connected with the output end of the error checking and correcting circuit and is used for storing the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit is used for repairing the memory to be tested according to the address code of the inconsistent data.
10. The memory device of claim 9, wherein the memory test repair circuit further comprises:
and the output end of the test data writing circuit is connected with the input end of the error checking and correcting circuit and is used for generating the test data and the address vector of the test data.
11. The memory device of claim 10, wherein the memory test repair circuit further comprises:
the built-in self-test control circuit is connected with the input end of the test data writing circuit and the storage circuit and is used for controlling the test data writing circuit to generate the test data and the address vector and reading the address code of the inconsistent data from the storage circuit;
the built-in self-repairing circuit is connected with the built-in self-testing control circuit and the memory chip to be tested and is used for repairing the memory to be tested under the control of the built-in self-testing control circuit.
12. The memory device according to any one of claims 8 to 11, wherein each of the memory chips under test is provided with a parameter setting circuit, the parameter setting circuit is configured to set an operation parameter of the memory chip under test, and the memory test repair circuit further includes:
and the chip parameter configuration circuit is connected with the parameter setting circuit and is used for inputting parameter codes to the parameter setting circuit so as to enable the parameter setting circuit to set the operating parameters of the storage chip to be tested according to the parameter codes.
13. The storage device of claim 12, wherein the parameter code comprises a parameter name code and a parameter value code.
14. The memory device according to any one of claims 8 to 11, wherein the test data is encoded by the error checking and correcting circuit and then written into the memory chip under test, and the error checking and correcting circuit is further configured to write check data generated by the error checking and correcting circuit into the memory chip under test, where the test data and the check data are written into the memory chip under test at different locations.
15. The memory device according to any one of claims 8 to 11, wherein the memory under test comprises a plurality of memory chips under test arranged in a stack.
16. A memory test repair method applied to the memory test repair circuit according to any one of claims 1 to 7, the method comprising:
controlling a test data writing circuit to input test data and address vectors of the test data to an error checking and correcting circuit;
the error checking and correcting circuit writes the coded test data into a memory chip to be tested of a memory to be tested according to the address vector of the test data;
after the preset time length, the error checking and correcting circuit reads out the storage data from the storage chip to be tested, and compares the test data with the storage data; when the test data is inconsistent with the stored data, outputting the address code of the inconsistent data;
the storage circuit stores the address code of the inconsistent data output by the error checking and correcting circuit;
and the built-in self-repairing circuit repairs the memory to be tested according to the address code of the inconsistent data.
17. The method of claim 16, wherein controlling the test data write circuit to input test data and an address vector of the test data to the error checking and correcting circuit comprises:
after the built-in self-test control circuit receives a data writing instruction, the built-in self-test control circuit controls the test data writing circuit to input test data and address vectors of the test data to the error checking and correcting circuit;
the step of repairing the memory to be tested by the built-in self-repairing circuit according to the address code of the inconsistent data comprises the following steps:
when the built-in self-test control circuit detects that the address code is stored in the storage circuit, the address code of the inconsistent data is sent to the built-in self-repair circuit, and the built-in self-repair circuit repairs the memory to be tested according to the address code of the inconsistent data.
18. The method as claimed in claim 17, wherein when a parameter setting circuit is provided on each of the memory chips to be tested and the memory test repair circuit is provided with a chip parameter configuration circuit, before the built-in self-test control circuit controls the test data write circuit to input test data and address vectors of the test data to the error check and correction circuit, the method further comprises:
the chip parameter configuration circuit inputs parameter codes to the parameter setting circuit, so that the parameter setting circuit sets the operating parameters of the memory chip to be tested according to the parameter codes.
19. The method of any one of claims 16 to 18, further comprising:
and the error checking and correcting circuit generates checking data and writes the checking data into the appointed storage bit in the memory chip to be detected.
20. The method of claim 19, wherein the test data and the check data are written to the memory chip under test at the same time.
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| CN115083507A (en) * | 2022-08-18 | 2022-09-20 | 中国电子科技集团公司第五十八研究所 | Method for testing ecc check bit storage array of memory |
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| CN115083507A (en) * | 2022-08-18 | 2022-09-20 | 中国电子科技集团公司第五十八研究所 | Method for testing ecc check bit storage array of memory |
| CN115656792A (en) * | 2022-12-29 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Test method and test platform for chip testability design |
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