CN114677348A - IC chip defect detection method and system based on vision and storage medium - Google Patents

IC chip defect detection method and system based on vision and storage medium Download PDF

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Publication number
CN114677348A
CN114677348A CN202210285852.4A CN202210285852A CN114677348A CN 114677348 A CN114677348 A CN 114677348A CN 202210285852 A CN202210285852 A CN 202210285852A CN 114677348 A CN114677348 A CN 114677348A
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detected
chip
image
line
chip product
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彭智浩
周振宇
彭仁杰
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Matrixtime Robotics Shanghai Co ltd
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Matrixtime Robotics Shanghai Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/001—Industrial image inspection using an image reference approach
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Abstract

The invention discloses a method and a system for detecting IC chip defects based on vision and a storage medium. The invention firstly processes the image of a normal IC chip product to obtain a template image IMAnd a line template image IBM(ii) a Then, drawing the IC chip product to be detected, and processing to obtain an affine transformation coefficient C and an approximate detection area R of the IC chip product to be detected; then, in the approximate detection area R of the IC chip product to be detected, a circuit binary image I of the IC chip product to be detected is obtained through processingBIThen affine transformation is carried out to obtain a circuit template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data; finally, the line binary image IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to IandMedium single line and IBCNumber of connected domains in corresponding region or IBCMedium single line and IandThe corresponding region in the middle is connected with the domainAnd judging whether the number is more than 1 so as to judge the defects of the IC chip products to be detected.

Description

IC chip defect detection method and system based on vision and storage medium
Technical Field
The invention belongs to the technical field of image processing, and particularly relates to a method and a system for detecting IC chip defects based on vision, and a storage medium.
Background
Various defects are inevitably generated in the production process of the IC chip due to various factors and the influence of the production process, wherein the defects of open circuit and short circuit of a metal circuit can cause the product to be unusable and generate waste products. Therefore, after the packaging process is completed, the IC chip needs to be strictly detected, and how to improve the product quality in the production flow and reduce the reject ratio of the final product becomes a continuous pursuit target of the industry.
At present, the defect detection of the IC chip mainly has two forms: firstly, the defect of traditional manual detection method, through people's eye visual combination workman to the understanding of defect to the product detect, this method detection efficiency is low, and relies on the understanding degree of workman to the defect, easily takes place to miss to examine. Non-contact detection, such as Automatic Optical Inspection (AOI), is an important research reversal in such methods, but most of the current vision-based methods use common template comparison or image subtraction methods to detect open circuit and short circuit of IC chips, and when template matching errors occur or the product itself has tolerance, such methods may result in missed detection or false detection.
In view of the above, it is necessary to develop a method for detecting defects of an IC chip based on vision to solve the above technical problems.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a system and a storage medium for detecting IC chip defects based on vision. The method solves the problems that in the existing vision-based method, the open circuit and the short circuit of an IC chip are mostly detected by adopting a common template comparison or image subtraction method, and when the template matching has errors or the product has tolerance, the method can cause missed detection or false detection and the like.
An object of the present invention is to provide a vision-based method for detecting defects of an IC chip.
A visual-based IC chip defect detection method comprises the following steps:
s1, acquiring and aligning K images of normal IC chip products, and then performing weighted fusion on the aligned images to obtain a template image IMDrawing of the templateLike IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM；
S2, drawing the IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching method MAffine transformation coefficient C of the image I of the IC chip product to be detected and approximate detection area R of the IC chip product to be detected;
s3, obtaining a circuit binary image I of the IC chip product to be detected by adopting a threshold-based binarization method in the approximate detection area R of the IC chip product to be detectedBIThen, the line template image IBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on image I of IC chip product to be detectedBCAnd performing connected domain marking on the data;
s4, binary line graph IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single lineBCBinary graph I of neutralization circuitandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 so as to judge the defects of the IC chip product to be detected.
Further, in step S1, the value range of K is 50 to 500.
Further, in step S1, the method of alignment is as follows: and selecting one image with the product angle close to the horizontal as a reference image, and aligning the other residual images with the reference image by an affine transformation method.
Further, in step S2, the template matching method is a shape-based template matching method.
Further, in step S4, according to the line binary diagram IandNeutralization of IBCWhether the number of the connected domains of the area corresponding to the single line is more than 1 or not is judged, so that the method for judging the defects of the IC chip product to be detected comprises the following steps: sequentially mapping the two-value circuit diagram IandNeutralization of IBCRegion R corresponding to single linei，(i＝[1:Nbc]，NbcIs shown as IBCNumber of connected domains in the line) is extracted, and R is calculatediThe number of connected domains M, if M>1, then judging RiThe circuit breaking defect exists in the IC chip to be detected, so that the circuit breaking defect exists in the IC chip to be detected.
Further, in step S4, according to whether the number of connected domains in the IBC corresponding to a single line in the line binary diagram Iand is greater than 1, the method for determining the defect of the IC chip product to be detected is as follows: sequentially extracting areas Rj (j is [1: Nand ], and Nand is the number of the line connected domains in the line binary image Iand) corresponding to a single line in the IBC, calculating the number N of the Rj connected domains, and judging that Rj has a short-circuit defect if N is greater than 1, thereby determining that the IC chip product to be detected has the short-circuit defect.
The present invention also provides a vision-based IC chip defect detection system, comprising:
a line template image acquisition unit: acquiring K images of normal IC chip products, aligning, and performing weighted fusion on the aligned images to obtain a template image I MTo template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM；
IC chip product processing unit awaits measuring: drawing an IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching methodMAffine transformation coefficient C of an image I of an IC chip product to be detected and an approximate detection area R of the IC chip product to be detected;
an affine transformation unit: obtaining a line binary image I of the IC chip product to be detected by adopting a threshold-based binarization method in an approximate detection area R of the IC chip product to be detectedBIThen the circuit template image I is processedBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data;
IC chip defect judgment unit: will routeBinary image IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single lineBCBinary graph I of neutralization circuitandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 so as to judge the defects of the IC chip product to be detected.
The invention finally provides a storage medium for storing a computer program to be loaded by a processor for performing the detection method of any one of the preceding claims.
Compared with the prior art, the invention has the following advantages:
the invention firstly processes the image of a normal IC chip product to obtain a template image IMAnd a line template image IBM(ii) a Then, drawing the IC chip product to be detected, and processing to obtain an affine transformation coefficient C and an approximate detection area R of the IC chip product to be detected; then, in the approximate detection area R of the IC chip product to be detected, a circuit binary image I of the IC chip product to be detected is obtained through processingBIThen, the circuit template image I is processedBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data; finally, the line binary image IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single lineBCBinary graph I of neutralization circuitandJudging whether the number of connected domains of the area corresponding to the single line is more than 1 so as to judge the defects of the IC chip product to be detected; the whole process is subjected to non-contact automatic detection, so that secondary damage of the product can be reduced, and the detection efficiency is improved; meanwhile, the method is not influenced by matching errors, and can more accurately detect open circuit and short circuit defects of the IC chip product.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of a vision-based method for detecting IC chip defects according to the present invention;
FIG. 2 is a block diagram of a vision-based inspection system for IC chip defects in accordance with the present invention;
FIG. 3 is a flowchart illustrating a vision-based detection process for open circuit defects of an IC chip according to the present invention;
FIG. 4 is a flow chart of the IC chip short defect detection based on vision according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the embodiments described are merely exemplary embodiments, rather than exemplary embodiments, and that all other embodiments may be devised by those skilled in the art without departing from the scope of the present invention.
Referring to fig. 1, a method for detecting IC chip defects based on vision includes the following steps:
s1, acquiring and aligning K images of normal IC chip products, and then performing weighted fusion on the aligned images to obtain a template image IMFor template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM；
S2, drawing the IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching methodMAffine transformation coefficient C of an image I of an IC chip product to be detected and an approximate detection area R of the IC chip product to be detected;
s3, obtaining the binary image of the IC chip product to be detected by using a threshold-based binarization method in the approximate detection region R of the IC chip product to be detectedCircuit binary image I for detecting IC chip product image IBIThen the circuit template image I is processedBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data;
s4, binary line graph IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single line BCMedian line binary diagram IandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 or not so as to judge the defects of the IC chip product to be detected.
Specifically, in step S1, the value range of K is 50 to 500. The image fusion method can select according to the fusion image effect, starts from 50, increases if the fusion image effect is not good, and aims to eliminate the burr phenomenon of the line mainly through fusion of a plurality of images, so that the line template image is more accurate.
Specifically, in step S1, the alignment method is as follows: and selecting one image with the product angle close to the horizontal as a reference image, and aligning the other residual images with the reference image by an affine transformation method.
Specifically, the template matching method is a shape-based template matching method. It should be noted that although the present embodiment employs a template matching method based on shape, other conventional template matching methods are also within the scope of the present invention.
Specifically, with continued reference to fig. 1 and 3, in step S4, according to the line binary pattern IandNeutralization ofBCWhether the number of connected domains of the area corresponding to the medium single line is more than 1 or not is judged, so that the method for judging the defects of the IC chip product to be detected is as follows: sequentially mapping the two-value circuit diagram I andNeutralization ofBCRegion R corresponding to single linei，(i＝[1:Nbc]，NbcIs IBCNumber of connected domains in the line) is extracted, and R is calculatediThe number of connected domains M, if M>1, then judging RiThe circuit breaking defect exists in the IC chip to be detected, so that the circuit breaking defect exists in the IC chip to be detected.
Specifically, with continuing reference to fig. 1 and 4, in step S4, according to whether the number of connected domains corresponding to a single line in the line binary diagram Iand in the IBC is greater than 1, the method for determining the defect of the IC chip product to be detected is as follows: sequentially extracting areas Rj (j is [1: Nand ], and Nand is the number of the line connected domains in the line binary image Iand) corresponding to a single line in the IBC, calculating the number N of the Rj connected domains, and judging that Rj has a short-circuit defect if N is greater than 1, thereby determining that the IC chip product to be detected has the short-circuit defect.
Referring to fig. 2, the present invention further provides a system for detecting IC chip defects based on vision, the system comprising: the circuit template image acquisition unit 301, the IC chip product processing unit to be detected 302, the affine transformation unit 303 and the IC chip defect judgment unit 304;
the circuit template image acquisition unit acquires and aligns K images of normal IC chip products, and then performs weighted fusion on the aligned images to obtain a template image I MTo template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM；
The processing unit of the IC chip product to be detected performs image taking on the IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then a template matching method is adopted to obtain a template image IMAffine transformation coefficient C of the image I of the IC chip product to be detected and approximate detection area R of the IC chip product to be detected;
the affine transformation unit obtains a line binary image I of an image I of the IC chip product to be detected by adopting a threshold-based binarization method in an approximate detection area R of the IC chip product to be detectedBIThen the circuit template image I is processedBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data;
the above-mentionedThe judging unit of IC chip defect will map the circuit binary IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single lineBCBinary graph I of neutralization circuitandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 so as to judge the defects of the IC chip product to be detected.
The invention also provides a storage medium for storing a computer program which is loaded by a processor to perform the detection method of any one of the above. For example, the computer program, when loaded by a processor, may perform the steps of:
acquiring K images of normal IC chip products, aligning, and performing weighted fusion on the aligned images to obtain a template image IMFor template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM(ii) a Drawing an IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching methodMAffine transformation coefficient C of an image I of an IC chip product to be detected and an approximate detection area R of the IC chip product to be detected; obtaining a line binary image I of the IC chip product to be detected by adopting a threshold-based binarization method in an approximate detection area R of the IC chip product to be detectedBIThen the circuit template image I is processedBMAffine transformation is carried out on the affine transformation coefficient C to obtain a line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data; binary line graph I BIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization of IBCNumber of connected domains or I of corresponding areas of medium single lineBCMedian line binary diagram IandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 or not so as to judge the defects of the IC chip product to be detected.
The computer-readable storage medium may be an internal storage unit of the image processing apparatus of the foregoing embodiment, such as a hard disk or a memory of the image processing apparatus. The computer-readable storage medium may also be an external storage device of the image processing apparatus, such as a plug-in hard disk provided on the image processing apparatus, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card (FlashCard), and the like.
Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.

Claims (8)

1. A visual-based IC chip defect detection method is characterized by comprising the following steps:
s1, acquiring and aligning K images of normal IC chip products, and then performing weighted fusion on the aligned images to obtain a template image IMTo template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image IBM；
S2, drawing the IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching methodMAffine transformation coefficient C of an image I of an IC chip product to be detected and an approximate detection area R of the IC chip product to be detected;
s3, obtaining a circuit binary image I of the IC chip product to be detected by adopting a threshold-based binarization method in the approximate detection area R of the IC chip product to be detectedBIThen the circuit template image I is processedBMAffine transformation is carried out by utilizing affine transformation coefficient C to obtain line template IBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data;
s4, binary line graph IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single line BCMedian line binary diagram IandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 or not so as to judge the defects of the IC chip product to be detected.
2. The vision-based method for detecting defects of an IC chip as recited in claim 1, wherein in step S1, K has a value in a range of 50-500.
3. The vision-based detection method of IC chip defects of claim 1, wherein in step S1, the alignment method is as follows: and selecting one image with the product angle close to the horizontal as a reference image, and aligning the other residual images with the reference image by an affine transformation method.
4. The vision-based detection method for defects of an IC chip according to claim 1, wherein in step S2, the template matching method is a shape-based template matching method.
5. The vision-based method for detecting IC chip defects of claim 1, wherein in step S4, the IC chip defects are detected according to the line binary pattern IandNeutralization ofBCWhether the number of connected domains of the area corresponding to the medium single line is more than 1 or not is judged, so that the method for judging the defects of the IC chip product to be detected is as follows: sequentially mapping the two-value circuit diagram I andNeutralization of IBCRegion R corresponding to single linei，(i＝[1:Nbc]，NbcIs shown as IBCNumber of connected domains in middle line) Extracting and calculating RiThe number of connected domains M, if M>1, then judging RiThe circuit breaking defect exists in the IC chip to be detected, so that the circuit breaking defect exists in the IC chip to be detected.
6. The vision-based method for detecting defects of an IC chip as claimed in claim 1, wherein in step S4, according to IBCBinary graph I of neutralization circuitandWhether the number of the connected domains of the area corresponding to the single line is more than 1 or not is judged, so that the method for judging the defects of the IC chip product to be detected comprises the following steps: sequentially mixing IBCBinary graph I of neutralization circuitandRegion R corresponding to single linej，(j＝[1:Nand]，NandIs a line binary diagram IandNumber of connected domains in the line) is extracted, and R is calculatedjThe number of connected domains N, if N>1, then judging RjAnd the short-circuit defect exists, so that the short-circuit defect of the IC chip product to be detected is determined.
7. A vision-based IC chip defect detection system, comprising:
a line template image acquisition unit: acquiring K images of normal IC chip products, aligning, and performing weighted fusion on the aligned images to obtain a template image IMFor template image IMPerforming binarization processing and extracting a line binary image to obtain a line template image I BM；
The IC chip product processing unit to be detected: drawing an IC chip product to be detected to obtain an image I of the IC chip product to be detected, and then obtaining a template image I by adopting a template matching methodMAffine transformation coefficient C of an image I of an IC chip product to be detected and an approximate detection area R of the IC chip product to be detected;
an affine transformation unit: obtaining a line binary image I of the IC chip product to be detected by adopting a threshold-based binarization method in an approximate detection area R of the IC chip product to be detectedBIThen the circuit template image I is processedBMAffine transformation with affine transformation coefficient CThe circuit template I is obtained by replacementBMProjection I on IC chip product image I to be detectedBCAnd performing connected domain marking on the data;
IC chip defect judgment unit: binary line graph IBIAnd IBCObtaining intersection to obtain a two-value line graph I after intersectionandAccording to the line binary diagram IandNeutralization ofBCThe number of connected domains or I of the region corresponding to the single lineBCBinary graph I of neutralization circuitandAnd judging whether the number of the connected domains of the area corresponding to the single line is more than 1 so as to judge the defects of the IC chip product to be detected.
8. A storage medium for storing a computer program which is loaded by a processor to perform the detection method according to any one of claims 1 to 6.
CN202210285852.4A 2022-03-22 2022-03-22 IC chip defect detection method and system based on vision and storage medium Pending CN114677348A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115018837A (en) * 2022-08-08 2022-09-06 聚时科技(深圳)有限公司 Method for detecting solder ball of semiconductor chip
CN117036342A (en) * 2023-10-07 2023-11-10 深圳模微半导体有限公司 Chip defect identification method and system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115018837A (en) * 2022-08-08 2022-09-06 聚时科技(深圳)有限公司 Method for detecting solder ball of semiconductor chip
CN117036342A (en) * 2023-10-07 2023-11-10 深圳模微半导体有限公司 Chip defect identification method and system
CN117036342B (en) * 2023-10-07 2024-02-06 深圳模微半导体有限公司 Chip defect identification method and system

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