CN114675780A

CN114675780A - Reading method, three-dimensional memory and memory system

Info

Publication number: CN114675780A
Application number: CN202111578306.1A
Authority: CN
Inventors: 夏仕钰; 许锋; 靳磊; 李海涛; 李楷威; 谢学准; 程婷
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2022-06-28

Abstract

The embodiment of the invention relates to a reading method, a three-dimensional memory and a memory system, wherein the three-dimensional memory comprises one or more memory pages and one or more word lines respectively coupled with the one or more memory pages; each memory page comprises one or more memory cells, and the reading method comprises the following steps: when the memory cells of the selected word line are read, judging whether the read operation is the first read operation; when the read operation is a first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

Description

Reading method, three-dimensional memory and memory system

Cross Reference to Related Applications

The present invention is set forth and claimed in priority from a chinese patent application having application number 202011531516.0 filed on 22/12/2020, the entire contents of which are incorporated herein by reference.

Technical Field

The invention relates to the technical field of memories, in particular to a three-dimensional memory reading method, a three-dimensional memory and a memory system.

Background

As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.

As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits (bit) of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells. Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.

In an enterprise-level three-dimensional memory (e.g., 3D NAND), Low-Density Parity-Check (LDPC) codes are typically used for error correction. FIG. 1 is a flow chart of LDPC error correction. As shown with reference to fig. 1, these error correction codes inevitably lead to additional read time delays and a degradation of the overall memory performance, especially soft-decision decoding (soft-decoding). Therefore, it is important to reduce the Fail Bit Count (FBC).

Transient Read Errors (TER) are a new threat to 3D NAND reliability, which means that after a period of idle time after the 3D NAND Flash (Flash) programming/reading is finished, a large number of transient Read Errors occur when the 3D NAND Flash (Flash) is Read for the first time, i.e. FBC is high, and FBC shows a stable value in the subsequent second Read result and third Read result. Fig. 2A and 2B are schematic diagrams of a multi-read FBC having no idle time from the end of programming to the first read and a multi-read FBC having an idle time from the end of programming to the first read, respectively. Fig. 2A shows FBCs in three readings without idle time, and fig. 2B shows FBCs in five readings after idle time of 24 hours. Referring to fig. 2A and 2B, the First Read Issue (FRI) is strongly correlated to the idle time before reading, and when no idle time is directly Read at the end of programming, FRI does not occur. FRI occurs when waiting 24 hours after the end of programming to read again, and the first layer Word Line (WL) read is the most severe. FIG. 3 is a schematic diagram of a conventional transient Read error (TER) (cited in C.Zambelli, R.Micheloni, S.Scommegna and P.Olivo, "First event of temporal Read Errors in TLC 3D-NAND Flash Memories identifying From Idle State"). Referring to FIG. 3, the first read phenomenon (w/TER in FIG. 3) can greatly increase the probability of triggering soft-decision decoding in LDPC, resulting in a degradation of the overall performance of the memory.

Disclosure of Invention

Embodiments of the present invention provide a method for reading a three-dimensional memory, and a memory system, which can at least reduce a failure bit count during a first read operation.

In one aspect, an embodiment of the present invention provides a method for reading a three-dimensional memory, where the three-dimensional memory includes one or more memory pages and one or more word lines respectively coupled to the one or more memory pages; each memory page comprises one or more memory cells, and the reading method comprises the following steps:

when a reading operation is executed on a memory cell of a selected word line, judging whether the reading operation is a first reading operation;

when the read operation is a first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line.

In another aspect, an embodiment of the present invention provides a three-dimensional memory, including:

a memory array comprising one or more memory pages; each of the memory pages comprises one or more memory cells;

one or more word lines respectively coupled to the one or more memory pages;

and peripheral circuitry coupled on the plurality of word lines and for controlling the memory array; wherein the content of the first and second substances,

The peripheral circuitry is configured to: when the memory cells of the selected word line are read, judging whether the read operation is the first read operation;

In another aspect, an embodiment of the present invention further provides a memory system, including a three-dimensional memory, where the three-dimensional memory includes:

a memory array comprising one or more memory pages; each memory page contains one or more memory cells;

one or more word lines respectively coupled to the one or more memory pages;

and peripheral circuitry coupled on the one or more word lines and for controlling the memory array; wherein the peripheral circuitry is configured to: when a reading operation is executed on a memory cell of a selected word line, judging whether the reading operation is a first reading operation; when the read operation is a first read operation, applying a first pulse voltage to the selected word line before applying a read voltage to the selected word line;

And a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a flow chart of LDPC error correction;

FIGS. 2A and 2B are schematic diagrams of a multiple read FBC with no idle time from the end of programming to the first read and a multiple read FBC with an idle time from the end of programming to the first read, respectively;

FIG. 3 is a diagram of a conventional transient read error (TER);

FIGS. 4-5 are schematic diagrams of transient read errors in different program states during a first read;

FIG. 6 is a schematic diagram of a reading method in TLC programming mode for a three-dimensional memory;

FIG. 7 is a schematic diagram of the physical mechanism of transient read errors on the first read;

FIG. 8 is a flowchart illustrating a method for reading a three-dimensional memory according to an embodiment of the invention;

FIG. 9 is a diagram illustrating a method for reading a three-dimensional memory according to an embodiment of the invention;

FIG. 10 is a schematic diagram of a failed bit count for a read method of a three-dimensional memory;

FIG. 11 is a circuit schematic of an exemplary three-dimensional memory 100 including peripheral circuitry in accordance with aspects provided by an embodiment of the invention;

FIG. 12 is a side view, in cross-section, of an example memory array 1101 that includes NAND memory strings 1108 in accordance with some aspects of the present invention;

FIG. 13 is a block diagram of an exemplary memory including a memory array and peripheral circuitry in accordance with some aspects of the present invention;

FIG. 14 is a block diagram of a memory system according to an embodiment of the present invention;

FIG. 15 is a block diagram of an exemplary data system 300 having a three-dimensional memory 100, in accordance with aspects of the present invention;

FIG. 16(A) is a diagram of an exemplary memory card having a three-dimensional memory 100, in accordance with some aspects of the present invention;

fig. 16(B) is a diagram of an exemplary Solid State Drive (SSD) with three-dimensional memory 100, according to some aspects of the invention.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, so that the scope of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood, not simply by the actual terms used but by the meaning of each term lying within.

The three-dimensional memory has a very large number of transient read errors when the first read is performed after a period of idle time after the programming/verifying/reading operations, i.e., the transient read errors during the first read are eliminated during the second read/the third read, which is not long in time. The failed bit count at the first read may be several times higher than the failed bit count at the second read. This phenomenon seriously affects the reliability of the three-dimensional memory because even though methods such as Low Density Parity Check (LDPC) code, etc. are used to solve the problem of high count of failed bits, it will greatly increase power consumption and affect the Quality of Service (QoS) of the whole device.

Fig. 4 to 5 are schematic diagrams of transient read errors when different logical pages are read for the first time in a TLC programming mode of a three-dimensional memory. FIG. 6 is a sequential schematic diagram of a TLC programming mode of a three-dimensional memory in which one read operation is performed on a certain page of memory to apply read voltages to selected word lines coupled to the certain page of memory. It should be noted that, the sequential schematic diagram of applying the read voltage shown in fig. 6 corresponds to a gray code encoding, and when the gray code encoding is adopted, for the three-dimensional memory TLC programming mode, the binary codes mapped by the 8 data states respectively are: (111) corresponding to an erasing state; (110) corresponding to a first programming state; (100) corresponding to the second programming state; (000) corresponding to the third programming state; (010) corresponding to the fourth programming state; (011) corresponding to the fifth programming state; (001) corresponding to the sixth programming state; (101) corresponding to the seventh programmed state. The 3-bit binary code may be named as a left-to-right Most Significant Bit (MSB), a middle significant bit (CSB), and a Least Significant Bit (LSB), for example, the fifth program state corresponds to a binary (011) with MSBs of "0", CSB of "1", and LSBs of "1". In some embodiments, for the reading of the memory, the reading is performed in units of memory pages, and for the TLC programming mode, each memory Page has a logic low Page (Lower Page), a logic Middle Page (Middle Page), and a logic high Page (Upper Page), as shown in table 1. That is, when reading each memory page in the TLC programming mode, three logical pages need to be read, which may be a read logical low page, a read logical middle page, and a read logical high page in order. In such a read sequence, the sequence of applying read voltages to the selected word line coupled to a certain page can be as shown in FIG. 6, first reading the logic low page by reading P1 and P5, requiring applying a first read voltage to read P1 and applying a fifth read voltage to read P5 to the selected word line; reading the logic middle page through reading P2, P4 and P6, and applying a second reading voltage for reading P2, a fourth reading voltage for reading P4 and a sixth reading voltage for reading P6 to the selected word line; finally, reading a logic high page by reading P3 and P7 requires applying a third read voltage for reading P3 and applying a seventh read voltage for reading P7 to the selected word line.

It should be understood that, in practical applications, the memory may also be programmed by using other encoding manners, and the reading sequence corresponding to different encoding manners may also be different, that is, the reading sequence shown in fig. 6 is only an example.

TABLE 1

	Er	P1	P2	P3	P4	P5	P6	P7
									Logic low page	1	0	0	0	0	1	1	1
Logical middle page	1	1	0	0	1	1	0	0
									Logic high page	1	1	1	0	0	0	1	0

Referring to fig. 4 to 6, in the storage encoding scheme shown in fig. 6, the transient read error at the first read is especially serious when the logic low page is read for the TLC programming mode of the three-dimensional memory, and especially the fifth programming state (P5) is the most serious. The reason is that when reading P5 is performed before reading the first programmed state (P1) as compared to reading the other programmed states, a negative voltage is applied to the control gate of the selected word line when reading P1, which causes more Grain Boundary Traps (GBTs) to release electrons, resulting in a larger faulty bit count and a more serious transient read error during the first read.

FIG. 7 is a schematic diagram of the physical mechanism of transient read errors on the first read. Referring to fig. 7, immediately after the programming of the memory cell is completed, the quasi-fermi level is close to the conduction band due to the higher applied gate voltage, and the probability of the trap being occupied at the fermi level is 50%. According to the fermi dirac function, below the fermi level, the closer to the valence band, the greater the probability that a trap is occupied. At time t0, most of the traps in the polysilicon channel are in a filled state. During the idle time from t0 to t1, the gate voltage becomes floating and finally drops to 0V, at which time the quasi-Fermi level moves down, and the traps in the polysilicon release electrons to become empty traps. Therefore, at time t1 when the first read just begins, a large number of empty traps are encountered, and the threshold voltage for reading at this time is small, resulting in a large number of faulty bit counts. After the first read, the traps are refilled, the filling state of the traps in the polysilicon is closer to the state at the end of programming, the count of failed bits at the time of reading is restored to the normal level, and the count of failed bits at the time of reading is greatly different from the count of failed bits at the time of reading for the first time. In addition, if a negative voltage is applied to the control gate of the selected word line, where the fermi level is further away from the conduction band, this may exacerbate the outward release of electrons from the traps, which may exacerbate transient read errors in the first read. In view of this, an optimized reading method for a three-dimensional memory is important.

In view of the above technical problems, the following embodiments of the present invention provide a method for reading a three-dimensional memory and a three-dimensional memory, so as to at least reduce the count of faulty bits during the first reading operation.

Fig. 8 is a flowchart of a method for reading a three-dimensional memory according to an embodiment of the invention. Fig. 9 is a schematic diagram illustrating a method for reading a three-dimensional memory according to an embodiment of the invention. The reading method will be described with reference to fig. 8 and 9. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.

Referring to fig. 8, a three-dimensional memory of the present invention includes one or more memory pages, and one or more word lines respectively coupled to the one or more memory pages, each memory page including one or more memory cells, and on this basis, the reading method includes:

Here, the selected word line is the word line to which the page of memory desired to be read is coupled (or connected).

It should be noted that the reading method is applicable to any type of memory cell, in other words, the memory cells in the memory page can be any of SLC, MLC, TLC and QLC. When a reading operation is executed on a memory cell of a selected word line, judging whether the reading operation is a first reading operation; when the read operation is a first read operation, a first pulse voltage is applied to the selected word line before a read voltage is applied to the selected word line. In some embodiments, the first pulse voltage is a positive voltage, so that before a first read operation is performed on the three-dimensional memory, the memory cells in the memory page coupled with the selected word line are refilled into the traps due to electrons released outwards by the traps of the long-term idle memory cells, thereby effectively improving transient read errors in the first read operation.

In some embodiments, the determining whether the read operation is a first read operation may include:

determining an idle time between a previous execution of a first operation on the three-dimensional memory and a read operation on the three-dimensional memory; the first operation is the same as or different from the read operation;

And judging whether the reading operation is the first reading operation or not based on the idle time.

In some embodiments, the first operation may include one of: programming or verifying or reading. Other operations on the three-dimensional memory may also be performed, for example, the first operation performed on the three-dimensional memory is a power-on operation, that is, the first operation of the three-dimensional memory before the read operation is performed is a power-on operation, that is, the three-dimensional memory is not idle for a period of time after being powered on to start the read operation.

In some embodiments, the determining whether the read operation is a first read operation based on the idle time may include:

judging whether the idle time is greater than or equal to a first time or not;

determining the read operation as a first read operation when it is determined that the idle time is greater than or equal to the first time;

determining that the read operation is not a first read operation when it is determined that the idle time is less than the first time.

That is, in an embodiment of the present invention, the reading method further includes determining whether the read operation is a first read operation according to an idle time of the three-dimensional memory before the read operation.

For example, when the idle time is greater than or equal to the first time, the read operation may be determined to be a first read operation. Determining that the read operation is not a first read operation when it is determined that the idle time is less than the first time.

Preferably, in an embodiment of the present invention, the first time is 12 hours. For example, if the idle time of the three-dimensional memory is greater than or equal to 12 hours before the read operation, it is determined that the read operation is the first read operation.

In some embodiments, the determining whether the read operation is a first read operation may also include:

determining a gate voltage applied to the selected word line a previous time a first operation was performed on the three-dimensional memory;

and judging whether the reading operation is a first reading operation or not based on the grid voltage.

In some embodiments, the determining whether the read operation is a first read operation based on the gate voltage includes:

judging whether the grid voltage is a negative voltage or not;

when the grid voltage is a negative voltage, the reading operation is determined to be a first reading operation.

Here, when the gate voltage applied to the selected word line is a negative voltage in the first operation performed on the three-dimensional memory at the previous time, the read operation at this time may also be considered as a first read operation, since it also has a phenomenon of a transient read error. When the gate voltage is not a negative voltage (e.g., a positive voltage), it is determined that the read operation is not the first read operation, i.e., the read operation is not considered to be the first read operation.

In the foregoing description, the reading method provided by the embodiment of the present invention is applicable to any type of memory cell, and in some embodiments, the memory cell of the selected word line is a three-level cell TLC. That is, in one embodiment of the present invention, the programming mode of the three-dimensional memory is a triple-Level Cell (TLC). The three-level cell programming mode is 3bit/cell, namely, each storage cell tube stores 3-bit data.

In some embodiments, the memory cells of the selected word line include different first, second, third, fourth, fifth, sixth, and seventh programmed states P1, P2, P3, P4, P5, P6, and P7.

It should be noted that, as described above, a TLC type memory cell has 8 in data states, an erased state and 7 in programmed state, which can be divided into a logic high page, a logic middle page and a logic low page to store 3 bits of data.

In some embodiments, for memory cells of the selected word line that are read when encoded according to the gray code shown in table 1, the sequence of applying the read voltage pulses to the selected word line may be as shown in fig. 6. At this time, in some embodiments, when reading the logic low page of the memory cells of the selected word line by applying a first read voltage for reading the first program state to the selected word line and applying a fifth read voltage for reading the fifth program state to the selected word line, the reading method further comprises:

Applying the first pulse voltage to the selected word line between applying the first read voltage to the selected word line and applying the fifth read voltage to the selected word line;

wherein the first programming state and the fifth programming state are two programming states in the TLC, and the threshold voltage corresponding to the first programming state is smaller than the threshold voltage corresponding to the fifth programming state.

It should be noted that when the read operation is a first read operation, the first program state P1 and the fifth program state P5 need to be read when reading the logic low page in the memory cells of the selected word line, that is, the first read voltage of the read P1 needs to be applied to the selected word line of the memory cells coupled to the selected word line first, since in some embodiments, in some examples, the first read voltage applied to the control gate of the selected word line of the three-dimensional memory is a negative voltage when reading the first program state P1; in reading the fifth program state P5, the fifth read voltage applied to the control gate of the three-dimensional memory selected word line is a positive voltage, that is: the first read voltage for read P1 may be a negative voltage; the fifth read voltage for reading P5 is a positive voltage. Based on the fact that the threshold voltage of the memory cell shifts to a small value after the three-dimensional memory in fig. 7 is idle for a period of time, the first read voltage is a negative voltage when reading P1, which results in a lower threshold voltage before reading the memory cell P5 and a higher count of failed bits when reading P5, therefore, in order to solve this problem, in this case, when reading the logic low page of the memory cell of the selected word line, the first pulse voltage is applied to the selected word line between the application of the first read voltage to the selected word line and the application of the fifth read voltage to the selected word line, as shown in fig. 9.

In some examples, the first pulse voltage may have a magnitude of 2-7V. The duration of the first pulse voltage may be 5-15 mus.

Preferably, the first pulse voltage is greater than the read voltage applied to the selected word line.

Optionally, the first pulse voltage is 2 volts; the read voltage is 1.41 volts. The read voltage here may be the aforementioned fifth read voltage.

It should be understood that, those skilled in the art can make corresponding adjustments to the magnitude and duration of the first pulse voltage according to actual needs, and the invention is not limited thereto.

In an embodiment of the present invention, the magnitude of the first pulse voltage is greater than the read voltage of the highest state in the programmed states. For example, in one example shown in fig. 9, the magnitude of the first pulse voltage may also be greater than the highest voltage in the programmed states (the seventh read voltage of the seventh programmed state P7).

In an embodiment of the present invention, the duration of the first pulse voltage is less than the duration of a read voltage required to read any one of the programmed states of the memory cells of the selected word line, i.e., the duration of the first pulse voltage is less than the duration of any one of the programmed states. That is, the duration of the first pulse voltage is less than the duration of the read voltage of any one of the first read voltage for reading the first program state P1, the fifth read voltage for reading the fifth program state P5, the second read voltage for reading the second program state P2, the fourth read voltage for reading the fourth program state P4, the sixth read voltage for reading the sixth program state P6, the third program voltage for reading the third program state P3, and the seventh read voltage for reading the seventh program state P7.

After the first pulse voltage is applied between the reading of the first programming state P1 and the reading of the fifth programming state P5, the first programming state P1 in the previous reading state is trapped by released electrons to recapture the electrons, so that the failure bit count when the fifth programming state P5 is read when the first reading operation is performed on the three-dimensional memory is reduced, and the transient reading error during the first reading is further optimized.

It will be appreciated that in some examples of the invention (e.g., one example shown in FIG. 9), the above-described read sequence includes sequentially reading the first program state P1, the fifth program state P5, the second program state P2, the fourth program state P4, the sixth program state P6, the third program state P3, and the seventh program state P7.

It should be noted that, according to the reading sequence shown in fig. 9, when the memory cell of the selected word line is read for the first time, the middle page and the high page are not read by applying the reading voltage to the selected word line for the first time, and at this time, the time between two times is relatively short, and the threshold voltage of the memory cell does not shift down due to TER, so that it is not necessary to apply a positive pulse voltage before reading when reading the second programming state P2, reading the fourth programming state P4, reading the sixth programming state P6, reading the third programming state P3, and reading the seventh programming state P7.

Fig. 9 is only an example, for different encoding methods of the three-dimensional memory, the corresponding reading sequence may also be different, for different reading sequences, TER occurs when the three-dimensional memory is read for the first time, and then FBC is higher, at this time, when the first reading operation is performed, a positive pulse voltage needs to be applied to the control gate of the selected word line to refill the traps of the memory cells with lost electrons, so as to effectively improve the transient reading error during the first reading.

Fig. 10 is a schematic diagram of a fail bit count of a read method of a three-dimensional memory. Referring to fig. 10, the gate voltage Vg on the word line is held Floating (Floating) and 2V, respectively, during an idle time before the first read operation. It is apparent that, when the first read operation is performed on the three-dimensional memory, the defective bit count when the fifth program state P5 is read is more severe than when other program states are read. Also, when the control gate voltage of the selected word line is maintained at 2V (first pulse voltage), the failed bit count when the fifth program state P5 is read is significantly reduced compared to when the control gate voltage of the selected word line is floating (i.e., Vg ═ 0V). Maintaining the control gate voltage of the selected word line at 2V has a much larger optimization space and better optimization for reading the fifth program state P5 than for reading the other program states. That is, in an embodiment of the present invention, the first pulse voltage is a positive pulse.

As can be seen from fig. 7, the first pulse voltage can induce the empty trap to recapture electrons, alleviating the problem of releasing more traps due to the negative voltage on the selected line when the first programming state P1 is read. This operation of applying the first pulse voltage to the selected word line is particularly important to alleviate the first read phenomenon (FRI) when reading the fifth program state P5, and the fifth program state P5 is the most serious one of the TLC program states in terms of FRI in the coding scheme shown in table 1, which solves the problem that the FRI reading the fifth program state P5 will greatly benefit the FRI of the entire three-dimensional memory in the TLC program mode.

On the other hand, if the time from the last programming/reading is not long at the time of the reading operation, i.e., the idle time is short, since the transient read error can be repaired by error correction control coding (ECC) such as low density parity check code at the time of the first reading, the application of the first pulse voltage can be omitted.

In an embodiment of the present invention, when the first operation is a read operation, the read method may further include:

determining a time interval between performing an Nth read operation on the three-dimensional memory and performing an N-1 th read operation on the three-dimensional memory when performing the Nth read operation on the memory cells of the selected word line;

Judging whether the time interval is greater than or equal to a second time;

when the time interval is greater than or equal to a second time, applying a second pulse voltage to the selected word line before performing the Nth read operation on the three-dimensional memory;

when the time interval is less than the second time, applying the read voltage directly to the selected word line while performing the Nth read operation on the three-dimensional memory; wherein N is greater than or equal to 2.

For a reading method of a three-dimensional memory with a plurality of reading operations, in a plurality of reading operations after a first reading operation, if a time interval between an Nth reading operation and an N-1 th reading operation before the Nth reading operation is greater than or equal to a second time, a second pulse voltage is applied to the selected word line before the Nth reading operation is performed on the three-dimensional memory, wherein N is greater than or equal to 2.

For example, a read method for a three-dimensional memory having three read operations. If the time interval between the second read operation and the first read operation is greater than or equal to a second time, a second pulse voltage needs to be applied to the selected word line before the second read operation is performed on the three-dimensional memory. Similarly, if the time interval between the third read operation and the second read operation is greater than or equal to the second time, the second pulse voltage needs to be applied to the selected word line before the third read operation is performed on the three-dimensional memory.

In some embodiments, when the time interval is less than the second time, the read voltage is applied directly to the selected word line when the nth read operation is performed on the three-dimensional memory; wherein N is greater than or equal to 2. That is, the time interval between two read operations is short, and it is not necessary to apply the second pulse voltage to the selected word line before the next read.

In some embodiments, the memory cells included in the selected word line are three level cells TLC; the sequence of the Nth reading operation performed on the memory cells of the selected word line sequentially comprises: reading a logic low page of memory cells of the selected word line, reading a logic middle page of memory cells of the selected word line, and reading a logic high page of memory cells of the selected word line; when reading a logical low page of memory cells of the selected word line by applying a first read voltage to the selected word line for reading a first program state and a fifth read voltage to the selected word line for reading a fifth program state, the reading method further comprises:

applying the second pulse voltage to the selected word line between the applying the first read voltage to the selected word line and the applying the fifth read voltage to the selected word line;

Namely: if the three-dimensional memory is programmed according to the TLC programming mode and the coding mode of the corresponding memory cell is in the form shown in table 1, when two read operations are performed, and the time interval between the two read operations is greater than or equal to a second time, the second pulse voltage is applied to the selected word line between the application of the first read voltage to the selected word line and the application of the fifth read voltage to the selected word line.

For example, a read method for a three-dimensional memory having three read operations. If the time interval between the second read operation and the first read operation is greater than or equal to the second time, the second read operation requires the application of the second pulse voltage between the reading of the first program state P1 and the reading of the fifth program state P5. Similarly, if the time interval between the third read operation and the second read operation is greater than or equal to the second time, the third read operation requires the application of the second pulse voltage between the reading of the first program state P1 and the reading of the fifth program state P5.

It should be noted that the three-dimensional memory is programmed according to the aforementioned TLC programming mode, and the coding mode of the corresponding memory cell is in the form shown in table 1, and the reading sequence when the three-dimensional memory is read is shown in fig. 6.

In one embodiment of the present invention, the second time period is 12 hours. That is, in several read operations after the first read operation, if the time interval between two adjacent read operations is greater than or equal to 12 hours, the corresponding read operation requires the application of the second pulse voltage between the first program state P1 and the fifth program state P5.

In an embodiment of the invention, the second pulse voltage has the same magnitude and/or duration as the first pulse voltage.

In an embodiment of the invention, the duration of the second pulse voltage is less than the duration of the first pulse voltage.

In some examples, the second pulse voltage may have a magnitude of 2-7V. The duration of the second pulse voltage may be 5-15 mus. By applying the first pulse voltage between the reading of the first program state P1 and the reading of the fifth program state P5 in the first reading operation or applying the second pulse voltage between the reading of the first program state P1 and the reading of the fifth program state P5 in a plurality of subsequent reading operations, the interference of electron releasing from grain boundary traps caused when the reading voltage applied to the control gate of the selected word line is negative in the reading of the previous program state can be suppressed, and the problem of a significant increase in the defective bit count caused by the electron releasing grain boundary traps occurring before the reading is optimized.

The above embodiments of the present invention provide a reading method of a three-dimensional memory, which can reduce the count of failed bits at the first reading operation. Due to the adoption of the technical scheme, compared with the prior art, the embodiment of the invention has the following remarkable advantages: according to the reading method of the three-dimensional memory and the three-dimensional memory provided by the embodiment of the invention, when the first reading operation is carried out, the first pulse voltage is applied before the reading operation is carried out, so that the downward shift of the threshold value unit of the storage unit caused by long-time idle of the memory is effectively relieved, and the fault bit count of the memory when the first reading operation is carried out is reduced.

Another aspect of the present invention is to provide a three-dimensional memory that can reduce a fail bit count when a first read or two read operations are performed with a time interval greater than a second time.

Fig. 11 is an architecture diagram of a three-dimensional memory according to an embodiment of the invention. A three-dimensional memory according to an embodiment of the present invention is described below with reference to fig. 11. It is to be understood that the following description is merely exemplary, and that variations may be made by those skilled in the art without departing from the spirit of the invention.

As shown in fig. 11, a circuit schematic of an exemplary three-dimensional memory 100 including peripheral circuitry is shown in accordance with aspects provided by embodiments of the present invention. Referring to fig. 11, a three-dimensional memory 100 provided by an embodiment of the invention may include a memory array 1101 and peripheral circuitry 1103 coupled to the memory array 1101. Specifically, as shown in fig. 11, the three-dimensional memory 100 may include:

a memory array 1101, the memory array 1101 comprising one or more memory pages; each of the memory pages comprises one or more memory cells;

one or more word lines 1102 respectively coupled with the one or more memory pages 1120;

and peripheral circuitry 1103 coupled on the one or more word lines and used to control the memory array; wherein the content of the first and second substances,

the peripheral circuitry is configured to: when a reading operation is executed on a memory cell of a selected word line, judging whether the reading operation is a first reading operation;

In some embodiments, the determining whether the read operation is a first read operation includes:

In some embodiments, said determining whether the read operation is a first read operation based on the idle time comprises:

judging whether the idle time is greater than or equal to a first time or not;

Judging whether the grid voltage is a negative voltage or not;

when the grid voltage is a negative voltage, judging that the reading operation is a first reading operation;

when the gate voltage is a negative voltage, it is determined that the read operation is not a first read operation.

In some embodiments, the first operation comprises one of: programming or verifying or reading.

In some embodiments, the first time is 12 hours.

In some embodiments, the memory cells of the selected word line are three level cell TLCs.

In some embodiments, when reading a logic low page of memory cells of the selected word line by applying a first read voltage for reading a first program state to the selected word line and a fifth read voltage for reading a fifth program state to the selected word line, the reading method further comprises:

applying the first pulse voltage to the selected word line between the applying the first read voltage to the selected word line and the applying the fifth read voltage to the selected word line;

Wherein the first programming state and the fifth programming state are two programming states in the TLC and the threshold voltage corresponding to the first programming state is less than the threshold voltage corresponding to the fifth programming state.

In some embodiments, when reading the logical low page of memory cells of the selected word line by applying a first read voltage to the selected word line for reading a first program state and a fifth read voltage to the selected word line for reading a fifth program state, the peripheral circuitry is further configured to: sequentially applying the first read voltage to the selected word line, the first pulse voltage to the selected word line; applying the fifth read voltage to the selected word line;

wherein the first programming state and the fifth programming state are two programming states in the TLC, and the threshold voltage corresponding to the first programming state is smaller than the threshold voltage corresponding to the fifth programming state. Namely: applying the first pulse voltage to the selected word line between the applying the first read voltage to the selected word line and the applying the fifth read voltage to the selected word line.

In some embodiments, the first read voltage is a negative voltage; the fifth read voltage is a positive voltage.

In some embodiments, the first pulse voltage is greater than the read voltage applied to the selected word line.

In some embodiments, the first pulse voltage is 2 volts; the read voltage is 1.41 volts.

In some embodiments, when the first operation is a read operation, the peripheral circuitry may be further configured to:

judging whether the time interval is greater than or equal to a second time;

when the time interval is less than the second time, directly applying the read voltage to the selected word line while performing the Nth read operation on the three-dimensional memory; wherein N is greater than or equal to 2.

In some embodiments, the memory cells included in the selected word line are three levels of cell TLC; the sequence of the Nth time of reading operation performed on the memory cells of the selected word line sequentially comprises: reading a logic low page of memory cells of the selected word line, reading a logic middle page of memory cells of the selected word line, and reading a logic high page of memory cells of the selected word line; when reading a logical low page of memory cells of the selected word line by applying a first read voltage to the selected word line for reading a first program state and a fifth read voltage to the selected word line for reading a fifth program state, the control voltages are further configured to:

In some embodiments, the memory array is a three-dimensional NAND array.

It should be noted that, in the reading method provided in the foregoing embodiment of the present invention, each term and step have been explained in detail, and are also applicable and not described herein again.

In some embodiments, as previously described, the memory array 1101 may be an array of NAND flash memory storage cells, wherein the storage cells 1106 are provided in an array of NAND memory strings 1108, each NAND memory string 1108 extending vertically above a substrate (not shown). in some embodiments, each NAND memory string 1108 includes a plurality of storage cells 1106 coupled in series and stacked vertically. Each memory cell 1106 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 1106. Each memory cell 1106 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 1106 may be a Single Level Cell (SLC) having two possible memory states and therefore may store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 1106 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell. In some embodiments, three bits per memory cell 1106 (also referred to as a three-level cell (TLC)) or four bits per memory cell 1106 (also referred to as a four-level cell (QLC)). Each MLC may be programmed to assume a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values to the memory cell. The fourth nominal storage value may be used for the erased state. In another example, if each TLC stores three bits of data, the TLC has 7 programmed states, 1 erased state, and may be encoded as described in table 1 above.

As shown in fig. 11, each NAND memory string 1108 may include a Source Select Gate (SSG)1110 at its source end and a Drain Select Gate (DSG)1112 at its drain end. The SSGs 1110 and 1112 may be configured to activate selected NAND memory strings 1108 (columns of the array) during read and program operations. In some implementations, the sources of NAND memory strings 1108 in the same block 1104 are coupled by the same Source Line (SL)1214 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 1108 in the same block 1104 have an Array Common Source (ACS). According to some embodiments, the DSG 1112 of each NAND memory string 1108 is coupled to a respective bit line 1116 from which data may be read or written via an output bus (not shown). In some implementations, each NAND memory string 1108 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 1112) or a deselect voltage (e.g., 0V) to the corresponding DSG 1112 via one or more DSG lines 1113 and/or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 1110) or a deselect voltage (e.g., 0V) to the corresponding SSG 1110 via one or more SSG lines 1115.

As shown in fig. 11, the NAND memory strings 1108 may be organized into a plurality of blocks 1104, each of the plurality of blocks 1104 may have a common source line 1114 (e.g., coupled to ground). In some embodiments, each block 1104 is the basic unit of data used for an erase operation, i.e., all memory cells 1106 on the same block 1104 are erased at the same time. To erase memory cells 1106 in a selected block 1104, the source line 1114 coupled to the selected block 1104 and to unselected blocks 1104 in the same plane as the selected block 1104 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, the erase operation may be performed at a half block level, at a quarter block level, or at any suitable fraction of a number of blocks or blocks. The memory cells 1106 of adjacent NAND memory strings 1108 may be coupled by a word line 1102, and the word line 1102 selects which row of memory cells 1106 is affected by read and program operations. In some implementations, each word line 1102 is coupled to a memory page 1120 of memory cells 1106, the memory page 1120 being the basic unit of data for a programming operation. The size of a page 1120 of memory in bits may be related to the number of NAND memory strings 1108 coupled by a word line 1102 in one block 1104. Each word line 1102 may include a plurality of control gates (gate electrodes) at each memory cell 1106 in a respective memory page 1120 and a gate line coupling the control gates. It is to be noted that the memory cells of the selected word line in the three-dimensional memory 100 provided in fig. 11 may include one or more memory pages 1120.

FIG. 12 illustrates a side view of a cross section of an example memory array 1101 including NAND memory strings 1108 in accordance with some aspects of the present invention. As shown in fig. 12, NAND memory strings 1108 may extend vertically through memory stack layers 1204 above substrate 1202. Substrate 1202 may comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

Memory stack layer 1204 may include alternating gate conductive layers 1206 and gate-to-gate dielectric layers 1208. The number of pairs of gate conductive layers 1206 and gate-to-gate dielectric layers 1208 in memory stack layer 1204 may determine the number of memory cells 1106 in memory array 1101. The gate conductive layer 1206 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 1206 comprises a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 1206 comprises a doped polysilicon layer. Each gate conductive layer 1206 may include a control gate surrounding a memory cell 1106 and may extend laterally at the top of memory stack layer 1204 as a DSG line 1113, laterally at the bottom of memory stack layer 1204 as an SSG line 1115, or laterally between DSG line 1113 and SSG line 1115 as a word line 1102.

As shown in FIG. 12, NAND memory string 1108 includes a channel structure 1212 that extends vertically through memory stack layers 1204. In some implementations, the channel structure 1212 includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel 1220) and dielectric material(s) (e.g., as a memory film 1218). In some embodiments, the semiconductor channel 1220 comprises silicon, e.g., polysilicon. In some embodiments, the memory film 1218 is a composite dielectric layer that includes a tunneling layer 1226, a storage layer 1224 (also referred to as a "charge trapping/storage layer"), and a blocking layer 1222. The channel structure 1212 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 1220, the tunneling layer 1226, the storage layer 1224, and the barrier layer 1222 are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer 1226 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 1224 may include silicon nitride, silicon oxynitride, or any combination thereof. Barrier layer 1222 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, memory film 1218 can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

According to some embodiments, as shown in fig. 12, a well 1214 (e.g., a P-well and/or an N-well) is formed in the substrate 1202, and the source terminal of the NAND memory string 1108 is in contact with the well 1214. For example, a source line 1114 may be coupled to the well 1214 to apply an erase voltage to the well 1214 (i.e., the source of the NAND memory string 1108) during an erase operation. In some implementations, the NAND memory string 1108 also includes a channel plug 1216 at the drain end of the NAND memory string 1108. It should be understood that although not shown in fig. 13, additional components of memory array 1101 can be formed, including but not limited to gate line apertures/source contacts, local contacts, interconnect layers, and the like.

Referring back to FIG. 11, peripheral circuitry 1103 may be coupled to the memory array 1101 by bit lines 1116, word lines 1102, source lines 1114, SSG lines 1115, and DSG lines 1113. The peripheral circuitry 1103 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory array 1101 by applying voltage and/or current signals to and sensing voltage and/or current signals from each target memory cell 1106 via the bit lines 1116, the word lines 1102, the source lines 1114, the SSG lines 1115, and the DSG lines 1113. The peripheral circuit 1103 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 13 shows some exemplary peripheral circuits, the peripheral circuits 1103 including page buffers/sense amplifiers 1304, column decoders/bit line drivers 1306, row decoders/word line drivers 1308, voltage generators 1310, control logic units 1312, registers 1314, interfaces 1316, and a data bus 1318. It should be understood that additional peripheral circuitry not shown in fig. 14 may also be included in some examples.

The page buffer/sense amplifier 1304 may be configured to read data from the memory array 1101 and program (write) data to the memory array 1101 in accordance with control signals from the control logic unit 1312. In one example, the page buffer/sense amplifier 1304 may store a page of programming data (write data) to be programmed into one memory page 1120 of the memory array 1101. In another example, the page buffer/sense amplifier 1304 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 1106 coupled to the selected word line 1102. In yet another example, page buffer/sense amplifier 1304 may also sense low power signals from bit line 1116 representing a data bit stored in memory cell 1106 and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder/bit line driver 1306 may be configured to be controlled by the control logic unit 1312 and select one or more NAND memory strings 1108 by applying a bit line voltage generated from the voltage generator 1310.

The row decoder/word line driver 1308 may be configured to be controlled by the control logic unit 1312 and to select/deselect a block 1104 of the memory array 1101 and to select/deselect a word line 1102 of the block 1104, wherein the selected word line, also referred to as the selected word line, is used to read a memory page coupled to the selected word line by applying a read voltage thereto or is used to program the memory page by applying a program voltage thereto. The row decoder/word line driver 1308 may also be configured to drive the word line 1102 using a word line voltage generated from the voltage generator 1310. In some embodiments, the row decoder/word line driver 1308 may also select/deselect and drive the SSG lines 1115 and the DSG lines 1113. For example, the row decoder/wordline driver 1308 is configured to perform an erase operation on memory cells 1106 coupled to the selected wordline(s) 1102. The voltage generator 1310 may be configured to be controlled by the control logic unit 1312 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 1101.

Control logic unit 1312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Registers 1314 may be coupled to control logic unit 1312 and include status, command, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 1316 may be coupled to control logic unit 1312 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 1312, and to buffer and relay status information received from control logic unit 1312 to the host. The interface 1316 may also be coupled to the column decoder/bit line drivers 1306 via a data bus 1318 and acts as a data I/O interface and data buffer to buffer data and relay it to or from the memory array 1101. It is to be noted that the interface 1316 may include a first storage interface and/or a second storage interface described below.

Based on the structure of the three-dimensional memory described above, when performing a write operation (or referred to as programming) on the three-dimensional memory, the three-dimensional memory can be programmed according to a memory page, or according to a single or multiple memory cells, and the programming principle can be to write data into a selected memory cell by using FN tunneling efficiency. Taking the selected memory cell 1106 as an example, the programming voltage VPG is applied to the word line coupled to the selected memory cell 1106 (referred to as the selected word line), for example, about 20V, and the remaining word lines (referred to as unselected word lines) are biased at the low voltage VPS 1; such as applying a low level (e.g., 0 volts (V)) to the bit line to which the selected NAND memory string 1108 is connected, the select transistor included is turned on; the bit line to which the unselected NAND memory string 1108 is connected applies a high level (e.g., the system voltage VDD), including the select transistor turned off.

When the three-dimensional memory is read, the electric charge quantity in the floating grid electrode is judged according to the conduction state of the selected memory unit, and therefore data represented by the electric charge quantity is obtained. Taking a memory page as a read unit, taking a selected memory page 1120 as an example, the word line coupled to the selected memory page 1120 (referred to as a selected word line) is biased at a read voltage Vread, and the remaining word lines (referred to as unselected word lines) are biased at a pass voltage Vpass. The on-state of a memory cell in the selected page 1120 is related to its threshold voltage, i.e., the amount of charge in the control gate, so that the data value can be determined from the on-states of the memory cells in the selected page 1120. And other memory cells of the same NAND memory string as the memory cell are always conducted under the action of the conducting voltage.

In some embodiments, the embodiment of the invention also provides a memory system comprising the three-dimensional memory. Fig. 14 is a schematic structural diagram of a memory system according to an embodiment of the present invention.

Referring to fig. 14, the memory system 200 includes the three-dimensional memory 100 described above; and a memory controller 1402 coupled to the three-dimensional memory and configured to control the three-dimensional memory.

In some embodiments, memory system 200 comprises a three-dimensional memory, wherein the three-dimensional memory comprises:

one or more word lines respectively coupled to the one or more memory pages;

In some embodiments, the memory cells of the selected word line are three-level cells TLC, wherein the memory cells include different first, second, third, fourth, fifth, sixth, and seventh program states P1, P2, P3, P4, P5, P6, and P7.

In some embodiments, the memory system 200 further comprises a first memory interface and a second memory interface, wherein the memory controller communicates with the three-dimensional controller through the first memory interface; the memory controller communicates with a host coupled to the memory system through the second communication interface.

In some embodiments, the memory system 200 is a solid state disk, SSD, or memory card.

It should be noted that the first storage interface and the second storage interface may be included in the interface 1316 in fig. 13.

It is noted that the memory system described in FIG. 14 may also be combined with a host to form a data system 300, for example, FIG. 15 shows a block diagram of an exemplary data system 300 with three-dimensional memory in accordance with aspects of the present invention. Data system 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 15, data system 300 may include a host 1501 and a memory system 200, the memory system 200 having one or more three-dimensional memories 100 and a memory controller 1402. The host 1501 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 1501 may be configured to transmit data to the three-dimensional memory 100 or receive data from the three-dimensional memory 100.

The three-dimensional memory 100 may be any of the three-dimensional memories disclosed in the present invention. As disclosed in detail below, the three-dimensional memory 100 (e.g., a NAND flash three-dimensional memory (e.g., a three-dimensional (3D) NAND flash three-dimensional memory)) may have reduced leakage current from the drive transistors (e.g., string drivers) coupled to unselected word lines during an erase operation, which allows for further scaling of the drive transistors.

According to some embodiments, memory controller 1402 is coupled to three-dimensional memory 100 and host 1501, and is configured to control three-dimensional memory 100. The memory controller 1402 can manage data stored in the three-dimensional memory 100 and communicate with the host 1501. In some implementations, the memory controller 1402 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 1402 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like. The memory controller 1402 may be configured to control operations of the three-dimensional memory 100, such as read, erase, and program operations. The memory controller 1402 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 100, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 1402 is further configured to process an Error Correction Code (ECC) with respect to data read from the three-dimensional memory 100 or written to the three-dimensional memory 100. The memory controller 1402 may also perform any other suitable functions, such as formatting the three-dimensional memory 100. The memory controller 1402 may communicate with an external device (e.g., the host 1501) according to a particular communication protocol. For example, the memory controller 1402 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The memory controller 1402 and the one or more three-dimensional memories 100 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 200 may be implemented and packaged into different types of terminal electronics. In one example as shown in fig. 16(a), the memory controller 1402 and the single three-dimensional memory 100 may be integrated into a memory card 1602. The memory card 1602 may include a PC card (PCMCIA, personal computer memory card International Association), CF card, Smart Media (SM) card, memory stick, MultiMedia card (MMC, RS-MMC, MMCmicro), SD card (SD, minisD, microsD, SDHC), UFS, and the like. The memory card 1602 may also include a memory card connector 1604 that couples the memory card 1602 to a host (e.g., host 1501 in FIG. 15). In another example as shown in fig. 16(B), the memory controller 1402 and the plurality of three-dimensional memories 100 may be integrated into the SSD 1606. SSD 1606 may also include SSD connector 1608 coupling SSD 1606 with a host (e.g., host 1501 in fig. 15). In some implementations, the storage capacity and/or operating speed of the SSD 1606 is greater than the storage capacity and/or operating speed of the memory card 1602.

It should be noted that the number and size of the components are not limited in the present invention, and as in another embodiment of the present invention, the parallel mechanism of the present invention comprises more than two sets of the first connecting member, the second connecting member and the telescopic rod, any selection and adjustment of the number and size of the components to achieve the effect of free rotation and meet the actual production requirement is within the spirit and scope of the present invention.

It is to be understood that while certain presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of illustration, and not by way of limitation, such details are provided for purposes of illustration only and the appended claims are intended to cover all such modifications and equivalent arrangements as fall within the true spirit and scope of the embodiments of the disclosure.

It should be understood that the above-described embodiments are illustrative only. The embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, and/or other electronic units designed to perform the functions described herein, or a combination thereof.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.

Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).

Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.

Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.

Where numerals describing the number of components, attributes or the like are used in some embodiments, it is to be understood that such numerals used in the description of the embodiments are modified in some instances by the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method for reading a three-dimensional memory, wherein the three-dimensional memory comprises one or more memory pages, and one or more word lines respectively coupled to the one or more memory pages, each memory page comprising one or more memory cells; the reading method comprises the following steps:

2. The method according to claim 1, wherein the determining whether the read operation is a first read operation comprises:

3. The reading method according to claim 2, wherein the determining whether the read operation is a first read operation based on the idle time comprises:

Judging whether the idle time is greater than or equal to a first time or not;

4. A reading method according to claim 3, characterized in that said first time is 12 hours.

5. The method according to claim 1, wherein the determining whether the read operation is a first read operation comprises:

6. The method of claim 5, wherein the determining whether the read operation is a first read operation based on the gate voltage comprises:

judging whether the grid voltage is negative voltage or not;

7. The reading method according to claim 2 or 5, wherein the first operation comprises one of: programming or verifying or reading.

8. The method according to claim 1, wherein the memory cells of the selected word line are three-level cell TLCs.

9. The method as claimed in claim 8, wherein the memory cells of the selected word line include different first, second, third, fourth, fifth, sixth and seventh program states P1, P2, P3, P4, P5, P6 and P7.

10. The reading method according to claim 9, wherein when reading the logic low page of the memory cells of the selected word line by applying a first read voltage for reading a first program state to the selected word line and applying a fifth read voltage for reading a fifth program state to the selected word line, the reading method further comprises:

11. The method according to claim 10, wherein the first read voltage is a negative voltage; the fifth read voltage is a positive voltage.

12. The method of claim 1, wherein the first pulse voltage is greater than the read voltage applied to a selected word line.

13. The reading method according to claim 12, wherein the first pulse voltage is 2 volts; the read voltage is 1.41 volts.

14. The method of claim 1, wherein the duration of the first pulse voltage is less than the duration of a read voltage required to read any one of the programmed states of the memory cells of the selected word line.

15. A three-dimensional memory, comprising:

one or more word lines respectively coupled to the one or more memory pages;

and peripheral circuitry coupled on the one or more word lines and for controlling the memory array; wherein the content of the first and second substances,

16. The three-dimensional memory according to claim 15, wherein the determining whether the read operation is a first read operation comprises:

17. The three-dimensional memory according to claim 16, wherein the determining whether the read operation is a first read operation based on the idle time comprises:

judging whether the idle time is greater than or equal to a first time or not;

18. The three-dimensional memory according to claim 15, wherein the determining whether the read operation is a first read operation comprises:

19. The three-dimensional memory according to claim 18, wherein the determining whether the read operation is a first read operation based on the gate voltage comprises:

judging whether the grid voltage is a negative voltage or not;

20. The three-dimensional memory according to claim 16 or 18, wherein the first operation comprises one of: programming or verifying or reading.

21. The three-dimensional memory according to claim 15, wherein the memory cells of the selected word line are three-level cells TLC, wherein the memory cells comprise different first, second, third, fourth, fifth, sixth, and seventh program states P1, P2, P3, P4, P5, P6, and P7.

22. The three-dimensional memory of claim 21, wherein, when reading the logical lower page of memory cells of the selected word line by applying a first read voltage to the selected word line for reading a first program state and applying a fifth read voltage to the selected word line for reading a fifth program state, the peripheral circuitry is further configured to: sequentially applying the first read voltage to the selected word line, the first pulse voltage to the selected word line; applying the fifth read voltage to the selected word line;

23. The three-dimensional memory according to claim 15, wherein the memory array is a three-dimensional NAND array.

24. A memory system comprising a three-dimensional memory, wherein the three-dimensional memory comprises:

one or more word lines respectively coupled to the one or more memory pages;

25. The memory system of claim 24, wherein the memory cells of the selected word line are Three Level Cells (TLC), wherein the memory cells comprise different first, second, third, fourth, fifth, sixth, and seventh program states P1, P2, P3, P4, P5, P6, and P7.

26. The memory system of claim 25, wherein, when reading the logical low page of memory cells of the selected word line by applying a first read voltage to the selected word line for reading a first program state and applying a fifth read voltage to the selected word line for reading a fifth program state, the peripheral circuitry is further configured to: sequentially applying the first read voltage to the selected word line, the first pulse voltage to the selected word line; applying the fifth read voltage to the selected word line;

27. The memory system of claim 24, further comprising a first memory interface and a second memory interface, wherein the memory controller communicates with the three-dimensional controller through the first memory interface; the memory controller communicates with a host coupled to the memory system through the second storage interface.

28. The memory system according to any one of claims 24 to 27, wherein the memory system is a Solid State Disk (SSD) or a memory card.