CN114666247B - Design performance evaluation method and system of MPSoCNoC communication architecture - Google Patents
Design performance evaluation method and system of MPSoCNoC communication architecture Download PDFInfo
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Abstract
The invention discloses a design performance evaluation method and system of a MPSoC NoC communication architecture, and relates to the technical field of communication architecture performance evaluation. Acquiring error correction performance parameters and encoding and decoding delay parameters of a target data packet according to the type of the FEC code selected by a user; acquiring a verification delay parameter of a target data packet; calculating the path delay parameter of the target data packet according to the channel bit width and the route calculation delay in the NoC; deducing error-free transmission probability and retransmission times expectation of a target data packet; and calculating the expected value of the effective information bit transmission delay of the target data packet according to the parameters. The delay and channel errors in the processes of coding, channel transmission, decoding, checking and the like in communication are analyzed, and the number of times of transmission and single-time transmission delay required by the correct transmission of the data packet are deduced by combining the error correction characteristic under the limited number of error bits of FEC, so that the delay expected value of the effective information bit transmission is obtained and is used as the advantages and disadvantages of an evaluation index evaluation scheme.
Description
Technical Field
The invention relates to the technical field of communication architecture performance evaluation, in particular to a design performance evaluation method and system of a MPSoC NoC communication architecture.
Background
With the progress of digital integrated circuit process nodes, MPSoC (Multiprocessor System On a Chip, multi-core system on a chip) has become the mainstream design architecture of digital integrated circuits. With the increasing number of cores, conventional bus architectures have failed to meet the ever-increasing communications demands. NoC (Network on a Chip, network on chip) communication architecture with advantages of high bandwidth, easy expansion, etc. has become a main solution for MPSoC communication. The increase in integration leads to an increase in on-chip interconnect line density, resulting in an increase in physical layer crosstalk. The reliability problems of high communication link blocking, multiple bit errors and the like are gradually becoming main factors restricting the development of MPSoC, and the crosstalk processing scheme is added into the nodes due to the node transmission characteristics of the NoC communication architecture, so that the problem of communication crosstalk in a chip can be effectively solved.
In the field of internet communication, an ARQ (Automatic Repeat-reQuest) scheme and an FEC (Forward Error Correction, forward error correction code) scheme are generally adopted, and the ARQ scheme has high system reliability and low throughput rate; FEC can guarantee a certain throughput rate, but on one hand, adding redundancy coding reduces the effective information bit rate, and on the other hand, only can guarantee the consistency of transmission data under a limited error rate; while HARQ combines the advantages and disadvantages of FEC and ARQ.
In the prior art, the application of ARQ and FEC for resisting crosstalk errors in the NoC high-reliability communication field of MPSoC is rough, unified and clear evaluation indexes are not available, and the scheme is difficult to determine.
Disclosure of Invention
The present invention aims to solve the above-mentioned problems of the background art, and provides a design performance evaluation method and system for a MPSoC NoC communication architecture.
The aim of the invention can be achieved by the following technical scheme:
in a first aspect of the embodiment of the present invention, there is provided a design performance evaluation method of an MPSoC NoC communication architecture, the method comprising:
acquiring error correction performance parameters and encoding and decoding delay parameters of a target data packet according to the type of the FEC code selected by a user;
when the target data packet performs data consistency verification, obtaining a verification delay parameter of the target data packet;
calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of the target data packet;
deducing error-free transmission probability and retransmission times expectation of the target data packet based on a Gaussian white noise model of a channel and the error correction performance parameter; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process;
and calculating an expected value of effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times.
Optionally, calculating a path delay according to the channel bit width and the route calculation delay in the NoC, wherein the path delay parameter used as the path delay parameter of the target data packet comprises:
acquiring channel bit width and route calculation delay in the NoC;
length n sum Path delay t of the target data packet of bits reaching the receiving node through (h-1) intermediate nodes h The method comprises the following steps:
where nw is the channel bit width, notT is the routing computation delay, and T is the circuit clock period.
Optionally, the error correction performance parameter includes a valid information bit length, a subcode length, and a maximum error correction bit number in the target data packet;
based on a Gaussian white noise model of a channel and the error correction performance parameters, deducing the error-free transmission probability and retransmission times expectation of the target data packet, wherein the method comprises the following steps of:
obtaining a single bit error rate of channel transmission based on a Gaussian white noise model of the channel;
calculating the probability that the subcode of the target data packet cannot be successfully corrected according to the single-bit error rate, the subcode length and the maximum error correction bit number, and taking the probability as a first probability;
calculating error-free transmission probability of the target data packet according to the single bit error rate and the effective information bit length;
calculating the probability of decoding errors after the target data packet is interfered by a Gaussian white noise channel according to the first probability, and taking the probability as a second probability;
and calculating the expected retransmission times of the target data packet according to the second probability and the effective information bit length.
Optionally, the error correction performance parameter includes a valid information bit length in the target data packet;
calculating an expected value of an effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times, wherein the method comprises the following steps:
calculating the initial transmission delay, retransmission delay and error-free transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the verification delay parameter and the path delay parameter; the error-free transmission delay is the transmission delay of the target data packet under the condition that the target data packet is completely free from errors in the transmission process;
calculating an expected value t of the transmission delay of the effective information bit of the target data packet by combining the error-free transmission probability and the retransmission times expected bit-exp The method comprises the following steps:
wherein K is sum T is the effective information bit length in the target data packet fst For the initial transmission delay, t rep For the retransmission delay, n rep T is expected for the number of retransmissions pft For the error-free transmission delay, P pft And the probability is the error-free transmission probability.
The second aspect of the embodiment of the invention also provides a design performance evaluation system of the MPSoC NoC communication architecture, which comprises a forward error correction code FEC coding and decoding model, a data packet verification model, a transmission path model, a data packet equivalent error rate model and an expected value model;
wherein, the liquid crystal display device comprises a liquid crystal display device,
the FEC coding and decoding model is used for acquiring error correction performance parameters and coding and decoding delay parameters of the target data packet according to the FEC code type selected by the user;
the data packet verification model is used for acquiring verification delay parameters of the target data packet when the data consistency verification is carried out on the target data packet after the FEC error correction;
the transmission path model is used for calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of the target data packet;
the data packet equivalent error rate model is used for deducing the error-free transmission probability and retransmission times expectation of the target data packet based on the Gaussian white noise model of the channel and the error correction performance parameter; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process;
and the expected value model is used for calculating an expected value of the effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the transmission error probability and the retransmission times.
Based on the design performance evaluation method of the MPSoC NoC communication architecture provided by the embodiment of the invention, the error correction performance parameter and the encoding and decoding delay parameter of the target data packet are obtained according to the FEC code type selected by the user; when the target data packet performs data consistency verification, obtaining verification delay parameters of the target data packet; calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of a target data packet; deducing error-free transmission probability and retransmission times expectation of a target data packet based on a Gaussian white noise model of a channel and error correction performance parameters; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process; and calculating an expected value of the transmission delay of the effective information bit of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times. The delay and channel errors in the processes of coding, channel transmission, decoding, checking and the like in communication are analyzed, and the number of times of transmission and single-time transmission delay required by the correct transmission of the data packet are deduced by combining the error correction characteristic under the limited number of error bits of FEC, so that the delay expected value of the effective information bit transmission is obtained and is used as the advantages and disadvantages of an evaluation index evaluation scheme.
Drawings
The invention is further described below with reference to the accompanying drawings.
Fig. 1 is a flowchart of a design performance evaluation method of an MPSoC NoC communication architecture according to an embodiment of the present invention;
FIG. 2 is a flowchart of another design performance evaluation method for an MPSoC NoC communication architecture according to an embodiment of the present invention;
fig. 3 is a block diagram of a mathematical model of an HARQ transmission system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a design performance evaluation method of an MPSoC NoC communication architecture. Referring to fig. 1, fig. 1 is a flowchart of a design performance evaluation method of an MPSoC NoC communication architecture according to an embodiment of the present invention. The method may comprise the steps of:
s101, acquiring error correction performance parameters and encoding and decoding delay parameters of a target data packet according to the FEC code type selected by a user.
S102, when data consistency verification is carried out on a target data packet, obtaining verification delay parameters of the target data packet;
s103, calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of the target data packet.
S104, deducing the error-free transmission probability and retransmission times expectation of the target data packet based on the Gaussian white noise model of the channel and the error correction performance parameter.
S105, calculating the expected value of the transmission delay of the effective information bit of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the verification delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times.
The error-free transmission probability is the probability that the target data packet is not in error in the transmission process.
According to the design performance evaluation method of the MPSoC NoC communication architecture provided by the embodiment of the invention, through analyzing delay and channel errors in the processes of coding, channel transmission, decoding, verification and the like in communication and combining the error correction characteristic under the FEC limited error bit number, the number of times of transmission required by correctly transmitting a data packet and single-time transmission delay are deduced, and further, the delay expected value of effective information bit transmission is obtained and is used as the advantages and disadvantages of an evaluation index evaluation scheme.
In one implementation, for a particular FEC scheme, its error correction performance parameters and codec delay parameters may be extracted. The error correction performance parameters include: effective information bit length K bits, redundant bit length (N-K) bits, subcode length N bits, maximum error correction bit number c bits; the codec delay parameters include: for continuous n c Delay t of coding by a subcode en And delay t of decoding de 。t en And t de May be obtained from a circuit clock cycle based on the hardware design of the particular encoder and decoder. The total delay t of encoding and decoding cor The method comprises the following steps:
t cor ＝t en +t de (1)
for a composition containing n c The head and tail flits of the target data packet of the sub-code are used for route calculation and data integrity check, FEC coding is used, error correction can not be carried out on the target data packet only at a receiving node, and because the length of the target data packet is very short relative to the data to be transmitted by the target data packet, the accuracy of the target data packet can be ensured by adopting methods such as repeated transmission, majority voting and the like, and the length of the target data packet is n h&t bits, the total length of the data packet n sum The method comprises the following steps:
n sum ＝(n c N+n h&t )bits (2)
in one implementation, the verification delay parameter may be obtained from a circuit clock cycle based on a hardware design of the verification value generator.
In one embodiment, step S103 includes:
step one, obtaining channel bit width and route calculation delay in the NoC.
Step two, the length is n sumbits The path delay t of the target data packet of (h-1) passing through the intermediate nodes to reach the receiving node h The method comprises the following steps:
wherein n is w Is the channel bit width, n ot T is the route calculation delay and T is the circuit clock period.
In one implementation, the retransmission request information is shorter after the packet is in error, so the retransmission request is delayed by t ack The method comprises the following steps:
t ack ＝h(1+n ot )T (4)
in one embodiment, the error correction performance parameters include a valid information bit length, a subcode length, and a maximum number of error correction bits in the target data packet;
referring to fig. 2, step S104 includes, on the basis of fig. 1:
s1041, obtaining single bit error rate of channel transmission based on Gaussian white noise model of the channel;
s1042, calculating the probability that the subcode of the target data packet cannot be successfully corrected according to the single bit error rate, the subcode length and the maximum error correction bit number as the first probability.
S1043, calculating error-free transmission probability of the target data packet according to the single bit error rate and the effective information bit length.
S1044, calculating the probability of decoding errors after the target data packet is interfered by the Gaussian white noise channel according to the first probability, and taking the probability as a second probability.
S1045, calculating the expected number of retransmission times of the target data packet according to the second probability and the effective information bit length.
In one implementation, assuming that the channel crosstalk noise in the transmission is additive white gaussian noise, the single bit error rate epsilon in the channel transmission is:
wherein Q (x) is a standard normal distributed Q function, i.e., the probability that the argument is greater than x; v (V) dd Is the supply voltage in the circuit; sigma is the standard deviation of noise.
After one subcode is transmitted in a channel with the single bit error rate epsilon, the probability of failing to correct errors through FEC decoding is as follows:
in one implementation manner, when a systematic code scheme is adopted for FEC, there is a case that the primary consistency check detects that the valid information bits are completely error-free, and the probability is as follows:
in one implementation, one contains n c The error probability after decoding of the target data packet of each subcode after being interfered by a Gaussian white noise channel is as follows:
further deducing the expected value of the number of times of sending required by the receiving node to obtain an error-correcting data packet as follows
In addition to the initial transmission, the number of retransmissions required is expectedValue n rep The method comprises the following steps:
n rep ＝n ARQ -1 (10)
in one embodiment, the error correction performance parameter includes a valid information bit length in the target data packet;
step S105 includes:
step one, according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter and the path delay parameter, calculating the initial transmission delay, the retransmission delay and the error-free transmission delay of the target data packet.
Calculating the expected value t of the transmission delay of the effective information bit of the target data packet by combining the error-free transmission probability and the expected number of times of retransmission bit-exp The method comprises the following steps:
wherein K is sum For the effective information bit length, t, in the target data packet fst For initial transmission delay, t rep Retransmission delay, n rep T is expected for the number of retransmissions pft For error-free transmission delay, P pft Is the probability of error-free transmission.
The error-free transmission delay is the transmission delay of the target data packet in the case of no error in the transmission process.
In one implementation, K is the number of bits of information for a single valid bit sum After the processes of FEC coding, check value generation, channel transmission, decoding, consistency check and the like are carried out on the target data packet of bits, the primary transmission of the data packet is completed, and the delay is t fst The method comprises the steps of carrying out a first treatment on the surface of the If the data packet still fails to pass the consistency check after the FEC error correction, the data packet is requested to be retransmitted by the uplink channel and retransmitted by the transmitting node, and the data packet is subjected to the FEC error correction and the check, and the retransmission delay is t each time rep The method comprises the steps of carrying out a first treatment on the surface of the Calculating the expected value of n of the retransmission times (excluding the primary transmission) required by the receiving node to receive the data packet capable of correcting errors according to the error rate of the data packet rep The method comprises the steps of carrying out a first treatment on the surface of the The average delay in the transmission of valid information bits in the packet transmission is then:
when FEC adopts a systematic code scheme, the effective information bits are independent of the redundant bits, so that a receiving node can perform primary consistency check at the same time of FEC error correction, if the condition that the effective information bits are completely correct is found, the effective information bits pass the check directly, and the delay is t at the moment pft The occurrence probability is P pft The time function of the expected value of the effective information bit transmission delay can be corrected as equation (11).
For the non-systematic code, the effective information bits and the redundant bits are entangled, so that the primary verification cannot be performed before the FEC decoding is completed, and P is taken pft Is 0.
In an implementation manner, referring to fig. 3, fig. 3 is a block diagram of a mathematical model of an HARQ transmission system according to an embodiment of the present invention. The initial transmission delay includes FEC encoding, decoding delay, transmission path delay and verification delay, thus
t fst ＝t cor +t h-chk +t h (13)
When the data packet of the primary transmission does not pass the verification, the receiving node will request retransmission through the uplink channel, and then the transmitting node transmits the data packet in the buffer, thus retransmitting the delay t rep Including retransmission request delay, path delay, FEC decoding delay and verification delay, i.e
t rep ＝t fst -t en +(1+n ot )hT (14)
In the case of adopting the systematic code scheme for FEC, there is a case where the primary consistency check detects that the valid information bits are completely error-free, in which case the transmission delay t pft Including FEC coding delay, path delay and initial consistency check delay, i.e
t pft ＝t en +t h +t h-chk (15)
Based on the same inventive concept, the embodiment of the invention also provides a design performance evaluation system of the MPSoC NoC communication architecture, which comprises a forward error correction code (FEC) coding and decoding model, a data packet verification model, a transmission path model, a data packet equivalent error rate model and an expected value model;
wherein, the liquid crystal display device comprises a liquid crystal display device,
the FEC coding and decoding model is used for acquiring error correction performance parameters and coding and decoding delay parameters of the target data packet according to the FEC code type selected by the user;
the data packet verification model is used for acquiring verification delay parameters of the target data packet when the data consistency verification is carried out on the target data packet after the FEC error correction;
a transmission path model for calculating a path delay according to the channel bit width and the route calculation delay in the NoC, as a path delay parameter of the target packet;
the data packet equivalent error rate model is used for deducing the error-free transmission probability and retransmission times expectation of the target data packet based on the Gaussian white noise model and the error correction performance parameter of the channel; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process;
and the expected value model is used for calculating the expected value of the effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the verification delay parameter, the path delay parameter, the transmission error probability and the retransmission times.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (4)
1. A design performance evaluation method of an MPSoC NoC communication architecture, the method comprising:
acquiring error correction performance parameters and encoding and decoding delay parameters of a target data packet according to the type of the FEC code selected by a user;
when the target data packet performs data consistency verification, obtaining a verification delay parameter of the target data packet;
calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of the target data packet;
deducing error-free transmission probability and retransmission times expectation of the target data packet based on a Gaussian white noise model of a channel and the error correction performance parameter; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process;
calculating an expected value of effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times;
the error correction performance parameters comprise effective information bit length, subcode length and maximum error correction bit number in the target data packet;
based on a Gaussian white noise model of a channel and the error correction performance parameters, deducing the error-free transmission probability and retransmission times expectation of the target data packet, wherein the method comprises the following steps of:
obtaining a single bit error rate of channel transmission based on a Gaussian white noise model of the channel;
calculating the probability that the subcode of the target data packet cannot be successfully corrected according to the single-bit error rate, the subcode length and the maximum error correction bit number, and taking the probability as a first probability;
calculating error-free transmission probability of the target data packet according to the single bit error rate and the effective information bit length;
calculating the probability of decoding errors after the target data packet is interfered by a Gaussian white noise channel according to the first probability, and taking the probability as a second probability;
and calculating the expected retransmission times of the target data packet according to the second probability and the effective information bit length.
2. The method for evaluating design performance of an MPSoC NoC communication architecture according to claim 1, wherein calculating a path delay according to a channel bit width and a routing calculation delay in the NoC, as the path delay parameter of the target packet, comprises:
acquiring channel bit width and route calculation delay in the NoC;
length n sum Path delay t of the target data packet of bits reaching the receiving node through (h-1) intermediate nodes h The method comprises the following steps:
wherein n is w For the channel bit width, n ot T is the route calculation delay, and T is the circuit clock period.
3. The method for evaluating design performance of an MPSoC NoC communication architecture according to claim 1, wherein the error correction performance parameter comprises a valid information bit length in the target data packet;
calculating an expected value of an effective information bit transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the checking delay parameter, the path delay parameter, the error-free transmission probability and the retransmission times, wherein the method comprises the following steps:
calculating the initial transmission delay, retransmission delay and error-free transmission delay of the target data packet according to the error correction performance parameter, the encoding and decoding delay parameter, the verification delay parameter and the path delay parameter; the error-free transmission delay is the transmission delay of the target data packet under the condition that the target data packet is completely free from errors in the transmission process;
calculating an expected value t of the transmission delay of the effective information bit of the target data packet by combining the error-free transmission probability and the retransmission times expected bit-exp The method comprises the following steps:
wherein K is sum T is the effective information bit length in the target data packet fst For the initial transmission delay, t rep For the retransmission delay, n rep T is expected for the number of retransmissions pft For the error-free transmission delay, P pft And the probability is the error-free transmission probability.
4. The design performance evaluation system of the MPSoC NoC communication architecture is characterized by comprising a forward error correction code (FEC) coding and decoding model, a data packet verification model, a transmission path model, a data packet equivalent error rate model and an expected value model;
wherein, the liquid crystal display device comprises a liquid crystal display device,
the FEC coding and decoding model is used for acquiring error correction performance parameters and coding and decoding delay parameters of the target data packet according to the FEC code type selected by the user;
the data packet verification model is used for acquiring verification delay parameters of the target data packet when the data consistency verification is carried out on the target data packet after the FEC error correction;
the transmission path model is used for calculating path delay according to the channel bit width and the route calculation delay in the NoC, and taking the path delay as a path delay parameter of the target data packet;
the data packet equivalent error rate model is used for deducing the error-free transmission probability and retransmission times expectation of the target data packet based on the Gaussian white noise model of the channel and the error correction performance parameter; the error-free transmission probability is the probability that the target data packet is not in error in the transmission process;
an expected value model, configured to calculate an expected value of an effective information bit transmission delay of the target data packet according to the error correction performance parameter, the codec delay parameter, the verification delay parameter, the path delay parameter, the error-free transmission probability, and the retransmission frequency expected;
the error correction performance parameters comprise effective information bit length, subcode length and maximum error correction bit number in the target data packet;
based on a Gaussian white noise model of a channel and the error correction performance parameters, deducing the error-free transmission probability and retransmission times expectation of the target data packet, wherein the method comprises the following steps of:
obtaining a single bit error rate of channel transmission based on a Gaussian white noise model of the channel;
calculating the probability that the subcode of the target data packet cannot be successfully corrected according to the single-bit error rate, the subcode length and the maximum error correction bit number, and taking the probability as a first probability;
calculating error-free transmission probability of the target data packet according to the single bit error rate and the effective information bit length;
calculating the probability of decoding errors after the target data packet is interfered by a Gaussian white noise channel according to the first probability, and taking the probability as a second probability;
and calculating the expected retransmission times of the target data packet according to the second probability and the effective information bit length.
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