CN113517949A

CN113517949A - Code word synchronization method, receiver, network equipment and network system

Info

Publication number: CN113517949A
Application number: CN202010424884.9A
Authority: CN
Inventors: 任浩; 何向; 王心远
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-04-10
Filing date: 2020-05-19
Publication date: 2021-10-19

Abstract

A codeword synchronization method, a receiver and a network device are provided. The method comprises the steps of determining alternative bits in a plurality of bits of a data sequence received by a receiving end, and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the initial position of a code word in the data sequence. The method is a self-synchronizing method, the technical effect of high-precision code word synchronization of the data stream of the receiving end can be realized without inserting extra data into the data stream of the transmitting end, and the synchronization performance of the method achieves higher reliability.

Description

Code word synchronization method, receiver, network equipment and network system

Technical Field

The present application relates to the field of communications, and in particular, to a codeword synchronization method, a receiver, a network device, and a network system.

Background

As the level of production technology has increased, channel loss and noise have become key factors limiting data transmission rate and distance. The occurrence of Forward Error Correction (Forward Error Correction) provides Error Correction protection for data in transmission, thereby improving the data transmission rate and transmission distance of a channel. FEC can be divided into block codes (block codes) and convolutional codes (convolutional codes) according to the processing method of information sequences. For block codes, the method can be subdivided into linear block codes (linear block codes) and non-linear block codes (non-linear block codes). Linear block codes are widely used in the physical layer (physical layer) and the media access control (media access control) sublayer of the Open System Interconnection Model (OSI) of ethernet because of their simple implementation of coding and decoding.

The implementation of error detection and correction functions for linear block codes must be done on the basis of complete codewords (codewords), and thus the codeword boundaries, i.e. the beginning and end of a complete codeword, need to be determined in the data stream, a process called codeword synchronization or frame synchronization.

Currently, there are synchronization schemes suitable for linear block codes in the industry. Taking an Alignment Marker (AM) synchronization scheme used in 200/400GE in the 802.3 standard as an example, in the scheme, a fixed AM sequence needs to be inserted into each codeword at a certain interval, and a receiving end recognizes the AM sequence to perform codeword synchronization. However, the presence of the AM sequence is equivalent to inserting extra data in the data stream at the transmitting end, adding redundant information.

Disclosure of Invention

The application provides a self-synchronizing code word synchronization method, a receiver and network equipment, which are used for solving the technical problem of adding extra data in an AM synchronization scheme.

In a first aspect, the present application provides a codeword synchronization method. The method comprises the following steps: receiving a data sequence, wherein the data sequence comprises a plurality of bits; determining alternative bits in the data sequence, wherein the alternative bits are included in the plurality of bits; and step three, determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the initial position of a code word in the data sequence.

The method is performed by a receiving device in a network. By the method, the technical effect of high-precision code word synchronization of the data stream of the receiving end can be realized without inserting extra data into the data stream of the transmitting end, and the synchronization performance of the method achieves higher reliability.

In a possible implementation manner, the third step includes: and verifying the alternative bit, and when the verification is successful, determining the position of the alternative bit as the synchronous position.

In a possible implementation manner, at least one second test data block is partitioned in the data sequence according to the alternative bit, and the position of the alternative bit is a starting position of the at least one second test data block; and verifying the characteristic value of the at least one second test data block, and when the verification is successful, determining the position of the alternative bit as the synchronous position.

In one possible implementation, verifying the characteristic value of the at least one second test data block includes: and sequentially accumulating the characteristic values of the second test data blocks in the at least one second test data block to obtain an accumulated value, and when the accumulated value meets the synchronization condition, successfully verifying.

In a possible implementation manner, the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of the test data blocks with the re-check bits being the same as the original check bits, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold; the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

In one possible implementation, verifying the characteristic value of the at least one second test data block includes: and adding the characteristic values of all the second test data blocks in the at least one second test data block to obtain a total value, and when the total value meets the synchronization condition, successfully verifying.

In a possible implementation manner, the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of nonzero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold value; or, the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of the uncorrectable test data blocks, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of the test data blocks with the re-check bits being the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of the test data blocks with the re-check bits different from the original check bits, and the synchronization condition is that the total value is less than or equal to a synchronization threshold; the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

In one possible implementation, the position of the candidate bit is taken as the synchronization position.

In one possible implementation, a plurality of observation bits are selected from the data sequence; selecting the candidate bit from the plurality of observation bits.

In one possible implementation, the selecting the alternative bit from the plurality of observation bits includes: determining a plurality of groups of first test data blocks from the data sequence according to the plurality of observation bits, wherein each group of first test data blocks in the plurality of groups of first test data blocks comprises at least one first test data block, and the position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks; and selecting one observation bit from the observation bits as the alternative bit according to the characteristic values of the plurality of groups of first test data blocks.

In a possible implementation manner, the selecting, according to the characteristic values of the plurality of groups of first test data blocks, one observation bit from the plurality of observation bits as the candidate bit includes: sequentially judging whether the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative conditions or not until the characteristic values of one group of first test data blocks meet the alternative conditions; and taking the observation bit corresponding to the group of first test data blocks meeting the alternative condition as the alternative bit.

In a possible implementation manner, the characteristic value of the group of first test data blocks is a total value of the number of all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or the characteristic value of the group of first test data blocks is a total value of the number of non-all-zero sequences in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or the characteristic value of the group of first test data blocks is a total value of the number of zero elements in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or the characteristic value of the group of first test data blocks is a total value of the number of non-zero elements in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a total value of the number of error-correctable test data blocks in all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a total value of the number of the uncorrectable test data blocks in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a total value of the number of test data blocks with the same re-check bits as the original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a total value of the number of test data blocks with different re-check bits from the original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or the characteristic value of the group of first test data blocks is a quantity accumulated value of all-zero sequences in check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; or the characteristic value of the group of first test data blocks is a quantity accumulated value of zero elements in the check sequence of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a cumulative number of error-correctable test data blocks in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the cumulative number is greater than or equal to a synchronization threshold; or, the characteristic value of the group of first test data blocks is a number accumulated value of test data blocks with the same re-check bits as the original check bits in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n, k and X are integers.

In a possible implementation manner, the selecting, according to the characteristic values of the plurality of groups of first test data blocks, one observation bit from the plurality of observation bits as the candidate bit includes: and comparing the characteristic value of each group of first test data blocks in the multiple groups of first test data blocks, and taking the observation bit corresponding to the group of first test data blocks of which the characteristic value is an extreme value as the alternative bit.

In a possible implementation manner, the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is a maximum value; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or, the characteristic value is the number of zero elements in the check sequence, and the extreme value is a maximum value; or, the characteristic value is the number of nonzero elements in the check sequence, and the extreme value is the minimum value; or, the characteristic value is the number of error-correctable test data blocks, and the extreme value is a maximum value; or, the characteristic value is the number of the uncorrectable test data blocks, and the extreme value is the minimum value; or, the characteristic value is the number of the test data blocks with the re-check bits being the same as the original check bits, and the extreme value is the maximum value; or, the characteristic value is the number of the test data blocks with different re-check bits and original check bits, and the extreme value is the minimum value; the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

In one possible implementation, the selecting a plurality of observation bits from the data sequence includes: selecting one bit from the data sequence every T bits as the observation bit, wherein T is an integer larger than zero; or selecting one bit from the data sequence at intervals of L × n + T bits as the observation bit, where L is the number of test data blocks at intervals, the length of the test data block is the n bits, and L and T are integers greater than zero.

In one possible implementation, the data sequence is a modulated signal, the data sequence includes a plurality of modulation symbols, and the selecting a plurality of observation bits from the first data includes: selecting the initial bit of the modulation code element from the data sequence at intervals of T modulation code elements as the observation bit, wherein T is an integer larger than zero; or selecting the starting bit of the modulation code element from the data sequence at intervals of L × m + T modulation code elements as the observation bit, where L is the number of test data blocks at intervals, the length of the test data block is the m modulation code elements, and L and T are integers greater than zero.

In a possible implementation manner, the number of observation bits is P, where P is a positive integer, and the length of the codeword is P bits.

In a possible implementation manner, in the second step, the determining the candidate bits in the data sequence includes determining the candidate bits in a first subsequence, and in the third step, the dividing into at least one second test data block in the data sequence according to the candidate bits includes dividing into at least one second test data block in a second subsequence according to the candidate bits, where the first subsequence and the second subsequence are included in the data sequence, and the second subsequence is the same as, partially the same as, or different from the first subsequence.

In a possible implementation manner, after the third step, the method further includes: and step four, responding to the fact that the data sequence is in an unlocked state, and determining the updated synchronous position of the data sequence.

In a possible implementation manner, the determining the update synchronization position of the data sequence includes: and re-executing the second step and the third step, and taking the synchronization position determined by the re-executed third step as the updated synchronization position.

In a possible implementation manner, after the third step and before the fourth step, the method further includes: dividing a plurality of synchronous code words from the data sequence according to the synchronous position, wherein the synchronous position is the starting position of the plurality of synchronous code words; and verifying the characteristic values of the plurality of synchronous code words, and determining the data sequence to be in the out-of-lock state when the verification fails.

In one possible implementation, verifying the characteristic values of the plurality of synchronization code words includes: and sequentially accumulating the characteristic values of all the synchronous code words in the plurality of synchronous code words to obtain an accumulated value, and failing to verify until the accumulated value meets the unlocking condition.

In a possible implementation manner, the characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of the uncorrectable codewords, and the lock-out condition is that the accumulated value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of code words with different re-check bits and original check bits, and the lock losing condition is that the accumulated value is greater than or equal to a synchronization threshold; the length of the code word is n bits, the first k bits of the code word are information bits, the last n-k bits of the code word are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

In one possible implementation, verifying the characteristic values of the plurality of synchronization code words includes: and adding the characteristic values of all the synchronous code words in the plurality of synchronous code words to obtain a total value, and when the total value meets the out-of-lock condition, the verification fails.

In a possible implementation manner, the characteristic value is the number of all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of zero elements in the check sequence, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of error-correctable codewords, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold; or, the characteristic value is the number of the uncorrectable code words, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold; or, the characteristic value is the number of code words with the same re-check bits as the original check bits, and the out-of-lock condition is that the total value is less than or equal to the synchronization threshold; or, the characteristic value is the number of code words with different re-check bits and original check bits, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold; the length of the code word is n bits, the first k bits of the code word are information bits, the last n-k bits of the code word are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

In one possible implementation, the data sequence is a linear block code.

In a second aspect, the present application provides a communication device that performs the method of the first aspect or any one of the possible implementation manners of the first aspect. In particular, the network device comprises means for performing the first aspect or the method in any one of its possible implementations.

In a third aspect, the present application provides a communication device comprising: a processor, a communication interface, and a memory. The communication interface may be a transceiver. The memory may be configured to store program code, and the processor is configured to call the program code in the memory to perform the method in the foregoing first aspect or any one of the possible implementations of the first aspect, which is not described herein again.

In a fourth aspect, the present application provides a network system, which includes a sending device and a receiving device, where the receiving device is the communication device provided in the foregoing second or third aspect, and the receiving device is configured to receive a data sequence sent by the sending device.

In a fifth aspect, the present application provides a computer-readable storage medium having stored therein instructions, which, when executed on a computer, cause the computer to perform the method of the above aspects.

In a sixth aspect, the present application provides a computer program product comprising computer program instructions that, when run on a network device, cause the network device to perform the method provided in the first aspect or any one of the possible implementations of the first aspect.

In a seventh aspect, the present application provides a chip, which includes a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so as to execute the method in the first aspect and any possible implementation manner of the first aspect.

Optionally, the chip only includes a processor, and the processor is configured to read and execute the computer program stored in the memory, and when the computer program is executed, the processor executes the method in the first aspect or any possible implementation manner of the first aspect.

In an eighth aspect, the present application provides a network node, comprising: a main control board and an interface board. The main control board includes: a first processor and a first memory. The interface board includes: a second processor, a second memory, and an interface card. The main control board is coupled with the interface board.

The first memory may be configured to store program code, and the first processor is configured to call the program code in the first memory to perform the following: determining alternative bits in the data sequence, the alternative bits included in the plurality of bits; and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the starting position of a code word in the data sequence.

The second memory may be configured to store program code, and the second processor may be configured to invoke the program code in the second memory to trigger the interface card to perform the following: a data sequence is received, the data sequence comprising a plurality of bits.

In a possible implementation manner, an inter-process communication protocol (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate with each other through the IPC channel.

Drawings

In order to more clearly explain the technical solution of the present application, the drawings used in the embodiments will be briefly described below. It should be apparent that the following drawings are only drawings of some embodiments of the present application, and it is obvious for a person skilled in the art that other technical solutions and drawings capable of implementing the present application can be obtained according to the drawings without any creative effort.

Fig. 1 is a diagram illustrating a synchronization position of a codeword according to an embodiment of the present application;

fig. 2 is a synchronization flowchart provided in an embodiment of the present application;

fig. 3 is a synchronization flowchart provided in an embodiment of the present application;

fig. 4 is a method for selecting observation bits according to an embodiment of the present disclosure;

fig. 5 is a method for selecting observation bits according to an embodiment of the present disclosure;

fig. 6 is a method for selecting observation bits according to an embodiment of the present disclosure;

fig. 7 is a method for selecting observation bits according to an embodiment of the present disclosure;

fig. 8 is a first phase of a synchronization lock determination according to an embodiment of the present application;

FIG. 9 is a second stage of determining synchronization lock according to an embodiment of the present application;

FIG. 10 is a block diagram illustrating a synchronous unlock determination provided in accordance with an embodiment of the present application;

fig. 11 is a synchronization flowchart according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described below with reference to the accompanying drawings.

Due to channel loss and noise, errors may occur when signals are transmitted in a channel, affecting the reliability of the communication system. When a signal is represented in the form of a data sequence consisting of a plurality of bits, a transmission error is embodied in that the value of a part of the bits in the data sequence changes, i.e. an erroneous bit occurs. FEC is a technique for controlling transmission errors in a communication system, in which redundant information is transmitted together with an original data sequence for error recovery during transmission to reduce a bit error rate. FEC can be divided into block codes and convolutional codes according to different processing modes for information sequences. For block codes, it can be subdivided into linear block codes and non-linear block codes. Taking a systematic code (systematic code) in a linear block code as an example, a transmitting end groups an original data sequence, and the length of each group is k bits (bit). Further, in each packet, redundant information of n-k bits, also called parity, is added according to a specific coding rule, and finally a codeword of length n bits is obtained. Therefore, in the code word with the length of n bits, the first k bits are original data and are also called information bits, the last n-k bits are check bits, and the whole code word consists of the information bits and the check bits. After the code word reaches the receiving end through the channel, if the number of the error bits in the code word is within the error correctable range, the receiving end can check and correct the errors through the decoding process, and the received code word is recovered to the original data sent by the sending end, so that the interference caused by the channel is resisted, and the reliability of the communication system is improved. The implementation of the error detection and correction function of the linear block code must be performed based on the complete codeword, and therefore, before decoding the data sequence received by the receiving end, the codeword boundary needs to be determined in the data sequence, i.e. the starting position and the ending position of a complete codeword are found. This process is called codeword synchronization or frame synchronization. If the codeword synchronization is incorrect, i.e. the true codeword boundary cannot be determined, the due effect of error detection or correction cannot be achieved in the subsequent decoding process, and even bit errors may be increased, which may cause the performance degradation of the communication system.

The starting position of each codeword may also be referred to as a synchronization position (synchronization position). Also taking systematic codes as an example, fig. 1 shows the synchronization positions in the code words. As shown in fig. 1, the length of the whole codeword is n bits, where the first k bits are original data (information bits), the last n-k bits are extra parity bits (parity bits) added by a coding rule, and the synchronization position is the start position of the codeword, i.e., the position of the first bit in the codeword. Wherein n and k are integers. It can be seen that, in the data sequence, the number of the synchronization positions is multiple, and the multiple synchronization positions are associated with each other, wherein the interval between each synchronization position is fixed, and the interval is the length of the codeword.

In the embodiment of the present application, although the systematic code is used for illustration, the present application is not limited to the systematic code, and is also applicable to a non-systematic code (non-systematic code). The linear block code includes, but is not limited to, Reed-Solomon code (RS code), Bose-Chaudhuri-Hocquenghem code (BCH code), Low-Density Parity-Check code (LDPC code), Hamming code (Hamming code), Gray code (Golay code), and Reed-Muller code, etc.

The embodiment of the application provides a code word synchronization method, and equipment and a system based on the method. These methods, devices and systems are based on the same inventive concept. The method can comprise two stages, in the first stage, dividing a plurality of groups of first test data blocks according to a plurality of observation bits, selecting an observation bit most probably positioned at a synchronous position from a plurality of observation bits according to the plurality of groups of first test data blocks, in the second stage, dividing a group of second test data blocks according to the observation bit most probably positioned at the synchronous position, and judging whether the observation bit most probably positioned at the synchronous position is the synchronous position according to the group of second test data blocks. The method may also comprise only the first stage, and after determining to select the observation bit most likely to be located at the synchronization position, directly taking the observation bit most likely to be located at the synchronization position as the synchronization position. In the method, the technical effect of high-precision code word synchronization of the data stream of the receiving end can be realized without inserting extra data into the data stream of the transmitting end, and the synchronization performance of the method achieves higher reliability.

Fig. 2 shows a method flow diagram of an embodiment of the present application. The method is applied to receiving end equipment in a communication network. The receiving end device may be various devices that perform FEC including, but not limited to, routers, switches, and servers. The method comprises the following steps:

s210, receiving a data sequence.

Specifically, the receiving end receives a data sequence from the transmitting end, where the data sequence includes multiple bits, and each bit is binary data. That is, the data sequence is a sequence of a plurality of bits, and may also be referred to as a bit sequence. In some embodiments, the data sequence is a linear block code. The data sequence is transmitted through a channel, and error may exist, and operations such as error detection and error correction are required.

S220, in the first stage, alternative bits in the data sequence are determined, and the alternative bits are included in the multiple bits. The candidate bit is an observed bit most likely to be located at a synchronization position among the plurality of observed bits, or the position of the candidate bit is the most likely synchronization position.

As shown in fig. 3, in the first stage, two steps S221 and S222 may be included:

s221, the receiving end selects a plurality of observation bits from the received data sequence. The positions of the observation bits comprise the synchronization position, i.e. the position of one of the observation bits may be the synchronization position, or the positions of the observation bits can cover the synchronization position.

Optionally, in the first stage, when determining the candidate bits in the data sequence, the method only uses a part of the data sequence, for example, the first subsequence in the data sequence, that is, determines the candidate bits in the first subsequence. The first subsequence comprises a plurality of bits and the first subsequence may be any one of the portions of the data sequence. The receiving end selects the plurality of observation bits from the first subsequence, and the positions of the observation bits may be synchronization positions. For example, the number of observation bits is P, which is an integer greater than 1.

Optionally, when a plurality of observation bits are selected from the received data sequence, intervals between every two adjacent observation bits in the plurality of observation bits are the same, and a position of each observation bit in the plurality of observation bits sequentially moves backward.

In the codeword synchronization process, the concept of testing data blocks is introduced. The test data block is a part of a data sequence, the test data block is composed of a plurality of continuous bits, and the length of the test data block is the same as that of the code word. The test data block is said to be used for simulating a code word.

Optionally, the observation bits may be located in the same test data block, and the position of each observation bit in the observation bits in the same test data block is sequentially shifted backward. Specifically, one bit is selected as the observation bit every T bits, where T is an integer greater than zero. FIG. 4 shows the choice of observation bits, where b₁,b₂,b₃The three adjacent observation bits respectively correspond to three bits of x (0), x (1) and x (2) in the data sequence. The interval between each observation bit is 1 bit, i.e. T is 1. The three observation bits are located in the same test data block, for example, the test data block divided by the starting position x (0) in fig. 4. Within the test data block, b₁At a first position in the test data block, b₂,b₃In accordance with the positionThe second and third positions in the test data block, i.e., the position of each of the three observed bits within the same test data block, are shifted back in sequence. Although fig. 4 only shows three observation bits, the selection of more observation bits can be analogized from this, and the description thereof is omitted here.

Optionally, the plurality of observation bits may be respectively located in a plurality of test data blocks, and the position of each observation bit in the plurality of observation bits in each test data block is sequentially shifted backward. Specifically, one bit is selected as the observation bit every L × n + T bits, L is the number of interval test data blocks, the length of the test data block is the n bits, and L and T are integers greater than zero. FIG. 5 shows the choice of observation bits, where b₁,b₂Two adjacent observation bits respectively correspond to x (0) and x (L × n +1) two bits in the data sequence. The two observation bits are located in two different test data blocks, for example, the test data block marked off with x (0) as the starting position and the test data block marked off with x (L × n) as the starting position in fig. 5. The interval between two test data blocks is L test data blocks, and the interval between two observation bits is L × n +1 bits, i.e., T is 1. In the test data block divided by the starting position of x (0), b₁In the test data block divided by x (L x n) as the initial position, b₂The position is the second position in the test data block, i.e. the position of each of the two observation bits in each test data block is shifted backwards in sequence. Although fig. 5 only shows two observation bits, the selection of more observation bits can be analogized from this, and the description thereof is omitted here. At this time, the interval between adjacent observation bits is farther, and the correlation between the observation bits is lower, so that the influence caused by burst bit errors can be reduced, and the accuracy of codeword synchronization is improved.

Optionally, when selecting the observation bits, the positions of the observation bits may be traversed to all positions within the test data block.

For example, when the plurality of observation bits are located within the same test data block, the positions of the plurality of observation bits may be made to traverse all positions within the same test data block, i.e., the positions of the plurality of observation bits may be made to traverse all positions within the same codeword. In the selection manner of observation bits shown in fig. 4, the length of the codeword is n bits, the number of observation bits is P, and when P is equal to n, the positions of the observation bits can traverse all the positions in the same test data block.

For example, when the observation bits are located in the test data blocks respectively, the same position in each of the test data blocks is regarded as an equivalent position, for example, the first position in each of the test data blocks is regarded as an equivalent position, and the positions of the observation bits may be made to traverse all the equivalent positions, that is, the positions of the observation bits traverse all the positions in the test data blocks. In the selection manner of observation bits shown in fig. 5, if the length of the codeword is n bits, the number of equivalent positions is n, and the number of observation bits is P, and when P is equal to n, the positions of the observation bits can traverse all the equivalent positions, that is, the positions of the observation bits can traverse all the positions in the test data blocks.

Optionally, when the observation bits are selected, the positions of the observation bits may not traverse all the positions in the codeword. I.e. the value of P may be smaller than n.

If the positions of the observation bits traverse all positions within the test data block, a higher accuracy of the codeword synchronization result will be achieved. However, as the number of observation bits increases, the system resources consumed by the codeword synchronization process will also increase.

The signal may be modulated at the transmitting end to obtain a modulated signal. Common Modulation methods include Pulse-Amplitude Modulation (PAM), Quadrature Amplitude Modulation (QAM), Phase-Shift Keying (PSK), and the like. Regulating deviceThe pulse amplitude of the modulation signal may include a number of orders, and the number of the orders may be referred to as an order of modulation. Taking PAM as an example, when the pulse amplitude of the modulation signal has 2 orders, the modulation order is 2, and the modulation mode may be referred to as PAM 2; when the pulse amplitude of the modulation signal has 4 orders, the modulation order is 4, the modulation mode may be referred to as PAM4, and so on. The modulated signal may be represented as a modulated data sequence. Compared with an unmodulated data sequence, the basic unit of a modulated data sequence is changed from bits to symbols, i.e. in a modulated data sequence, a code word consists of several symbols, and a symbol consists of several bits. The number of bits included in a symbol is related to the order of the modulation. When the modulation order is M, the number of bits included in the symbol is log₂M, wherein M is an integer multiple of 2. For example, when the modulation order is 2, 1 bit is included in the symbol, and when the modulation order is 4, 2 bits are included in the symbol. It follows that the start position of a code word must also be the start position of a certain symbol, and not other positions of the symbol. Thus, for a modulated signal, only the starting bit of a symbol may be considered in selecting the plurality of observation bits, without considering other bits of the symbol.

Optionally, the observation bits are start bits of a plurality of symbols, the plurality of symbols are in the same test data block, and positions of the plurality of symbols in the same test data block sequentially move backward. Specifically, every T modulation symbols, the start bit of a modulation symbol is selected as the observation bit, and T is an integer greater than zero. That is, T.log per interval₂And M bits, and selecting the initial bit of the modulation code element as the observation bit. Fig. 6 shows the selection of observation bits, where the data sequence is a modulation signal, the modulation order is 4, and the data sequence includes a plurality of modulation symbols, each symbol includes 2 bits, for example, a symbol composed of x (0) and x (1), a symbol composed of x (2) and x (3), a symbol composed of x (4) and x (5), and so on. Wherein b is₁,b₂,b₃The three adjacent observation bits respectively correspond to three bits of x (0), x (2) and x (4) in the data sequence.The three observation bits are respectively the initial bits of three symbols, the three symbols are symbols consisting of x (0) and x (1), the symbols consisting of x (2) and x (3), and the symbols consisting of x (4) and x (5). Every two adjacent symbols in the three symbols are separated by 1 symbol, namely T is 1. And, the positions of the three symbols in the same test data block are sequentially shifted backward. Although fig. 6 only shows three observation bits, the selection of more observation bits can be analogized, and the description thereof is omitted here.

Optionally, the observation bits are start bits of symbols, the symbols are located in test data blocks, and the position of each symbol in the symbols in each test data block is sequentially shifted backward. Specifically, every interval of L × m + T modulation symbols, the starting bit of the modulation symbol is selected as the observation bit, L is the number of interval test data blocks, the length of the test data block is the m modulation symbols, and L and T are integers greater than zero. That is, log per interval (L.m + T)₂And M bits, and selecting the initial bit of the modulation code element as the observation bit. Fig. 7 shows the selection of observation bits, where the data sequence is a modulation signal, the modulation order is 4, and the data sequence includes a plurality of modulation symbols, each symbol includes 2 bits, for example, a symbol composed of x (0) and x (1), a symbol composed of x (L × n) and x (L × n +1), a symbol composed of x (L × n +2) and x (L × n +3), and so on. Wherein b1 and b2 are two adjacent observation bits, which respectively correspond to two bits of x (0) and x (L × n +2) in the data sequence. The two observation bits are respectively the initial bits of two code elements, the two code elements are code elements consisting of x (0) and x (1), and the code elements consisting of x (L x n +2) and x (L x n + 3). The two observation bits are located in two different test data blocks, for example, the test data block divided by the starting position x (0) and the test data block divided by the starting position x (L × n) in fig. 7. The interval between the two test data blocks is L test data blocks, and the interval between two observation bits is L × m +1 symbols, i.e., T is 1. In a test data block divided by x (0) as a start position，b₁The symbol is the first symbol in the test data block, and in the test data block divided by x (L x n) as the initial position, b₂The symbol is the second symbol in the test data block, i.e., the position of each of the two symbols in each test data block is shifted backward in sequence. Although fig. 7 shows only two observation bits, the selection of more observation bits can be analogized, and the description thereof is omitted here. At this time, the interval between adjacent observation bits is farther, and the correlation between the observation bits is lower, so that the influence caused by burst bit errors can be reduced, and the accuracy of codeword synchronization is improved.

S222, selecting alternative bits from the observation bits. The candidate bit is one of the observation bits, and the candidate bit is the observation bit most likely to be located at the synchronization position. Specifically, S222 may include two steps S2221 and S2222.

S2221, dividing a plurality of groups of first test data blocks from the data sequence according to the observation bits, where the plurality of groups of first test data blocks correspond to the observation bits one to one. Specifically, each group of first test data blocks in the multiple groups of first test data blocks includes at least one first test data block, and a position of each observation bit in the multiple observation bits is a start position of each group of first test data blocks in the multiple groups of first test data blocks.

Optionally, each observation bit in the observation bits is taken as a start position, and then N test data blocks are selected, where N is an integer greater than or equal to 1. The position of each observation bit in the plurality of observation bits is a starting position of each first test data block in the plurality of groups of first test data blocks. And taking the N test data blocks selected by taking each observation bit as the initial position as a group of first test data blocks, and taking each observation bit in the observation bits as the initial position respectively, wherein the selected groups of N test data blocks are the groups of first test data blocks. Each of the first test data blocks in the plurality of groups of first test data blocks corresponds to an observation bit serving as a start position of the group of first test data blocks, that is, the plurality of groups of first test data blocks correspond to the observation bits one to one.

Optionally, the N test data blocks may be consecutive, that is, each group of first test data blocks includes consecutive N data blocks. When the length of each test data block is N bits, the next continuous N x N bits are selected, and the N test data blocks are obtained.

Optionally, the N test data blocks may also be discontinuous, and a start position of each test data block in the N test data blocks is associated with an observation bit corresponding to the group of test data blocks. Specifically, the interval between the start position of each test data block and the observation bit corresponding to the group of test data blocks is an integer multiple of the length of the code word, that is, the interval between every two test data blocks in the N test data blocks is an integer multiple of the length of the code word. Moreover, the interval between every two test data blocks in the N test data blocks may be the same or different.

As shown in fig. 4, to observe bit b₁Selecting a group of first test data blocks as a starting position, wherein the group of first test data blocks comprises N test data blocks, namely B₁,B₂,…,B_NEach test data block is n bits long. Similarly, to observe bit b₂Or b₃The following set of first test data blocks can also be selected separately for the starting position. Respectively by observing bit b₁，b₂Or b₃And selecting the multiple groups of first test data blocks as the initial positions. In fig. 5, 6 and 7, the manner of the plurality of groups of first test data blocks is similar to that in fig. 4, and is not repeated here.

S2222, according to the characteristic values of the multiple groups of first test data blocks, selecting an observation bit from the observation bits as the candidate bit, that is, the observation bit most likely to be located at the synchronization position.

Optionally, when one observation bit is selected from the observation bits as the observation bit most likely to be located at the synchronization position according to the characteristic values of the plurality of groups of first test data blocks, the selection manner may be a selection manner that terminates early. Specifically, whether the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks satisfy the alternative condition is sequentially judged until it is determined that the characteristic values of one group of first test data blocks satisfy the alternative condition, and observation bits corresponding to the group of first test data blocks satisfying the alternative condition are used as the alternative bits.

Optionally, when one observation bit is selected from the observation bits as the observation bit most likely to be located at the synchronization position according to the characteristic values of the plurality of groups of first test data blocks, the selection manner may be a traversal selection manner. Specifically, comparing the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks, and taking the observation bits corresponding to the group of first test data blocks of which the characteristic values are extremum values as the alternative bits.

In both the early-terminated selection mode and the traversal selection mode, the characteristic values can be calculated in parallel, that is, a plurality of calculation units are used to calculate the characteristic values of a plurality of test data blocks simultaneously. For example, 10 calculation units are used to simultaneously calculate the characteristic values of 10 test data blocks. The parallel computing mode can save computing time and reduce time delay.

Alternatively, the characteristic value may be a characteristic value of a check sequence.

A check matrix (parity-check matrix) may be generated for each linear block code, which describes a linear relationship between data within codewords of the linear block code, and may be applied to a decoding process. When the data sequence is a linear block code, the check matrix also exists for the data sequence, and may be referred to as a check matrix of the data sequence. Specifically, the following relation is satisfied between the data sequence and the check matrix of the data sequence:

wherein, C is a code word in the data sequence, S is the check sequence of the code word, and H is the check matrix of the data sequence. As can be seen from the above relation (1), the check sequence of the codeword in the data sequence is obtained by multiplying the codeword by the transpose matrix of the check matrix of the data sequence, and the check sequence is a zero vector, that is, an all-zero matrix.

As described above, when the data sequence is a data sequence received by the receiving end, the start position of the codeword needs to be determined in the data sequence. If the code word is not divided from the data sequence with the correct starting position, the resulting code word will no longer satisfy the above relation (1). At this time, the check sequence of the codeword in the data sequence can be expressed by the following relation:

S_R＝R·H^T (2)

where R is a code word in the data sequence received by the receiving end, S_RH is a check matrix of the original data sequence sent by the sending end. In the above relation (2), the check sequence of the codeword in the data sequence received by the receiving end is a product of the codeword and a transpose matrix of the check matrix of the original data sequence transmitted by the transmitting end. From the above analysis, it can be seen that S is the error bit in the codeword_RNo longer an all-zero matrix. Therefore, the code word synchronization can be realized by using the check sequence of the test data block in the data sequence received by the receiving end. Specifically, an observation bit may be selected from the observation bits as the observation bit most likely to be located at the synchronization position by using a check sequence of the test data block in the data sequence received by the receiving end.

Optionally, the check sequence of each group of first test data blocks in the multiple groups of first test data blocks is calculated respectively.

As shown in fig. 4, to compute to observe bit b₁The check sequence of the first test data block of a group of start bits, i.e. S as shown in FIG. 4⁽¹⁾Including S₁ ⁽¹⁾,S₂ ⁽¹⁾,…,S_N ⁽¹⁾Respectively correspond to the test dataBlock B₁,B₂,…,B_N. By analogy, respectively calculate to observe bit b₂,b₃The check sequence of the first test data block of a group of start bits, i.e. S as shown in FIG. 4⁽²⁾,S⁽³⁾. Although fig. 4 only shows the calculation of the check sequence of the first test data block with the three observation bits as the start bits, more calculation of the check sequence may be performed by analogy, and thus, the description is omitted here. In fig. 5, 6 and 7, the calculation manner of the check sequences of the multiple groups of first test data blocks is similar to that in fig. 4, and is not repeated here.

For example, the characteristic value may be the number of all-zero sequences in the check sequence. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is greater than or equal to a synchronization threshold. Specifically, the relationship between the number of all-zero sequences in the check sequences of each group of first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of first test data blocks which meet the candidate condition are used as the candidate bits until it is determined that the number of all-zero sequences in the check sequences of the group of first test data blocks is greater than or equal to the synchronization threshold. The observation bits corresponding to a group of first test data blocks, i.e. the observation bits as the start bits of the group of first test data blocks.

The value of the synchronization threshold can be obtained through simulation analysis. For example, a segment of data sequence is used as a data sequence received by a receiving end, the error rate of the data sequence is designed to be within an acceptable range, the number of all-zero sequences in the check sequences of a group of test data blocks divided based on a synchronous position and the number of all-zero sequences in the check sequences of a group of test data blocks divided based on an asynchronous position are respectively counted, and a synchronous threshold value is determined according to the difference between the two numbers, so that the synchronous threshold value can be used for distinguishing the synchronous position from the asynchronous position.

When the characteristic value is the number of all-zero sequences in the check sequence, and the selection mode of early termination is adopted, the most probable position isThe process of selecting the observation bits of the synchronization position can be seen in fig. 4. Wherein the synchronization threshold may be 2. As shown in FIG. 4, the check sequence S is sequentially judged⁽¹⁾,S⁽²⁾,S⁽³⁾The number of all-zero sequences in the synchronization threshold, e.g. the number Q of all-zero sequences in the check sequence of the first set of first test data blocks₁0, less than the synchronization threshold, the number Q of all-zero sequences in the check sequences of the second set of first test data blocks₂B is selected to be 2 and equal to the synchronization threshold₂The observation bit most likely to be located at the synchronization position. And, when judging to b₂When b is determined₂If the alternative condition is satisfied, the relation between the number of all-zero sequences in the check sequence corresponding to the subsequent observation bit and the synchronization threshold is not judged, that is, the S is not judged⁽³⁾The number of mid-all-zero sequences versus the synchronization threshold.

Optionally, in the above-mentioned selection manner of early termination, for the characteristic value of each group of the first test data blocks, a statistical manner of early termination may also be adopted. That is, the characteristic value of the group of first test data blocks may be a total value of the number of all-zero sequences in the check sequences of all first test data blocks in the group of first test data blocks, and accordingly, the alternative condition may be that the total value is greater than or equal to the synchronization threshold. In the selection process shown in fig. 4, each group of check sequences S is sequentially determined⁽¹⁾,S⁽²⁾,S⁽³⁾When the number of the all-zero sequences in the group is in relation to the synchronization threshold, calculating the check sequence of each test data block in sequence for each group of first test data blocks, when the check sequence is the all-zero sequence, increasing the number of the all-zero sequences by 1, when the number accumulated value of the all-zero sequences meets the alternative condition, namely the number accumulated value of the all-zero sequences is greater than or equal to the synchronization threshold, considering that the group of first test data blocks meets the alternative condition, and not calculating the test data blocks of which the check sequences are not calculated in the group. For example, for the second set of first test data blocks, if S₁ ⁽²⁾,S₂ ⁽²⁾All zero sequences are considered as the second set of first measurementsNumber Q of all-zero sequences in the check sequence of the test data block₂B is selected if the number of the first test data blocks reaches the synchronization threshold and the set of the first test data blocks meets the alternative condition after the number of the first test data blocks reaches 2₂For the observation bits most likely to be in the sync position, the subsequent S is not calculated any more₃ ⁽²⁾To S_N ⁽²⁾The check sequence of (1). Optionally, in the above-mentioned selection manner of early termination, a statistical manner of traversal may also be adopted for the characteristic value of each group of the first test data blocks. That is, the characteristic value of the group of first test data blocks may be a cumulative value of the number of all-zero sequences in the check sequence of the first X first test data blocks in the group of first test data blocks, and accordingly, the alternative condition may be that the cumulative value is greater than or equal to the synchronization threshold. In the specific selection process, the check sequence of each first test data block in the group is calculated to determine whether the total value of the number of all-zero sequences in the group of check sequences meets the alternative condition, that is, whether the total value of the number of all-zero sequences in the group of check sequences is greater than or equal to the synchronization threshold, and the specific operation process is not described herein again.

For example, the characteristic value may be the number of all-zero sequences in the check sequence. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of all-zero sequences in the check sequence of each group of first test data blocks may be counted, a group of first test data blocks with the largest number of all-zero sequences is determined, and observation bits corresponding to the group of first test data blocks are used as the observation bits most likely to be located at the synchronization position.

When the characteristic value is the number of all-zero sequences in the check sequence, and the above-mentioned traversal selection manner is adopted, the selection process of the observation bits most likely to be located at the synchronization position can also be referred to fig. 4. As shown in fig. 4, the check sequence S is counted separately⁽¹⁾,S⁽²⁾,S⁽³⁾The number of all-zero sequences, respectively denoted as Q₁,Q₂,Q₃Determining the maximum value therein, e.g. Q₁＝0,Q₂＝0,Q ₃2, i.e. maximum value Q₃B is selected when 2 is satisfied₃For the observation bits most likely to be in the sync position, b₃The position is the most likely synchronization position.

For example, the characteristic value may be the number of non-all-zero sequences in the check sequence. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-all-zero sequences in the check sequences of each group of first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of first test data blocks which meet the candidate condition are used as the candidate bits until it is determined that the number of non-all-zero sequences in the check sequences of the group of first test data blocks is less than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis, and the specific process is similar to the synchronization threshold corresponding to the all-zero sequence, which is not described herein again.

For example, the characteristic value may be the number of non-all-zero sequences in the check sequence. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of non-all-zero sequences in the check sequence of each group of first test data blocks may be counted, a group of first test data blocks with the smallest number of non-all-zero sequences is determined, and observation bits corresponding to the group of first test data blocks are used as the observation bits most likely to be located at the synchronization position.

For example, the characteristic value may be the number of zero elements in the check sequence. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is greater than or equal to a synchronization threshold. Specifically, the relationship between the number of zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of first test data blocks which meet the candidate condition are used as the candidate bits until it is determined that the number of zero elements in the check sequence of the group of first test data blocks is greater than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

For example, the characteristic value may be the number of zero elements in the check sequence. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of zero elements in the check sequence of each group of first test data blocks may be counted, a group of first test data blocks with the largest number of zero elements is determined, and observation bits corresponding to the group of first test data blocks are used as the observation bits most likely to be located at the synchronization position.

For example, the characteristic value may be the number of non-zero elements in the check sequence. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of non-zero elements in the check sequence of each group of first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of first test data blocks that satisfy the candidate condition are used as the candidate bits until it is determined that the number of non-zero elements in the check sequence of the group of first test data blocks is less than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

For example, the characteristic value may be the number of non-zero elements in the check sequence. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of non-zero elements in the check sequence of each group of first test data blocks may be counted, a group of first test data blocks with the smallest number of non-zero elements is determined, and observation bits corresponding to the group of first test data blocks are used as the observation bits most likely to be located at the synchronization position.

When the characteristic value is a non-all-zero sequence, a zero element, or a non-zero element in the check sequence, reference may be made to the description when the characteristic value is an all-zero sequence in the check sequence in combination with the specific implementation process of the data sequence shown in fig. 4, and details are not described here again.

Alternatively, the characteristic value may be an error-correctable characteristic value. After dividing the code words in the data sequence, the receiving end can determine the states of the code words, wherein the states include an error correctable state and an error uncorrectable state. When a codeword is in an error-correctable state, the codeword is also referred to as an error-correctable codeword; when a codeword is in a non-error-correctable state, the codeword is also referred to as a non-error-correctable codeword. The value of the error correctable characteristic of a set of codewords may be associated with the state of the codewords in the set of codewords. Similarly, for the test data block marked out in the data sequence received by the receiving end, the state of the test data block can also be determined, and the state includes an error-correctable state and an error-uncorrectable state. When the test data block is in an error-correctable state, the test data block is also referred to as an error-correctable test data block; when a test data block is in a non-error-correctable state, the test data block is also referred to as a non-error-correctable test data block. The error correctable characteristic values of a set of test data blocks may be associated with the status of the test data blocks in the set of test data blocks.

For example, the error correctable characteristic value may be a number of error correctable test data blocks. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is greater than or equal to a synchronization threshold. Specifically, the relationship between the number of error-correctable test data blocks in each group of first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of first test data blocks which meet the candidate condition are used as the candidate bits until it is determined that the number of error-correctable test data blocks in the group of first test data blocks is greater than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

When the error-correctable characteristic value is the number of error-correctable test data blocks, the selection process of the observation bits most likely to be located at the synchronous position is performed in the manner of early termination as described above, as shown in fig. 4. Wherein the synchronization threshold may be 2. As shown in FIG. 4, the error-correctable test data blocks in each set of first test data blocks are sequentially judgedNumber versus synchronization threshold, e.g. number Q of error correctable test data blocks in the first set of first test data blocks₁0, less than the synchronization threshold, the number Q of error correctable test data blocks in the second set of first test data blocks₂B is selected to be 2 and equal to the synchronization threshold₂The observation bit most likely to be located at the synchronization position. And, when judging to b₂When b is determined₂If the alternative condition is satisfied, the relation between the number of the error-correctable test data blocks corresponding to the subsequent observation bits and the synchronization threshold is not judged, that is, Q is not judged₃Relation to synchronization threshold.

For example, the error correctable characteristic value may be a number of error correctable test data blocks. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of error-correctable test data blocks in each group of first test data blocks may be counted, a group of first test data blocks with the largest number of error-correctable test data blocks is determined, and observation bits corresponding to the group of first test data blocks are used as the observation bits most likely to be located at the synchronization position.

When the error-correctable characteristic value is the number of error-correctable test data blocks, the selection process of the observation bits most likely to be located at the synchronous position is also shown in fig. 4. As shown in fig. 4, to observe the bit b₁,b₂,b₃The number of error correctable test data blocks in the first test data blocks of each group for the start bit is denoted as Q₁,Q₂,Q₃Determining the maximum value therein, e.g. Q₁＝0,Q₂＝0,Q ₃2, i.e. maximum value Q₃B is selected when 2 is satisfied₃For the observation bits most likely to be in the sync position, b₃The position is the most likely synchronization position.

For example, the error correctable characteristic value may be a number of non-error correctable test data blocks. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be that the characteristic value of the set of first test data blocks is less than or equal to a synchronization threshold. Specifically, the relationship between the number of the uncorrectable test data blocks in each group of the first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of the first test data blocks meeting the candidate condition are used as the candidate bits until it is determined that the number of the uncorrectable test data blocks in the group of the first test data blocks is less than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

For example, the error correctable characteristic value may be a number of non-error correctable test data blocks. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of the uncorrectable test data blocks in each group of the first test data blocks may be counted, a group of the first test data blocks with the smallest number of the uncorrectable test data blocks is determined, and observation bits corresponding to the group of the first test data blocks are used as the observation bits most likely to be located at the synchronization position.

Alternatively, the characteristic value may be a re-check characteristic value. The re-check characteristic value is associated with a relationship between the re-check bits and the original check bits. In combination with the above description, in the codeword with length of n bits, the first k bits are information bits, and the last n-k bits are check bits. The check bits of the last n-k bits are calculated according to a specific coding rule based on the information bits of the first k bits. For the data sequence received by the receiving end, if the initial position of the code word in the data sequence is not found, the relationship between the information bit and the check bit is no longer satisfied in the divided code words. That is, even according to the same characteristic encoding rule, the content identical to the last n-k bits in each test data block cannot be obtained based on the first k bits. In each test data block in the data sequence received by the receiving end, the last n-k bits and the first k bits may no longer satisfy the specific coding rule. Therefore, when the last n-k bits obtained by recalculation according to the specific coding rule based on the first k bits in each test data block in the data sequence received by the receiving end are compared with the last n-k bits in each test data block in the data sequence received by the receiving end, there may be a difference. The last n-k bits in each test data block in the data sequence received by the receiving end may be referred to as original check bits, and the last n-k bits recalculated according to the specific coding rule based on the first k bits in each test data block in the data sequence received by the receiving end may be referred to as re-check bits.

From the above analysis, when there is an error bit in the test data block, the parity bit is different from the original parity bit. Therefore, the parity bits in each test data block in the data sequence received by the receiving end can be compared with the original parity bits to achieve codeword synchronization. Specifically, the parity bits in each test data block in the data sequence received by the receiving end may be compared with the original parity bits, and one observation bit may be selected from the observation bits as the observation bit most likely to be located at the synchronization position.

For example, the re-verification feature value may be the number of test data blocks with re-verification bits identical to the original verification bits. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be greater than or equal to a synchronization threshold. Specifically, the relationship between the number of the test data blocks with the same re-check bits as the original check bits in each group of the first test data blocks and the synchronization threshold is sequentially judged, and the observation bits corresponding to the group of the first test data blocks meeting the alternative conditions are used as the alternative bits until it is determined that the number of the test data blocks with the same re-check bits as the original check bits in the group of the first test data blocks is greater than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

When the re-check characteristic value is the number of the test data blocks with the re-check bits identical to the original check bits, and the selection manner terminated in advance is adopted, the selection process of the observation bits most likely to be located at the synchronous position can be seen in fig. 4. Wherein the synchronization threshold may be 2. As shown in fig. 4, sequentially judgeInterrupting the relationship between the number of test data blocks with the same re-check bits as the original check bits in each group of first test data blocks and the synchronization threshold, e.g. the number Q of test data blocks with the same re-check bits as the original check bits in the first group of first test data blocks₁0, less than the synchronization threshold, and the number Q of test data blocks with the same re-check bits as the original check bits in the second group of first test data blocks₂B is selected to be 2 and equal to the synchronization threshold₂The observation bit most likely to be located at the synchronization position. And, when judging to b₂When b is determined₂If the alternative condition is met, the relation between the number of the test data blocks with the same re-check bits corresponding to the subsequent observation bits and the original check bits and the synchronous threshold value is not judged, namely Q is not judged any more₃Relation to synchronization threshold.

For example, the re-verified property value may be the number of test data blocks with the re-verified bits being the same as the original parity bits. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a maximum value. Specifically, the number of the test data blocks with the same re-check bits as the original check bits in each group of the first test data blocks may be counted, a group of the first test data blocks with the largest number of the test data blocks with the same re-check bits as the original check bits is determined, and the observation bits corresponding to the group of the first test data blocks are used as the observation bits most likely to be located at the synchronization position.

When the re-check characteristic value is the number of the test data blocks with the re-check bits identical to the original check bits, and the above-mentioned traversal selection manner is adopted, the selection process of the observation bits most likely to be located at the synchronization position can also be referred to fig. 4. As shown in fig. 4, to observe the bit b₁,b₂,b₃The number of test data blocks with the same re-check bits as the original check bits in each group of first test data blocks of the start bits is respectively marked as Q₁,Q₂,Q₃Determining the maximum value therein, e.g. Q₁＝0,Q₂＝0,Q ₃2, i.e. maximum value Q₃B is selected when 2 is satisfied₃Is the most probableObservation bits at synchronous positions, b₃The position is the most likely synchronization position.

For example, the re-check characteristic value may be the number of test data blocks for which the re-check bits are not the same as the original check bits. When the selection mode of early termination is adopted, the alternative condition is associated with the characteristic value. The alternative condition may be less than or equal to a synchronization threshold. Specifically, the relationship between the number of the test data blocks with different re-check bits and original check bits in each group of the first test data blocks and the synchronization threshold is sequentially judged, and observation bits corresponding to the group of the first test data blocks meeting the alternative condition are used as the alternative bits until it is determined that the number of the test data blocks with different re-check bits and original check bits in the group of the first test data blocks is smaller than or equal to the synchronization threshold. The value of the synchronization threshold can also be obtained through simulation analysis.

For example, the re-check characteristic value may be the number of test data blocks for which the re-check bits are not the same as the original check bits. And when the ergodic selection mode is adopted, the extreme value is associated with the characteristic value. The extreme value may be a minimum value. Specifically, the number of the test data blocks with different re-check bits from the original check bits in each group of the first test data blocks may be counted, a group of the first test data blocks with the smallest number of the test data blocks with different re-check bits from the original check bits is determined, and the observation bits corresponding to the group of the first test data blocks are used as the observation bits most likely to be located at the synchronization position.

Optionally, a synchronization probability index (synchronization probability index) of the observation bits is determined according to the characteristic values of the plurality of groups of first test data blocks, and the larger the value of the synchronization probability index is, the higher the probability that the position of the observation bit is a synchronization position is. For example, when the characteristic values of the multiple groups of first test data blocks are the number of all-zero sequences in the check sequences of each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility indicator may be positively correlated with the number of all-zero sequences, that is, the greater the number of all-zero sequences, the greater the value of the synchronization possibility indicator, the greater the possibility that the position of the observation bit is the synchronization position is. For example, when the characteristic value of the plurality of groups of first test data blocks is the number of non-all-zero sequences in the check sequence of each group of first test data blocks in the plurality of groups of first test data blocks, the synchronization possibility indicator may be negatively correlated with the number of non-all-zero sequences, that is, the smaller the number of non-all-zero sequences, the greater the value of the synchronization possibility indicator, the greater the possibility that the position of the observed bit is the synchronization position. Similarly, when the characteristic value of the multiple groups of first test data blocks is the number of zero elements in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of error-correctable test data blocks in each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of test data blocks with the same re-check bits as the original check bits in each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility indicator may be positively correlated with the number of zero elements, the number of error-correctable test data blocks, or the number of test data blocks with the same re-check bits as the original check bits; when the characteristic value of the multiple groups of first test data blocks is the number of non-zero elements in the check sequence of each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of uncorrectable test data blocks in each group of first test data blocks in the multiple groups of first test data blocks, or the characteristic value of the multiple groups of first test data blocks is the number of test data blocks with different re-check bits from the original check bits in each group of first test data blocks in the multiple groups of first test data blocks, the synchronization possibility index may be negatively correlated with the number of non-zero elements, the number of uncorrectable test data blocks, or the number of test data blocks with different re-check bits from the original check bits; and will not be described in detail herein.

Optionally, when the number of observation bits with the largest value of the synchronization possibility indicator in the plurality of groups of first test data blocks is greater than 1, one of the observation bits may be selected as the observation bit most likely to be located at the synchronization position according to other conditions. For example, from the observation bits with the largest value of the synchronization possibility index, one observation bit is randomly selected as the observation bit most likely to be located at the synchronization position. For example, from the observation bits with the largest value of the synchronization possibility indicator, the observation bit ranked the first in the data sequence is selected as the observation bit most likely to be located at the synchronization position.

And S230, in the second stage, verifying the alternative bit, and when the verification is successful, determining the position of the alternative bit as the synchronous position. Specifically, S230 may include two steps S231 and S232.

And S231, dividing a group of second test data blocks in the data sequence according to the alternative bits, wherein the group of second test data blocks comprises at least one second test data block. The alternative bits are the observation bits most likely to be in the sync position.

Optionally, in the second stage, the method may utilize only a part of the data sequence, for example, a second subsequence of the data sequence, when dividing at least one second test data block in the data sequence according to the candidate bits. And dividing a group of second test data blocks in the data sequence according to the alternative bits, namely dividing a group of second test data blocks in the second subsequence according to the alternative bits.

Optionally, the second sub-sequence may be the same as the first sub-sequence in the first stage, that is, all bits of the second sub-sequence are the same as those of the first sub-sequence, and the two sub-sequences are completely overlapped. Optionally, the second sub-sequence may also be partially identical to the first sub-sequence in the first stage, that is, the second sub-sequence and the first sub-sequence have the same partial bits, and the two sub-sequences partially coincide. Optionally, the second subsequence may be different from the first subsequence in the first stage, that is, all bits of the second subsequence are different from all bits of the first subsequence, and the two subsequences do not intersect.

When the intersection between the data used in the first stage and the data used in the second stage are less, the independence between the data used in the first stage and the data used in the second stage is stronger, and the accuracy of the code word synchronization result is higher. Therefore, when the first subsequence is different from the second subsequence, the accuracy of the codeword synchronization result is higher.

In a second phase, a set of second test data blocks is partitioned in the second sub-sequence according to the candidate bits, i.e. the observation bits most likely to be located at the synchronization position, the set of second test data blocks including at least one second test data block.

Wherein, according to the alternative bit, a group of second test data blocks is partitioned in the second subsequence, which may be partitioning the at least one second test data block by using the alternative bit as a start bit of the at least one second test data block.

According to the observation bits most probably located at the synchronous position, a group of second test data blocks are divided in the second subsequence, or the observation bits most probably located at the synchronous position are used as the start bits of the test data blocks, so that the second subsequence is divided into a plurality of test data blocks, and at least one test data block is selected from the plurality of test data blocks as the at least one second test data block. At this time, the at least one second test data block and the observation bit most likely to be located at the synchronization position are separated by several test data blocks, and the at least one second test data block may be located before the observation bit most likely to be located at the synchronization position or may be located after the observation bit most likely to be located at the synchronization position.

Optionally, the at least one second test data block may be consecutive, i.e. the at least one second test data block comprises N consecutive data blocks. And when the length of each test data block is N bits, selecting the next continuous N x N bits to obtain the at least one second test data block.

Optionally, the at least one second test data block may also be discontinuous, and a start position of each of the at least one second test data block is associated with the candidate bit. Specifically, the interval between the start position of each test data block and the candidate bit is an integer multiple of the length of the codeword, that is, the interval between every two test data blocks in the at least one second test data block is an integer multiple of the length of the codeword. Moreover, the interval between every two test data blocks in the at least one second test data block may be the same or different.

S232, verifying the characteristic value of the at least one second test data block, and determining the position of the candidate bit as the synchronization position when the verification is successful.

Optionally, the characteristic value of the at least one second test data block is verified, and the verification mode may be a verification mode that terminates early. Specifically, the characteristic values of each second test data block in the at least one second test data block are sequentially accumulated to obtain an accumulated value, until the accumulated value meets the synchronization condition, verification is successful, and the position of the candidate bit is determined as the synchronization position.

Wherein the synchronization condition is associated with the characteristic value, in particular,

the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of the test data blocks with the re-check bits being the same as the original check bits, and the synchronization condition is that the accumulated value is greater than or equal to a synchronization threshold value;

wherein, the value of the synchronization threshold value can also be obtained through simulation analysis. Moreover, the synchronization threshold in step 230 and the synchronization threshold in step 2222 may be the same value or different values.

Optionally, the characteristic value of the at least one second test data block is verified, and the verification manner may be a traversal verification manner. Specifically, the characteristic values of all the second test data blocks in the at least one second test data block are added to obtain a total value, when the total value meets a synchronization condition, verification is successful, and the position of the candidate bit is determined to be the synchronization position.

the characteristic value is the number of all-zero sequences in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of non-all-zero sequences in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold value; or,

the characteristic value is the number of zero elements in the check sequence, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of non-zero elements in the check sequence, and the synchronization condition is that the total value is less than or equal to a synchronization threshold value; or,

the characteristic value is the number of error-correctable test data blocks, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold; or,

the characteristic value is the number of the uncorrectable test data blocks, and the synchronization condition is that the total value is less than or equal to a synchronization threshold value; or,

the characteristic value is the number of the test data blocks with the re-check bits being the same as the original check bits, and the synchronization condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of the test data blocks with the re-check bits different from the original check bits, and the synchronization condition is that the total value is smaller than or equal to a synchronization threshold value.

In both the verification mode of early termination and the verification mode of traversal, the calculation of the characteristic values can be performed in parallel, that is, a plurality of calculation units are used to calculate the characteristic values of a plurality of test data blocks at the same time. For example, 10 calculation units are used to simultaneously calculate the characteristic values of 10 test data blocks. The parallel computing mode can save computing time and reduce time delay.

Fig. 8 to 9 show an exemplary procedure for determining the observation bit most likely to be located at the sync location in the data sequence and verifying whether the position of the observation bit most likely to be located at the sync location is the sync location. The linear block code shown in fig. 8 is a BCH (360,340) code, i.e., where each codeword has a length of 360 bits and the information data within each codeword has a length of 340 bits. The BCH (360,340) code has a modulation mode of Non-Return-to-Zero (NRZ) and a modulation order M of 2, and each code element comprises 1 bit. The check matrix for this BCH (360,340) code is as follows:

wherein alpha is a Galois field GF (2)¹⁰) A principal element (principal element).

Fig. 8 shows a part of a data sequence received by a receiving end, and a start position, i.e. a synchronization position, of a codeword in the data sequence needs to be confirmed. In connection with the above description, in said first phase, the observation bits in the data sequence that are most likely to be located at the synchronization positions are determined. As shown in FIG. 8, in the first stage, every interval T.log₂And selecting the initial bit of the modulation code element as an observation bit by M bits, wherein T is 1, namely selecting the initial bit of the modulation code element as the observation bit by 1 bit every interval. Thus, a continuous 360 bits are selected as observation bits, i.e. the number P of observation bits is 360, as shown in fig. 8 b₁,b₂,b₃,…,b₃₅₉,b₃₆₀. From the data sequence according to these observation bitsA plurality of groups of first test data blocks are divided, the number N of the test data blocks in each group of the first test data blocks is 2, that is, each group of the first test data blocks includes 2 test data blocks, such as a plurality of groups B shown in fig. 8₁,B₂。

In conjunction with the above description, only one observation bit position among the observation bit positions in the data sequence shown in fig. 8 is the true synchronization position of the data sequence. And taking the number of all-zero sequences in the check sequences of each group of first test data blocks as a basis for selecting the observation bits most probably positioned at the synchronous position. As shown in FIG. 8, the check sequence S is a length-4 row vector, e.g., to observe bit b₁The set of check sequences for a set of first test data blocks being the start bit is S⁽¹⁾Including S₁ ⁽¹⁾,S₂ ⁽¹⁾Respectively correspond to the test data blocks B₁,B₂Similarly, to observe bit b₂,b₃,…,b₃₅₉,b₃₆₀A set of check sequences of a first test data block, S respectively, of a start bit⁽²⁾,S⁽³⁾,…,S⁽³⁵⁹⁾,S⁽³⁶⁰⁾. Counting the number of all-zero sequences in the check sequence of each group of first test data blocks, and respectively recording as Q₁,Q₂,Q₃,…,Q₃₅₉,Q₃₆₀. As shown in FIG. 8, wherein Q ₁0, i.e. to observe bit b₁The check sequence of the first test data block of the set of start bits has no all-zero sequence, and similarly, Q₂＝0,Q₃＝1,…,Q₃₅₉＝2,Q ₃₆₀0. Suppose that Q is eventually in all 360Q values₃₅₉Has the largest value, bit b will be observed₃₅₉As the observation bit most likely to be located at the sync position. I.e. consider the observation bit b₃₅₉Is the start bit of a test data block, and is the start bit of the subsequent test data block every 360 bits thereafter.

Selecting the observation bit most probably positioned at the synchronous position as b₃₅₉Then, after the part of the data sequence used in the first phase, i.e. after said first subsequence, according to b₃₅₉And dividing a group of second test data blocks. I.e. a set of second test data blocks is divided in a second sub-sequence, which is different from the first sub-sequence. As shown in fig. 9, the set of second test data blocks includes 4 test data blocks. And verifying the characteristic value of the at least one second test data block, wherein the characteristic value is the number of all-zero sequences in the check sequence of the at least one second test data block. And adopting the traversal verification mode, namely adding the number of all zero sequences in the check sequences of all the second test data blocks in the at least one second test data block to obtain a total value, and when the total value is greater than or equal to a synchronization threshold, successfully verifying, wherein the synchronization threshold is 2. As shown in fig. 9, the number of all-zero sequences in the check sequences of 4 test data blocks is 3 and greater than 2, and thus b is determined₃₅₉The position is a synchronous position.

Optionally, when the verification is not successful, the step S220 is executed again, that is, the first stage is executed again, and the observation bits most likely to be located at the synchronization position are reselected.

Step S230 is an optional step, i.e. the method may comprise only said first stage. At this time, step S240 is directly entered after step S220. In this case, in this method, after the candidate bit is determined, the position of the candidate bit is directly determined as the synchronization position. I.e. directly taking the most probable synchronisation position as the synchronisation position.

S240, determining that the data sequence is in a synchronous locking state.

After the receiving end determines the synchronization position, the receiving end can divide the received data sequence into a plurality of synchronization code words according to the synchronization position. When a data sequence is divided into a plurality of sync code words according to a sync position, the data sequence can be considered to be in a sync lock position. That is, after determining the synchronization position, the receiving end determines that the data sequence is in a synchronization locked state. When the data sequence is in a synchronous locking state, the receiving end can perform operations such as error detection and error correction on the data sequence.

And S250, judging losing lock.

After the receiving end starts to perform operations such as error detection and error correction on the data sequence, it is still necessary to continuously observe whether the codeword division in the data sequence is accurate, i.e., whether the synchronization position is accurate. When the synchronization position is not accurate, the content of each test data block divided according to the synchronization position no longer corresponds to a real codeword, and at this time, it can also be referred to as that the synchronization locking state of the data sequence is lost. Therefore, the process of determining whether the synchronization position of the data sequence is accurate may also be referred to as an out-of-lock determination process.

In the process of lock loss judgment, dividing a plurality of synchronous code words from the data sequence according to the synchronous position, wherein the synchronous position is the initial position of the plurality of synchronous code words; and verifying the characteristic values of the plurality of synchronous code words, and determining the data sequence to be in the out-of-lock state when the verification fails.

Optionally, the plurality of synchronization code words may be consecutive, that is, the plurality of synchronization code words includes consecutive N code words. When the length of each code word is N bits, the next continuous N x N bits are selected, and the plurality of synchronous code words are obtained.

Optionally, the plurality of synchronization code words may also be discontinuous, and a start position of each of the plurality of synchronization code words is associated with a synchronization position. Specifically, the interval between the start position and the synchronization position of each synchronization codeword is an integer multiple of the length of the codeword, that is, the interval between every two synchronization codewords in the plurality of synchronization codewords is an integer multiple of the length of the codeword. Moreover, the intervals between every two synchronization code words in the plurality of synchronization code words may be the same or different.

Optionally, the characteristic values of the plurality of synchronization code words are verified, and the verification mode may be a verification mode that terminates early. Specifically, the characteristic values of each of the plurality of synchronization code words are sequentially accumulated to obtain an accumulated value, until the accumulated value meets the lock losing condition, the verification fails, and the position of the candidate bit is determined as the synchronization position.

Wherein the out-of-lock condition is associated with the characteristic value, in particular,

the characteristic value is the number of non-all-zero sequences in the check sequence, and the unlocking condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of non-zero elements in the check sequence, and the unlocking condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of the non-error-correcting code words, and the unlocking condition is that the accumulated value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of code words with different re-check bits and original check bits, and the unlocking condition is that the accumulated value is greater than or equal to a synchronization threshold value;

the length of the code word is n bits, the first k bits of the code word are information bits, the last n-k bits of the code word are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

Wherein, the value of the synchronization threshold value can also be obtained through simulation analysis. The synchronization threshold in step 250 and the synchronization threshold in step 230,2222 may be the same value or different values.

Optionally, the characteristic values of the multiple synchronization code words are verified, and the verification mode may be a traversal verification mode. Specifically, the characteristic values of all the synchronization code words in the plurality of synchronization code words are added to obtain a total value, when the total value meets an out-of-lock condition, verification fails, and the position of the candidate bit is determined as the synchronization position.

the characteristic value is the number of all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold value; or,

the characteristic value is the number of non-all-zero sequences in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of zero elements in the check sequence, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold value; or,

the characteristic value is the number of non-zero elements in the check sequence, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of error-correctable code words, and the out-of-lock condition is that the total value is less than or equal to a synchronization threshold; or,

the characteristic value is the number of the non-error-correcting code words, and the out-of-lock condition is that the total value is greater than or equal to a synchronization threshold value; or,

the characteristic value is the number of code words with the same re-check bits and original check bits, and the unlocking condition is that the total value is smaller than or equal to a synchronous threshold value; or,

the characteristic value is the number of code words with different re-check bits and original check bits, and the unlocking condition is that the total value is greater than or equal to a synchronous threshold value;

FIG. 10 illustrates an exemplary process of an out-of-lock determination. As shown in fig. 10, 5 sync code words are divided from the data sequence according to the sync position, and the number of error-correctable code words therein is counted. For example, in the decoding state (decoding state), 0 indicates that error correction is not possible and 1 indicates that error correction is possible, the number of error-correctable codewords is 1 among the 5 sync codewords shown in fig. 10. And if the out-of-lock threshold is 3, determining that the number of the error-correctable code words is less than the out-of-lock threshold, and determining that 5 synchronous code words meet the out-of-lock condition, wherein the data sequence is in an out-of-lock state.

Optionally, when the verification fails, it is determined that the synchronization locking state of the data sequence is not lost.

Optionally, after determining that the synchronization locking state of the data sequence is not lost, the data sequence may continue to move backward for a certain interval, select a plurality of synchronization code words, and continue to determine whether the plurality of synchronization code words selected backward satisfy the lock losing condition. Optionally, the moving backward by a certain interval may be moving one test data block, that is, each synchronization codeword starts to observe a plurality of synchronization codewords backward, so as to perform lock loss determination.

And S260, determining that the data sequence is in an unlocked state.

Optionally, when the data sequence is determined to be in an unlocked state, the updated synchronization position of the data sequence is continuously determined. Specifically, the first stage and the second stage are re-executed, and the synchronization position determined in the re-executed second stage is used as the updated synchronization position. Therefore, a closed-loop operation of synchronous locking-losing-synchronous locking is formed, and the communication system is ensured to be in a normal working state of synchronous locking in as much time as possible.

By the method, the technical problems of extra data addition and poor cascade expansibility in an AM synchronization scheme can be solved. In addition, extra data does not need to be inserted into the data stream of the sending end, so that an Idle (Idle) code block adding and deleting mechanism does not need to be introduced into the Ethernet interface, a corresponding logic processing unit does not need to be designed, and the bandwidth does not need to be reserved in advance for the inserted AM sequence. If one-level FEC is needed to be added on the basis of the original FEC, and when two-level FEC cascade is adopted, the technical problems that the original idle code block adding and deleting mechanism cannot be suitable for the AM sequence of the second-level FEC and the high-precision clock synchronization performance is influenced by adding the AM sequence aiming at the second-level FEC can be solved. The method can realize the technical effect of high-precision code word synchronization of the data stream of the receiving end, and the synchronization performance of the method achieves higher reliability.

Steps S240, S250, and S260 are optional steps, that is, the method may be used only to determine the synchronization position, may not perform error detection or error correction processing on the data sequence in the synchronization locking state, or may not determine whether the data sequence subsequently enters the out-of-lock state.

Compared with the existing AM synchronization scheme, the code word synchronization method provided by the application is superior to the existing AM synchronization scheme in all performance indexes such as average synchronous locking time, mean occurrence time of false locking, mean occurrence time of false unlocking and the like. Therefore, the codeword synchronization method provided by the present application can achieve better synchronization performance than the AM synchronization scheme as a whole.

Fig. 11 shows a codeword synchronization method according to an embodiment of the present application. The method comprises the following steps:

step one, receiving a data sequence, wherein the data sequence comprises a plurality of bits. The specific process of the step one can refer to the above description of the step S210.

And step two, determining alternative bits in the data sequence, wherein the alternative bits are included in the plurality of bits. The alternative bit is the observation bit most likely to be located at the synchronization position. The specific process of step two may be referred to the above description of step S220.

And step three, determining a synchronous position according to the alternative bit, wherein the synchronous position is used for indicating the initial position of the code word.

Optionally, determining the synchronization position according to the candidate bit may be further verifying whether the position of the observation bit most likely to be located at the synchronization position is the synchronization position after selecting the observation bit most likely to be located at the synchronization position. The alternative bit is the observation bit most likely to be located at the synchronization position. At this time, the specific process of step three may refer to the description of step S230 above. At this time, the method includes at least S210, S220, and S230 shown in fig. 2.

Optionally, determining the synchronization position according to the candidate bit may also be directly taking the observation bit most likely to be located at the synchronization position as the synchronization position after selecting the observation bit most likely to be located at the synchronization position. The alternative bit is the observation bit most likely to be located at the synchronization position. At this time, the method includes at least S210 and S220 shown in fig. 2.

It can be seen that, in the above two ways of determining the synchronization position according to the candidate bits, the bit located at the synchronization position is included in the candidate bits, and the candidate bit is the observation bit most likely to be located at the synchronization position.

Optionally, after the third step, the method further includes: determining that the data sequence is in a synchronization locked state. The specific process can be referred to the above description of step S240.

Optionally, after the third step, the method further includes: and (6) judging lock losing. The specific process can be referred to the above description of step S250.

Optionally, the method may further include a fourth step of determining an updated synchronization position of the data sequence in response to the data sequence being in an unlocked state. The specific process can be referred to the above description of step S260.

The codeword synchronization method of the embodiment of the present application is performed by a communication device, which may be any device that performs FEC, including but not limited to a router, a switch, a server, and a terminal device.

Fig. 12 is a schematic diagram illustrating a possible structure of a communication device according to an embodiment of the present application, and referring to fig. 12, a communication device 1200 includes: a receiving unit 1201 and a processing unit 1202. These units may perform the corresponding steps of the methods shown in fig. 2-11 described above. For example,

a receiving unit 1201 is configured to receive a data sequence, where the data sequence includes a plurality of bits.

A processing unit 1202, configured to determine candidate bits in the data sequence, where the candidate bits are included in the plurality of bits; and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the starting position of a code word in the data sequence.

Fig. 13 is another schematic structural diagram of a communication device according to an embodiment of the present application. Referring to fig. 13, the communication device 1300 includes at least one processor 1301 and at least one communication interface 1304, and optionally, the device 1300 may further include a memory 1303.

The processor 1301 may be a Central Processing Unit (CPU), a general purpose processor, a Digital Signal Processor (DSP), an application-specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, transistor logic, hardware components, or any combination thereof. Which may implement or perform the various logical blocks, modules, and circuits described in connection with the embodiment disclosure of the present application. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others. A processor may be configured to determine candidate bits in the data sequence and to determine a synchronization position based on the candidate bits. To implement the methods provided in the embodiments of the present application.

Optionally, a communication bus 1302 is used to transfer information between the processor 1301, a communication interface 1304, and memory 1303. The bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 13, but this is not intended to represent only one bus or type of bus.

The Memory 1303 may be, but is not limited to, a read-only Memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only Memory (EEPROM), a compact disc read-only Memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Memory 1303 may be separate and coupled to processor 1301 via communication bus 1302. Memory 1303 may also be integrated with processor 1301.

Optionally, the memory 1303 is used for storing program codes or instructions for executing the scheme of the present application, and is controlled by the processor 1301 to execute the program codes or instructions. In the case of implementing the embodiment shown in fig. 12, and in the case where each unit described in the embodiment of fig. 12 is implemented by software, software or program codes necessary for executing the functions of each unit in fig. 12 are stored in the memory 1303. Processor 1301 is configured to execute program code stored in memory 1303. One or more software modules may be included in the program code. Optionally, the processor 1301 itself may also store program code or instructions to perform aspects of the present application.

Communication interface 1304, using any transceiver or the like, is used to communicate with other devices or communication networks, such as ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc. In this embodiment, the communication interface 1304 may be configured to receive a packet sent by another node in the segment routing network, or send a packet to another node in the segment routing network. The communication interface 1304 may be an Ethernet (Ethernet) interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, or an Asynchronous Transfer Mode (ATM) interface.

In particular implementations, device 1300 may include multiple processors, such as processor 1301 and processor 1305 shown in fig. 13, as an example. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

In a particular embodiment, the processor 1301 in the network device 1300 is configured to receive a data sequence through the communication interface, the data sequence comprising a plurality of bits; determining alternative bits in the data sequence, the alternative bits included in the plurality of bits; and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the starting position of a code word in the data sequence. For the detailed processing procedure of the processor, please refer to steps S210, S220, S230, S240, S250, and S260 in the embodiment shown in fig. 2, steps S221 and S222 in the embodiment shown in fig. 3, and detailed descriptions of steps one to three in fig. 11, which are not repeated herein.

The communication interfaces in the network device 1300 are used for the network device 1300 to receive and transmit data sequences over the network system. For a specific process, please refer to S210 in the embodiment shown in fig. 2 and detailed description of the step one shown in fig. 11, which are not repeated herein.

Fig. 14 is a schematic structural diagram of a communication device according to an embodiment of the present application. When the communication device is a forwarding device in a network, such as a router or a switch, the communication device may refer to the device structure diagram shown in fig. 14. The device 1400 includes a main control board and one or more interface boards, the main control board being communicatively connected to the interface boards. The main control board is also called a Main Processing Unit (MPU) or a route processor card (route processor card), and is responsible for controlling and managing various components in the device 1400, including routing computation, device management, and maintenance functions. An interface board is also called a Line Processing Unit (LPU) or a line card (line card) and is used to forward data. In some embodiments, the device 1400 may also include a switch network board, where the switch network board is communicatively connected to the main control board and an interface board, the switch network board is used to forward data between the interface boards, and the switch network board may also be referred to as a Switch Fabric Unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip, and a Physical Interface Card (PIC). The central processor is in communication connection with the memory, the network processor and the physical interface card respectively. The memory is used for storing a forwarding table. The forwarding chip is used for forwarding the received data frame based on a forwarding table stored in the memory, and if the destination address of the data frame is the address of the device 1400, the data frame is uploaded to the CPU for processing; if the destination address of the data frame is not the address of the device 1400, the next hop and the egress interface corresponding to the destination address are found from the forwarding table according to the destination address, and the data frame is forwarded to the egress interface corresponding to the destination address. The forwarding chip may be a Network Processor (NP). The PIC is also called a daughter card and can be installed on an interface board to convert the photoelectric signal into a data frame, and forward the data frame to a forwarding chip for processing after validity check is performed on the data frame. In some embodiments, the central processing unit may also perform the functions of a forwarding chip, such as implementing software forwarding based on a general purpose CPU, so that no forwarding chip is needed in the interface board. The communication connection among the main control board, the interface board and the exchange network board can be realized through a bus. In some embodiments, the forwarding chip may be implemented by an application-specific integrated circuit (ASIC) or a Field Programmable Gate Array (FPGA).

Logically, the device 1400 includes a control plane including a main control board and a central processor, and a forwarding plane including various components performing forwarding, such as a memory, a PIC, and an NP. The control plane executes the functions of the router, generating a forwarding table, processing signaling and protocol messages, configuring and maintaining the state of the PE1, and the like, and the control plane issues the generated forwarding table to the forwarding plane, and in the forwarding plane, the NP looks up the table of the message received by the PIC of the device 1400 and forwards the table based on the forwarding table issued by the control plane. The forwarding table issued by the control plane may be stored in a memory. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same device.

In a specific embodiment, the interface board is configured to receive a data sequence, and the data sequence includes a plurality of bits. For a specific process, please refer to S210 in the embodiment shown in fig. 2 and detailed description of the step one shown in fig. 11, which are not repeated herein. The main control board is used for determining alternative bits in the data sequence, wherein the alternative bits are included in the plurality of bits; and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the starting position of a code word in the data sequence. For the detailed processing, please refer to steps S210, S220, S230, S240, S250, and S260 in the embodiment shown in fig. 2, steps S221 and S222 in the embodiment shown in fig. 3, and detailed descriptions of steps one to three in fig. 11, which are not repeated herein.

Embodiments of the present application provide a chip, which includes a memory for storing a computer program and a processor for calling and running the computer program from the memory to execute the method in the above method embodiments, i.e., the method in the embodiments shown in fig. 2 to 11.

Alternatively, the chip only comprises a processor for reading and executing a computer program stored in a memory, which when executed performs the method of the above-described method embodiment, i.e. the method of the embodiment shown in fig. 2-11.

Optionally, the chip may be used in an application scenario of two-stage FEC concatenation. Specifically, the two-stage FEC cascade includes an inner-layer FEC and an outer-layer FEC, and the chip provided in this embodiment is used for the inner-layer FEC. The inner layer FEC adopts the codeword synchronization method described in the present application, also referred to as FEC 1; the outer FEC may employ an AM synchronization scheme, also referred to as FEC 2. In this case, the FEC1 and the FEC2 may be located on the same chip or different chips. That is, the chip provided in the embodiment of the present application may include only the FEC1, or may include the FEC1 and the FEC 2.

The embodiment of the application provides a network system. The network system includes a receiving device and a transmitting device. The receiving device is used for receiving the data sequence sent by the sending device. The receiving device may perform the steps in the embodiments of fig. 2-11 described above.

The present application further provides a non-transitory storage medium for storing software instructions used in the foregoing embodiments, which includes a program for executing the method shown in the foregoing embodiments, and when the program is executed on a computer or a network device, the computer or the network device is caused to execute the method in the foregoing method embodiments.

Embodiments of the present application also provide a computer program product comprising computer program instructions, which when run on a computer, cause the network node to perform the method in the aforementioned method embodiments.

It should be noted that any of the above-described device embodiments are merely schematic, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of embodiments of the network device or the host provided by the present application, a connection relationship between modules indicates that there is a communication connection therebetween, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.

The steps of a method or algorithm described in the disclosure of the embodiments of the present application may be implemented in hardware, or may be implemented by a processor executing software instructions. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash memory, read-only memory (ROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), a hard disk, a removable hard disk, an optical disk, or any other form of storage medium known in the art. A storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor.

The above-mentioned embodiments, objects, technical solutions and advantages of the present application are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present application, and are not intended to limit the scope of the present application, and any modifications, substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.

The terms "first," "second," and the like in this application are used for distinguishing between similar items and items that have substantially the same function or similar functionality, and it should be understood that "first," "second," and "nth" do not have any logical or temporal dependency or limitation on the number or order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image, without departing from the scope of the various described examples. Both the first image and the second image may be images, and in some cases, may be separate and distinct images.

The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more, for example, the plurality of second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

It is to be understood that the terminology used in the description of the various described examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various described examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and/or" is an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present application generally indicates that the former and latter related objects are in an "or" relationship.

It should also be understood that, in the embodiments of the present application, the size of the serial number of each process does not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be understood that determining B from a does not mean determining B from a alone, but may also be determined from a and/or other information.

It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also understood that the term "if" may be interpreted to mean "when" ("where" or "upon") or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined." or "if [ a stated condition or event ] is detected" may be interpreted to mean "upon determining.. or" in response to determining. "or" upon detecting [ a stated condition or event ] or "in response to detecting [ a stated condition or event ]" depending on the context.

It should be appreciated that reference throughout this specification to "one embodiment," "an embodiment," "one possible implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "one possible implementation" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Claims

1. A method for codeword synchronization, the method comprising:

receiving a data sequence, wherein the data sequence comprises a plurality of bits;

determining alternative bits in the data sequence, wherein the alternative bits are included in the plurality of bits;

and step three, determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the initial position of a code word in the data sequence.

2. The method of claim 1, wherein step three comprises:

and verifying the alternative bit, and when the verification is successful, determining the position of the alternative bit as the synchronous position.

3. The method of claim 2, wherein step three comprises:

dividing at least one second test data block in the data sequence according to the alternative bit, wherein the position of the alternative bit is the starting position of the at least one second test data block;

and verifying the characteristic value of the at least one second test data block, and when the verification is successful, determining the position of the alternative bit as the synchronous position.

4. The method of claim 3,

verifying the characteristic value of the at least one second test data block, including:

and sequentially accumulating the characteristic values of the second test data blocks in the at least one second test data block to obtain an accumulated value, and when the accumulated value meets the synchronization condition, successfully verifying.

5. The method of claim 4,

the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n and k are integers.

6. The method of claim 3,

and adding the characteristic values of all the second test data blocks in the at least one second test data block to obtain a total value, and when the total value meets the synchronization condition, successfully verifying.

7. The method of claim 6,

the characteristic value is the number of the test data blocks with the re-check bits different from the original check bits, and the synchronization condition is that the total value is smaller than or equal to a synchronization threshold value;

8. The method of claim 1, wherein step three comprises:

and taking the position of the alternative bit as the synchronous position.

9. The method according to claim 1, wherein the second step comprises:

selecting a plurality of observation bits from the data sequence;

selecting the candidate bit from the plurality of observation bits.

10. The method of claim 9, wherein the selecting the candidate bit from the plurality of observation bits comprises:

determining a plurality of groups of first test data blocks from the data sequence according to the plurality of observation bits, wherein each group of first test data blocks in the plurality of groups of first test data blocks comprises at least one first test data block, and the position of each observation bit in the plurality of observation bits is the starting position of each group of first test data blocks in the plurality of groups of first test data blocks;

and selecting one observation bit from the observation bits as the alternative bit according to the characteristic values of the plurality of groups of first test data blocks.

11. The method of claim 10, wherein,

selecting an observation bit from the observation bits as the alternative bit according to the characteristic values of the plurality of groups of first test data blocks, including:

sequentially judging whether the characteristic values of each group of first test data blocks in the multiple groups of first test data blocks meet the alternative conditions or not until the characteristic values of one group of first test data blocks meet the alternative conditions;

and taking the observation bit corresponding to the group of first test data blocks meeting the alternative condition as the alternative bit.

12. The method of claim 11,

the characteristic value of the group of first test data blocks is the total value of the number of all-zero sequences in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is the total value of the number of non-all-zero sequences in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is the total value of the number of zero elements in the check sequences of all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is the total value of the number of nonzero elements in the check sequences of all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is smaller than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a total value of the number of error-correctable test data blocks in all first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a total value of the number of the error-uncorrectable test data blocks in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is less than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is the total value of the number of test data blocks with the same re-check bits and original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is the total value of the number of test data blocks with different re-check bits and original check bits in all the first test data blocks in the group of first test data blocks, and the alternative condition is that the total value is smaller than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a quantity accumulated value of all zero sequences in check sequences of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a quantity accumulated value of zero elements in the check sequence of the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a quantity accumulated value of error-correctable test data blocks in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold; or,

the characteristic value of the group of first test data blocks is a quantity accumulated value of the test data blocks with the same re-check bits and original check bits in the first X first test data blocks in the group of first test data blocks, and the alternative condition is that the accumulated value is greater than or equal to a synchronization threshold;

the length of the test data block is n bits, the first k bits of the test data block are information bits, the last n-k bits of the test data block are the original check bits, the re-check bits are obtained according to the information bits, the length of the re-check bits is n-k bits, and n, k and X are integers.

13. The method of claim 10, wherein,

and comparing the characteristic value of each group of first test data blocks in the multiple groups of first test data blocks, and taking the observation bit corresponding to the group of first test data blocks of which the characteristic value is an extreme value as the alternative bit.

14. The method of claim 13,

the characteristic value is the number of all-zero sequences in the check sequence, and the extreme value is the maximum value; or,

the characteristic value is the number of non-all-zero sequences in the check sequence, and the extreme value is the minimum value; or,

the characteristic value is the number of zero elements in the check sequence, and the extreme value is the maximum value; or,

the characteristic value is the number of nonzero elements in the check sequence, and the extreme value is the minimum value; or,

the characteristic value is the number of the error-correctable test data blocks, and the extreme value is the maximum value; or,

the characteristic value is the number of the uncorrectable test data blocks, and the extreme value is the minimum value; or,

the characteristic value is the number of the test data blocks with the re-check bits same as the original check bits, and the extreme value is the maximum value; or,

the characteristic value is the number of the test data blocks with the re-check bits different from the original check bits, and the extreme value is the minimum value;

15. The method of any one of claims 9-14, wherein,

the selecting a plurality of observation bits from the data sequence includes:

selecting one bit from the data sequence every T bits as the observation bit, wherein T is an integer larger than zero; or,

selecting one bit from the data sequence at intervals of L x n + T bits as the observation bit, wherein L is the number of the test data blocks at intervals, the length of the test data block is the n bits, and L and T are integers greater than zero.

16. The method according to any of claims 9-14, wherein the data sequence is a modulated signal, the data sequence comprising a plurality of modulation symbols, wherein,

the selecting a plurality of observation bits from the data sequence includes:

selecting the initial bit of the modulation code element from the data sequence at intervals of T modulation code elements as the observation bit, wherein T is an integer larger than zero; or,

selecting the initial bit of the modulation code element as the observation bit from every L m + T modulation code elements in the data sequence, wherein L is the number of the test data blocks at intervals, the length of the test data block is the m modulation code elements, and L and T are integers greater than zero.

17. The method according to any of claims 9-16, wherein the number of observation bits is P, wherein P is a positive integer, and wherein the length of the codeword is P bits.

18. The method according to any one of claims 3 to 7, wherein,

in the second step, the determining alternative bits in the data sequence includes determining alternative bits in a first subsequence, and in the third step, the dividing at least one second test data block in the data sequence according to the alternative bits includes dividing at least one second test data block in a second subsequence according to the alternative bits, the first subsequence and the second subsequence being included in the data sequence, and the second subsequence being the same as, partially the same as, or different from the first subsequence.

19. The method of any one of claims 1-18, wherein after step three, the method further comprises:

and step four, responding to the fact that the data sequence is in an unlocked state, and determining the updated synchronous position of the data sequence.

20. The method of claim 19, wherein the determining the updated synchronization position of the data sequence comprises:

and re-executing the second step and the third step, and taking the synchronization position determined by the re-executed third step as the updated synchronization position.

21. The method of claim 19 or 20, wherein after step three and before step four, the method further comprises:

dividing a plurality of synchronous code words from the data sequence according to the synchronous position, wherein the synchronous position is the starting position of the plurality of synchronous code words;

and verifying the characteristic values of the plurality of synchronous code words, and determining the data sequence to be in the out-of-lock state when the verification fails.

22. The method of claim 21,

verifying the characteristic values of the plurality of synchronization codewords, comprising:

and sequentially accumulating the characteristic values of all the synchronous code words in the plurality of synchronous code words to obtain an accumulated value, and failing to verify until the accumulated value meets the unlocking condition.

23. The method of claim 22,

24. The method of claim 21,

and adding the characteristic values of all the synchronous code words in the plurality of synchronous code words to obtain a total value, and when the total value meets the out-of-lock condition, the verification fails.

25. The method of claim 24,

26. The method according to any of claims 1-25, wherein the data sequence is a linear block code.

27. A communication device, characterized in that the communication device comprises:

a receiving unit, configured to perform the first step: receiving a data sequence, the data sequence comprising a plurality of bits;

a processing unit, configured to perform step two: determining alternative bits in the data sequence, the alternative bits included in the plurality of bits; and a third step: and determining a synchronous position according to the alternative bits, wherein the synchronous position is used for indicating the starting position of a code word in the data sequence.

28. The communication device of claim 27,

the processing unit is further configured to verify the candidate bit, and determine that the position of the candidate bit is the synchronization position when the verification is successful.

29. The communication device of claim 28,

the processing unit is further configured to partition at least one second test data block in the data sequence according to the candidate bit, where a position of the candidate bit is a start position of the at least one second test data block; and verifying the characteristic value of the at least one second test data block, and when the verification is successful, determining the position of the alternative bit as the synchronous position.

30. The communication device of claim 29,

the processing unit is further configured to sequentially accumulate the characteristic values of each of the at least one second test data block to obtain an accumulated value, and the verification is successful until the accumulated value meets the synchronization condition.

31. The communication device of claim 30,

32. The communication device of claim 29,

the processing unit is further configured to add the characteristic values of all the second test data blocks in the at least one second test data block to obtain a total value, and when the total value satisfies the synchronization condition, the verification is successful.

33. The communication device of claim 32,

34. The communication device of claim 27,

the processing unit is further configured to use the position of the candidate bit as the synchronization position.

35. The communication device of claim 27,

the processing unit is further configured to select a plurality of observation bits from the data sequence; selecting the candidate bit from the plurality of observation bits.

36. The communication device of claim 35,

the processing unit is further configured to determine multiple groups of first test data blocks from the data sequence according to the observation bits, where each group of first test data blocks in the multiple groups of first test data blocks includes at least one first test data block, and a position of each observation bit in the observation bits is a starting position of each group of first test data blocks in the multiple groups of first test data blocks; and selecting one observation bit from the observation bits as the alternative bit according to the characteristic values of the plurality of groups of first test data blocks.

37. The communication device of claim 36, wherein,

the processing unit is further configured to sequentially determine whether the characteristic value of each of the plurality of groups of first test data blocks satisfies an alternative condition until it is determined that the characteristic value of one group of first test data blocks satisfies the alternative condition; and taking the observation bit corresponding to the group of first test data blocks meeting the alternative condition as the alternative bit.

38. The communication device of claim 37,

39. The communication device of claim 36,

the processing unit is further configured to compare a characteristic value of each group of first test data blocks in the plurality of groups of first test data blocks, and use observation bits corresponding to a group of first test data blocks of which the characteristic value is an extremum as the candidate bits.

40. The communication device of claim 39,

41. The communication device according to any of claims 35-40,

the processing unit is further configured to select one bit from the data sequence every T bits as the observation bit, where T is an integer greater than zero; or,

the processing unit is further configured to select one bit from the data sequence at intervals of L × n + T bits as the observation bit, where L is the number of test data blocks at intervals, the length of each test data block is n bits, and L and T are integers greater than zero.

42. The communication device according to any of claims 35-40,

the processing unit is further configured to select, from every T modulation symbols in the data sequence, a start bit of a modulation symbol as the observation bit, where T is an integer greater than zero; or,

the processing unit is further configured to select, from each interval of L × m + T modulation symbols in the data sequence, a start bit of a modulation symbol as the observation bit, where L is the number of test data blocks at the interval, the length of the test data block is the m modulation symbols, and L and T are integers greater than zero.

43. The communication device according to any of claims 35-42, wherein the number of observation bits is P, wherein P is a positive integer, and wherein the length of the codeword is P bits.

44. The communication device of any one of claims 29-33, wherein,

45. The communication device according to any of claims 27-44,

the processing unit is further configured to perform step four: and in response to the data sequence being in an unlocked state, determining an updated synchronization position of the data sequence.

46. The communication device of claim 45,

the processing unit is further configured to re-execute the second step and the third step, and use the synchronization position determined by the re-executed third step as the updated synchronization position.

47. The communication device of claim 45 or 46,

the processing unit is further configured to divide a plurality of synchronization code words from the data sequence according to the synchronization position, where the synchronization position is a start position of the plurality of synchronization code words; and verifying the characteristic values of the plurality of synchronous code words, and determining the data sequence to be in the out-of-lock state when the verification fails.

48. The communication device of claim 47,

the processing unit is further configured to sequentially accumulate the characteristic values of each of the plurality of synchronization code words to obtain an accumulated value, and the verification fails until the accumulated value satisfies the lock losing condition.

49. The communication device of claim 48,

50. The communication device of claim 47,

the processing unit is further configured to add the characteristic values of all the synchronization code words in the plurality of synchronization code words to obtain a total value, and when the total value satisfies an out-of-lock condition, the verification fails.

51. The communication device of claim 50,

52. The communication device according to any of claims 27-51, wherein the data sequence is a linear block code.

53. A communication device, characterized in that the communication device comprises: a processor, a communication interface, and a memory operable to store program code, the processor being operable to invoke the program code in the memory to perform the method of any of claims 1-26.

54. A chip, characterized in that the chip comprises a memory for storing a computer program and a processor for calling and running the computer program from the memory for performing the method of any of claims 1-26.

55. A computer-readable storage medium, in which a computer program is stored which, when run on a processor, implements the method of any one of claims 1-26.

56. A network system, characterized in that the network system comprises a sending device and a receiving device, the receiving device being a communication device according to any one of claims 27-53.