CN114664841A

CN114664841A - 3D memory device and method of manufacturing the same

Info

Publication number: CN114664841A
Application number: CN202210223761.8A
Authority: CN
Inventors: 马闯; 郑晓芬; 郭振
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-09
Filing date: 2022-03-09
Publication date: 2022-06-24

Abstract

The present disclosure provides a 3D memory device and a method of manufacturing the same, the method of manufacturing including: forming a laminated structure having a plurality of steps on a substrate, including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked, surfaces of the plurality of steps exposing the respective sacrificial layers; forming conductive contact pads on the surfaces of the corresponding steps respectively, wherein the contact pads are separated from the side walls of the adjacent steps, and forming isolation layers on the laminated structure, wherein the isolation layers cover the contact pads; etching the sacrificial layers to form gaps; and forming a gate conductor layer in the gap, wherein the contact pad, the sacrificial layer and the gate conductor layer are made of different materials, and in the step of etching the plurality of sacrificial layers, the etching rate of the sacrificial layer is greater than that of the contact pad, the contact pad is exposed in the gap, and each contact pad is in contact with the corresponding gate conductor layer. According to the manufacturing method, the contact pad and the sacrificial layer are made of different materials, so that the difficulty in filling the gap with the gate conductor layer is reduced in the process of replacing the sacrificial layer with the gate conductor layer.

Description

3D memory device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of memory technologies, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The three-dimensional memory architecture can solve the density limitation of a planar memory, and for a three-dimensional nonvolatile memory (3D NAND), also called a 3D memory device, a laminated structure is formed by alternately stacking multiple gate conductor layers and insulating layers, the laminated structure comprises multiple steps, and the gate conductor layers coplanar with the surfaces of the steps are respectively electrically connected with different conductive channels. Typically, the thickness of the gate conductor layer is increased here by providing a contact pad at the step surface, which is formed together with the gate conductor layer. However, the yield of such three-dimensional memories is to be improved due to the structural characteristics and the process influence.

Disclosure of Invention

An object of the present disclosure is to provide an improved 3D memory device and a method for fabricating the same, which reduces difficulty in filling a gap with a gate conductor layer in a process of replacing a sacrificial layer with the gate conductor layer by providing a contact pad and the sacrificial layer with different materials.

According to an aspect of the present disclosure, there is provided a method of manufacturing a 3D memory device, including: forming a stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on a substrate, the stacked structure including a plurality of steps, surfaces of the plurality of steps exposing the respective sacrificial layers; forming conductive contact pads on the surfaces of the corresponding steps, wherein the contact pads are separated from the adjacent step side walls, and forming an isolation layer on the laminated structure, wherein the isolation layer covers the contact pads; etching the plurality of sacrificial layers to form gaps; forming a gate conductor layer in the void, each contact pad being in contact with a respective gate conductor layer; and forming a plurality of conductive channels in the isolation layer, wherein each contact pad is connected with the corresponding conductive channel, the contact pads are made of different materials from the sacrificial layer and the gate conductor layer, the etching rate of the sacrificial layer is greater than that of the contact pads in the step of etching the plurality of sacrificial layers, and the contact pads are reserved and exposed in the gaps.

Optionally, the step of forming conductive contact pads on the surfaces of the corresponding steps respectively includes: forming a buffer layer on the stacked structure, including a first portion covering a surface of the step and a second portion covering a sidewall of the step; modifying the buffer layer to make the first part and the second part of the buffer layer have different properties; and according to the modified property of the buffer layer, removing a second part of the buffer layer to separate the remained first part of the buffer layer from the step and serve as the contact pad.

Optionally, the step of modifying the buffer layer includes: doping the buffer layer, wherein a doping concentration of a first portion of the buffer layer is greater than a doping concentration of a second portion of the buffer layer.

Optionally, the doping the buffer layer includes: and synchronously doping the first part and the second part of the buffer layer from the upper part of the buffer layer along the direction vertical to the step surface.

Optionally, the step of removing the second portion of the buffer layer includes: and wet etching the buffer layer, and stopping the wet etching after removing the second part of the buffer layer, wherein the etching rate of the first part of the buffer layer is less than that of the second part of the buffer layer.

Optionally, the material of the buffer layer comprises polysilicon, and the doping impurities comprise boron and/or phosphorus.

Optionally, the buffer layer further includes a third portion of the sacrificial layer covering the top layer, and in the step of wet etching the buffer layer, the third portion of the buffer layer serves as a protection layer of the sacrificial layer of the top layer.

Optionally, the step of forming a plurality of conductive vias in the isolation layer comprises: etching the isolation layer to form a plurality of contact holes, wherein the contact holes extend from the surface of the isolation layer to the direction of the substrate; and forming respective said conductive channels in said plurality of contact holes, wherein the bottoms of said contact holes reach respective said contact pads and/or reach said gate conductor layer under and adjacent to respective said contact pads.

According to another aspect of the present disclosure, there is provided a 3D memory device including: a substrate; a stacked structure including a plurality of insulating layers and a plurality of gate conductor layers stacked alternately, the stacked structure including a plurality of steps, a part of surfaces of the plurality of gate conductor layers being coplanar with surfaces of the respective steps; a plurality of conductive contact pads respectively located on the surfaces of the corresponding steps and connected with the gate conductor layer; the isolation layer is positioned on the laminated structure and covers the contact pad; and a plurality of conductive vias passing through the isolation layer and connecting to corresponding contact pads, wherein the contact pads are made of a different material than the gate conductor layer.

Optionally, the material of the contact pad comprises polysilicon.

According to the 3D memory device and the manufacturing method thereof provided by the embodiment of the disclosure, the contact pad and the sacrificial layer are made of different materials, and in the process of etching the sacrificial layer to form the gap, the etching rate of the sacrificial layer is greater than that of the contact pad, so that the contact pad can be reserved, the width of the gap is basically consistent with the thickness of the original sacrificial layer, the width of the gap is uniform, and therefore when the grid conductor layer is formed in the gap, the grid conductor layer is more easily and uniformly filled in the gap, and the yield of the device is improved.

In the process of forming the contact pad, only three steps of depositing the buffer layer, modifying the buffer layer and removing the buffer layer covering the side wall of the step are needed, so that the process step of forming the contact pad is simplified, the manufacturing period is shortened, and the manufacturing cost is reduced.

The buffer layer is modified by using a doping process, the effect that different parts of the buffer layer have different properties can be achieved by only controlling the doping concentration of different parts in the buffer layer, and the control of the doping concentration is simpler, so that the process step of forming the contact pad is further simplified, the manufacturing period is shortened, and the manufacturing cost is reduced.

And synchronously doping the buffer layer covering the surface of the step and the buffer layer covering the side wall of the step, wherein the doping direction is vertical to the surface of the step. Since the buffer layer covering the side wall of the step is substantially perpendicular to the surface of the step, the contact area with the impurity is small. On the contrary, the buffer layer covering the surface of the step can contact more doping impurities, so that the effect of enabling different parts of the buffer layer to have different properties is achieved, and the parts of the buffer layer do not need to be doped respectively, thereby further simplifying the process steps of the contact pad, shortening the manufacturing period and reducing the manufacturing cost.

The buffer layer covering the step side wall is removed by adopting a wet etching process, compared with a dry etching process, the wet etching process cannot cause serious damage to the sacrificial layer below the buffer layer, and after the buffer layer covering the step side wall is removed, the sacrificial layer can be completely protected, so that the problem of disconnection caused by damage of the sacrificial layer cannot occur to the replaced grid conductor layer, and the yield of devices is further improved.

Because the buffer layer also covers the sacrificial layer on the top layer, in the step of wet etching the buffer layer, the buffer layer covering the top layer can protect the sacrificial layer on the top layer, and prevent the surface of the sacrificial layer on the top layer from being damaged due to a large amount of contact with an etchant, so that the replaced top gate conductor layer can not have the problems of conductive material loss and thinner thickness caused by the damage of the sacrificial layer on the top layer, and the yield of the device is further improved.

Accordingly, the 3D memory device and the method of manufacturing the same according to the embodiments of the present disclosure improve product yield and reliability.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 shows a perspective view of a 3D memory device.

Figure 3 shows a schematic diagram of a shorting defect between different gate conductor layers.

Fig. 4 illustrates a first structural diagram of a method of fabricating a 3D memory device according to a first embodiment of the present disclosure.

Fig. 5 illustrates a second structural schematic diagram of a 3D memory device manufacturing method according to a first embodiment of the present disclosure.

Fig. 6 illustrates a third structural view of a method of fabricating a 3D memory device according to a first embodiment of the present disclosure.

Fig. 7 illustrates a fourth structural diagram of a method of fabricating a 3D memory device according to a first embodiment of the present disclosure.

Fig. 8 illustrates a fifth structural view of a method of fabricating a 3D memory device according to a first embodiment of the present disclosure.

Fig. 9 illustrates a sixth structural view of a method of fabricating a 3D memory device according to a first embodiment of the present disclosure.

Fig. 10 shows a seventh structural schematic diagram of a 3D memory device manufacturing method of a first embodiment of the present disclosure.

Fig. 11 illustrates an eighth structural schematic diagram of a 3D memory device manufacturing method according to a first embodiment of the present disclosure.

Fig. 12 illustrates a schematic view of a sacrificial layer defect occurring in the method of manufacturing a 3D memory device according to the first embodiment of the present disclosure.

Fig. 13 illustrates a schematic diagram of a gate conductor layer defect occurring in the method of manufacturing the 3D memory device according to the first embodiment of the present disclosure.

Fig. 14 illustrates a landing tip defect diagram of a gate conductor layer occurring in the method of manufacturing a 3D memory device according to the first embodiment of the present disclosure.

Fig. 15a and 15b illustrate a first structural schematic diagram of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 16 illustrates a second structural diagram of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 17 illustrates a third structural view of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 18a and 18b illustrate a fourth structural schematic diagram of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 19a and 19b illustrate a fifth structural schematic diagram of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 20a and 20b illustrate a sixth structural view of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 21 illustrates a seventh structural diagram of a method of fabricating a 3D memory device according to a second embodiment of the present disclosure.

Fig. 22 illustrates an eighth structural schematic diagram of a 3D memory device manufacturing method according to a second embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

Numerous specific details of the present disclosure, such as structure, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be appreciated that the present disclosure is not so limited and that the number of memory cells in a memory cell string can be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a Bit Line (BL), and a second terminal is connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor (drain side selection transistor) Q1, memory transistors M1 to M4, and a second selection transistor (source side selection transistor) Q2. The Gate of the first select transistor Q1 is connected to a Drain select Gate line (SGD), also called a top Gate select line. The Gate of the second select transistor Q2 is connected to a Source select Gate line (SGS), also called a bottom Gate select line. The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.

As shown in fig. 1b, the select transistors Q1 and Q2 of the memory cell string 100 include a gate conductor layer 121 at the bottom and a gate-to-body layer 121 at the bottom, respectively, and the memory transistors M1 to M4 include a gate conductor layer 121 in the middle, respectively. The gate conductor layers 121 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A gate dielectric layer 114 is sandwiched between the gate conductor layer 121 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunneling dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layer 121 is composed of a conductive material such as tungsten, copper, polysilicon, graphite, or the like. The channel layer 111 is used to provide channel regions of the control select transistor and the control transistor, and the doping type of the channel layer 111 is the same as the type of the select transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4 may be formed separately in steps independent of each other. In the channel column 110, the semiconductor layers of the selection transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In some other embodiments, the selection transistor Q1 may also be fabricated as the memory transistors M1 to M4, specifically, on the upper portion of the channel pillar 110, the tunneling dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 are sandwiched between the gate conductor layer 121 and the channel layer 111, so as to form the selection transistor Q1. Since the selection transistor Q1 has the same structure as the memory transistors M1 to M4, the formation process of the channel column can be simplified.

Fig. 2 shows a perspective view of a 3D memory device. Where X, Y, Z denote the length direction, width direction, and height direction of the 3D memory device, respectively, and the respective insulating layers and dummy gate conductor layers in the 3D memory device are not shown in fig. 2 for clarity.

The 3D memory device shown in this embodiment includes 4 x 4 and 16 memory cell strings 100 in total, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is understood that the present disclosure is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layer 121. The gate conductor layers 121 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. The channel pillars 110 penetrate through the gate stack structure and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 101.

The gate conductor layer 121 of the drain side selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 107. The gate lines of the plurality of channel pillars 110 in the same row are commonly connected to the same drain select gate line (i.e., one of the drain select gate lines SGD1 through SGD 4).

The gate conductor layers 121 of the memory transistors M1 and M4 are integrally connected to each other at different levels. If the gate conductor layers 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 107, the gate lines of the same layer reach the interconnection layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductors of the source side select transistors Q2 are connected in one piece. If the bottom gate conductor layer 121 of the source side selection crystal Q2 is divided into different gate lines by the gate line slit 107, the gate lines reach the interconnect layer 132 via respective conductive channels 131 to be interconnected with each other, and then are connected to the same source selection line SGS via the conductive channel 133. The connection between the conductive channel 131 and the gate conductor layer 121 will be described in detail with reference to fig. 3 to 22, wherein fig. 3 to 14 can be regarded as partial sectional views taken along line AA in fig. 2, and for clarity, only the specific structure corresponding to the step region is shown in the sectional view taken along line AA in fig. 2, and the specific structure of the core region corresponding to the channel pillar 110 is not shown.

As shown in fig. 3, in the prior art, a gate stack structure 120 is located on a substrate 101, the gate stack structure 120 includes a plurality of layers of alternately stacked insulating layers 123 and gate conductor layers 121, and an isolation layer 103 covers the gate stack structure 120. At each step, it is desirable that the conductive via 131 is connected only to the gate conductor layer 121 corresponding to the step, however, due to the limitation of the etching process, there arises a problem that the conductive via 131 is connected to the gate conductor layer 121 of another step below through the insulating layer 123 of the step (such as a structure in a dotted frame). The short circuit between different gate conductor layers 121 may cause control errors of the memory cells, resulting in memory failure.

To improve the shorting problem between different gate conductor layers, increasing the thickness of the landing tip (landing) of the conductive via 131 in the gate conductor layer 121 may be used. As shown in fig. 4, an insulating stacked structure 102 comprising a plurality of insulating layers 123 and sacrificial layers 124 stacked alternately is formed on a substrate 101, wherein the material of the insulating layers 123 includes, but is not limited to, silicon oxide, and the material of the sacrificial layers 124 includes, but is not limited to, silicon nitride. An etching process is then used to form a plurality of steps on the insulating stacked structure 102, and a surface of each step is a sacrificial layer 124. A thickening layer 125 is then deposited overlying the step surface and sidewalls and the top sacrificial layer 124, the thickening layer 125 being of the same material as the sacrificial layer 124. A mask layer 108 is then formed overlying the thickening layer 125, the material of the mask layer 108 including, but not limited to, carbon. Further, the deposited mask layer 108 is sequentially subjected to two process steps of calibration (cure) and trimming (trim) to remove a portion of the mask layer 108, leaving the mask layer 108 on the surface of the thickening layer 125 as a hard mask, as shown in fig. 5. The sidewall of the step and the thickening layer 125 in the core region are exposed, and the hard mask on the adjacent step is separated.

Further, the exposed thickening layer 125 is removed using a dry etching process, and then the hard mask is removed using a wet etching process, as shown in fig. 6. Wherein the thickening layer 125 remaining at the step surface is separated from the adjacent step sidewalls.

Further, an isolation layer 103 is formed on the insulating stack 102, the isolation layer 103 covering the thickening layer 125, as shown in fig. 7, wherein the material of the isolation layer 103 includes, but is not limited to, silicon oxide. After the isolation layer 103 is formed, a plurality of channel pillars 110 penetrating the insulation stack 102 are continuously formed in the core region.

Further, the sacrificial layer 124 and the thickening layer 125 are removed by a wet etching process, so that a gap 104 is formed between the isolation layer 103 and the insulating layer 123 and between adjacent insulating layers 123, as shown in fig. 8. Wherein the space at the end of the void 104 corresponding to the thickening layer 125 is larger.

Further, the conductive material is filled in the gap 104 to form a gate conductor layer 121, as shown in fig. 9. The gate conductor layer 121 at the end of the gap 104 is thicker and serves as a landing 121 a.

Further, the isolation layer 103 is dry-etched in the step region, forming a contact hole 105, as shown in fig. 10. The bottom of the contact hole 105 is located on the landing tip 121a of the gate conductor layer 121.

Further, a conductive material is filled in the contact hole 105 to form a conductive channel 131, as shown in fig. 11.

In the above solution, since the landing tips 121a of the gate conductor layers 121 are thickened (the thickened portions are equivalent to contact pads), the etching process of the contact holes 105 is easier to control, so that the etching does not pass through the insulating layer 123 any more, thereby improving the problem of short between different gate conductor layers 121. However, the above solution brings new problems, as shown in fig. 12, in the process of removing part of the thickening layer 125 by using the dry etching process, damage is easily caused to the sacrificial layer 124, so that the sacrificial layer 124 forms the groove 11, and the thickness of the part of the sacrificial layer 124 is reduced. And during the process of removing the hard mask by using the wet etching process, the top sacrificial layer 124 may be in large contact with the etchant to form the recess 12, and the thickness of the portion of the sacrificial layer 124 is also reduced. In this case, the gate conductor layer 121 is also formed to be thin at the defective portion of the corresponding sacrificial layer 124, as shown in fig. 13, thereby affecting the reliability of the device.

In addition, as the integration of the 3D memory device is further improved, the landing tips 121a of the gate conductor layer 121 need to be increased, which is achieved by increasing the thickness of the thickening layer 125, but for the step of depositing the conductive material in the voids 104, the thicker the thickening layer 125 is, the more difficult it is to fill the end portions 104a of the voids 104 completely, as shown in fig. 14, which means that the thickness of the landing tips 121a of the gate conductor layer 121 cannot meet the requirement.

In order to improve the above-mentioned problems, a second embodiment of the present disclosure provides an improved 3D memory device and a method of manufacturing the same. Fig. 15a, 15b, 16, 17, 18a, 19b, 20a, 21 and 22 may be regarded as partial sectional views taken along line AA in fig. 2, and for clarity, only the specific structure corresponding to the step region is shown in the sectional views taken along line AA in fig. 2, and the specific structure of the core region corresponding to the channel pillar 110 is not shown; fig. 18b, 19a and 20b can be seen as partial cross-sectional views taken along the line BB in fig. 2.

As shown in fig. 15a, an insulating stacked structure 102 is formed on a substrate 101, and then a plurality of steps 21 are formed on a step region 20 by removing a part of the insulating stacked structure 102. The substrate 101 may be a semiconductor substrate capable of forming a circuit, such as a single crystal silicon substrate; the memory array can also be used as a support layer, and can be removed in a subsequent process, and then the memory array is bonded to other semiconductor layers through a bonding process. The material of the substrate 101 that can be removed may be a semiconductor material, an insulating material, or the like.

In the present embodiment, the insulating stacked structure 102 is composed of a plurality of insulating layers 123 and a plurality of sacrificial layers 124 which are alternately stacked. The surface of each step 21 exposes a respective sacrificial layer 124. The number of the insulating layer 123 and the sacrificial layer 124 corresponding to each step 21 can be set by those skilled in the art as needed, for example, each step 21 corresponds to only one insulating layer 123 and one sacrificial layer 124. Or the number of layers of the insulating layer 123 and the sacrificial layer 124 is increased on the top-most step 21 and the bottom-most step 21, as shown in fig. 15b, the top-most step 21 and the bottom-most step 21 correspond to the two insulating layers 123 and the two sacrificial layers 124 which are alternately stacked, respectively, wherein the sacrificial layer 124 exposed on the surface of the step 21 is replaced with the gate conductor layer 121, and the sacrificial layer 124 not exposed on the surface of the step 21 is replaced with the dummy gate conductor layer (dummy layer). The sacrificial layer 124 has a high etching selectivity with respect to the insulating layer 123, so that the sacrificial layer 124 is replaced with the gate conductor layer 121 in a subsequent process, for example, the material of the insulating layer 123 includes, but is not limited to, silicon oxide, and the material of the sacrificial layer 124 includes, but is not limited to, silicon nitride.

Further, a buffer layer 140 is formed on the stacked-layer structure 102, as shown in fig. 16.

In this step, buffer Layer 140 is formed, for example, using an Atomic Layer Deposition (ALD) process, such that buffer Layer 140 conforms to the shape of steps 21, buffer Layer 140 covers the surface and sidewalls of a plurality of steps 21, contacts corresponding sacrificial Layer 124 at the surface of each step 21, and buffer Layer 140 also covers sacrificial Layer 124 at the top Layer.

In the present embodiment, buffer layer 140 includes a first portion 140a covering the surface of step 21, a second portion 140b covering the sidewall of step 21, and a third portion 140c of sacrificial layer 124 covering the top layer. Buffer layer 140 has a high etching selectivity with respect to sacrificial layer 124 and insulating layer 123, such that the etching rate of buffer layer 140 is greater than the etching rates of sacrificial layer 124 and insulating layer 123 in subsequent steps of removing portions of buffer layer 140. Buffer layer 140 material includes, but is not limited to, polysilicon.

After buffer layer 140 is formed, buffer layer 140 needs to be modified at least such that first portion 140a and second portion 140b of the buffer layer have different properties. The modification is, for example, doping of the buffer layer 140. In some embodiments, buffer layer 140 is polysilicon and the dopant impurities include, but are not limited to, boron and/or phosphorus. For example, by doping the buffer layer 140 in the direction of the arrow in fig. 16, since the doping direction is perpendicular to the surface of the step 21, the doping concentration of the buffer layer 140 covering the surface of the step 21 and the top sacrificial layer 124 is higher, and the doping concentration of the buffer layer 140 covering the sidewall of the step 21 is lower.

Further, the second portion 140b of the buffer layer is selectively removed according to the properties of the modified buffer layer 140, as shown in fig. 17.

In this step, for example, the buffer layer 140 is wet-etched, and the wet etching is stopped after removing the buffer layer 140 covering the sidewalls of the steps 21, while the buffer layer 140 that remains the surface of the steps 21 is used as the contact pad 141, and the buffer layer 140 that covers the sacrificial layer 124 of the top layer is also left, wherein each contact pad 141 is separated from the sidewall of the adjacent step 21.

In this embodiment, since the doping concentration of the buffer layer 140 covering the sidewall of the step 21 is low, in the wet etching process, an alkaline etchant is used, and the etching rate of the buffer layer 140 covering the sidewall of the step 21 is faster. The principle is that polysilicon doped with boron and/or phosphorus forms silicate like BPSG, resulting in a reduced polysilicon etch rate with alkaline etchants. The buffer layer 140 covering the sidewall of the step 21 is approximately vertical, and the dopant amount therein is small, so that the buffer layer 140 covering the sidewall of the step 21 is etched away more quickly.

Further, an isolation layer 103 is formed on the insulation stack structure 102, and then a channel pillar 110 penetrating through the buffer layer 140 and the insulation stack 102 is formed in the core region, as shown in fig. 18a and 18b, wherein the structure of the channel pillar 110 can be described with reference to fig. 1b, and is not repeated herein. The isolation layer 103 covers the contact pad 141, the material of the isolation layer 103 includes but is not limited to an insulating material such as silicon oxide, and the isolation layer 103 has a high etching selectivity with respect to the sacrificial layer 124.

Further, the plurality of sacrificial layers 124 are replaced with a plurality of gate conductor layers 121.

In this step, the insulating stacked structure 102 is first subjected to anisotropic etching, which may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation, for example. For example, by controlling the etching time, the etching is stopped to form a plurality of gate line gaps 107 near the substrate 101 as shown in fig. 18 b.

The sacrificial layers 124 are then removed through the gate line gaps 107, for example, by a wet etching process, to form voids 104 between the contact pads 141 and the insulating layer 123, the third portion 140c of the buffer layer, and the adjacent insulating layer 123, as shown in fig. 19a and 19 b.

Then filling the gate gaps 107 and the gaps 104 with a conductive material, wherein the conductive material includes but is not limited to metal tungsten; finally, a back etching process is performed to re-form the gate line gap 107, and the conductive material remaining in 104 forms the gate conductor layer 121, as shown in fig. 20a and 20 b. In the subsequent step, the gate line gap 107 may be filled with an insulating material, or a material for forming a conductive channel.

In this step, the plurality of sacrificial layers 124 replace the gate conductor layer 121, and the gate conductor layer 121 and the insulating layer 123 form the gate stack structure 120.

Further, the isolation layer 103 is etched to form a contact hole 105, as shown in fig. 21.

In this step, the insulating stacked structure 102 is first subjected to anisotropic etching, which may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation, for example. For example, by controlling the etching time, the plurality of contact holes 105 are exposed to the contact pads 141 and/or the gate conductor layer 121 is exposed through the contact pads 141.

Further, the conductive paths 131 are formed in the contact holes, so that the conductive paths 131 are electrically connected to the corresponding gate conductor layers 121, as shown in fig. 22.

The buffer layer is modified by using a doping process, the effect that different parts of the buffer layer have different properties can be achieved only by controlling the doping concentration of different parts in the buffer layer, and the control of the doping concentration is simpler, so that the process step of forming the contact pad is further simplified, the manufacturing period is shortened, and the manufacturing cost is reduced.

Therefore, the 3D memory device and the method of manufacturing the same according to the embodiments of the present disclosure improve product yield and reliability.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, the person skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A method of manufacturing a 3D memory device, comprising:

forming a stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on a substrate, the stacked structure including a plurality of steps, surfaces of the plurality of steps exposing the respective sacrificial layers;

forming an electrically conductive contact pad on a surface of each of the steps, the contact pad being spaced apart from an adjacent sidewall of the step,

forming an isolation layer on the stacked structure, the isolation layer covering the contact pad;

etching the plurality of sacrificial layers to form gaps;

forming a gate conductor layer in the void, each contact pad being in contact with a respective gate conductor layer; and

forming a plurality of conductive vias in the isolation layer, each of the contact pads being connected to a respective one of the conductive vias,

the contact pad, the sacrificial layer and the gate conductor layer are made of different materials, in the step of etching the sacrificial layers, the etching rate of the sacrificial layer is greater than that of the contact pad, and the contact pad is reserved and exposed in the gap.

2. The manufacturing method according to claim 1, wherein the step of forming the conductive contact pads on the surfaces of the respective steps respectively comprises:

forming a buffer layer on the stacked structure, including a first portion covering a surface of the step and a second portion covering a sidewall of the step;

modifying the buffer layer to make a first portion and a second portion of the buffer layer have different properties; and

according to the modified property of the buffer layer, removing the second part of the buffer layer to make the first part of the buffer layer separated from the step and used as the contact pad.

3. The manufacturing method according to claim 2, wherein the step of modifying the buffer layer includes: the buffer layer is doped with a dopant,

wherein a doping concentration of the first portion of the buffer layer is greater than a doping concentration of the second portion of the buffer layer.

4. The manufacturing method according to claim 3, wherein the step of doping the buffer layer comprises: and synchronously doping the first part and the second part of the buffer layer from the upper part of the buffer layer along the direction vertical to the step surface.

5. The manufacturing method of claim 3, wherein the removing the second portion of the buffer layer comprises:

wet etching the buffer layer and stopping the wet etching after removing the second portion of the buffer layer,

wherein an etch rate of the first portion of the buffer layer is less than an etch rate of the second portion of the buffer layer.

6. The manufacturing method according to claim 5, wherein the material of the buffer layer comprises polysilicon, and the doping impurity comprises boron and/or phosphorus.

7. The manufacturing method of claim 5, wherein the buffer layer further comprises a third portion of the sacrificial layer overlying the top layer,

and in the step of wet etching the buffer layer, the third part of the buffer layer is used as a protective layer of the sacrificial layer on the top layer.

8. The manufacturing method according to any one of claims 1 to 7, wherein the step of forming a plurality of conductive paths in the separation layer includes:

etching the isolation layer to form a plurality of contact holes, wherein the contact holes extend from the surface of the isolation layer to the direction of the substrate; and

forming respective said conductive vias in said plurality of contact holes,

wherein the bottom of the contact hole reaches the corresponding contact pad and/or reaches the gate conductor layer under and adjacent to the contact pad.

9. A 3D memory device comprising:

a substrate;

a stacked structure including a plurality of insulating layers and a plurality of gate conductor layers stacked alternately, the stacked structure including a plurality of steps, a part of surfaces of the plurality of gate conductor layers being coplanar with surfaces of the respective steps;

a plurality of conductive contact pads which are respectively positioned on the surfaces of the corresponding steps and connected with the grid conductor layer;

the isolating layer is positioned on the laminated structure and covers the contact pad; and

a plurality of conductive vias connected to respective ones of the contact pads through the isolation layer,

wherein the contact pad is of a different material than the gate conductor layer.

10. The 3D memory device of claim 9, wherein the material of the contact pad comprises polysilicon.