CN114664793B - Chip side surface interconnection packaging structure and manufacturing method thereof - Google Patents
Chip side surface interconnection packaging structure and manufacturing method thereof Download PDFInfo
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- CN114664793B CN114664793B CN202210565813.XA CN202210565813A CN114664793B CN 114664793 B CN114664793 B CN 114664793B CN 202210565813 A CN202210565813 A CN 202210565813A CN 114664793 B CN114664793 B CN 114664793B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000005022 packaging material Substances 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 abstract description 2
- 238000000465 moulding Methods 0.000 description 11
- WWTBZEKOSBFBEM-SPWPXUSOSA-N (2s)-2-[[2-benzyl-3-[hydroxy-[(1r)-2-phenyl-1-(phenylmethoxycarbonylamino)ethyl]phosphoryl]propanoyl]amino]-3-(1h-indol-3-yl)propanoic acid Chemical compound N([C@@H](CC=1C2=CC=CC=C2NC=1)C(=O)O)C(=O)C(CP(O)(=O)[C@H](CC=1C=CC=CC=1)NC(=O)OCC=1C=CC=CC=1)CC1=CC=CC=C1 WWTBZEKOSBFBEM-SPWPXUSOSA-N 0.000 description 9
- 229940126208 compound 22 Drugs 0.000 description 8
- TVTJUIAKQFIXCE-HUKYDQBMSA-N 2-amino-9-[(2R,3S,4S,5R)-4-fluoro-3-hydroxy-5-(hydroxymethyl)oxolan-2-yl]-7-prop-2-ynyl-1H-purine-6,8-dione Chemical compound NC=1NC(C=2N(C(N(C=2N=1)[C@@H]1O[C@@H]([C@H]([C@H]1O)F)CO)=O)CC#C)=O TVTJUIAKQFIXCE-HUKYDQBMSA-N 0.000 description 6
- 229940125851 compound 27 Drugs 0.000 description 6
- 239000012778 molding material Substances 0.000 description 5
- 238000010137 moulding (plastic) Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a chip side surface interconnection packaging structure and a manufacturing method thereof. The invention realizes the lateral interconnection of the bumps by utilizing the close contact between the packaging bodies with the bumps exposed at the side surfaces, realizes the direct electrical interconnection between the two packaging bodies by utilizing the laser ablation, shortens the electrical connection path and can save the manufacturing cost. And meanwhile, six sides of the plastic package are carried out by utilizing the first plastic package material and the second plastic package material, so that the reliability of the sealing body is ensured.
Description
Technical Field
The invention relates to the field of semiconductor chip packaging test, in particular to a chip side surface interconnection packaging structure and a manufacturing method thereof.
Background
The multiple chips are combined to form a module with a specific function, so that the terminal equipment is assembled and formed. The direction of multi-chip combination can be to form a single package by using a subsequent process, but for chips of different manufacturers, the chips can be individually packaged to form a package, in order to form a specific function, the different packages need to be secondarily packaged and then rewired, the process is complex, and the interconnection path between the chips is long.
Disclosure of Invention
Based on the above problem, the present invention provides a method for manufacturing a chip side interconnection package structure, which comprises the following steps:
(1) providing a first package and a second package; wherein the first top surface of the first package comprises first bumps exposed from the first side surface of the first package; the second top surface of the second package comprises second bumps exposed from the second side surface of the second package;
(2) providing a mold, wherein the mold is provided with a first surface, the first surface is provided with a groove, and a first plastic packaging material is partially filled in the groove;
(3) attaching the first side surface of the first packaging piece and the second side surface of the second packaging piece by using a clamp to form a press-fit body, wherein the first top surface and the second top surface are coplanar, the first bump is tightly attached to the side surface of the second bump, and the bottom of the press-fit body is pressed into the first plastic packaging material;
(4) solidifying the first plastic packaging material, and removing the clamp;
(5) laser ablating the first and second bumps such that the first and second bumps are eutectic together to effect an electrical interconnection.
According to the embodiment of the present invention, in the step (3), when the bottom of the press-fit body is pressed into the first plastic molding material, the end of the jig is inserted into the first plastic molding material; and in the step (4), when the clamp is removed, forming a recess located on the periphery of the pressing body in the first plastic package material.
According to the embodiment of the invention, the method further comprises the step (6): and forming a solder ball on the first bump and the second bump, wherein the top end of the solder ball is higher than the first surface of the die.
According to an embodiment of the present invention, further comprising step (7): and filling a second plastic packaging material in the groove, wherein the top surface of the second plastic packaging material is coplanar with the first surface of the mold, so that the solder balls are exposed from the top surface of the second plastic packaging material, and the second plastic packaging material fills the recess.
According to an embodiment of the present invention, further comprising step (8): and curing the second plastic packaging material, and removing the mold to obtain the final side surface interconnection packaging structure.
According to an embodiment of the present invention, the first package and the second package each include a main body portion and an electrical interconnection structure on the main body portion, the main body portion of the first package is different in thickness from the main body portion of the second package, and the electrical interconnection structure of the first package is the same in thickness as the electrical interconnection structure of the second package.
According to an embodiment of the present invention, the body portion includes a sealing layer and a chip embedded in the sealing layer, and the electrical interconnection structure includes a wiring layer on the body portion, a plurality of bumps on the wiring layer, and a passivation layer covering the plurality of bumps.
The invention also provides a chip side interconnection packaging structure, which is formed according to the manufacturing method of the chip side interconnection packaging structure and specifically comprises the following steps:
the package structure comprises a first package and a second package, wherein a first top surface of the first package comprises a first bump, and the first bump is exposed from a first side surface of the first package; the second top surface of the second package comprises second bumps exposed from the second side surface of the second package; the first side face of the first packaging piece and the second side face of the second packaging piece are jointed to form a pressing body, wherein the first top face and the second top face are coplanar, the first bump is tightly attached to the side face of the second bump, and the first bump and the second bump are ablated by laser so that the first bump and the second bump are fused together to realize electrical interconnection;
a first plastic package material sealing a lower half portion of the press-bonded body;
solder balls bonded to the first bumps and the second bumps;
and the second plastic packaging material is used for sealing the upper half part of the pressure combination body, wherein the solder balls are exposed out of the top surface of the second plastic packaging material.
According to an embodiment of the present invention, the first package and the second package each include a main body portion and an electrical interconnection structure on the main body portion, the main body portion of the first package is different in thickness from the main body portion of the second package, and the electrical interconnection structure of the first package is the same in thickness as the electrical interconnection structure of the second package.
According to an embodiment of the present invention, the body portion includes a sealing layer and a chip embedded in the sealing layer, and the electrical interconnection structure includes a wiring layer on the body portion, a plurality of bumps on the wiring layer, and a passivation layer covering the plurality of bumps.
The invention has the following advantages: the packaging bodies with the protruding blocks exposed from the side surfaces are tightly attached to each other, so that the lateral interconnection of the protruding blocks is realized, laser is used for ablation, and the direct electrical interconnection between the two packaging bodies is realized, so that the electrical connection path is shortened, and the manufacturing cost can be saved. And meanwhile, six-face plastic package is performed by utilizing the first plastic package material and the second plastic package material, so that the reliability of the sealing body is ensured.
Drawings
FIG. 1 is a top view of the package of the present invention, not singulated;
FIG. 2 is a cross-sectional view taken along line A1A2 of FIG. 1;
FIG. 3 is a cross-sectional view of the package of the present invention after singulation;
FIGS. 4-7 are schematic diagrams illustrating a method of fabricating a chip side interconnect package structure according to the present invention;
a body portion-10; a chip-11; a pad-12; sealing layer-13; a wiring layer 14; a passivation layer-15; bumps-16, 17, 18; mold-20; a groove-21; a first mold compound 22; -23; a pit-24; -25 recesses; solder ball-26; and a second molding compound-27.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Embodiment of the invention referring first to fig. 1-3, the manufacturing method of the chip side interconnection package structure of the invention first includes forming a package structure, which may specifically refer to fig. 3, including a main body portion 10 and an electrical interconnection structure on the main body portion 10, where the main body portion includes a sealing layer 13 and a chip 11 in the sealing layer 13, and the chip 11 is covered by the sealing layer 13 at least on the side of the chip 11, so that an active surface of the chip 11 having a pad 12 is exposed.
The chip 11 and the encapsulation layer 13 are covered by an electrical interconnect structure comprising a wiring layer 14 extending over the active face of the chip 11, the wiring layer 14 being formed as a fan-out structure. At least one of the wires in the wiring layer 14 extends to the side edge of the package, and a bump 18 is disposed on the wire, the side of the bump 18 being disposed flush with the side of the package. In addition, other bumps 16 are included, and referring to fig. 1 and 2, the bumps 16 are formed on other wiring layers, and the side surfaces thereof are completely wrapped by the passivation layer 15 without being exposed. Wherein the tops of the bumps 16 and 18 are arranged coplanar with the passivation layer 15.
The package may be formed by a conventional semiconductor packaging method, specifically, the plurality of chips 11 may be fixed on the carrier plate in an active-surface-up manner, and then the plurality of chips 11 are wrapped by a plastic package material to form the sealing layer 13, so that the active surfaces of the plurality of chips 11 are exposed on the upper surface of the sealing layer 13. Next, a wiring layer 14 is deposited on the encapsulation layer 13, said wiring layer 14 comprising a wiring which is connected from a pad of a certain chip to a pad of an adjacent chip, i.e. which crosses a dicing lane C between the chips (as shown in fig. 1 or 2). In addition, the routing layer 14 also includes other fan-out routing that does not cross any dicing streets.
Then, a plurality of bumps 16, 17 are formed on the wiring layer 14, wherein the size of the bump 17 is large, which crosses the dicing street C. Wherein the plurality of bumps 16, 17 may be solder. Finally, a passivation layer 15 is formed, wherein the plurality of bumps 16, 17 are laterally surrounded by the passivation layer 15. Wherein the tops of the plurality of bumps 16 and 17 are disposed coplanar with the passivation layer 15. To this end, a structure to be cut as in fig. 1 or 2 is obtained.
The structure is cut along the cutting path C to obtain a singulated package, as shown in fig. 3. When cutting, the bump 17 is cut into two parts to obtain a bump 18 with exposed side surfaces.
Furthermore, the invention provides a manufacturing method of the chip side surface interconnection packaging structure in order to form the multi-chip combined packaging structure. First, forming a first package and a second package by the above package manufacturing method, wherein a first top surface of the first package includes a first bump exposed from a first side surface of the first package; the second top surface of the second package includes second bumps exposed from the second side surface of the second package.
The body portion of the first package is different in thickness from the body portion of the second package, but the electrical interconnect structure of the first package is the same thickness as the electrical interconnect structure of the second package. Thereby making the first and second packages have different thicknesses.
Referring then to fig. 4, a mold 20 is provided, the mold 20 having a first surface with a recess 21 therein. The mold 20 may be made of stainless steel or a ceramic material, and a release layer (not shown) is disposed on an inner wall of the groove 21 and is partially filled with a first molding compound 22, where the first molding compound 22 may be a thermosetting resin material. The amount of this first mold compound 22 is controllable and its volume should not be more than half the volume of the recess 21.
Then, a clamp 23 is used to attach the first side surface of the first package and the second side surface of the second package to form a press-fit body, wherein the first top surface and the second top surface are coplanar, and the first bump is closely attached to the side surface of the second bump.
And pressing the bottom of the press-fit body into the first plastic package material 22, wherein a gap is reserved between the press-fit body and the side wall of the groove, so that the first plastic package material 22 flows in the gap to at least partially package the side surface of the press-fit body. Meanwhile, the end of the clamp 23 is inserted into the first molding compound 22. The top surface of the press body is slightly higher than the upper surface of the mold 20.
Further, the first molding compound 22 is thermally cured, the clamp 23 is removed, and a recess 25 located at the periphery of the compression body is formed in the first molding compound 22, see fig. 5. The recess 25 surrounds the periphery of the press-fit body, and the recess 25 can increase the path for water vapor to enter when a second plastic package material is formed subsequently, so that the sealing reliability is ensured.
The first bump and the second bump are locally ablated with a laser such that the first bump and the second bump are eutectic together to effect an electrical interconnection. The laser ablation may cause a depression 24 to be formed in the upper surface of the eutectic formed by the first bump and the second bump. The dimples 24 may be used to carry solder balls 26, as shown in fig. 6, with a plurality of solder balls 26 being formed simultaneously over bumps 16 and 18. The top ends of the solder balls 26 are higher than the first surface of the mold 20.
And filling a second plastic package material 27 in the groove 21 of the mold 20 and curing, wherein the second plastic package material 27 wraps the lower half portions of the solder balls 26, so that the solder balls 26 are exposed. The second molding compound 27 and the first molding compound 22 form a six-sided encapsulation structure, and a portion of the second molding compound 27 is filled in the recess 25 to ensure sealability. The first mold compound 22 and the second mold compound 27 may be the same material or different materials.
Finally, the mold 20 is removed to obtain a final chip side interconnect package structure, as shown in fig. 7, which specifically includes:
a first package and a second package, wherein a first top surface of the first package includes a first bump exposed from a first side surface of the first package; the second top surface of the second package comprises second bumps exposed from the second side surface of the second package; the first side face of the first packaging piece and the second side face of the second packaging piece are jointed to form a pressing body, wherein the first top face and the second top face are coplanar, the first bump is tightly attached to the side face of the second bump, and the first bump and the second bump are ablated by laser so that the first bump and the second bump are fused together to realize electrical interconnection; a first molding material 22 sealing a lower half portion of the compression bonded body; solder balls 26 bonded to the first bumps and the second bumps; and a second molding compound 27 sealing an upper half portion of the bonded body, wherein the solder balls are exposed from a top surface of the second molding compound 27.
The first packaging piece and the second packaging piece respectively comprise a main body part and an electric interconnection structure on the main body part, the thickness of the main body part of the first packaging piece is different from that of the main body part of the second packaging piece, and the thickness of the electric interconnection structure of the first packaging piece is the same as that of the electric interconnection structure of the second packaging piece.
Wherein the body portion includes a sealing layer and a chip embedded in the sealing layer, and the electrical interconnect structure includes a wiring layer on the body portion, a plurality of bumps on the wiring layer, and a passivation layer covering the plurality of bumps.
A recess 25 located at the periphery of the pressing body is formed in the first plastic molding material 22, and the recess 25 is filled with a second plastic molding material 27.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to another example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.
Claims (6)
1. A manufacturing method of a chip side interconnection packaging structure is characterized by comprising the following steps:
(1) providing a first package and a second package; wherein the first top surface of the first package comprises first bumps exposed from the first side surface of the first package; the second top surface of the second package comprises second bumps exposed from the second side surface of the second package;
(2) providing a mold, wherein the mold is provided with a first surface, the first surface is provided with a groove, and a first plastic packaging material is partially filled in the groove;
(3) attaching the first side surface of the first packaging piece and the second side surface of the second packaging piece by using a clamp to form a press-fit body, wherein the first top surface and the second top surface are coplanar, the first bump is tightly attached to the side surface of the second bump, the bottom of the press-fit body is pressed into the first plastic packaging material, and when the bottom of the press-fit body is pressed into the first plastic packaging material, the end part of the clamp is inserted into the first plastic packaging material;
(4) solidifying the first plastic packaging material, removing the clamp, and forming a recess positioned at the periphery of the pressing body in the first plastic packaging material when the clamp is removed;
(5) laser ablating the first bump and the second bump such that the first bump and the second bump are eutectic together to effect an electrical interconnection;
(6) forming solder balls on the first bump and the second bump, wherein the top ends of the solder balls are higher than the first surface of the die;
(7) filling a second plastic package material in the groove, wherein the top surface of the second plastic package material is coplanar with the first surface of the mold, so that the solder balls are exposed from the top surface of the second plastic package material, and the second plastic package material fills the recess;
(8) and curing the second plastic packaging material, and removing the mold to obtain the final side surface interconnection packaging structure.
2. The method of manufacturing a chip side interconnect package structure of claim 1, wherein: the first package and the second package each include a main body portion and an electrical interconnect structure on the main body portion, the main body portion of the first package is different in thickness from the main body portion of the second package, and the electrical interconnect structure of the first package is the same in thickness as the electrical interconnect structure of the second package.
3. The method of manufacturing a chip side interconnect package structure of claim 2, wherein: the body portion includes a sealing layer and a chip embedded in the sealing layer, and the electrical interconnect structure includes a wiring layer on the body portion, a plurality of bumps on the wiring layer, and a passivation layer covering the plurality of bumps.
4. A chip side interconnection package structure formed according to the method for manufacturing a chip side interconnection package structure of any one of claims 1 to 3, the chip side interconnection package structure comprising:
the package structure comprises a first package and a second package, wherein a first top surface of the first package comprises a first bump, and the first bump is exposed from a first side surface of the first package; the second top surface of the second package comprises second bumps exposed from the second side surface of the second package; the first side face of the first packaging piece and the second side face of the second packaging piece are jointed to form a pressing body, wherein the first top face and the second top face are coplanar, the first bump is tightly attached to the side face of the second bump, and the first bump and the second bump are ablated by laser so that the first bump and the second bump are fused together to realize electrical interconnection;
a first plastic package material sealing a lower half portion of the press-bonded body;
solder balls bonded to the first bumps and the second bumps; and
and the second plastic packaging material is used for sealing the upper half part of the pressure combination body, wherein the solder balls are exposed out of the top surface of the second plastic packaging material.
5. The chip side interconnect package structure of claim 4, wherein: the first package and the second package each include a main body portion and an electrical interconnect structure on the main body portion, the main body portion of the first package is different in thickness from the main body portion of the second package, and the electrical interconnect structure of the first package is the same in thickness as the electrical interconnect structure of the second package.
6. The chip side interconnect package structure of claim 5, wherein: the body portion includes a sealing layer and a chip embedded in the sealing layer, and the electrical interconnect structure includes a wiring layer on the body portion, a plurality of bumps on the wiring layer, and a passivation layer covering the plurality of bumps.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159225A (en) * | 2003-11-28 | 2005-06-16 | Kyoritsu Kagaku Sangyo Kk | Forming method of insulating film, and manufacturing method of electronic device |
| JP2007207906A (en) * | 2006-01-31 | 2007-08-16 | Toshiba Corp | Semiconductor integrated circuit and method for manufacturing the same |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| TW201830619A (en) * | 2017-01-03 | 2018-08-16 | 南亞科技股份有限公司 | Semiconductor package and method for preparing the same |
| CN109904122A (en) * | 2017-12-08 | 2019-06-18 | 矽品精密工业股份有限公司 | Electronic packing piece and its preparation method |
| CN111863791A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN113506748A (en) * | 2021-09-08 | 2021-10-15 | 南通汇丰电子科技有限公司 | Semiconductor stacking component and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10290512B2 (en) * | 2017-05-17 | 2019-05-14 | Nanya Technology Corporation | Semiconductor structure having bump on tilting upper corner surface |
| JP6836485B2 (en) * | 2017-09-15 | 2021-03-03 | 株式会社東芝 | Semiconductor chips and their manufacturing methods, as well as integrated circuit devices and their manufacturing methods |
-
2022
- 2022-05-24 CN CN202210565813.XA patent/CN114664793B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005159225A (en) * | 2003-11-28 | 2005-06-16 | Kyoritsu Kagaku Sangyo Kk | Forming method of insulating film, and manufacturing method of electronic device |
| JP2007207906A (en) * | 2006-01-31 | 2007-08-16 | Toshiba Corp | Semiconductor integrated circuit and method for manufacturing the same |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with silicon through holes and side bonding pads |
| TW201830619A (en) * | 2017-01-03 | 2018-08-16 | 南亞科技股份有限公司 | Semiconductor package and method for preparing the same |
| CN109904122A (en) * | 2017-12-08 | 2019-06-18 | 矽品精密工业股份有限公司 | Electronic packing piece and its preparation method |
| CN111863791A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN113506748A (en) * | 2021-09-08 | 2021-10-15 | 南通汇丰电子科技有限公司 | Semiconductor stacking component and preparation method thereof |
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