CN114664790B - Integrated circuit structure and forming method thereof - Google Patents
Integrated circuit structure and forming method thereof Download PDFInfo
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- CN114664790B CN114664790B CN202210566009.3A CN202210566009A CN114664790B CN 114664790 B CN114664790 B CN 114664790B CN 202210566009 A CN202210566009 A CN 202210566009A CN 114664790 B CN114664790 B CN 114664790B
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000010410 layer Substances 0.000 claims abstract description 272
- 230000004888 barrier function Effects 0.000 claims abstract description 99
- 238000009792 diffusion process Methods 0.000 claims abstract description 98
- 239000011229 interlayer Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000000126 substance Substances 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims description 51
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000007517 polishing process Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000012360 testing method Methods 0.000 abstract description 30
- 238000000227 grinding Methods 0.000 abstract description 17
- 239000007788 liquid Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 206010040844 Skin exfoliation Diseases 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- FERIUCNNQQJTOY-UHFFFAOYSA-N Butyric acid Chemical compound CCCC(O)=O FERIUCNNQQJTOY-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- YJQWZJOWDRXSEW-UHFFFAOYSA-N O.[C].[Si] Chemical compound O.[C].[Si] YJQWZJOWDRXSEW-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- XBDQKXXYIPTUBI-UHFFFAOYSA-N dimethylselenoniopropionate Natural products CCC(O)=O XBDQKXXYIPTUBI-UHFFFAOYSA-N 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 150000007522 mineralic acids Chemical class 0.000 description 2
- 150000007524 organic acids Chemical class 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XNGIFLGASWRNHJ-UHFFFAOYSA-N phthalic acid Chemical compound OC(=O)C1=CC=CC=C1C(O)=O XNGIFLGASWRNHJ-UHFFFAOYSA-N 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OFOBLEOULBTSOW-UHFFFAOYSA-N Propanedioic acid Natural products OC(=O)CC(O)=O OFOBLEOULBTSOW-UHFFFAOYSA-N 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000007942 carboxylates Chemical group 0.000 description 1
- 125000002843 carboxylic acid group Chemical group 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 235000015165 citric acid Nutrition 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- VZCYOOQTPOCHFL-UPHRSURJSA-N maleic acid Chemical compound OC(=O)\C=C/C(O)=O VZCYOOQTPOCHFL-UPHRSURJSA-N 0.000 description 1
- 239000011976 maleic acid Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000019260 propionic acid Nutrition 0.000 description 1
- IUVKMZGDUIUOCP-BTNSXGMBSA-N quinbolone Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H]([C@]4(C=CC(=O)C=C4CC3)C)CC[C@@]21C)C1=CCCC1 IUVKMZGDUIUOCP-BTNSXGMBSA-N 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- VZCYOOQTPOCHFL-UHFFFAOYSA-N trans-butenedioic acid Natural products OC(=O)C=CC(O)=O VZCYOOQTPOCHFL-UHFFFAOYSA-N 0.000 description 1
Images
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides an integrated circuit structure and a method of forming the same, the integrated circuit structure comprising a substrate; the interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer; a diffusion barrier layer covering sidewalls and a bottom wall of the opening; the conductive structure is filled in the opening, and the height of the top surface of the conductive structure is lower than that of the top surface of the side wall of the diffusion barrier layer; and the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer. When the diffusion barrier layer is ground by using a chemical mechanical grinding process, the time for grinding the conductive material layer in the grinding process is increased, the conductive material layer with the preset height in the opening is removed, the surface area of the subsequent etching stop layer attached to the side wall of the diffusion barrier layer is increased, the etching stop layer is firmer, and the risk of stripping the etching stop layer in the test is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an integrated circuit structure and a method for forming the same.
Background
With the rapid development of the integrated circuit manufacturing technology, the process nodes of the traditional integrated circuit are gradually reduced, the size of the integrated circuit device is continuously reduced, the number of components integrated on the same wafer is continuously increased, and therefore the integrated circuit manufacturing process is continuously innovated to improve the performance of the integrated circuit device. To meet the demand for increased numbers of semiconductor components or higher product performance, integrated circuit fabrication processes utilize batch processing techniques to form various types of devices on a substrate and interconnect them through integrated circuit structures to have complete electronic functionality. The metal copper can improve the transmission speed of signals between semiconductor devices by virtue of excellent conductivity and good electromigration resistance; meanwhile, a low-k (dielectric constant) material is used as a dielectric layer between metal layers, so that the parasitic capacitance between the metal layers is reduced, and therefore, the copper interconnection process becomes one of solutions of interconnection integration technologies in the field of ultra large scale integrated circuits (ULSI).
The copper interconnect process typically includes the following steps: firstly, an opening is formed in an interlayer dielectric layer, then a diffusion barrier layer is formed, then metal copper is electroplated, after the electroplating deposition of copper is completed, redundant copper is removed to the height of the diffusion barrier layer (diffusion barrier) by a Chemical Mechanical Polishing (CMP) process in a grinding mode, and then an etching barrier layer (ESL) is formed. However, this Etch Stop Layer (ESL) risks peeling (peeling) during the quality mechanical test of drop test (drop test) or peel test (peeling test).
Disclosure of Invention
The invention aims to provide an integrated circuit structure and a forming method thereof, which are used for solving the problem that an etching stop layer has stripping risk in a quality mechanical test of a drop test or a stripping test.
To solve the above technical problem, the present invention provides an integrated circuit structure, comprising:
a substrate;
the interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer;
a diffusion barrier layer covering sidewalls and a bottom wall of the opening;
the conductive structure is filled in the opening, and the height of the top surface of the conductive structure is lower than that of the top surface of the side wall of the diffusion barrier layer; and the number of the first and second groups,
and the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer.
Optionally, the height difference between the sidewall of the diffusion barrier layer and the conductive structure is greater than 30 angstroms.
Optionally, the etching stop layer is one or more materials of aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.
Optionally, the conductive structure is made of copper, and the diffusion barrier layer is made of tantalum nitride or tantalum.
Based on the same inventive concept, the invention also provides a method for forming an integrated circuit structure, which comprises the following steps:
providing a substrate, wherein an interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer;
forming a diffusion barrier layer which covers the side wall and the bottom wall of the opening;
forming a conductive material layer, wherein the conductive material layer fills the opening, covers the side wall and the bottom wall of the diffusion barrier layer and also covers the top surface of the interlayer dielectric layer;
removing the conductive material layer on the interlayer dielectric layer by adopting a chemical mechanical polishing process to form a conductive structure, wherein the chemical mechanical polishing process is used for removing the conductive material layer with a preset height in the opening by polishing to expose part of the side wall of the diffusion barrier layer;
and forming an etching stop layer, wherein the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer.
Optionally, the height difference between the sidewall of the diffusion barrier layer and the conductive structure is greater than 30 angstroms.
Optionally, in the over-grinding process, the grinding selection ratios of the diffusion barrier layer and the conductive material layer are different.
Optionally, in the over-polishing process, a polishing rate of the diffusion barrier layer is less than a polishing rate of the conductive material layer.
Optionally, the conductive structure is made of copper, and the diffusion barrier layer is made of tantalum nitride or tantalum.
Optionally, the conductive material layer is formed by an electroplating process.
In the integrated circuit structure and the forming method thereof provided by the invention, the height of the side wall of the diffusion barrier layer is greater than that of the conductive structure so as to increase the exposed depth of the side wall of the diffusion barrier layer, so that the etching stop layer is contacted with the side wall of the diffusion barrier layer, the surface area of the subsequent etching stop layer attached to the side wall of the diffusion barrier layer is increased, the etching stop layer is firmer, and the risk of stripping the etching stop layer in the quality mechanical test of a drop test or a stripping test is reduced; furthermore, when the chemical mechanical grinding process is used for grinding the diffusion barrier layer, the time for grinding the conductive material layer in the grinding process is increased, the conductive material layer with the preset height in the opening is removed, the side wall of the diffusion barrier layer with the preset height is exposed, the exposed depth of the side wall of the diffusion barrier layer is increased, the etching stop layer is in contact with the side wall of the diffusion barrier layer, the surface area of the subsequent etching stop layer attached to the side wall of the diffusion barrier layer is increased, and the possibility of stripping the etching stop layer in the quality mechanical test of a drop test or a stripping test is further prevented.
Drawings
FIG. 1 is a schematic diagram of an integrated circuit structure according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a method of forming an integrated circuit structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an embodiment of the present invention;
FIG. 4 is a schematic diagram of a diffusion barrier layer formation structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure for forming a conductive material layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure for forming a conductive structure according to an embodiment of the present invention;
FIG. 7 is a transmission electron microscope image of an integrated circuit structure of an embodiment of the invention;
in the figure, the position of the upper end of the main shaft,
10-a substrate; 11-an interlayer dielectric layer; 12-an opening; 13-a diffusion barrier layer; 14-a layer of conductive material; 14 a-a conductive structure; 15-etch stop layer.
Detailed Description
An integrated circuit structure and a method for forming the same according to the present invention are further described in detail below with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
Specifically, please refer to fig. 1, which is a schematic structural diagram of an integrated circuit structure according to an embodiment of the present invention. As shown in fig. 1, the present embodiment provides an integrated circuit structure, including a substrate 10; an interlayer dielectric layer 11 formed on the substrate 10, wherein an opening 12 is formed in the interlayer dielectric layer 11; a diffusion barrier layer 13, the diffusion barrier layer 13 covering the side walls and the bottom wall of the opening 12; and the conductive structure 14a is filled in the opening 12, the height of the top surface of the conductive structure 14a is lower than that of the side wall of the diffusion barrier layer 13, and the etching stop layer 15 covers the top surface of the interlayer dielectric layer 11, the top surface of the conductive structure 14a, the top surface of the diffusion barrier layer 13 and part of the side wall of the diffusion barrier layer 13.
Specifically, the substrate 10 may be a single crystal or compound semiconductor substrate. Active and passive components (not shown), such as transistors, resistors, and inductors, may be formed on the substrate 10. capping layers (overlayers) may also be formed on the substrate 10, which may include contact Etch Stop Layers (ESLs), inter-layer dielectric layers (ild), and inter-metal dielectric layers (IMD), wherein metallization layers (not shown) may also be formed.
Further, the height difference between the sidewall of the diffusion barrier layer 13 and the conductive structure 14a is greater than a preset height h. The predetermined height h is, for example, 30 angstroms. That is, the height of the contact between the sidewall of the diffusion barrier layer 13 and the etching stop layer 15 is greater than 30 angstroms, and the adhesion between the sidewall of the diffusion barrier layer 13 and the etching stop layer 15 is increased by increasing the surface area of the contact between the sidewall of the diffusion barrier layer 13 and the etching stop layer 15, so that the risk of peeling off the etching stop layer 15 in the quality mechanical test of a drop test or a peel-off test is reduced.
Further, the etch stop layer 15 has a single-layer structure or a structure in which at least two layers are stacked. The etch stop layer 15 is formed of a dielectric material, which may include one or more materials such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The etch stop layer 15 may be formed of a material having a high etch selectivity with respect to an upper dielectric layer in a subsequent process, so that etching of the upper dielectric layer in the subsequent process may be stopped on the etch stop layer 15.
Further, the material of the diffusion barrier layer 13 is tantalum nitride or tantalum. The diffusion barrier layer 13 has a function of preventing a conductive material (e.g., copper) of the conductive structure 14a from diffusing into the interlayer dielectric layer 11. The diffusion barrier layer 13 is formed using an ALD process or a CVD process.
Further, the interlayer dielectric layer 11 is an ILD (Inter-layer Dielectrics) in which the conductive structure 14a is formed. The interlayer dielectric layer 11 may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using Tetraethylorthosilicate (TEOS)), or a combination thereof; the interlayer dielectric layer 11 may also be silicon-oxygen-hydride-carbon (SiCOH) which includes porous SiCOH. The interlevel dielectric layer 11 may be formed using spin coating, Atomic Layer Deposition (ALD), Flowable Chemical Vapor Deposition (FCVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD).
Further, the conductive structure 14a may be formed of one metal or a metal alloy of copper, a copper alloy, aluminum, or a combination thereof, and in this embodiment, the material of the conductive structure 14a is, for example, copper, and is formed by an electroplating process.
FIG. 2 is a flow chart illustrating a method of forming an integrated circuit structure according to an embodiment of the invention; the present embodiment further provides a method for forming an integrated circuit structure, including:
step S10, providing a substrate, wherein an interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer;
step S20, forming a diffusion barrier layer which covers the side wall and the bottom wall of the opening;
step S30, forming a conductive material layer, wherein the conductive material layer fills the opening and covers the side wall and the bottom wall of the diffusion barrier layer and also covers the top surface of the interlayer dielectric layer;
step S40, removing the conductive material layer on the interlayer dielectric layer by using a chemical mechanical polishing process to form a conductive structure, wherein the chemical mechanical polishing process is performed to polish and remove the conductive material layer with a predetermined height in the opening to expose a part of the sidewall of the diffusion barrier layer;
step S50, forming an etching stop layer, wherein the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer.
Fig. 3-6 are schematic structural diagrams corresponding to steps of a method for forming an integrated circuit structure according to an embodiment of the invention, and a method for forming an integrated circuit structure is described in detail below with reference to fig. 3-6.
Referring to fig. 3, in step S10, a substrate 10 is provided, wherein the substrate 10 may be a single crystal or compound semiconductor substrate. Active and passive components (not shown), such as transistors, resistors, and inductors, may be formed on the substrate 10. capping layers (overlayers) may also be formed on the substrate 10, which may include contact Etch Stop Layers (ESLs), inter-layer dielectric layers (ild), and inter-metal dielectric layers (IMD), wherein metallization layers (not shown) may also be formed.
An interlayer dielectric layer 11 is formed on the substrate 10, and the interlayer dielectric layer 11 is an ILD (Inter-layer Dielectrics) in which a conductive structure 14a is formed. The interlayer dielectric layer 11 may be formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using Tetraethylorthosilicate (TEOS)), or a combination thereof; the interlayer dielectric layer 11 may also be silicon-oxygen-hydride-carbon (SiCOH) which includes porous SiCOH. The interlevel dielectric layer 11 may be formed using spin coating, Atomic Layer Deposition (ALD), Flowable Chemical Vapor Deposition (FCVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD).
An opening 12 is formed in the interlayer dielectric layer 11, and the step of forming the opening 12 includes: forming a patterned photoresist on the interlayer dielectric layer 11, and etching the interlayer dielectric layer 11 by using the patterned photoresist as a mask to form an opening 12.
Referring to fig. 4, in step S20, a diffusion barrier layer 13 is formed in the opening 12; the diffusion barrier layer 13 covers the top surface of the interlayer dielectric layer 11 and the sidewalls and the bottom wall of the opening 12, the diffusion barrier layer 13 is used to prevent the conductive material (e.g. copper) of the conductive structure 14a from diffusing into the interlayer dielectric layer 11, and in this embodiment, the material of the diffusion barrier layer 13 is, for example, tantalum nitride or tantalum. The diffusion barrier layer 13 is formed using an ALD process or a CVD process.
Referring to fig. 5, in step S30, a conductive material layer 14 is formed in the opening 12, wherein the conductive material layer 14 covers the diffusion barrier layer 13, fills the opening 12, and extends to the interlayer dielectric layer 11; in the present embodiment, the material of the conductive material layer 14 is, for example, copper, and the conductive material layer 14 is formed by an electroplating process.
Referring to fig. 6, in step S40, the conductive material layer 14 and the diffusion barrier layer 13 on the interlayer dielectric layer 11 are removed by a chemical mechanical polishing process to form a conductive structure 14a, wherein the chemical mechanical polishing process is performed to polish and remove the conductive material layer 14 with a predetermined height in the opening 12 to expose a portion of the sidewall of the diffusion barrier layer 13. In the present embodiment, the predetermined height is, for example, 30 angstroms. In the over-grinding process, the grinding selection ratios of the diffusion barrier layer 13 and the conductive material layer 14 are different. In the over-grinding process, the grinding rate of the diffusion barrier layer 13 is less than that of the conductive material layer 14. A person skilled in the art knows how to remove the conductive material layer 14 with a predetermined height h in the opening 12 by controlling the polishing pressure, the polishing slurry and the polishing speed, so as to expose the sidewall of the diffusion barrier layer 13 with the predetermined height h.
The conductive material layer 14 and the diffusion barrier layer 13 are planarized by a chemical mechanical polishing method, specifically, a chemical mechanical polishing machine is used for polishing, the chemical mechanical polishing machine comprises a polishing table, a polishing pad, a polishing head and a liquid supply device, the polishing pad is fixedly mounted on the polishing table, the polishing head is located above the polishing pad and used for fixing an integrated circuit structure, the polishing head and the polishing pad can move relatively, the liquid supply device is located above the polishing pad and used for containing polishing liquid, the liquid supply device comprises a liquid supply port, and the polishing liquid in the liquid supply device is supplied to the polishing pad through the liquid supply port. The integrated circuit structure is fixed by the polishing head, the surface of the conductive material layer 14 away from the substrate 10 is contacted with the polishing pad, the polishing liquid in the liquid supply device is supplied to the polishing pad through the liquid supply port, and at the same time, the relative motion of the polishing table and the polishing head is controlled, for example, the relative rotational motion of the polishing table and the polishing head is controlled, so that the polishing pad and the integrated circuit structure perform the relative rotational motion, and the surface of the conductive material layer 14 away from the substrate 10 is polished by the polishing pad. The grinding fluid selectively removes a part of the conductive material layer 14 higher than the interlayer dielectric layer 11 and a part of the conductive material layer 14 with a predetermined height in the opening 12, and the grinding process is stopped until the depth of the exposed sidewall of the diffusion barrier layer 13 is larger than a predetermined height h.
According to the embodiment, by etching the part of the conductive material layer 14, the height difference between the part of the conductive material layer 14 and the part of the side wall of the diffusion barrier layer 13 is larger than the predetermined height h, so that when the etching stop layer 15 is formed subsequently, the surface area of the etching stop layer 15 in contact with the diffusion barrier layer 13 is increased, the adhesion between the etching stop layer 15 and the diffusion barrier layer 13 is increased, and the risk of stripping the etching stop layer 15 in a quality mechanical test of a drop test or a stripping test is reduced.
In some embodiments, the material of the polishing pad may be polyurethane, or non-woven fabric, or porous resin.
In some embodiments, the abrasive liquid may include silica, an organic or inorganic acid, and water, wherein the organic acid may include at least one of acetic acid, propionic acid, butyric acid, citric acid, tartaric acid, oxalic acid, maleic acid, and phthalic acid, and the inorganic acid includes at least one of hydrochloric acid, nitric acid, and phosphoric acid; or the first polishing liquid may include cerium oxide, a water-soluble organic polymer, and water, wherein the water-soluble organic polymer has a carboxylic acid group or a carboxylate group.
In addition, the chemical mechanical polishing process may at least include a main polishing step and a deionized water cleaning step, in the main polishing step, a chemical preparation with polishing particles is used as a polishing solution to polish the conductive material layer 14; the lower pressure used in the deionized water cleaning process is in the same direction as the lower pressure used in the main grinding process, so that the roughness of the conductive material layer 14, the top surface of the diffusion barrier layer 13 and the surface of the interlayer dielectric layer 11 meets the requirement. Further, the polishing parameters of the cmp process may include down force, polishing time and polishing rotation speed, and by adjusting the polishing parameters, the roughness of the conductive material layer 14, the top surface of the diffusion barrier layer 13 and the surface of the interlayer dielectric layer 11 may be dynamically adjusted or trimmed to meet the requirements of the subsequent process steps.
Therefore, in at least one embodiment of the present application, a Chemical Mechanical Polishing (CMP) process is used in the step of removing a portion of the conductive material layer 14 to expose the sidewall of the diffusion barrier layer 13, so as to form the sidewall of the diffusion barrier layer 13 with a height higher than that of the conductive structure 14a, which meets the requirements of the subsequent process steps and improves the conductivity and yield of the finally formed semiconductor device product.
Referring to fig. 1, in step S50, an etching stop layer 15 is formed on the conductive structure 14a, where the etching stop layer 15 covers a top surface of the interlayer dielectric layer 11, a top surface of the conductive structure 14a, a top surface of the diffusion barrier layer 13, and a portion of a sidewall of the diffusion barrier layer 13. The contact height of the etch stop layer 15 with the sidewall of the diffusion barrier layer 13 is greater than the predetermined height h, which is, for example, 30 angstroms. The etch stop layer 15 has a single-layer structure or a structure in which at least two layers are stacked. The etch stop layer 15 is formed of a dielectric material, which may include one or more materials such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The etch stop layer 15 may be formed of a material having a high etch selectivity with respect to an upper dielectric layer in a subsequent process, so that etching of the upper dielectric layer in the subsequent process may be stopped on the etch stop layer 15.
FIG. 7 is a transmission electron microscope image of an integrated circuit structure of an embodiment of the invention; as can be seen from fig. 7, the etching stop layer 15 is a stacked structure, the height of the sidewall of the diffusion barrier layer 13 is greater than the height of the conductive structure 14a, the contact height between the etching stop layer 15 and the sidewall of the diffusion barrier layer 13 is greater than a predetermined height h, the surface area of the etching stop layer attached to the sidewall of the diffusion barrier layer 13 is increased, the etching stop layer is firmer, and the risk of peeling off the etching stop layer 15 in a quality mechanical test of a drop test or a peeling test is reduced.
In summary, in the embodiment of the present invention, an integrated circuit structure and a forming method thereof are provided, where the integrated circuit structure includes a substrate and an interlayer dielectric layer formed on the substrate, a conductive structure is formed in the interlayer dielectric layer, a diffusion barrier layer is formed between the conductive structure and the interlayer dielectric layer, and a sidewall of the diffusion barrier layer is formed to have a height greater than a height of the conductive structure, so as to increase a depth of exposure of the sidewall of the diffusion barrier layer; the etching stop layer is formed on the conductive structure, so that the etching stop layer is contacted with the side wall of the diffusion barrier layer, the surface area of the subsequent etching stop layer attached to the side wall of the diffusion barrier layer is increased, the etching stop layer is firmer, and the risk of stripping the etching stop layer in a quality mechanical test of a drop test or a stripping test is reduced. The etch stop layer is made more robust to reduce the risk of etch stop layer delamination in drop tests or quality mechanical tests of the lift-off test.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. An integrated circuit structure, comprising:
a substrate;
the interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer;
a diffusion barrier layer covering sidewalls and a bottom wall of the opening;
the conductive structure is filled in the opening, and the height of the top surface of the conductive structure is lower than that of the top surface of the side wall of the diffusion barrier layer; and the number of the first and second groups,
and the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer.
2. The integrated circuit structure of claim 1, wherein a height difference between sidewalls of the diffusion barrier layer and the conductive structure is greater than 30 angstroms.
3. The integrated circuit structure of claim 1, wherein the etch stop layer is one or more materials of aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.
4. The integrated circuit structure of claim 1, wherein the conductive structure is copper and the diffusion barrier layer is tantalum nitride or tantalum.
5. A method of forming an integrated circuit structure, comprising:
providing a substrate, wherein an interlayer dielectric layer is formed on the substrate, and an opening is formed in the interlayer dielectric layer;
forming a diffusion barrier layer which covers the side wall and the bottom wall of the opening;
forming a conductive material layer, wherein the conductive material layer fills the opening, covers the side wall and the bottom wall of the diffusion barrier layer and also covers the top surface of the interlayer dielectric layer;
removing the conductive material layer on the interlayer dielectric layer by adopting a chemical mechanical polishing process to form a conductive structure, wherein the chemical mechanical polishing process is used for removing the conductive material layer with a preset height in the opening by polishing to expose part of the side wall of the diffusion barrier layer;
and forming an etching stop layer, wherein the etching stop layer covers the top surface of the interlayer dielectric layer, the top surface of the conductive structure, the top surface of the diffusion barrier layer and part of the side wall of the diffusion barrier layer.
6. The method of claim 5, wherein a height difference between sidewalls of the diffusion barrier layer and the conductive structure is greater than 30 angstroms.
7. The method of claim 5, wherein the polishing selectivity of the diffusion barrier layer to the conductive material layer is different during the over-polishing.
8. The method of claim 7, wherein a polishing rate of the diffusion barrier layer is less than a polishing rate of the conductive material layer during the over-polishing.
9. The method of claim 5, wherein the conductive structure is copper and the diffusion barrier layer is tantalum nitride or tantalum.
10. The method of claim 5, wherein the conductive material layer is formed using an electroplating process.
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| US5847460A (en) * | 1995-12-19 | 1998-12-08 | Stmicroelectronics, Inc. | Submicron contacts and vias in an integrated circuit |
| US6383925B1 (en) * | 2000-02-04 | 2002-05-07 | Advanced Micro Devices, Inc. | Method of improving adhesion of capping layers to cooper interconnects |
| JP2004349572A (en) * | 2003-05-23 | 2004-12-09 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| CN112397515A (en) * | 2019-08-13 | 2021-02-23 | 美光科技公司 | Apparatus including aluminum interconnects, memory devices including interconnects, and related methods |
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| US5847460A (en) * | 1995-12-19 | 1998-12-08 | Stmicroelectronics, Inc. | Submicron contacts and vias in an integrated circuit |
| US6383925B1 (en) * | 2000-02-04 | 2002-05-07 | Advanced Micro Devices, Inc. | Method of improving adhesion of capping layers to cooper interconnects |
| JP2004349572A (en) * | 2003-05-23 | 2004-12-09 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
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