CN114664223B - Driving circuit of display panel, array substrate and driving method of array substrate - Google Patents
Driving circuit of display panel, array substrate and driving method of array substrate Download PDFInfo
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- CN114664223B CN114664223B CN202210337363.9A CN202210337363A CN114664223B CN 114664223 B CN114664223 B CN 114664223B CN 202210337363 A CN202210337363 A CN 202210337363A CN 114664223 B CN114664223 B CN 114664223B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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Abstract
The application discloses drive circuit, array substrate and drive method of display panel, wherein, the drive circuit of display panel includes: an N +1 th stage output module; the output end of the (N + 1) th charging module is connected with the controlled end of the (N + 1) th output module, and the (N + 1) th charging module is used for pre-charging the (N + 1) th output module; and the input end of the compensation module is connected with the Nth-stage drive circuit, the output end of the compensation module is connected with the controlled end of the (N + 1) th-stage output module, and the compensation module is used for pre-charging the (N + 1) th-stage output module in advance according to a first preset compensation signal output by the Nth-stage drive circuit before the (N + 1) th-stage output module is pre-charged. The technical scheme of the application can improve the display effect of the display panel with the high refresh rate.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a driving circuit of a display panel, an array substrate and a driving method thereof.
Background
At present, a two-stage driving circuit with a pull-up node and a pull-down node shared with each other is generally adopted in a display panel with a high refresh rate, but the display effect of the display panel with the high refresh rate is affected because the charging time of the two-stage driving circuit to pixels is short.
Disclosure of Invention
The present application mainly aims to provide a driving circuit of a display panel, which aims to solve the problem that a two-stage driving circuit affects the display effect of a display panel with a high refresh rate.
In order to achieve the above object, the present application provides a driving circuit of a display panel, the driving circuit of the display panel includes an nth stage driving circuit, an N +1 th stage driving circuit, and a compensation module, the driving circuit of the N +1 th stage display panel includes:
an N +1 th stage output module;
the output end of the (N + 1) th-stage charging module is connected with the controlled end of the (N + 1) th-stage output module, and the (N + 1) th-stage charging module is used for pre-charging the (N + 1) th-stage output module;
the input end of the compensation module is connected with the nth stage drive circuit, the output end of the compensation module is connected with the controlled end of the (N + 1) th stage output module, and the compensation module is used for pre-charging the (N + 1) th stage output module in advance according to a first preset compensation signal output by the nth stage drive circuit before the (N + 1) th stage output module is pre-charged.
Optionally, the compensation module comprises:
and the first end of the compensation capacitor is the input end of the compensation module, and the second end of the compensation capacitor is the output end of the compensation module.
Optionally, the N +1 th stage output module includes:
the N +1 th stage pre-charging capacitor is connected between the controlled end and the output end of the N +1 th stage output module, and the capacitance value of the N +1 th stage pre-charging capacitor is equal to that of the compensation capacitor.
Optionally, the nth stage driving circuit includes:
the N-th-stage output module is provided with an N-th-stage pre-charging capacitor, the N-th-stage pre-charging capacitor is connected between a controlled end and an output end of the N-th-stage output module, and the capacitance value of the N-th-stage pre-charging capacitor is equal to that of the compensation capacitor.
Optionally, an input end of the nth-stage output module is configured to access a first timing control signal, an output end of the nth-stage output module is connected to an input end of the compensation module, and the nth-stage output module is configured to output the accessed first timing control signal as an nth-stage row driving signal and the first preset compensation signal.
Optionally, the nth stage driving circuit further includes:
the input end of the Nth-level transmission module is used for accessing a first timing control signal, the output end of the Nth-level transmission module is connected with the input end of the compensation module, and the Nth-level transmission module is used for outputting the accessed first timing control signal as a first preset-level transmission signal and a first preset compensation signal.
Optionally, the number of the compensation modules is multiple, an input end of each compensation module is connected to the nth stage driving circuit, and an output end of each compensation module is connected to the controlled end of the (N + 1) th stage output module.
The application also provides a driving circuit of the display panel, wherein the driving circuit of the display panel comprises an Nth-stage driving circuit, an N +1 th-stage driving circuit and a compensation module, and the Nth-stage driving circuit comprises an Nth-stage transmission module and an Nth-stage output module;
the driving circuit of the N +1 th-level display panel includes:
an N +1 th stage output module;
the output end of the (N + 1) th-stage charging module is connected with the controlled end of the (N + 1) th-stage output module, and the (N + 1) th-stage charging module is used for pre-charging the (N + 1) th-stage output module; and the number of the first and second groups,
the first input end of the compensation module is connected with the output end of the Nth-level transmission module, the second input end of the compensation module is connected with the output end of the Nth-level output module, the output end of the compensation module is connected with the controlled end of the (N + 1) th-level output module, and the compensation module is used for pre-charging the (N + 1) th-level output module in advance according to the first preset-level transmission signal output by the Nth-level transmission module and the Nth-level row driving signal output by the Nth-level output module.
The application further provides an array substrate, the array substrate comprises an effective display area and an ineffective display area, the ineffective display area surrounds the periphery of the effective display area, and the driving circuit of the display panel is arranged in the ineffective display area of the array substrate.
The application also provides a driving method of the array substrate, based on the array substrate, the driving method of the array substrate includes:
the nth stage driving circuit works to output a first preset compensation signal to the compensation module before the (N + 1) th stage charging module precharges the (N + 1) th stage output module;
the compensation module pre-charges the (N + 1) th-level output module in advance according to the received first preset compensation signal until the (N + 1) th-level charging module pre-charges the (N + 1) th-level output module.
According to the technical scheme, the pre-charging duration of the (N + 1) th-level output module can be equal to the sum of the pre-charging duration and the normal pre-charging duration, so that the pre-charging effect and the terminal voltage of the (N + 1) th-level output module can be effectively guaranteed, the (N + 1) th-level output module can have high current mobility to reduce the rise time of the (N + 1) th-level row driving signal, and the terminal voltage with enough magnitude is used for lifting the signal amplitude of the (N + 1) th-level row driving signal, and therefore the charging effect of pixels and the display effect of a display panel are favorably improved, and the problem that the display effect of the high-refresh-rate display panel is influenced by a two-stage driving circuit is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a signal waveform of an embodiment of a driving circuit of the present application;
fig. 5 is a schematic block diagram of a driving circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic structural diagram of an array substrate according to the present application;
fig. 7 is a schematic flow chart of a driving method of an array substrate according to the present application.
The reference numbers illustrate:
the implementation, functional features and advantages of the object of the present application will be further explained with reference to the embodiments, and with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Furthermore, descriptions in this application as to "first," "second," etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between the embodiments may be combined with each other, but must be based on the realization of the technical solutions by a person skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope claimed in the present application.
The first embodiment is as follows:
the application provides a driving circuit of a display panel.
Referring to fig. 1, in an embodiment, the driving circuit of the display panel includes an nth stage driving circuit, an N +1 th stage driving circuit, and a compensation module 30, and the driving circuit of the N +1 th stage display panel includes:
an N +1 th-stage output module 21;
the output end of the (N + 1) th charging module 22 is connected to the controlled end of the (N + 1) th output module 21, and the (N + 1) th charging module 22 is configured to precharge the (N + 1) th output module 21; and the number of the first and second groups,
the input end of the compensation module 30 is connected to the nth stage driving circuit 10, the output end of the compensation module 30 is connected to the controlled end of the (N + 1) th stage output module 21, and the compensation module 30 is configured to pre-charge the (N + 1) th stage output module 21 in advance according to a first preset compensation signal output by the nth stage driving circuit 10 before the (N + 1) th stage output module 21 is pre-charged.
In this embodiment, the nth stage driver circuit 10 and the (N + 1) th stage driver circuit 20 are two adjacent stages of driver circuits in the two stages of driver circuits, and this specification takes the nth stage driver circuit 10 as a previous stage driver circuit of the (N + 1) th stage driver circuit 20 as an example for explanation, where N may be a natural number. The (N + 1) th stage output module 21 and the (N + 1) th stage charging module 22 may be implemented by at least one thin film transistor, and in the embodiments of fig. 2 and 3, the (N + 1) th stage output module 21 includes a sixth thin film transistor T6, and the (N + 1) th stage charging module 22 includes a fourth thin film transistor T4. The controlled end and the input end of the (N + 1) th-stage charging module 22 are both connected to the output end of the second preset-stage output module or the second preset-stage transmission module, so as to be turned on when receiving the second preset-stage row driving signal G (N-3) of high level output by the second preset-stage output module or receiving the second preset-stage transmission signal C (N-3) of high level output by the second preset-stage transmission module, and when being turned on, output the second preset-stage row driving signal G (N-3) of high level or the second preset-stage transmission signal C (N-3) of high level to the controlled end of the (N + 1) th-stage output module 21, so as to pull up the potential of the controlled end of the (N + 1) th-stage output module 21; wherein, the second preset stage may be the first 3 stages.
An (N + 1) th stage pre-charge capacitor C2 may be connected between the controlled terminal and the output terminal of the (N + 1) th stage output module 21. The controlled end of the (N + 1) th stage output module 21 is a Q (N + 1) point, and the input end of the (N + 1) th stage output module 21 may be connected to a clock signal line to access a timing control signal transmitted by the clock signal line. When the potential of the controlled terminal of the (N + 1) th stage output module 21 is pulled up and the input terminal receives the low level timing control signal, the (N + 1) th stage pre-charge capacitor C2 can be pre-charged by the high level second pre-stage row driving signal G (N-3) or the second pre-stage transfer signal C (N-3). Thus, when the low-level timing control signal is converted into the high level, the N +1 th stage output module 21 may output the high-level timing control signal as the N +1 th stage row driving signal, and since the N +1 th stage pre-charge capacitor C2 has a characteristic that the terminal voltage cannot change suddenly, the signal amplitude of the N +1 th stage row driving signal is equal to the sum of the terminal voltage of the N +1 th stage pre-charge capacitor C2 and the signal amplitude of the high-level timing control signal, thereby achieving the effect of raising the signal amplitude of the N +1 th stage row driving signal. In addition, after the N +1 th stage precharge capacitor C2 is precharged, the gate voltage of the thin film transistor in the N +1 th stage output module 21 is increased, and the current mobility of the thin film transistor is increased, so that the stability of the N +1 th stage row driving signal is improved. It should be noted that, for a display panel with a high refresh rate, the precharge time in each frame is very short, and the terminal voltage of the N +1 th stage precharge capacitor C2 is very easy to be insufficient due to incomplete precharge, so that the current mobility is low, and the rise time of the N +1 th stage row driving signal is long, thereby affecting the charging effect of the N +1 th stage pixel, and the signal amplitude of the N +1 th stage row driving signal is also affected.
The compensation module 30 can be implemented by a tank circuit composed of energy storage devices. The nth stage driving circuit 10 may include a compensation signal generating circuit dedicated to generating a first predetermined compensation signal, so as to output the first predetermined compensation signal to the compensation module 30 before the (N + 1) th stage output module 21 is precharged, so that the compensation module 30 may correspondingly raise the voltage value of the controlled terminal of the (N + 1) th stage output module 21 by using the first predetermined compensation signal, thereby pre-charging the (N + 1) th stage precharge capacitor C2 in advance, and not affecting the normal precharge time of the subsequent (N + 1) th stage output module 21. Of course, the first preset compensation signal may also be obtained by multiplexing other output signals of the nth stage driving circuit 10, for example, the nth stage row driving signal or the first preset stage transfer signal, which is not limited herein.
Therefore, the precharging time length of the (N + 1) th-stage output module 21 can be equal to the sum of the precharging time length in advance and the normal precharging time length, so that the precharging effect and the terminal voltage size of the (N + 1) th-stage output module 21 can be effectively guaranteed, the (N + 1) th-stage output module 21 can have higher current mobility to reduce the rising time of the (N + 1) th-stage row driving signal, and the terminal voltage with enough size is used for lifting the signal amplitude of the (N + 1) th-stage row driving signal, the pixel charging effect and the display effect of the display panel can be favorably improved, and the problem that the display effect of the high-refresh-rate display panel is influenced by the two-stage driving circuit is solved.
Referring to fig. 1-3, in one embodiment, the compensation module 30 includes:
a compensation capacitor Cplus, a first terminal of the compensation capacitor Cplus being an input terminal of the compensation module 30, and a second terminal of the compensation capacitor Cplus being an output terminal of the compensation module 30.
In this embodiment, the number of the compensation capacitors Cplus may be at least one. The compensation capacitor Cplus may be charged by a first predetermined compensation signal outputted from the nth stage driving circuit 10, and may load a terminal voltage to the controlled terminal of the N +1 th stage output module 21 after the charging is completed, so as to raise the voltage value of the controlled terminal of the N +1 th stage output module 21. Secondly, the compensation capacitor Cplus has a small volume, and does not occupy an excessively large area of the non-effective display area, so that the gap region between the nth stage driver circuit 10 and the (N + 1) th stage driver circuit 20 can be conveniently used for setting. In addition, since the compensation capacitor Cplus has a characteristic that the terminal voltage thereof cannot change suddenly and the pre-charging and pre-charging time is very short, the compensation capacitor Cplus can also increase the voltage value of the controlled terminal thereof when the N +1 th stage output module 21 outputs the N +1 th stage row driving signal, so as to reduce the rise time of the N +1 th stage row driving signal and improve the signal waveform.
Referring to fig. 1 to 3, in an embodiment, the N +1 th stage output module 21 includes:
the N +1 th stage pre-charge capacitor C2, the N +1 th stage pre-charge capacitor C2 is connected between the controlled terminal and the output terminal of the N +1 th stage output module 21, and a capacitance value of the N +1 th stage pre-charge capacitor C2 is equal to a capacitance value of the compensation capacitor Cplus.
In this embodiment, the N +1 th stage pre-charge capacitor C2 and the compensation capacitor Cplus have the same capacitance value to ensure the same charge amount and charge/discharge capability.
The present invention is explained by taking a display panel with 8 clock signal lines as an example, and specifically, refer to fig. 4. When the nth stage driving circuit 10 does not output the nth stage row driving signal and the (N + 1) th charging module 22 precharges the (N + 1) th output module 21, the voltage value of the controlled terminal Q (N + 1) of the (N + 1) th output module 21 is the voltage value V1 corresponding to the second preset stage row driving signal G (N-3) or the second preset stage transfer signal C (N-3), and the voltage values of the output terminal G (N) of the nth stage output module 11 and the output terminal G (N + 1) of the (N + 1) th output module 21 are both low level V2, so that the terminal voltage of the (N + 1) th precharge capacitor C2 is V1-V2. If the voltage value corresponding to the high-level timing control signal is V3, it can be known from the pre-charging process that when the nth-stage driving circuit 10 outputs the nth-stage row driving signal, the voltage value corresponding to the nth-stage row driving signal is V4= V3+ (V1-V2), i.e., the voltage value of the controlled terminal Q (N + 1) of the N +1 th-stage output module 21 is also pulled up to V4. Since the voltage values corresponding to the high-level timing control signals accessed by the nth stage output module 11 and the (N + 1) th stage output module 21 are the same, that is, both are V3, and the capacitance values of the (N + 1) th stage precharge capacitor C2 and the compensation capacitor Cplus are equal, the voltage value of the controlled terminal Q (N + 1) of the (N + 1) th stage output module 21 is pulled up to V4 in advance, thereby implementing the pre-precharge of the (N + 1) th stage output module 21. In the embodiment shown in fig. 4, the time T is the time for pre-charging the N +1 th stage output module 21 by using the scheme of the present application, and the time T is approximately equal to one fourth of the normal charging time.
Referring to fig. 1-3, in an embodiment, the nth stage driving circuit 10 includes:
the nth stage output module 11, wherein the nth stage output module 11 has an nth stage pre-charge capacitor C1, the nth stage pre-charge capacitor C1 is connected between the controlled terminal and the output terminal of the nth stage output module 11, and a capacitance value of the nth stage pre-charge capacitor C1 is equal to a capacitance value of the compensation capacitor Cplus.
The nth stage driving circuit 10 may include an nth stage charging module 12 and an nth stage output module 11, where a controlled terminal and an input terminal of the nth stage charging module 12 may be connected to an output terminal of a third preset stage output module or a third preset stage transmission module, so as to be turned on when receiving a high-level third preset stage row driving signal G (N-4) output by the third preset stage output module or receiving a high-level third preset stage transmission signal C (N-4), and may output an accessed high-level third preset stage row driving signal G (N-4) or third preset stage transmission signal C (N-4) to a controlled terminal of the nth stage output module 11 when being turned on, so as to precharge the nth stage output module 11; wherein, the third preset stage may be the first 4 stages. In this embodiment, the nth stage precharge capacitor C1 may be connected between the controlled terminal and the output terminal of the nth stage output module 11, and the capacitance value is the same as the capacitance value of the compensation capacitor Cplus, so that when the nth stage output module 11 is precharged, since the voltage values corresponding to each timing control signal and each row driving signal in the display panel are the same, the terminal voltage of the N-th stage compensated capacitor after precharging is V1-V2, and the voltage value corresponding to the nth stage row driving signal is V4= V3+ (V1-V2).
Optionally, an input end of the nth stage output module 11 is configured to access a first timing control signal, an output end of the nth stage output module 11 is connected to an input end of the compensation module 30, and the nth stage output module 11 is configured to output the accessed first timing control signal as the nth stage row driving signal and the first preset compensation signal.
In this embodiment, the nth stage output module 11 may be implemented by a thin film transistor; in the embodiment of fig. 2 and 3, the nth stage output module 11 includes a third thin film transistor T3. The nth stage output module 11 may further use the nth stage row driving signal as the first preset compensation signal by using a characteristic that a timing when the nth stage row driving signal is output by the nth stage output module is before the N +1 th output module is precharged. With such an arrangement, it is not necessary to additionally provide a compensation signal generating circuit in the nth stage driving circuit 10, so that the area occupied by the driving circuit on the non-display effective area of the array substrate can be reduced, and the integration level of the nth stage output module 11 can be improved.
Referring to fig. 1-3, in an embodiment, the nth stage driving circuit 10 further includes:
an nth stage transmission module 13, an input end of the nth stage transmission module 13 is used for accessing a first timing control signal, an output end of the nth stage transmission module 13 is connected to an input end of the compensation module 30, and the nth stage transmission module 13 is used for outputting the accessed first timing control signal as a first preset stage transmission signal and a first preset compensation signal.
In this embodiment, the nth stage transfer module 13 may be implemented by a thin film transistor T3; in the embodiment of fig. 2 and 3, the nth stage transfer module 13 includes a second thin film transistor T2. The controlled end of the nth stage transmission module 13 may be connected to the output end of the nth stage charging module 12, and the input end may be connected to the same clock signal line as the nth stage output module 11, so as to synchronously operate and output the accessed first timing control signal as the first preset stage transmission signal and the first preset compensation signal when the controlled end potential of the nth stage output module 11 is pulled up; wherein the first predetermined stage may be a last 4 stages. The nth stage transfer module 13 may also pre-charge the (N + 1) th stage output module 21 with the first predetermined stage transfer signal as the first predetermined compensation signal by utilizing the characteristic of the timing when the nth stage transfer module outputs the first predetermined stage transfer signal before the (N + 1) th stage transfer module is pre-charged. It is understood that the (N + 1) th stage driving circuit 20 may further include an (N + 1) th stage transfer module 23. With such an arrangement, it is not necessary to additionally provide a compensation signal generating circuit in the nth stage driving circuit 10, so that the area occupied by the driving circuit on the non-display effective area of the array substrate can be reduced, and the integration level of the nth stage output module 11 can be improved.
Referring to fig. 1-3, in an embodiment, the number of the compensation modules 30 is multiple, an input terminal of each compensation module 30 is connected to the nth stage driver circuit 10, and an output terminal of each compensation module is connected to the controlled terminal of the (N + 1) th stage output module 21.
In this embodiment, each compensation module 30 may access one path of the first predetermined compensation signal output by the nth stage driving circuit 10 before the N +1 th stage output module 21 is precharged, and may output a plurality of paths of the first predetermined compensation signal to the controlled end of the N +1 th stage output module 21, respectively, so as to further reduce the rise time of the N +1 th stage row driving signal and improve the signal waveform. In addition, by the arrangement, the probability of failure of the scheme can be reduced to the minimum due to the damage of any compensation module 30, and the stability of the scheme is improved.
Example two:
referring to fig. 5, in an embodiment, the driving circuit of the display panel includes an nth stage driving circuit 10, an N +1 th stage driving circuit 20, and a compensation module 30, where the nth stage driving circuit 10 includes an nth stage transfer module 13 and an nth stage output module 11;
the driving circuit of the N +1 th-level display panel includes:
an N +1 th-stage output module 21;
the output end of the (N + 1) th charging module 22 is connected to the controlled end of the (N + 1) th output module 21, and the (N + 1) th charging module 22 is configured to precharge the (N + 1) th output module 21; and the number of the first and second groups,
the compensation module 30, a first input end of the compensation module 30 is connected to an output end of the nth stage transmission module 13, a second input end of the compensation module 30 is connected to an output end of the nth stage output module 11, an output end of the compensation module 30 is connected to a controlled end of the (N + 1) th stage output module 21, and the compensation module 30 is configured to pre-charge the (N + 1) th stage output module 21 in advance according to a first preset stage transmission signal output by the nth stage transmission module 13 and an nth stage row driving signal output by the nth stage output module 11.
In this embodiment, the embodiments of the nth stage transmission module 13, the nth stage output module 11, the (N + 1) th stage output module 21, and the (N + 1) th stage charging module 22 refer to the first embodiment, and are not repeated herein. The compensation module 30 can utilize the characteristics of the nth stage output module 11 outputting the nth stage row driving signal and the nth stage transmission module 13 outputting the first preset stage transmission signal before the N +1 th output module is precharged, and the nth stage row driving signal and the first preset stage transmission signal are accessed as two first preset compensation signals and are precharged for the N +1 th stage output module 21 in advance, so as to further reduce the rise time of the N +1 th stage row driving signal and improve the signal waveform. In addition, because the nth stage transmission module 13 and the (N + 1) th stage output module 21 of the nth stage driving circuit 10 are adopted, two paths of compensation signal generating circuits do not need to be additionally arranged in the nth stage driving circuit 10, the occupied area of the driving circuit on a non-display effective area of the array substrate can be reduced, the probability of failure of the scheme of the application due to abnormity of the nth stage row driving signal or the first preset stage transmission signal can be reduced, and the stability of the scheme of the application can be improved.
Example three:
referring to fig. 6, an array substrate is disclosed, the array substrate includes an active display area 101 and a non-active display area, the non-active display area surrounds the active display area 101, and the driving circuit 102 of the display panel is disposed in the non-active display area of the array substrate. The specific structure of the driving circuit of the display panel refers to the above embodiments, and since the array substrate adopts all the technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
Example four:
referring to fig. 7, a driving method of an array substrate is disclosed, based on the array substrate 100, the specific structure of the array substrate 100 can refer to the above embodiments, and is not repeated here. The driving method of the array substrate comprises the following steps:
step S10, before the N +1 th stage charging module 22 precharges the N +1 th stage output module 21, the nth stage driving circuit 10 outputs a first preset compensation signal to the compensation module 30;
step S20, the compensation module 30 pre-charges the N +1 th stage output module 21 according to the received first preset compensation signal until the N +1 th stage charging module 22 pre-charges the N +1 th stage output module 21.
The nth stage driving circuit 10 may be provided with a compensation signal generating circuit dedicated to generating a first predetermined compensation signal, so as to output the first predetermined compensation signal to the compensation module 30 before the N +1 th stage output module 21 is precharged, so that the compensation module 30 may correspondingly raise the voltage value of the controlled terminal of the N +1 th stage output module 21 by using the first predetermined compensation signal, thereby implementing the precharge for the N +1 th stage precharge capacitor C2. In addition, the compensation module 30 does not affect the normal precharging time of the subsequent (N + 1) th stage output module 21, and the (N + 1) th stage output module 21 can be precharged in advance until it is precharged normally, in other words, the precharging time of the (N + 1) th stage output module 21 can be equal to the sum of the precharge time period and the normal precharging time period. Therefore, the pre-charging effect and the terminal voltage of the (N + 1) th-level output module 21 can be effectively guaranteed, so that the (N + 1) th-level output module 21 can have higher current mobility to reduce the rise time of the (N + 1) th-level row driving signal, and the terminal voltage with enough magnitude is used for raising the signal amplitude of the (N + 1) th-level row driving signal, thereby being beneficial to improving the charging effect of pixels and the display effect of a display panel, and further solving the problem that the display effect of the display panel with high refresh rate is influenced by the two-level driving circuit.
Of course, the first preset compensation signal may also be obtained by multiplexing other output signals of the nth stage driving circuit 10, for example, the nth stage row driving signal or the first preset stage transfer signal, which is not limited herein. Therefore, a special compensation signal generating circuit does not need to be arranged in the nth stage driving circuit 10, that is, the driving method of the array substrate of the present application is implemented without changing the circuit structure of the nth stage driving circuit 10, which is beneficial to reducing the implementation difficulty and cost of the driving method of the present application.
The above description is only an alternative embodiment of the present application, and not intended to limit the scope of the present application, and all modifications, equivalents, and other technical fields that can be directly or indirectly applied to the present application and the claims of the present application are included in the scope of the present application.
Claims (9)
1. A driving circuit of a display panel, the driving circuit of the display panel comprising an Nth stage driving circuit, an N +1 th stage driving circuit and a compensation module, the N +1 th stage driving circuit comprising:
an N +1 th stage output module;
the output end of the (N + 1) th-stage charging module is connected with the controlled end of the (N + 1) th-stage output module, and the (N + 1) th-stage charging module is used for pre-charging the (N + 1) th-stage output module;
the input end of the compensation module is connected with the nth-stage drive circuit, the output end of the compensation module is connected with the controlled end of the (N + 1) th-stage output module, and the compensation module is used for pre-charging the (N + 1) th-stage output module in advance according to a first preset compensation signal output by the nth-stage drive circuit before the (N + 1) th-stage output module is pre-charged;
the compensation module comprises:
and the first end of the compensation capacitor is the input end of the compensation module, and the second end of the compensation capacitor is the output end of the compensation module.
2. The driving circuit of the display panel according to claim 1, wherein the N +1 th-stage output module includes:
the N +1 th stage pre-charging capacitor is connected between the controlled end and the output end of the N +1 th stage output module, and the capacitance value of the N +1 th stage pre-charging capacitor is equal to that of the compensation capacitor.
3. The drive circuit of the display panel according to claim 2, wherein the nth stage drive circuit includes:
the N-th-stage output module is provided with an N-th-stage pre-charging capacitor, the N-th-stage pre-charging capacitor is connected between a controlled end and an output end of the N-th-stage output module, and the capacitance value of the N-th-stage pre-charging capacitor is equal to that of the compensation capacitor.
4. The driving circuit of claim 3, wherein an input terminal of the Nth stage output module is configured to receive a first timing control signal, an output terminal of the Nth stage output module is connected to an input terminal of the compensation module, and the Nth stage output module is configured to output the received first timing control signal as an Nth stage row driving signal and the first preset compensation signal.
5. The drive circuit of the display panel according to claim 1, wherein the nth stage drive circuit further comprises:
the input end of the Nth-stage transmission module is used for accessing a first timing control signal, the output end of the Nth-stage transmission module is connected with the input end of the compensation module, and the Nth-stage transmission module is used for taking the accessed first timing control signal as a first preset-stage transmission signal and outputting the first preset compensation signal.
6. The driving circuit of any one of claims 1 to 5, wherein the number of the compensation modules is multiple, an input terminal of each of the compensation modules is connected to the Nth stage driving circuit, and an output terminal of each of the compensation modules is connected to the controlled terminal of the (N + 1) th stage output module.
7. A driving circuit of a display panel comprises an Nth-stage driving circuit, an (N + 1) th-stage driving circuit and a compensation module, and is characterized in that the Nth-stage driving circuit comprises an Nth-stage transmission module and an Nth-stage output module;
the driving circuit of the N +1 th-level display panel includes:
an N +1 th stage output module;
the output end of the (N + 1) th-stage charging module is connected with the controlled end of the (N + 1) th-stage output module, and the (N + 1) th-stage charging module is used for pre-charging the (N + 1) th-stage output module; and the number of the first and second groups,
a first input end of the compensation module is connected with an output end of the nth stage transmission module, a second input end of the compensation module is connected with an output end of the nth stage output module, an output end of the compensation module is connected with a controlled end of the (N + 1) th stage output module, and the compensation module is used for pre-charging the (N + 1) th stage output module in advance according to a first preset stage transmission signal output by the nth stage transmission module and an nth stage row driving signal output by the nth stage output module;
the compensation module includes:
and the first end of the compensation capacitor is the input end of the compensation module, and the second end of the compensation capacitor is the output end of the compensation module.
8. An array substrate, comprising an active display area and a non-active display area, wherein the non-active display area surrounds the active display area, and the driving circuit of the display panel according to any one of claims 1 to 7 is disposed in the non-active display area of the array substrate.
9. A driving method of an array substrate, based on the array substrate of claim 8, comprising:
the nth stage driving circuit works to output a first preset compensation signal to the compensation module before the (N + 1) th stage charging module precharges the (N + 1) th stage output module;
the compensation module pre-charges the (N + 1) th-level output module in advance according to the received first preset compensation signal until the (N + 1) th-level charging module pre-charges the (N + 1) th-level output module.
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| CN104103244A (en) * | 2013-04-03 | 2014-10-15 | 瀚宇彩晶股份有限公司 | Liquid crystal display and bidirectional shift temporary storage device thereof |
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| JP4484451B2 (en) * | 2003-05-16 | 2010-06-16 | 奇美電子股▲ふん▼有限公司 | Image display device |
| KR101182300B1 (en) * | 2005-09-06 | 2012-09-20 | 엘지디스플레이 주식회사 | A driving circuit of liquid crystal display device and a method for driving the same |
| TWI473438B (en) * | 2011-11-28 | 2015-02-11 | Sitronix Technology Corp | Automatic sensing of the drive circuit |
| CN104091577B (en) * | 2014-07-15 | 2016-03-09 | 深圳市华星光电技术有限公司 | Be applied to the gate driver circuit of 2D-3D signal setting |
| KR102420489B1 (en) * | 2015-10-27 | 2022-07-14 | 엘지디스플레이 주식회사 | Display Device |
| CN105204249B (en) * | 2015-10-29 | 2018-07-17 | 深圳市华星光电技术有限公司 | Scan drive circuit in array substrate and array substrate |
| CN109473069B (en) * | 2017-09-07 | 2021-03-23 | 瀚宇彩晶股份有限公司 | Gate drive circuit and display panel |
| CN114187878B (en) * | 2021-12-31 | 2023-05-26 | 长沙惠科光电有限公司 | Driving circuit of display panel, array substrate and display panel |
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| CN104103244A (en) * | 2013-04-03 | 2014-10-15 | 瀚宇彩晶股份有限公司 | Liquid crystal display and bidirectional shift temporary storage device thereof |
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