CN114661614A

CN114661614A - FPGA hardware design capability evaluation system and method for cloud environment

Info

Publication number: CN114661614A
Application number: CN202210372828.4A
Authority: CN
Inventors: 陈文智; 魏成坤; 施青松; 刘剑文; 王淼; 陈义全; 张紫徽
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2022-04-11
Filing date: 2022-04-11
Publication date: 2022-06-24

Abstract

The invention discloses a system and a method for evaluating the design capability of FPGA hardware facing to a cloud environment, comprising a cloud platform and an FPGA test module; the cloud platform is used for compiling the uploaded hardware language codes to form compiling information and an executable file, and storing and sending the compiling information and the executable file to the FPGA test module; the FPGA test device is also used for receiving and displaying the FPGA test result; the FPGA test module is used for calling an idle FPGA development board to test the executable file to be tested so as to obtain an FPGA test result, and returning the test result to the cloud platform. The system and the method can realize the online test of the hardware language code of the FPGA.

Description

FPGA hardware design capability evaluation system and method oriented to cloud environment

Technical Field

The invention belongs to the field of hardware language testing, and particularly relates to a system and a method for evaluating the design capability of FPGA hardware facing to a cloud environment.

Background

The hardware language test has important significance for the function development of hardware. An Online Join (OJ) test system is a system which authorizes users to answer and submit questions according to the requirements of the questions within a limited time through questions displayed by a webpage and finally returns the answering conditions, and the users only need one computer capable of being networked in the whole test process.

The existing online evaluation systems such as pat (programming instrumentation test) of the university of zhejiang, leetecode question brushing website, and skateboar question recruitment website can only compile, execute and evaluate high-level programming languages such as C + +, Java, and Python, and very few platforms can compile, execute simulation and evaluate hardware language codes.

Fewer online evaluation systems can compile Verilog language (a hardware language) and perform software logic simulation, namely, testing can be realized by a logic algebra operation method. The Jutge platform can evaluate the hardware language, for a combined circuit, an evaluation program provides all possible inputs for simulation operation to obtain a result, but for a module with more input signals, the data volume is increased in a geometric order of magnitude mode; for sequential circuits (which can be seen as essentially making a state machine), even if all inputs are provided, there is no guarantee that all states are correct, i.e. that all states can be entered.

The existing remote FPGA experiment platform, such as a cloud experiment platform ZyCube of the national defense science and technology university, wherein each cloud node is composed of an ARM processor and a closely coupled reconfigurable structure, manual operation hardware and software programming experience can be provided for students, the experiment results of the students cannot be automatically evaluated, and checking and running of each code is a task with large workload.

An existing remote FPGA experiment platform is a WeLab remote experiment platform of the university of Jiangsu. The platform has an excellent experiment operation interface, but the main purpose of the platform is to enable a user to understand the principle of computer composition, a plurality of preset hardware circuit experiments exist in the system, and the user can click and download the hardware circuit experiments and then observe experiment phenomena through a virtual panel. The CPU designed in the system can be programmed to observe the data change. The platform is mainly used for showing and demonstrating, and a user cannot carry out autonomous hardware design and cannot verify own hardware codes.

Existing Integrated Development Environments (IDEs), such as the ISE and Vivado of Xilinx corporation, are capable of performing emulation debugging on hardware code, but are not capable of simulating other peripherals on the Development board, such as the simplest LEDs, etc., array keyboard wait. For hardware programming, debugging the code is more difficult, especially when only a small data error exists in the code, and the position of the error is difficult to locate in long simulation data.

Disclosure of Invention

In view of the above, the present invention provides a system and a method for evaluating the hardware design capability of an FPGA facing a cloud environment, so as to implement an online test on hardware language codes of the FPGA.

In order to achieve the above object, an embodiment of the present invention provides a system for evaluating a hardware design capability of an FPGA, which is oriented to a cloud environment, and includes:

the system comprises a cloud platform and an FPGA test module;

the cloud platform is used for compiling the uploaded hardware language codes to form compiling information and an executable file, and storing and sending the compiling information and the executable file to the FPGA test module; the FPGA test device is also used for receiving and displaying the FPGA test result;

the FPGA test module is used for calling an idle FPGA development board to test an executable file to be tested so as to obtain an FPGA test result, and returning the test result to the cloud platform.

In one embodiment, the cloud platform comprises a Web server, a compiling service module and an FPGA control server;

the Web server is used for receiving the uploaded hardware language codes, storing the uploaded hardware language codes in a database, reading a test file of a test question from the data, compressing the test file and the hardware language codes and transmitting the compressed test file and the compressed hardware language codes to the compiling service module; the system is also used for receiving compiling information and executable files and storing the compiling information and the executable files in a database; the FPGA control server is also used for sending the executable file to the FPGA control server; the FPGA test system is also used for receiving the FPGA test result, storing the FPGA test result in a database and visually displaying the FPGA test result;

the compiling service module is used for compiling the uploaded hardware language codes, generating compiling information and an executable file and transmitting the compiling information and the executable file to the Web server;

the FPGA control server is used for routing the received executable file to an idle PFGA; and the FPGA test result is forwarded to the Web server.

In one embodiment, the compiling service module comprises a plurality of compiling hosts, wherein one compiling host is a main compiling machine, the other compiling hosts are slave compiling machines, the slave compiling machines can be connected in an expandable manner, and the number of the slave compiling machines is not limited;

the master compiler is used for managing and scheduling the slave compilers and forwarding hardware language codes to be compiled to the idle slave compilers; the server is also used for forwarding the compiling information and the executable file from the compiler to the Web server;

and the slave compiler performs a compiling task on the received hardware language code, generates compiling information and an executable file and sends the compiling information and the executable file to the master compiler.

In one embodiment, the slave compiler has a process manager, and a plurality of compiling server processes are started and managed through the process manager to perform compiling tasks on the hardware language codes.

In one embodiment, the FPGA control server includes a socket server and a RocketMQ server;

the socket server is used for receiving a test task which is sent by the Web server and contains an executable file, and is also used for interactively communicating with the FPGA test module, routing the executable file to the FPGA test module, and returning an FPGA test result corresponding to the executable file to the Web server;

the RocktMQ server is used for processing the test tasks sent by the Web server according to a time sequence.

In one embodiment, the FPGA test module comprises a router, a plurality of FPGA development board assemblies, each FPGA development board assembly comprising an FPGA development board and a sub-controller controlling the FPGA development board;

the router is used for routing the executable file to be tested to the idle sub-controllers and also used for routing the FPGA test result to the cloud platform;

the sub-controller is used for controlling the executable file to be burnt into the FPGA development board and controlling the FPGA development board to test the executable file; the FPGA test system is also used for acquiring an FPGA test result and forwarding the FPGA test result to the router;

the FPGA development board is used for testing the executable file and outputting an FPGA test result to the sub-controller.

In one embodiment, the sub-controller is further configured to read a test state of the FPGA development board on the executable file, and obtain an FPGA test result after the test state indicates that the test is finished.

In order to achieve the above object, an embodiment provides a method for evaluating a hardware design capability of an FPGA facing a cloud environment, where the method employs the above system, and the method includes the following steps:

step 1, a cloud platform receives a hardware language code uploaded by a user, compiles the hardware language code to form compilation information and an executable file, and stores and sends the compilation information and the executable file to an FPGA test module;

step 2, the FPGA test module calls an idle FPGA development board to test the received executable file to obtain an FPGA test result, and the test result is returned to the cloud platform;

and 3, the cloud platform displays the received FPGA test result.

In one embodiment, step 1, comprises:

step 1-1, a Web server receives a hardware language code uploaded by a user and stores the hardware language code in a database;

step 1-2, the Web server reads a test file of a test topic from a database, compresses the test file and a hardware language code and transmits the compressed test file and the compressed hardware language code to a compiling service module;

step 1-3, compiling the uploaded hardware language code by a compiling service module to generate compiling information and an executable file and transmitting the compiling information and the executable file to a Web server;

step 1-4, the Web server stores the received compiling information and the executable file in a database;

step 1-5, the Web server inquires whether an FPGA test module has an idle FPGA development board or not and sends an executable file to be tested to an FPGA control server;

and 1-5, the FPGA control server forwards the executable file to be tested to the FPGA test module.

In one embodiment, step 2, comprises:

step 2-1, the router routes the executable file to be tested to an idle sub-controller;

step 2-2, burning the executable file to the FPGA development board by the sub-controller, and controlling the FPGA development board to operate the executable file;

step 2-3, the FPGA development board tests the received executable file and returns the FPGA test result to the sub-controller;

and 2-4, the sub-controller sends the FPGA test result to an FPGA control server through the router.

Compared with the prior art, the invention has the beneficial effects that at least:

the test system and the test method provided by the embodiment are applied to online test of the hardware language code obtained by FPGA hardware design, so that the correctness of the hardware language code is verified remotely through real FPGA hardware, and the test is simple and efficient.

The test system and the test method provided by the embodiment can test the hardware language code on line, and further can evaluate whether the hardware equipment corresponding to the hardware language code for solving the problem of the actual engineering scene is in line with production.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an FPGA hardware design capability evaluation system facing a cloud environment according to an embodiment;

fig. 2 is a schematic structural diagram of an FPGA hardware design capability evaluation method for a cloud environment according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Fig. 1 is a schematic structural diagram of an FPGA hardware design capability evaluation system oriented to a cloud environment according to an embodiment. As shown in fig. 1, the system for evaluating the hardware design capability of an FPGA facing a cloud environment according to the embodiment includes a cloud platform and an FPGA testing module. The cloud platform is deployed at the cloud end and used for compiling the uploaded hardware language codes to form compiling information and an executable file, and storing and sending the compiling information and the executable file to the FPGA test module; and the FPGA test system is also used for receiving and displaying the FPGA test result. The FPGA test module is deployed in the local or other places other than the cloud end and used for calling an idle FPGA development board to test an executable file to be tested so as to obtain an FPGA test result and returning the test result to the cloud platform.

As shown in fig. 1, the cloud platform includes a Web server, a compiling service module, and an FPGA control server. The Web server adopts a django framework based on Python language as a website application framework, and similar Web application frameworks also comprise Spring based on Java, Zend frame based on PHP, AngularJS based on Javascript and the like. The user can access the Web server through a browser through different types of terminal devices such as a computer, a notebook, a mobile phone and a tablet.

In an embodiment, the Web server includes a database, where the database may be a mysql database, and of course, any other database supported by the django framework may also be used.

In the embodiment, the Web server is used for receiving the uploaded hardware language codes, storing the uploaded hardware language codes in the database, reading a test file of a test question from the data, compressing the test file and the hardware language codes and transmitting the compressed test file and the compressed hardware language codes to the compiling service module; the system is also used for receiving compiling information and executable files and storing the compiling information and the executable files in a database; the FPGA control server is also used for sending the executable file to the FPGA control server; and the FPGA test system is also used for receiving the FPGA test result, storing the FPGA test result in a database and visually displaying the FPGA test result.

And the compiling service module is used for compiling the uploaded hardware language codes, generating compiling information and an executable file and transmitting the compiling information and the executable file to the Web server.

In an embodiment, the compiling service module comprises a plurality of compiling hosts, wherein one compiling host is a main compiling machine, the other compiling hosts are slave compiling machines, the slave compiling machines can be connected in an expandable mode, and the number of the slave compiling machines is not limited. The master compiler is used for managing and scheduling the slave compilers and forwarding hardware language codes to be compiled to the idle slave compilers; and also for forwarding compiled information and executable files from the compiler to the Web server. In the embodiment, the compiling host adopts nginx software to perform reverse proxy of HTTP, namely, a user accesses an address, and the nginx software selects one idle slave compiler to provide compiling service according to the load condition of the slave compiler.

Each slave compiler is provided with vivado software, starts a small Web service based on a Python language Tornado framework from the slave compiler for receiving a compiling request, compiles a hardware language code, and returns compiling information and an executable file after compiling is completed. Since each compiling server of the slave compiler can only perform one compiling task at the same time, in order to improve resource utilization, each slave compiler has a process manager (such as a hypervisor process manager), and a plurality of compiling server processes are started and managed by the process manager to perform the compiling task on the hardware language code.

The FPGA control server is used for routing the received executable file to an idle PFGA; and the FPGA test result is forwarded to the Web server. In the embodiment, the FPGA control server includes a socket server and a rockmq server, is essentially a communication transfer station, and has a specific function of managing and controlling the FPGA test modules, taking charge of collection and distribution of test tasks, taking charge of interaction and communication with sub-controllers in all the FPGA test modules, and taking charge of providing the test state and the FPGA test result of the FPGA to the Web server.

The socket server is used for receiving a test task which is sent by the Web server and contains an executable file, and is also used for interactively communicating with the FPGA test module, routing the executable file to the FPGA test module, and returning an FPGA test result corresponding to the executable file to the Web server. The RocktMQ server is used for processing the test tasks sent by the Web server according to the time sequence, so that the performance of the platform is improved while the test sequence is ensured.

The FPGA test module comprises a router and a plurality of FPGA development board assemblies, and each FPGA development board assembly comprises an FPGA development board and a sub-controller for controlling the FPGA development board. The sub-controllers can be realized by raspberry pies, and can also be realized by controllers such as stm32, a single chip microcomputer and other ARM development boards. The FPGA development board can adopt a SWORD4 development board, and of course, development boards of other versions of SWORD, development boards of Xilinx ZYNQ series and the like can also be adopted.

In the embodiment, the router is used for routing the executable file to be tested to the idle sub-controllers and is also used for routing the FPGA test result to the FPGA control server of the cloud platform.

In the embodiment, the sub-controller is used for controlling the executable file to be burnt into the FPGA development board and controlling the FPGA development board to test the executable file; and the FPGA test result is obtained and forwarded to the router. Specifically, the sub-controller is realized by using the raspberry group 3B, a python program is operated, a djtgcfg tool is used for reading the model of the FPGA chip and burning an executable file in a JTAG mode, a GPIO port of the raspberry group and a DuPont line are used for connecting a pin on the FPGA with an IO pin of the raspberry group sub-controller, the pin and the IO pin are connected with the common ground (the voltage of GND is the same), and the communication process of the sub-controller and the FPGA development board can be completed by adopting physical sampling.

In the embodiment, the FPGA development board is used for testing the executable file and outputting the FPGA test result to the raspberry dispatching controller.

Fig. 2 is a schematic structural diagram of an FPGA hardware design capability evaluation method for a cloud environment according to an embodiment. The evaluation method adopts the test system. As shown in fig. 2, the method for evaluating the hardware design capability of the FPGA according to the embodiment includes the following steps:

step 1, a user logs in the system, the user submits a tested hardware language code, and the Web server stores the hardware language code and records the submitting state of the user as 'submitting'.

And 2, packaging and compressing the test file of the corresponding title and the hardware language code into zip by the Web server, and uploading the compressed package to the compiling service module.

Step 3, the compiling service module distributes a compiling server to decompress the compressed packet and complete a compiling task;

step 4, after compiling is completed, compiling information and executable files are returned to a database of the Web server for storage and user interface display, and if compiling is successful, the fact that compiling is successful is displayed, and subsequent processes are continued; otherwise, displaying 'compiling failure' and terminating the test flow;

step 5, the Web server sends the executable file to an FPGA control server, the FPGA control server creates a test task and pushes the test task to a task queue of a RockettMQ server, and whether an FPGA development board is idle is detected in a circulating mode;

step 6, if the FPGA development board is idle, acquiring a test task submitted earliest in the RocktMQ server, and sending an executable file of the test task to a sub-controller corresponding to the idle FPGA development board;

step 7, after receiving the executable file, the sub-controllers update the state of the sub-controllers to be busy, execute burning work and automatically start testing, namely the FPGA development board realizes testing by comparing correct results with calculation results of the file to be executed;

step 8, circularly reading the test state of the FPGA development board through the serial port by the sub-controller, and waiting for the test to be completed;

step 9, after receiving a test completion signal provided by the FPGA, the sub-controller reads back a test result through a serial port, sends the test result to the FPGA control server, and changes the state of the sub-controller from busy to idle;

step 10, the FPGA control server transmits the test result back to the Web server and updates the state submitted by the user;

and 11, the Web server stores the test result in the database and displays the test result to the user, so that the test is finished.

The FPGA hardware design capability evaluation system and the FPGA hardware design capability evaluation method provided by the embodiment can enable a user to verify whether a designed hardware language code is correct at any time and any place, namely, a functional test can be carried out, and the user does not need to specially go to a place with hardware for verification.

Compared with the existing simulation test, the FPGA hardware design capability evaluation system and method provided by the embodiment have more physical authenticity, and can perform physical experiments on hardware according to user requirements, such as testing of contents completely related to the hardware, such as memory drive design and the like in a fidelity manner.

The FPGA hardware design capability evaluation system and method provided by the embodiment are simple and efficient in test, cost can be saved, and the use efficiency of physical equipment is improved.

Aiming at specific engineering problems, a user can edit hardware language codes on line, and submit the FPGA hardware design capability evaluation system provided by the embodiment for testing, so that a physical detection result of a user writing module on an FPGA development board can be obtained. For the combinational circuit, physical verification can be carried out on all legal inputs, and key data (boundary data (such as 0 of a natural number)) can be selected according to the requirement of a theme for testing; for a sequential circuit, detecting output corresponding to a state which is possibly reached by a pre-designed execution flow according to a module application scene; detecting the output, thereby being able to check whether the state transition is correct; different state transitions can be detected according to different inputs of an application scene, so that the correct function of the module in the scene of the theme can be ensured.

The FPGA hardware design capability evaluation system provided by the embodiment can allow a user to interact with physical hardware on an FPGA development board at the rear stage of the system in a controllable range, so that the user can seamlessly migrate to a local FPGA development board if the user has the same development board.

For some functional modules, corresponding test questions are designed based on the system, developers design the functional modules and submit tests, communication cost between a demand side and designers is reduced, and the acceptance process of the functional modules is simplified.

The FPGA hardware design capability evaluation system and method provided by the embodiment can provide convenience for teaching and help teachers test hardware language codes provided by students to evaluate the hardware programming capability of the students.

The FPGA hardware design capability evaluation system and method provided by the embodiment can test hardware language codes of enterprises to help select people with excellent hardware programming capability.

The test implemented by the system and the method for evaluating the hardware design capability of the FPGA in the hardware language provided by the embodiment can also perform software simulation on Verilog codes through other tools such as open source software verilator on gitubs, and can also complete evaluation of code logicality through simulation, but the software simulation cannot completely simulate the time sequence on the hardware with fidelity, that is, the software simulation cannot necessarily work correctly physically through 100%.

The above-mentioned embodiments are intended to illustrate the technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only the most preferred embodiments of the present invention, and are not intended to limit the present invention, and any modifications, additions, equivalents, etc. made within the scope of the principles of the present invention should be included in the scope of the present invention.

Claims

1. A FPGA hardware design capability evaluation system facing a cloud environment is characterized by comprising a cloud platform and an FPGA test module;

the FPGA test module is used for calling an idle FPGA development board to test the executable file to be tested so as to obtain an FPGA test result, and returning the test result to the cloud platform.

2. The system for evaluating the hardware design capability of the FPGA facing the cloud environment according to claim 1, wherein the cloud platform comprises a Web server, a compiling service module and an FPGA control server;

3. The system for evaluating the hardware design capability of the FPGA facing the cloud environment according to claim 2, wherein the compiling service module comprises a plurality of compiling hosts, one of the compiling hosts is a main compiling machine, the other compiling hosts are slave compiling machines, the slave compiling machines can be connected in an expandable manner, and the number of the slave compiling machines is not limited;

4. The system for evaluating the hardware design capability of the FPGA facing the cloud environment according to claim 3, wherein the slave compiler has a process manager, and a plurality of compilation server processes are started and managed by the process manager to perform compilation tasks on the hardware language codes.

5. The cloud environment-oriented FPGA hardware design capability evaluation system according to claim 3, wherein the FPGA control server comprises a socket server and a RockketMQ server;

6. The cloud environment-oriented FPGA hardware design capability evaluation system of claim 1, wherein the FPGA test module comprises a router, a plurality of FPGA development board assemblies, each FPGA development board assembly comprising an FPGA development board and a sub-controller controlling the FPGA development board;

the router is used for routing the executable file to be tested to an idle sub-controller and also used for routing the FPGA test result to the cloud platform;

7. The cloud-environment-oriented FPGA hardware design capability evaluation system according to claim 6, wherein the sub-controller is further configured to read a test state of the FPGA development board for the executable file, and obtain the FPGA test result after the test state indicates that the test is finished.

8. An FPGA hardware design capability evaluation method oriented to a cloud environment, characterized in that the method adopts the system of any one of claims 1-7, and the method comprises the following steps:

and 3, the cloud platform displays the received FPGA test result.

9. The method for evaluating the hardware design capability of the FPGA facing the cloud environment according to claim 8, wherein the step 1 comprises the following steps:

10. The method for evaluating the hardware design capability of the FPGA facing the cloud environment according to claim 8, wherein the step 2 comprises the following steps: