CN112231165B - Memory fault simulation method based on link library injection and memory mapping modes - Google Patents
Memory fault simulation method based on link library injection and memory mapping modes Download PDFInfo
- Publication number
- CN112231165B CN112231165B CN202011053886.8A CN202011053886A CN112231165B CN 112231165 B CN112231165 B CN 112231165B CN 202011053886 A CN202011053886 A CN 202011053886A CN 112231165 B CN112231165 B CN 112231165B
- Authority
- CN
- China
- Prior art keywords
- command
- memory
- fault
- fault simulation
- allocation failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a memory fault simulation method based on a link library injection and memory mapping mode, which comprises the following steps: the fault simulator is started on the target server, a command interface is initialized, a user inputs a fault simulation command, the fault simulator transmits the command to Command Dispatcher and Command Dispatcher to analyze the fault simulation command after receiving the fault simulation command, and a corresponding command processor is found according to a command mapping table; and the command processor completes corresponding fault injection according to the corresponding fault simulation command. The memory fault simulation method based on the link library injection and memory mapping modes can simulate the memory fault on the premise of not damaging the memory hardware, and is used for verifying the disaster tolerance of software to the memory fault. With non-intrusive transparency, the original hardware does not need to be destroyed and the original code does not need to be modified.
Description
Technical Field
The invention relates to the technical field of memory faults, in particular to a memory fault simulation method based on a link library injection and memory mapping mode.
Background
With the development of technology, computers have entered into thousands of households. The hardware system of the computer is composed of an arithmetic unit, a controller, a memory, an input device and an output device. The memory in a computer is divided into a memory and an external memory. The memory is used for storing programs and data which are currently used or are used at any time. Once the memory is in error or fault, the program can not work normally or be down. Therefore, the method has important significance in researching possible faults of the memory.
Memory failure is one of the most common failures in computer systems, and in critical systems with extremely high availability requirements, it is necessary to evaluate their fault tolerance to memory failures. The most effective method for evaluating fault tolerance mechanism by fault injection. The fault injection is to aim at specific fault models, consciously promote faults in a target system, accelerate the occurrence of errors and failures, and verify the fault tolerance, the fault safety and other information by analyzing the response information of the system to the injected faults.
Disclosure of Invention
The invention provides a memory fault simulator which simulates memory faults on the premise of not damaging memory hardware by means of link library injection and memory mapping, and is used for verifying the disaster tolerance of software to the memory faults.
The invention relates to a memory fault simulation method based on a link library injection and memory mapping mode, which comprises the following steps:
1. the memory fault simulation method based on the link library injection and memory mapping modes is characterized by comprising the following steps of:
A. the fault simulator is started on the target server, a command interface is initialized, and a user waits for inputting a fault simulation command;
B. the user inputs fault simulation commands, including a memory allocation failure command and a memory shortage command;
C. after receiving the fault simulation command, the fault simulator transmits the fault simulation command to Command Dispatcher and Command Dispatcher to analyze the fault simulation command, and finds a corresponding command processor according to the command mapping table;
D. and the command processor completes corresponding fault injection according to the corresponding fault simulation command.
The invention simulates the memory fault on the premise of not damaging the memory hardware, is used for verifying the disaster tolerance of software to the memory fault, has non-invasive transparency, does not need to damage the original hardware, and does not need to modify the original code.
Further, step D includes: the fault simulation command comprises a memory allocation failure command and a memory shortage command;
the memory allocation failure command is executed as follows:
after receiving the allocation failure command, the fault simulator sets an LD_PRELOAD environment variable to an operating system, loads newmalloc.so with a memory allocation failure function in advance, covers malloc and brk functions in glibc.so, and when software applies for a memory through the malloc and brk functions, memory allocation failure occurs;
the execution steps of the memory shortage command are as follows:
after receiving the memory shortage command, the command processor firstly executes mkdir-p/mnt/tmpfs & & mount tmpfs/mnt/tmpfs-t tmpfs to map the file into the memory; and then circularly executing dd if=/dev/zero of=/mnt/tmpfsbs=1m and then writing 1M data into the memory mapping file, wherein the memory of the system is continuously reduced, namely the memory deficiency occurs.
The command principle of the step D memory allocation failure is as follows: the software process runs on a run time provided by the operating system, which provides malloc, brk functions for software use to apply for memory to the operating system, and any memory allocation function is ultimately implemented using brk. The malloc, brk functions are located in glibc.
The command principle of the step D of insufficient memory is as follows: the operating system supports mapping a part of the memory into a file through memory mapping, and can conveniently consume a large amount of memory of the operating system by writing a large amount of data into the mapped file, so that the fault of insufficient memory is simulated.
The memory fault simulation method based on the link library injection and memory mapping modes can simulate the memory fault on the premise of not damaging the memory hardware, and is used for verifying the disaster tolerance of software to the memory fault. With non-intrusive transparency, the original hardware does not need to be destroyed and the original code does not need to be modified.
Drawings
FIG. 1 is a schematic diagram of a memory failure simulation architecture according to the present invention.
FIG. 2 is a schematic diagram of an architecture for simulating memory starvation caused by memory failure according to the present invention.
Detailed Description
The foregoing of the invention will be described in further detail with reference to the following detailed description of the examples. It should not be understood that the scope of the above subject matter of the present invention is limited to the following examples only. Various substitutions and alterations are also possible, without departing from the spirit of the invention, and are intended to be within the scope of the invention.
The architecture of the present invention as shown in figure 1 simulates the memory failure resulting in the application memory failure,
the fault simulator sets an LD_PRELOAD environment variable to an operating system, loads newmalloc.so with a memory allocation failure function in advance, covers malloc and brk functions in glibc.so, and when software applies for a memory through the malloc or brk functions, memory allocation failure occurs;
the fault simulator is started on the target server, a command interface is initialized, and a user inputs a memory allocation failure command; after receiving the memory allocation failure command, the fault simulator transmits the command to Command Dispatcher and Command Dispatcher to analyze the fault simulation command, and finds a corresponding command processor according to a command mapping table; after triggering a memory allocation failure command, the fault simulator sets an LD_PRELOAD environment variable to an operating system, loads newmalloc.so with a memory allocation failure function in advance, covers malloc and brk functions in glibc.so, and when software applies for a memory through the malloc or brk functions, memory allocation failure occurs;
as shown in FIG. 2, the architecture of the present invention simulates the memory failure resulting in insufficient memory
The fault simulator first executes mkdir-p/mnt/tmpfs & & mount tmpfs/mnt/tmpfs-t tmpfs to map the file into memory. Then, the dd if=/dev/zero of=/mnt/tmpfsbs=1m is circularly executed, and 1M data is written into the memory mapping file, at this time, the system memory is continuously reduced, and the memory deficiency simulation is successful.
The specific steps are that the fault simulator is started on the target server, a command interface is initialized, a user inputs a memory shortage command, the fault simulator transmits the command to Command Dispatcher and Command Dispatcher to analyze the fault simulation command after receiving the memory shortage command, and a corresponding command processor is found according to a command mapping table; after the command processor triggers the memory shortage command, the fault simulator firstly executes mkdir-p/mnt/tmpfs & & mount tmpfs/mnt/tmpfs-t tmpfs to map the file into the memory. Then, the dd if=/dev/zero of=/mnt/tmpfsbs=1m is circularly executed, and 1M data is written into the memory mapping file, at this time, the system memory is continuously reduced, and the memory deficiency simulation is successful.
Claims (1)
1. The memory fault simulation method based on the link library injection and memory mapping modes is characterized by comprising the following steps of:
A. the fault simulator is started on the target server, a command interface is initialized, and a user waits for inputting a fault simulation command;
B. the user inputs fault simulation commands, including a memory allocation failure command and a memory shortage command;
C. after receiving the fault simulation command, the fault simulator transmits the fault simulation command to Command Dispatcher and Command Dispatcher to analyze the fault simulation command, and finds a corresponding command processor according to the command mapping table;
D. the command processor triggers corresponding faults according to the corresponding fault simulation commands;
the step D comprises the following steps: the fault simulation command comprises a memory allocation failure command and a memory shortage command;
the memory allocation failure command is executed as follows:
after receiving the allocation failure command, the fault simulator sets an LD_PRELOAD environment variable to an operating system, loads newmalloc.so with a memory allocation failure function in advance, covers malloc and brk functions in glibc.so, and when software applies for a memory through the malloc and brk functions, memory allocation failure occurs;
the execution steps of the memory shortage command are as follows:
after receiving the memory shortage command, the command processor firstly executes mkdir-p/mnt/tmpfs & & mount tmpfs/mnt/tmpfs-t tmpfs to map the file into the memory; and then circularly executing dd if=/dev/zero of=/mnt/tmpfsbs=1m and then writing 1M data into the memory mapping file, wherein the memory of the system is continuously reduced, namely the memory deficiency occurs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011053886.8A CN112231165B (en) | 2020-09-29 | 2020-09-29 | Memory fault simulation method based on link library injection and memory mapping modes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011053886.8A CN112231165B (en) | 2020-09-29 | 2020-09-29 | Memory fault simulation method based on link library injection and memory mapping modes |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112231165A CN112231165A (en) | 2021-01-15 |
CN112231165B true CN112231165B (en) | 2023-06-06 |
Family
ID=74120810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202011053886.8A Active CN112231165B (en) | 2020-09-29 | 2020-09-29 | Memory fault simulation method based on link library injection and memory mapping modes |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112231165B (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111491037A (en) * | 2020-06-28 | 2020-08-04 | 四川新网银行股份有限公司 | Communication method with object storage server through SFTP data stream |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10387239B2 (en) * | 2017-04-10 | 2019-08-20 | Western Digital Technologies, Inc. | Detecting memory failures in the runtime environment |
US11204861B2 (en) * | 2019-03-05 | 2021-12-21 | Honeywell International Inc. | Systems and methods for fault injection and ensuring failsafe FMS SaaS platforms |
-
2020
- 2020-09-29 CN CN202011053886.8A patent/CN112231165B/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111491037A (en) * | 2020-06-28 | 2020-08-04 | 四川新网银行股份有限公司 | Communication method with object storage server through SFTP data stream |
Non-Patent Citations (3)
Title |
---|
一种面向龙芯3A平台的软件模拟故障注入系统设计与实现;苏雄;《中国优秀硕士论文》;第3章 * |
网络模式的电网故障仿真培训系统;王振江,盛四清,顾雪平;广西电力(第02期);12-14+17 * |
面向单粒子翻转效应的模拟故障注入技术;于航;王晶;周继芹;李亚;张伟功;;计算机工程与设计(第01期);115-119+139 * |
Also Published As
Publication number | Publication date |
---|---|
CN112231165A (en) | 2021-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7209034B2 (en) | Edge computing test method, apparatus, equipment and readable storage medium | |
KR101132560B1 (en) | System and method for automatic interface testing based on simulation for robot software components | |
US9898388B2 (en) | Non-intrusive software verification | |
US20190034318A1 (en) | Hardware-Software Co-Verification for Debugging Firmware on a Hardware Simulator | |
US20090248390A1 (en) | Trace debugging in a hardware emulation environment | |
US9824000B1 (en) | Testing calling code dynamically with random error injection based on user-specified configuration | |
CN109933521A (en) | Automated testing method, device, computer equipment and storage medium based on BDD | |
US7783927B2 (en) | Intelligent processing tools | |
CN110704315B (en) | Fault injection device for embedded software test | |
CN111459814A (en) | Automatic test case generation method and device and electronic equipment | |
CN105453033A (en) | Program testing service | |
CN102331961B (en) | Method, system and dispatcher for simulating multiple processors in parallel | |
CN112231165B (en) | Memory fault simulation method based on link library injection and memory mapping modes | |
Bansal et al. | Taming complexity while gaining efficiency: Requirements for the next generation of test automation tools | |
CN103077104B (en) | Verification method, device and system for on-chip system | |
CN115757099A (en) | Automatic test method and device for platform firmware protection recovery function | |
CN112765018B (en) | Instrument and meter debugging system and method | |
RU2729210C1 (en) | Electronic devices software testing system | |
CN112765021A (en) | Debugging and checking method, device, equipment and storage medium of boot program | |
CN113917859B (en) | Method for constructing complex safety logic link model of radar servo system | |
EP4113282A1 (en) | Method and system for generating programs for an automation system by code-similarity based approach | |
CN114692382B (en) | Management method and device for nuclear power simulation model development data and computer equipment | |
EP4141653A1 (en) | Method and system for generating engineering programs which are compatible with a specific engineering environment | |
CN114327648B (en) | Driving debugging method and device, electronic equipment and storage medium | |
CN110309038B (en) | Performance test method and device, electronic equipment and computer readable storage medium |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |