CN114650192B - CRPB bus system - Google Patents
CRPB bus system Download PDFInfo
- Publication number
- CN114650192B CN114650192B CN202011499678.0A CN202011499678A CN114650192B CN 114650192 B CN114650192 B CN 114650192B CN 202011499678 A CN202011499678 A CN 202011499678A CN 114650192 B CN114650192 B CN 114650192B
- Authority
- CN
- China
- Prior art keywords
- power supply
- bus
- polling
- response
- slave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000004044 response Effects 0.000 claims abstract description 97
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 53
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 4
- 230000005669 field effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 16
- 230000009467 reduction Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000004891 communication Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005316 response function Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a CRPB bus system, which can be applied to a master multi-slave electronic system, and comprises: the bus harness is provided with a ground wire and a bidirectional signal/power multiplexing wire; a set of host bus circuits having a host bus control module, a power switch module coupled to the multiplexing line, a polling signal transmitting unit, and a response receiving unit; at least one group of slave bus circuits having a slave bus control module, a power supply and voltage stabilizing module coupled to the multiplexing line, a polling signal receiving unit and a reply transmitting unit; the high-low level is alternately output through a first port of a host bus control module connected with a switch control end of a power supply switch module, so that the bus system alternately enters a power supply period T1 or a state polling and response period T2. The invention adopts the polling response/power multiplexing technology, and can realize the reduction of transmission time and the reduction of the number of transmission lines.
Description
Technical Field
The invention belongs to the technical field of buses, and particularly relates to a polling response power bus system.
Background
Among the electronic systems composed of a master and a plurality of slaves (referred to as "a master-multi-slave electronic system"), there are a kind of remote one-master-multi-slave electronic systems, such as multi-node interactive entertainment systems, stage control systems, conference systems, etc., and such remote one-master-multi-slave electronic systems generally have the following characteristics: 1) The number of the master computers is 1, and the maximum number of the slaves can reach 200; 2) The maximum distance between the slave and the host can reach 1000 meters; 3) The state of the slave is sent to the host, and the state of the slave is only two (with or without, true or false); 4) The slave state is to be sent to the master in a very short time (e.g., less than 10 ms); 5) The power supply of the slave is provided by the host; 6) The number of wires between the master and the slave is as small as possible, preferably 2 wires.
At present, transmission buses with the transmission distance of 1000 meters mainly comprise an RS-422 bus and an RS-485 bus. When these external buses are used in a remote one-master-multiple-slave electronic system, there are two problems that are: 1) The delay does not meet the requirements; 2) The number of lines is high.
The above problems are described by taking an RS-485 bus as an example in connection with fig. 1. In the case of using the RS-485 bus as the transmission bus, in order to prevent a plurality of slaves (for example, 100 slaves numbered 1, 2 slaves numbered 2, …, 100 slaves in sequence) from simultaneously transmitting data and causing data errors, the master can only use a polling method to receive the data of the slaves. The polling process is as follows: the host computer sends the code of the No. 1 slave computer, all the slave computers receive the code, and only the No. 1 slave computer judges that the code is consistent with the number of the slave computer, so the No. 1 slave computer sends the state of the code to the host computer; next, the master sends the code of slave No. 2, and so on, until slave No. 100 sends its status to the master. Therefore, the time taken for one poll (from 1 to 100) is the product of the time of a single transmission and reception and the number of slaves. When the UART (universal asynchronous receiver transmitter) +RS-485 bus is adopted for communication, if the transmission baud rate is 9600, the transmission format is 1-bit start bit, 8-bit data bit and 1-bit stop bit. The time of single transmission or reception is 10/9600=1.04 ms, and thus the transmission time is about 100×2×1.04 ms=208 ms, and it is obvious that the system requirements cannot be satisfied. If the communication is performed in a half duplex mode, the number of wires is 4, wherein the number of the RS-485 buses is 2, the number of the power supply wires is 1, and the number of the ground wires is 1. If the communication is performed in a full duplex mode, the number of lines is 6, wherein the number of RS-485 buses is 4, the number of power supply lines is 1, and the number of ground lines is 1. In addition, the RS-485 bus has the problems that communication cannot be performed when common mode interference is large, a certain node fault can affect adjacent nodes, and the like, and the fault rate is high. In addition, because the RS485 needs to use chips such as photoelectric isolation and the like when in use, the cost is higher than that of devices such as a common photoelectric coupler and the like.
Therefore, the existing bus application has the technical problems of long transmission time and more connection lines in the application of a remote one-master-multiple-slave electronic system, and the problems of high fault rate, high cost and the like in the conventional bus application are also solved.
Disclosure of Invention
In order to solve the problems of longer transmission time and more connection lines in the application of the existing bus in a long-distance one-master-multiple-slave electronic system, the invention provides a polling response power bus system, also called CRPB (Circular query Response Power Bus) bus system, which can realize the reduction of transmission time and the reduction of the number of transmission lines by adopting a polling response/power multiplexing technology.
The invention discloses a CRPB bus system, which can be applied to a master multi-slave electronic system, and comprises:
the bus harness is provided with a ground wire and a bidirectional signal/power multiplexing wire;
a set of host bus circuits having a host bus control module, a power switch module coupled to the multiplexing line, a polling signal transmitting unit, and a response receiving unit;
at least one group of slave bus circuits having a slave bus control module, a power supply and voltage stabilizing module coupled to the multiplexing line, a polling signal receiving unit and a reply transmitting unit;
the method comprises the steps that a first port of a host bus control module connected with a switch control end of a power supply switch module is controlled to alternately output high and low levels, so that the bus system alternately enters a power supply period T1 or a state polling and response period T2;
the power supply period T1: the power supply switch module is started, the first power supply reaches the multiplexing line through the power supply switch module, and the power supply and the voltage stabilizing module output the power to supply power to the slave;
the status poll and response period T2: the power supply switch module is closed, the host computer sends a polling pulse signal to the multiplexing line through the polling signal sending unit, and the slave computer receives the polling pulse signal through the polling signal receiving unit and responds to the polling pulse signal according to the state of the slave computer; the slave machine self state comprises a first state and a second state. For example, the first state is "there" and the second state is "no"; the first state is true and the second state is false.
As a preferred scheme, the status poll and response period T2:
the host computer sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and specifically comprises the following steps: the second port of the host bus control module connected with the input end of the polling signal transmitting unit is controlled to alternately output high and low levels, so that an occupied state and an idle state alternately appear on the multiplexing line to form the polling pulse signal; adjacent occupied states and idle states form a query period, each query period corresponds to a slave number, and the query periods of all the slaves form a polling period;
the slave machine receives the polling pulse signal through the polling signal receiving unit, and when judging that the polling period corresponds to the number of the slave machine, the slave machine selectively transmits a response pulse signal to the multiplexing line or does not respond according to the state of the slave machine when the slave machine is in an idle state through the response transmitting unit;
the host receives the response pulse signal through the response receiving unit and judges that the slave with the corresponding number has a response.
As a preferable scheme, in the inquiry period, the time width of the occupied state is consistent with that of the idle state; the occupied state is forward and the idle state is backward.
As a preferable scheme, the power supply end of the power supply switch module is connected with a first power supply, and the switch control end is connected with a first port of the host bus control module; the input end of the polling signal transmitting unit is connected with the second port of the host bus control module; the output end of the response receiving unit is connected with a third port of the host bus control module; the output end of the power supply switch module, the output end of the polling signal transmitting unit and the first input end of the response receiving unit are respectively connected to the multiplexing line;
the power supply and voltage stabilizing module is provided with a power supply sensing unit and a voltage stabilizing unit, and the output end of the power supply sensing unit is connected with the voltage stabilizing unit; the input end of the response transmitting unit is connected with the first port of the slave bus control module; the output end of the polling signal receiving unit is connected with the second port of the slave bus control module; the input end of the power supply sensing unit, the input end of the polling signal receiving unit and the output end of the response transmitting unit are respectively connected to the multiplexing line;
the power supply switch module, the polling signal transmitting unit, the response receiving unit, the power supply sensing unit, the voltage stabilizing unit, the polling signal receiving unit and the grounding end of the response transmitting unit are connected with a ground wire;
the host judges whether the multiplexing line is in an idle state or an occupied state according to the level of a third port of the bus control module; and the slave judges whether the multiplexing line is in an idle state or an occupied state according to the level of the second port of the bus control module.
As a preferable scheme, the power supply end of the polling signal transmitting unit is connected with a second power supply; the second input end of the response receiving unit is connected with a second power supply, and the output end of the response receiving unit is also connected with a third power supply;
the voltage stabilizing unit is constructed to comprise a primary voltage stabilizing unit and a secondary voltage stabilizing unit which are sequentially connected; the input end of the primary voltage stabilizing unit is connected with the output end of the power supply sensing unit, and the output end is also respectively connected with the second input end of the polling signal receiving unit and the power supply end of the response transmitting unit; the output end of the secondary voltage stabilizing unit is also connected with the output end of the polling signal receiving unit; the power supply sensing unit is also provided with a reference voltage end, and the reference voltage end is connected with the output end of the primary voltage stabilizing unit or the secondary voltage stabilizing unit.
As a preferable scheme, the voltage of the output end of the primary voltage stabilizing unit is equal to the voltage of the second power supply, and/or the voltage of the output end of the secondary voltage stabilizing unit is equal to the voltage of the third power supply.
As a preferred scheme, the power supply switch module is realized by a first switch circuit controlled by a first switch device, wherein the first switch device comprises at least one of a bipolar transistor and a field effect transistor; the power supply sensing unit is realized by a second switching circuit controlled by a second switching device, and the second switching device comprises at least one of a bipolar transistor and a field effect transistor;
when the first switch circuit and the second switch circuit are both conducted, the bus system enters a power supply period T1; when the first switch circuit and the second switch circuit are opened, the bus system enters a state polling and response period T2.
As a preferable scheme, the polling signal transmitting unit is realized by a third switching circuit controlled by a polling switch, and the polling switch comprises at least one of a bipolar transistor and a field effect transistor; the response receiving unit is realized by adopting a first optocoupler circuit; the response transmitting unit is realized by a fourth circuit controlled by a response switch, and the response switch comprises at least one of a bipolar transistor and a field effect transistor; the polling signal receiving unit is realized by adopting a second optical coupler circuit;
when the third switch circuit and the fourth switch circuit are turned off, the bus system is in an idle state in a state polling and response state; when the third switch circuit or any one of the fourth switch circuits is turned on, the bus system is in an occupied state of state polling and response states.
As a preferred scheme, the third switching circuit and the fourth switching circuit adopt the same circuit design; the first optocoupler circuit and the second optocoupler circuit adopt the same circuit design comprising the optocoupler.
As a preferable scheme, the host bus control module is a separate processor or is integrated in the host processor; and/or the slave bus control module is a stand-alone processor or is integrated in a slave processor.
The invention has the following technical effects:
(1) The CRPB bus system disclosed by the invention adopts a polling response and power multiplexing mode, can complete bus requirements by only 2 wires, and can realize that the polling period of the bus is controlled within 10 ms.
(2) The CRPB bus system disclosed by the invention adopts the photoelectric coupler at the receiving ends of the host and the slave, so that the output voltage of the receiving end is ensured to be only taken from the power supply of the receiving end, and the interference increase caused by long-distance power taking is avoided.
(3) The CRPB bus system disclosed by the invention adopts a current-driven circuit mode for bus communication, has stronger anti-interference capability, and can achieve a transmission distance of 1000 meters.
(4) The CRPB bus system disclosed by the invention has the advantages of simple structure, low cost, relatively independent nodes and low failure rate.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of an RS-485 transmission bus in a master multi-slave electronic system;
FIG. 2 is a schematic diagram of the overall structure of a CRPB bus system in a master multi-slave electronic system 1;
FIG. 3 is a schematic diagram of the overall structure of a CRPB bus system in a master multi-slave electronic system 2;
FIG. 4 is a schematic circuit diagram of a CRPB bus system;
FIG. 5 is a schematic diagram of a power supply and voltage regulation circuit;
FIG. 6 is a schematic diagram of a status poll and response module architecture;
FIG. 7 is a schematic diagram of power and poll response timing for the CRPB bus;
FIG. 8 is a schematic diagram of a poll response timing of the CRPB bus;
fig. 9 is a schematic diagram of the time characteristics of the poll response/power bus.
Detailed Description
The invention is further illustrated by the following description in conjunction with the accompanying drawings and specific embodiments.
Referring to fig. 2 to 6, the invention discloses a polling response power bus system suitable for a remote one-master-multiple-slave electronic system, which is also called CRPB (Circular query Response Power Bus) bus system, and mainly comprises a host bus circuit, a slave bus circuit and a bus harness, wherein the bus harness is composed of 2 wires, one is a bidirectional signal/power multiplexing wire (abbreviated as a multiplexing wire, a bus or a CRPB bus), and the other is a ground wire. The ground wire is mainly used for connecting the ground terminal of each device, and is not drawn in other figures for simplifying the illustration. It should be understood that in practical application, in a master-multi-slave electronic system, there are typically more than two slaves, and for simplicity of illustration and description, the reference numerals of the respective slaves are collectively indicated in the embodiment, and only one slave is shown in the circuit configuration diagram.
In FIG. 4, section A is mainly used for power supply and voltage regulation, wherein A Main unit Power supply switch module for host machine A From the slave The power supply and voltage stabilizing module is used for the slave. Part B is mainly used for status polling and response, wherein part B Main unit A poll signal sending and response receiving module for the host, B From the slave A module for receiving and responding to the polling signal of the slave.
The host bus circuit mainly comprises a host bus processor, and a power supply switch module, a polling signal transmitting and receiving module, which are connected with the host bus processor. The power supply switch module (also called a power supply circuit) can be realized by a common MOS tube switch circuit, a bipolar transistor (triode) switch circuit and the like, and is provided with at least four ports of an input end, an output end, a switch control end and a grounding end, so that all the slaves can use electricity. The input end of the power supply switch module is connected with the power supply V1, the output end of the power supply switch module is connected with the bus, the switch control end of the power supply switch module is connected with the port 1 of the host bus processor, the power supply switch module receives a high-level or low-level signal output by the port 1 of the host bus processor, and the grounding end of the power supply switch module is connected with the ground wire. In this embodiment, the switching device in the power supply switching module mainly includes a P-type MOS transistor Q1 and an NPN-type triode Q2, the power supply V1 is connected to the bus through the MOS transistor Q1, the port 1 of the host bus processor is connected to the base (i.e., the control end) of the triode Q2, and the collector of the triode Q2 is connected to the gate of the MOS transistor Q1 through R6. When the port 1 of the host bus processor outputs a high level, the triode Q2 and the MOS tube Q1 are sequentially conducted, so that the power supply switch module is in an on state, and a power supply function is realized; and in the closed state, switching to a polling signal transmitting and response receiving function.
The polling signal transmitting and receiving module includes a polling signal transmitting unit and a polling signal receiving unit. The polling signal transmitting unit is used for transmitting a polling signal to the bus, and can be realized by a MOS transistor switch circuit, a bipolar transistor (triode) switch circuit and the like, and is also called a host transmitting circuit, and is provided with an input end, an output end, a power end and a grounding end. The input end of the polling signal transmitting unit is connected with the port 2 of the host bus processor, the output end of the polling signal transmitting unit is connected with the bus, the power supply end of the polling signal transmitting unit is connected with the power supply V2, and the grounding end of the polling signal transmitting unit is connected with the ground wire. In this embodiment, the switching device in the polling signal sending unit mainly includes an NPN transistor Q6 and an N-type MOS transistor Q4, the port 2 of the host bus processor is connected to the bus through a resistor R14, a transistor Q6, a resistor R12, and an MOS transistor Q4 that are sequentially connected, when the port 2 outputs a low level, the transistor Q6 is turned off, the MOS transistor Q4 is turned on, the bus enters an occupied state, whereas the transistor is turned on, the MOS transistor Q4 is turned off, and the bus enters an idle state.
The response receiving unit can be realized by adopting an optical coupling circuit, also called a host receiving circuit, and is used for receiving the slave response pulse signal from the bus, wherein the input end of the response receiving unit is connected with the bus, and the output end of the response receiving unit is connected with the port 3 of the bus processor. The optocoupler circuit is provided with an optocoupler, and is mainly used for isolating the signal coupling relation of each voltage and avoiding the mutual interference of signals. The first input end of the photoelectric coupler U1 is connected with a power supply V2 output by the primary voltage stabilizing unit, the second input end of the photoelectric coupler U1 is connected with the multiplexing line, the first output end of the photoelectric coupler U1 is connected with a power supply V3 output by the secondary voltage stabilizing unit, the second output end of the photoelectric coupler U1 is connected with a ground wire, and a port 3 of the host bus processor is arranged at the first output end. In this embodiment, the optocoupler circuit may be composed of a photo-coupler U1, a resistor R1 and a pull-up resistor R3, where the photo-coupler U1 includes a light emitting diode and a phototriode, the positive electrode of the light emitting diode is a first input end of the photo-coupler U1, the positive electrode of the light emitting diode is connected in series with a voltage dividing resistor R1 and then connected to a power supply V2 output by the primary voltage stabilizing unit, the negative electrode of the light emitting diode is a second input end of the photo-coupler U1, the collector of the phototriode (i.e. a first output end of the photo-coupler U1) is connected in series with a pull-up resistor R3 and then connected to a power supply V3 output by the secondary voltage stabilizing unit, and the emitter of the phototriode (i.e. a second output end of the photo-coupler U1) is grounded. In order to enhance the bus anti-interference capability, the voltage of the power supply V2 is relatively high, typically 12V. And the power supply V3 is a voltage for supplying power to the processor, and the voltage value is lower, typically 5V.
When the bus-connected MOS transistors Q3 and Q4 are all in cut-off state, the light emitting diodes of the photoelectric coupler connected with the bus are cut-off and do not emit light, the corresponding phototriodes are cut-off, the collector of the phototriodes outputs high level, and the IO port (port 3 of the host and port 3 of the slave) of the processor reads the value of 1. When any one of the MOS transistors Q3 and Q4 connected with the bus is conducted, the light emitting diode of the photoelectric coupler connected with the bus emits light due to conduction, the corresponding phototransistor is conducted, the collector of the phototransistor outputs a low level, and the IO port (port 3 of the host and port 3 of the slave) of the processor reads the value of 0. Thus, the bus state may reach both the master bus processor and the slave processor.
The slave bus circuit mainly comprises a slave bus processor, a power supply and voltage stabilizing module, a polling signal receiving and responding module. The power supply and voltage stabilizing module, also called slave power taking circuit, mainly comprises a power supply sensing unit and a voltage stabilizing unit. The polling signal receiving and responding module has the functions of receiving polling pulses from the bus and responding, and mainly comprises a polling signal receiving unit and a response transmitting unit. The polling signal receiving and responding module may be implemented with the same or similar circuit structure as the polling signal transmitting and responding module of the host.
The power supply sensing unit can be realized by a common MOS transistor, a bipolar transistor (triode) and other switching circuits, and is provided with an input end, an output end, a grounding end and a reference voltage end. The input end of the power supply sensing unit is connected with the bus, the output end of the power supply sensing unit is connected with the voltage stabilizing unit, the grounding end of the power supply sensing unit is connected with the ground wire, the reference voltage end of the power supply sensing unit is connected with the power supply V4 or can be connected with the power supply V5, and the reference voltage end is mainly used for sensing whether the bus supplies power or not. The power supply V1 output by the host power supply switch module on the bus is processed by the power supply sensing unit and then outputs the power supply V6. Because the MOS tube has a certain tube voltage drop, V6 is slightly lower than V1. In this embodiment, the switching devices in the power supply sensing unit mainly include a PNP transistor Q7, an NPN transistor Q9, and a P-type MOS transistor Q8. When the bus outputs the power supply V1, the triodes Q7 and Q9 and the MOS tube Q8 are sequentially conducted, the power supply V1 outputs the power supply V6 after passing through the MOS tube Q8, and the power supply V6 is used as an input power supply of the voltage stabilizing unit.
The voltage stabilizing unit can adopt a secondary voltage stabilizing circuit and is provided with a primary voltage stabilizing unit and a secondary voltage stabilizing unit which are sequentially connected. In this embodiment, the output power V4 of the primary voltage stabilizing unit is used to supply power to the polling signal receiving unit and the response transmitting unit, and simultaneously provides a reference voltage to the power supply sensing unit. The output power supply V5 of the secondary voltage stabilizing unit is used for supplying power to a phototriode (positioned in a photoelectric coupler) circuit of the polling signal receiving unit and the slave bus processor.
The polling signal receiving unit can be realized by adopting an optical coupler circuit and is used for receiving a polling pulse signal from a bus, wherein the input end of the polling signal receiving unit is connected with the bus, and the output end of the polling signal receiving unit is connected with the port 2 of the slave bus processor. The first input end of the photoelectric coupler U2 is connected with a power supply V2 output by the primary voltage stabilizing unit, the second input end of the photoelectric coupler U2 is connected with the bus, the first output end of the photoelectric coupler U2 is connected with a power supply V3 output by the secondary voltage stabilizing unit, the second output end of the photoelectric coupler U2 is connected with the ground wire, and the port 2 of the slave bus processor is arranged at the first output end. In this embodiment, the optocoupler circuit may be composed of a photo-coupler U2, a voltage dividing resistor R2 and a pull-up resistor R4, where the photo-coupler U2 includes a light emitting diode and a phototriode, the positive electrode of the light emitting diode is a first input end of the photo-coupler U2, the positive electrode of the light emitting diode is connected in series with the voltage dividing resistor R2 and then with the power supply V2 output by the primary voltage stabilizing unit, the negative electrode of the light emitting diode is a second input end of the photo-coupler U2, the collector of the phototriode is a first output end of the photo-coupler U2, the serial pull-up resistor R4 is connected in series with the power supply V3 output by the secondary voltage stabilizing unit, and the emitter of the phototriode is a second output end of the photo-coupler U2. The working principle of the device is the same as that of the response receiving unit of the host bus circuit, and the slave bus processor can sense the state of the bus and is not repeated here.
The response transmitting unit is used for transmitting response pulse signals to the bus and can be realized by adopting a MOS tube switch circuit, and the response transmitting unit is provided with an input end, an output end, a power end and a grounding end, wherein the input end is connected with the slave bus processor port 1, the output end is connected with the bus, the power end is connected with the power V4, and the grounding end is connected with the ground wire. In this embodiment, the switching device in the response transmitting unit includes an NPN triode Q5 and an N-type MOS transistor Q3, the port 1 of the slave bus processor is connected to the bus through a resistor R13, a triode Q5, a resistor R11, and a MOS transistor Q3 that are sequentially connected, when the port 1 outputs a low level, the triode Q5 is turned off, the MOS transistor Q3 is turned on, the bus enters an occupied state, otherwise, the triode Q5 is turned on, the MOS transistor Q3 is turned off, and the bus enters an idle state.
It should be noted that, the switching devices in the above unit circuits include devices not limited to bipolar transistors (BJTs, also called triodes), field effect transistors (MOSFETs), and the like, and may be specifically configured according to requirements, and the overall circuit structure is basically unchanged.
In this embodiment, the host bus processor and the slave bus processor are independent processors, where the host bus processor is electrically connected to the host processor through a parallel or serial interface, and the slave bus processor is electrically connected to the slave processor through a parallel or serial interface. In other embodiments, the master/slave bus processor may also be a control module integrated with the master/slave processor.
The power supplies V1, V2 and V3 are positioned in the host bus circuit, wherein the power supply V1 is the power supply for supplying power to the slave machine by the host machine, the power supply V2 is the power supply used by the host machine for inquiring the state of the slave machine, and the power supply V3 is the host bus processor C Main unit The power source used. The power supplies V4, V5 and V6 are positioned in the slave bus circuit, wherein the power supply V6 is the power supply of V1 processed by the slave electric sensing module, and is the input end of the slave voltage stabilizing circuit and is slightly lower than V1; the power supply V4 is obtained after the voltage of the V6 is stabilized and is used as the power supply of the state polling and response module, so that the voltage of the power supply V4 is smaller than the voltage of the V6, and the voltage of the V4 can be set to be the same as the voltage of the V2; the power supply V5 is obtained after the voltage of the power supply V4 is stabilized, and the voltage of the power supply V5 is smaller than the voltage of the V4 as a power supply of the slave bus processor C. For example, the power supply V1 may be set to 24V, the power supplies V2 and V4 may be set to 12V, and the power supplies V3 and V5 may be set to 3.3V, although the power supplies V2 and V4 and the power supplies V3 and V5 may be set differently according to the requirement. It should be noted that, when actually applied, the host computer is generally arranged in the machine room, electricity is conveniently taken, and the slave computer is often difficult to take electricity, so that V2 and V3 can be obtained after V1 is stabilized, and can also be provided by other power supplies.
Referring to FIG. 5, the host bus processor port 1 is a host bus processor C Main unit For controlling the switching state of the power supply and voltage regulator circuits. The working principle of the power supply and voltage stabilizing circuit is as follows:
when the port 1 of the host bus processor is at a low level, the triode Q2 is cut off, the grid electrode of the MOS tube Q1 is at a high voltage, the MOS tube Q1 is cut off, and the power supply V1 cannot reach the bus. At this point, the bus is available for status polling and acknowledgement. Specifically, the voltage of the grid electrode of the MOS tube Q1 is ensured to be close to V1 by designing the values of the resistors R5, R6 and R8. For example, when V2 and V4 are 12V, the collector current of Q2 is set to around 1mA, and thus R5 may be 10 kiloohms, R6 may be 10 ohms, and R8 may be 10 kiloohms.
When the host bus processor port 1 is high, the triode Q2 is conductedOn, the gate of the MOS transistor Q1 is low voltage (negative relative to the power supply V1), the MOS transistor Q1 is turned on, the power supply V1 reaches the bus through the MOS transistor Q1, and the status polling and response functions of the bus are suspended. Since the bus voltage is higher than the voltage of the power supply V4 at this time, the transistor Q7 is turned on, the transistor Q9 is turned on, and the gate of the MOS transistor Q8 is turned on at a negative voltage (with respect to the power supply V1). The power V1 on the bus is slightly reduced to a power V6 after passing through the power supply sensing unit, the power V6 is stabilized to a power V4 through the voltage stabilizing circuit VR1, and the voltage of the power V4 is stabilized to a power V5 through the voltage stabilizing circuit VR 2. The sense that the voltage of the power V1 is greater than the voltage of the power V4 is that it can sense whether the power supply circuit is operating (i.e. whether the switch is closed). Because the power supply V2 and the power supply V4 are used for bus communication, the voltage value is larger in floating and cannot be directly used for the processor, the voltage is regulated twice, namely the power supply V4 is further regulated to obtain the power supply V5 and then is supplied to the slave bus processor C From the slave And (5) supplying power.
As shown in connection with fig. 6, when the poll/answer switch connected to the bus is turned off, none of the leds in the optocouplers connected to the bus are turned on, and the CRPB bus is in an idle state. When one of the poll/answer switch tubes connected to the bus is in a conducting state, the light emitting diodes in the photocoupler connected to the bus are all conducting, and the state of the CRPB bus is in an occupied state. The polling/response switch tube on the bus mainly comprises a MOS tube Q4 in a host bus circuit, a MOS tube Q3 in a slave bus circuit and the like, wherein the MOS tube Q4 is a polling switch, and the MOS tube Q3 is a response switch.
When the CRPB bus is in the idle state, the bus can be brought into the occupied state by changing the level of the ports of the master or slave (the master bus processor port 2, the slave bus processor port 1, etc.). Taking host control as an example, the specific process is: the host bus processor port 2 is changed from high output level to low output level, the triode Q6 is cut off, the grid electrode of the MOS tube Q4 is changed into high voltage, the MOS tube Q4 is conducted, and the bus enters an occupied state.
The state of the bus (idle or occupied) can be perceived by the master or any slave. If the bus is in an idle state, the light emitting diode in the photoelectric coupler U1 in the host does not emit light, and the phototriode in the photoelectric coupler U1 is not conducted, so that the port 3 of the host bus processor outputs a high level; if the bus is in an occupied state, the light emitting diode in the photoelectric coupler U1 in the host emits light, so that the phototriode in the photoelectric coupler U1 is conducted, and the port 3 of the host bus processor outputs a low level. Therefore, the host bus processor can determine whether the bus is in an idle state or an occupied state according to the level of the port 3.
Similarly, if the bus is in an idle state, the light emitting diode in the photoelectric coupler U2 in the slave machine N does not emit light, and the phototransistor in the photoelectric coupler U2 is not conducted, so that the slave machine N outputs a high level from the processor port 2; if the bus is in an occupied state, the light emitting diode in the photoelectric coupler U2 in the slave machine N emits light, so that the phototriode in the photoelectric coupler U2 is conducted, and the slave machine N outputs a low level from the processor port 2. Therefore, the slave N processor can determine whether the bus is in an idle state or an occupied state according to the level of the port 2.
As shown in fig. 7, the timing of the CRPB bus divides time into two segments T1 and T2, with timing T1 representing the power up time and T2 representing the status poll and response times. On the time axis, T1 is followed by T2, T2 is followed by T1, and the alternating occurrence and continuous circulation are realized. At power time T1, the master supplies power to all slaves via the bus, while the status polling and response functions of the bus are suspended; at the status polling and response time T2, the power supply circuit stops operating, and the master performs status polling via the bus and the slave responds.
Specifically, at power time T1, the master powers all slaves through the bus, and the status polling and response functions of the bus are suspended. Referring to fig. 5, the host bus processor port 1 is high, so that Q1 is turned on, and the power V1 reaches the bus through Q1. The slave Q7 is on, and Q9 and Q8 are therefore on. The power supply V1 is stabilized by VR1 to form a power supply V4, and then is stabilized by VR2 to form a power supply V5.
At the status polling and response time T2, the power supply circuit stops operating, and the master performs status polling via the bus and the slave responds. At the beginning of T2, all slave bus processor ports 1 and host bus processor ports 2 are high, so that the bus is idle. Subsequently, the host bus processor port 2 alternately outputs a low level (corresponding to the occupied state at this time) and a high level, so that the occupied state (low level) and the idle state (high level) alternately appear on the bus, and 1 low level and the immediately following high level are referred to as 1 pulse. The adjacent occupied state and idle state (the occupied state is before and the idle state is after) are called a query period, and 1 pulse corresponds to a query period. In practical application, the system can be in a pre-occupied state and then in an idle state; or can be in an idle state and then in an occupied state. The time of the occupied state and the idle state can be properly adjusted according to the speed of the master/slave processor, in the embodiment, the time of the occupied state and the idle state are consistent, but the time of the occupied state and the idle state can be different.
For the relation between the pulse and the slave number on the bus, the sequence of the output pulse (inquiry period) on the bus determines the corresponding slave number, the number output first is small and then the number output is large (the opposite can be also realized, namely, the number appearing first is large and then the number appearing second is small). Taking the number of slaves as 100 as an example, referring to fig. 7, the 1 st inquiry period (1 st pulse) corresponds to the number 1 slave; the 2 nd inquiry period (2 nd pulse) corresponds to the number 2 slave; … … the 100 th interrogation cycle (100 th pulse) corresponds to slave 100.
The master inquiry and slave response processes are: the slave selects to answer or not answer in the inquiry period corresponding to the own number. The reply and non-reply represent two states of the slave, e.g., presence or absence, true or false. The correspondence between the response and the non-response and the actual state can be set by itself. For example, a response corresponds to a sum of true, a non-response corresponds to none or false, and vice versa.
In fig. 7, none of the slaves No. 1, no. 2, no. 3, no. 5, no. …, no. 100 responded, and No. 4 responded. From the shape of the bus signal, the slave No. 4 outputs a response pulse with a smaller width than that of the idle state in the idle state of the 4 th inquiry period. For example: the idle state is set to 10uS, and the width of the response pulse signal is set to 3uS.
Fig. 8 lists waveforms for 4 signals, which follow the following relationship: the host bus processor port 2 and the slave computer 4 processor port 1 (both are output) phase acquire bus signals; the bus signal will reach both the host bus processor port 3 and the slave bus processor port 2 (both inputs). These 4 signals follow the following time relationship: 1. the host bus processor port 2 issues a poll pulse (first signal); 2. a polling pulse signal (third signal) appears on the bus; 3. the slave bus processor port 2 receives a polling pulse signal (first signal); 4. outputting a response pulse (second signal, recess signal) from the slave bus processor port 1; 5. the host bus processor port 3 receives the response pulse signal (fourth signal).
At the beginning of T2, the host bus processor port 2 outputs a polling signal that reaches the slave bus processor port 2 via the bus, and the slave bus processor No. 4 counts the polling signal and compares it with the local number. When the count value reaches 4, the number 4 slave bus processor port 1 outputs a response pulse, which is the same as the number of the slave, and the bus signal is recessed. The host bus processor port 3 receives the recess signal, and determines that the slave No. 4 has a response, thereby obtaining state information of the slave.
Currently, the time for an IO port of a mid-high-end processor (e.g., STM32 processor) to execute an output instruction or an input instruction is typically several hundred ns (nanoseconds), so that a query cycle can be set to within 10 μs or 10 μs so that the processor has enough time to read. The on and off time of the switching devices such as the field effect transistor, the bipolar transistor and the like is ns level (generally tens of ns), and the requirements of the polling response time sequence are completely met. As shown in fig. 9, assuming that T1 is 6ms, T2 is 100×20μs=2ms, one polling period is 20 μs, one polling response period is 6ms+2ms=8ms, and the time characteristic requirement that the bus polling period is less than 10ms is fully satisfied.
For the application scenario that the communication distance is not less than 200 meters, a master multi-slave bus system should have stronger anti-interference capability, because under the condition of longer distance, signal distortion caused by interference can cause the difference between a receiving value and an actual transmitting value to cause system breakdown. In the invention, two anti-interference measures are adopted, on one hand, photoelectric couplers are adopted at the receiving ends of the host and the slave, so that the output voltage of the receiving end is ensured to only be taken from the power supply of the receiving end, and the interference increase caused by long-distance power taking is avoided; on the other hand, the communication of the bus adopts a circuit mode of current driving, so that the bus has strong anti-interference capability, and the stable and reliable communication is ensured. In practical application, the actual current can be set as 10mA current per node, while the interference signal has certain voltage amplitude, the power is smaller, the driving party of current driving is equivalent to a signal source with smaller internal resistance, and when the interference signal is superimposed on the signal source, most of energy is consumed on the internal resistance, and the amplitude is greatly attenuated. Therefore, the current driving mode has stronger anti-interference capability. For example, in fig. 6, the voltage V4 is 12V, the resistance of r2 is 1 kiloohm, and when the MOS transistor Q3 is turned on, the current flowing through the light emitting diode in the optocoupler U2 is about 10mA. The communication reliability is enhanced due to the effect of the current.
Finally, it should be noted that while the above describes embodiments of the invention in terms of drawings, the present invention is not limited to the above-described embodiments and fields of application, which are illustrative, instructive, and not limiting. Those skilled in the art, having the benefit of this disclosure, may effect numerous forms of the invention without departing from the scope of the invention as claimed.
Claims (10)
1. A CRPB bus system comprising:
the bus harness is provided with a ground wire and a bidirectional signal/power multiplexing wire;
a set of host bus circuits having a host bus control module, a power switch module coupled to the multiplexing line, a polling signal transmitting unit, and a response receiving unit;
at least one group of slave bus circuits having a slave bus control module, a power supply and voltage stabilizing module coupled to the multiplexing line, a polling signal receiving unit and a reply transmitting unit;
the method comprises the steps that a first port of a host bus control module connected with a switch control end of a power supply switch module is controlled to alternately output high and low levels, so that the bus system alternately enters a power supply period T1 or a state polling and response period T2;
the power supply period T1: the power supply switch module is started, the first power supply reaches the multiplexing line through the power supply switch module, and the power supply and the voltage stabilizing module output the power to supply power to the slave;
the status poll and response period T2: the power supply switch module is closed, the host computer sends a polling pulse signal to the multiplexing line through the polling signal sending unit, and the slave computer receives the polling pulse signal through the polling signal receiving unit and responds to the polling pulse signal according to the state of the slave computer; the slave machine self state comprises a first state and a second state.
2. The CRPB bus system of claim 1, wherein the status poll and response period T2: the host computer sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and specifically comprises the following steps: the second port of the host bus control module connected with the input end of the polling signal transmitting unit is controlled to alternately output high and low levels, so that an occupied state and an idle state alternately appear on the multiplexing line to form the polling pulse signal; adjacent occupied states and idle states form a query period, each query period corresponds to a slave number, and the query periods of all the slaves form a polling period;
the slave machine receives the polling pulse signal through the polling signal receiving unit, and when judging that the polling period corresponds to the number of the slave machine, the slave machine selectively transmits a response pulse signal to the multiplexing line or does not respond according to the state of the slave machine when the slave machine is in an idle state through the response transmitting unit;
the host receives the response pulse signal through the response receiving unit and judges that the slave with the corresponding number has a response.
3. The CRPB bus system of claim 2, wherein the time widths of the busy and idle states coincide during the interrogation period; the occupied state is forward and the idle state is backward.
4. A CRPB bus system as claimed in any of claims 1 to 3 wherein the power supply terminal of the power supply switch module is connected to a first power supply and the switch control terminal is connected to a first port of the host bus control module; the input end of the polling signal transmitting unit is connected with the second port of the host bus control module; the output end of the response receiving unit is connected with a third port of the host bus control module; the output end of the power supply switch module, the output end of the polling signal transmitting unit and the first input end of the response receiving unit are respectively connected to the multiplexing line;
the power supply and voltage stabilizing module is provided with a power supply sensing unit and a voltage stabilizing unit, and the output end of the power supply sensing unit is connected with the voltage stabilizing unit; the input end of the response transmitting unit is connected with the first port of the slave bus control module; the output end of the polling signal receiving unit is connected with the second port of the slave bus control module; the input end of the power supply sensing unit, the input end of the polling signal receiving unit and the output end of the response transmitting unit are respectively connected to the multiplexing line;
the power supply switch module, the polling signal transmitting unit, the response receiving unit, the power supply sensing unit, the voltage stabilizing unit, the polling signal receiving unit and the grounding end of the response transmitting unit are connected with a ground wire;
the host judges whether the multiplexing line is in an idle state or an occupied state according to the level of a third port of the bus control module; and the slave judges whether the multiplexing line is in an idle state or an occupied state according to the level of the second port of the bus control module.
5. The CRPB bus system of claim 4, wherein the power supply terminal of the polling signal transmitting unit is connected to a second power supply; the second input end of the response receiving unit is connected with a second power supply, and the output end of the response receiving unit is also connected with a third power supply;
the voltage stabilizing unit is constructed to comprise a primary voltage stabilizing unit and a secondary voltage stabilizing unit which are sequentially connected; the input end of the primary voltage stabilizing unit is connected with the output end of the power supply sensing unit, and the output end is also respectively connected with the second input end of the polling signal receiving unit and the power supply end of the response transmitting unit; the output end of the secondary voltage stabilizing unit is also connected with the output end of the polling signal receiving unit; the power supply sensing unit is also provided with a reference voltage end, and the reference voltage end is connected with the output end of the primary voltage stabilizing unit or the secondary voltage stabilizing unit.
6. The CRPB bus system of claim 5, wherein the voltage at the output of the primary voltage regulator unit is equal to the voltage of the second power supply and/or the voltage at the output of the secondary voltage regulator unit is equal to the voltage of the third power supply.
7. The CRPB bus system of claim 4, wherein the power switching module is implemented with a first switching circuit controlled by a first switching device, the first switching device comprising at least one of a bipolar transistor, a field effect transistor; the power supply sensing unit is realized by a second switching circuit controlled by a second switching device, and the second switching device comprises at least one of a bipolar transistor and a field effect transistor;
when the first switch circuit and the second switch circuit are both conducted, the bus system enters a power supply period T1; when the first switch circuit and the second switch circuit are opened, the bus system enters a state polling and response period T2.
8. The CRPB bus system of claim 4, wherein the polling signal transmitting unit is implemented with a third switching circuit controlled by a polling switch comprising at least one of a bipolar transistor, a field effect transistor; the response receiving unit is realized by adopting a first optocoupler circuit; the response transmitting unit is realized by a fourth circuit controlled by a response switch, and the response switch comprises at least one of a bipolar transistor and a field effect transistor; the polling signal receiving unit is realized by adopting a second optical coupler circuit;
when the third switch circuit and the fourth switch circuit are turned off, the bus system is in an idle state in a state polling and response state; when the third switch circuit or any one of the fourth switch circuits is turned on, the bus system is in an occupied state of state polling and response states.
9. The CRPB bus system of claim 8, wherein the third switching circuit and the fourth switching circuit are of the same circuit design; the first optocoupler circuit and the second optocoupler circuit adopt the same circuit design comprising the optocoupler.
10. The CRPB bus system of any of claims 1 to 3, wherein the host bus control module is a stand-alone processor or integrated within a host processor; and/or the slave bus control module is a stand-alone processor or is integrated in a slave processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011499678.0A CN114650192B (en) | 2020-12-18 | 2020-12-18 | CRPB bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011499678.0A CN114650192B (en) | 2020-12-18 | 2020-12-18 | CRPB bus system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114650192A CN114650192A (en) | 2022-06-21 |
| CN114650192B true CN114650192B (en) | 2023-12-05 |
Family
ID=81989938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011499678.0A Active CN114650192B (en) | 2020-12-18 | 2020-12-18 | CRPB bus system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114650192B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6721285B1 (en) * | 1999-03-30 | 2004-04-13 | International Business Machines Corporation | Polling system for a duplex asymmetrical communications link |
| KR100689323B1 (en) * | 2005-09-22 | 2007-03-08 | 엘에스산전 주식회사 | Fieldbus network multiplexing system |
| CN105607583A (en) * | 2014-10-29 | 2016-05-25 | 中兴通讯股份有限公司 | Monitoring unit, monitoring device and first monitoring unit in power system |
| CN111669058A (en) * | 2020-05-26 | 2020-09-15 | 中国科学院电工研究所 | Three-phase CLLC bidirectional DC converter and control method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017122437A1 (en) * | 2017-09-27 | 2019-03-28 | Dr. Johannes Heidenhain Gmbh | Bus system and slave unit for a bus system |
-
2020
- 2020-12-18 CN CN202011499678.0A patent/CN114650192B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6721285B1 (en) * | 1999-03-30 | 2004-04-13 | International Business Machines Corporation | Polling system for a duplex asymmetrical communications link |
| KR100689323B1 (en) * | 2005-09-22 | 2007-03-08 | 엘에스산전 주식회사 | Fieldbus network multiplexing system |
| CN105607583A (en) * | 2014-10-29 | 2016-05-25 | 中兴通讯股份有限公司 | Monitoring unit, monitoring device and first monitoring unit in power system |
| CN111669058A (en) * | 2020-05-26 | 2020-09-15 | 中国科学院电工研究所 | Three-phase CLLC bidirectional DC converter and control method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 两种基于总线结构的局域网通信协议的分析与实现;苟帅;《中国优秀硕士学位论文全文数据库 信息科技辑》;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114650192A (en) | 2022-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103384184A (en) | Transmitter circuit and method for controlling operation thereof | |
| CN101594171B (en) | Power cord chopper communication transceiving circuit | |
| EP1230683A2 (en) | I2c opto-isolator circuit | |
| CN114650192B (en) | CRPB bus system | |
| CN101226672A (en) | Communication control alarm device | |
| CN108616292B (en) | Communication circuit, communication method thereof, controller and electric equipment | |
| CN210380807U (en) | 5-24V compatible pulse receiving circuit | |
| CN115499267A (en) | Polling response bus system | |
| CN114900394B (en) | Modulation and demodulation method for two buses of power supply communication | |
| US5729547A (en) | Automatic driver/receiver control for half-duplex serial networks | |
| CN210041858U (en) | One-master multi-slave high-speed serial communication device | |
| CN111404504B (en) | RS485 bus differential signal amplifier | |
| CN114938316A (en) | Isolated asynchronous communication circuit and method of household appliance and household appliance | |
| CN208922247U (en) | A kind of anti-jamming circuit, interface circuit and master-slave communication system | |
| CN109474505B (en) | Single-bus communication signal enhancement circuit with monitoring function | |
| CN114124613A (en) | Anti-competition industrial 485 networking system and control method thereof | |
| CN113606761A (en) | Current loop communication circuit and air conditioner | |
| CN209358569U (en) | Differential signaling bus circuit | |
| CN216901649U (en) | Multi-node RS232 serial bus communication interface circuit | |
| CN203193608U (en) | High isolation direct splice half-duplex communication interface module for interconnection of multiple controllers | |
| CN218482773U (en) | Compatible circuit of power supply based on RS485 interface | |
| CN112202573B (en) | Two-wire system power supply and networking communication system | |
| CN111600696A (en) | Design circuit and method based on half-duplex communication bus and robot | |
| CN218124699U (en) | Single-wire serial transceiving circuit | |
| CN216599583U (en) | Communication circuit, electronic equipment and communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |