CN114650192A

CN114650192A - CRPB bus system

Info

Publication number: CN114650192A
Application number: CN202011499678.0A
Authority: CN
Inventors: 戚海峰
Original assignee: Nanjing Qihe Electronic Technology Co ltd
Current assignee: Nanjing Qihe Electronic Technology Co ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2022-06-21
Anticipated expiration: 2040-12-18
Also published as: CN114650192B

Abstract

The invention discloses a CRPB bus system, which can be applied to a master multi-slave electronic system and comprises: the bus wire harness is provided with a ground wire and a bidirectional signal/power multiplexing wire; a set of host bus circuits having a host bus control module and a power switch module, a polling signal transmitting unit and a reply receiving unit coupled to the multiplexed line; at least one group of slave bus circuits, which are provided with a slave bus control module, a power supply and voltage stabilization module, a polling signal receiving unit and a response sending unit, wherein the power supply and voltage stabilization module, the polling signal receiving unit and the response sending unit are coupled to the multiplexing line; the bus system alternately enters a power supply period T1 or a status polling and answering period T2 by controlling the first port of the host bus control module connected with the switch control terminal of the power supply switch module to alternately output high and low levels. The invention adopts the polling response/power multiplexing technology, and can realize the reduction of transmission time and the reduction of the number of transmission lines.

Description

CRPB bus system

Technical Field

The invention belongs to the technical field of buses, and particularly relates to a polling response power bus system.

Background

Among electronic systems composed of a master and a plurality of slaves (referred to as "master-slave electronic systems"), there are remote-master-slave electronic systems, such as multi-node interactive entertainment systems, stage control systems, conference systems, etc., which generally have the following features: 1) the number of the main machines is 1, and the maximum number of the auxiliary machines can reach 200; 2) the maximum distance between the slave machine and the host machine can reach 1000 meters; 3) the state of the slave is sent to the master, and the state of the slave is only two (existence or nonexistence, true or false); 4) the slave state is sent to the master in a very short time (e.g., less than 10 ms); 5) the power supply of the slave is provided by the host; 6) the number of the connecting lines between the host and the slave is as small as possible, and 2 lines are preferred.

At present, transmission buses with the transmission distance of 1000 meters are mainly RS-422 buses and RS-485 buses. When these external buses are applied to a remote-master multi-slave electronic system, there are two problems, namely: 1) the time delay does not meet the requirement; 2) the number of lines is large.

The RS-485 bus is taken as an example to illustrate the above problems in conjunction with fig. 1. When the RS-485 bus is used as the transmission bus, in order to prevent data errors caused by simultaneous data transmission from a plurality of slaves (for example, 100 slaves, which are numbered as slave No. 1, slave No. 2, …, and slave No. 100 in sequence), the master can only adopt a polling method to receive the data from the slaves. The polling process is as follows: the master machine sends the code of the slave machine No. 1, all the slave machines receive the code, and only the slave machine No. 1 judges that the code is consistent with the number of the slave machine, so the slave machine No. 1 sends the state of the slave machine No. 1 to the master machine; next, the master sends the code for slave No. 2, and so on until slave No. 100 sends its status to the master. Thus, the time taken for one poll (from 1 to 100) is the product of the time of a single transmission and reception times the number of slaves. When communication is carried out in a mode of UART (universal asynchronous receiver transmitter) + RS-485 bus, if the transmission baud rate is 9600, the transmission format is 1-bit start bit, 8-bit data bit and 1-bit stop bit. The time for a single transmission or reception is 10/9600 × 1.04ms, so the transmission time is about 100 × 2 × 1.04ms — 208ms, and obviously cannot meet the system requirement. If the communication is carried out in a half-duplex mode, the number of the lines is 4, wherein 2 RS-485 buses, 1 power supply line and 1 ground line are provided. If the communication is carried out in a full duplex mode, the number of the lines is 6, wherein 4 RS-485 buses, 1 power supply line and 1 ground line are provided. In addition, the RS-485 bus has the problems that communication cannot be carried out when common-mode interference is large, a fault of a certain node can affect adjacent nodes, and the like, and the fault rate is high. In addition, since the RS485 needs to use a chip such as a photoelectric isolator when used, the cost is higher than that of a device such as a general photoelectric coupler.

Therefore, the existing bus application has the technical problems of long transmission time and large number of connecting wires in a long-distance one-master-multi-slave electronic system application, and the problems of high failure rate, high cost and the like in the conventional bus application.

Disclosure of Invention

In order to solve the problems of longer transmission time and more connecting lines of the conventional bus in the application of a long-distance one-master multi-slave electronic system, the invention provides a polling Response Power bus system, also called a CRPB (Cyclic query Power bus) bus system, which adopts a polling Response/Power multiplexing technology to realize the reduction of transmission time and the reduction of the number of transmission lines.

The invention discloses a CRPB bus system, which can be applied to a master multi-slave electronic system and comprises:

the bus wire harness is provided with a ground wire and a bidirectional signal/power multiplexing wire;

a set of host bus circuits having a host bus control module and a power switch module, a polling signal transmitting unit and a reply receiving unit coupled to the multiplexed line;

at least one group of slave bus circuits, which are provided with a slave bus control module, a power supply and voltage stabilization module, a polling signal receiving unit and a response sending unit, wherein the power supply and voltage stabilization module, the polling signal receiving unit and the response sending unit are coupled to the multiplexing line;

the method comprises the steps that a first port of a host bus control module connected with a switch control end of a power supply switch module is controlled to alternately output high and low levels, so that a bus system alternately enters a power supply period T1 or a state polling and response period T2;

the power supply period T1: the power supply switch module is started, and a first power supply reaches the multiplexing line through the power supply switch module and supplies power to the slave after being output by the power supply and voltage stabilization module;

the status polling and response period T2: the power supply switch module is closed, the host machine sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and the slave machine receives the polling pulse signal through a polling signal receiving unit and responds to the polling pulse signal according to the self state; the self state of the slave comprises a first state and a second state. For example, the first state is "present", and the second state is "absent"; the first state is true and the second state is false.

As a preferable scheme, the status polling and response period T2:

the host sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and specifically includes: controlling a second port of a host bus control module connected with an input end of a polling signal sending unit to alternately output high and low levels, so that an occupied state and an idle state alternately appear on the multiplexing line to form a polling pulse signal; an inquiry period is formed by the adjacent occupied state and the idle state, each inquiry period corresponds to one slave machine number, and the inquiry periods of all the slave machines form a polling period;

the slave machine receives the polling pulse signal through the polling signal receiving unit and selects to send a response pulse signal to the multiplexing line or does not make any response through the response sending unit according to the idle state of the slave machine when the polling period is judged to correspond to the self number;

the host receives the response pulse signal through the response receiving unit and judges that the slave with the corresponding number has a response.

As a preferred scheme, in the query period, the time widths of the occupied state and the idle state are consistent; the occupied state is before and the idle state is after.

As a preferred scheme, a power end of the power supply switch module is connected with a first power supply, and a switch control end is connected with a first port of the host bus control module; the input end of the polling signal sending unit is connected with a second port of the host bus control module; the output end of the response receiving unit is connected with a third port of the host bus control module; the output end of the power supply switch module, the output end of the polling signal sending unit and the first input end of the response receiving unit are respectively connected to the multiplexing line;

the power supply and voltage stabilization module is provided with a power supply sensing unit and a voltage stabilization unit, and the output end of the power supply sensing unit is connected with the voltage stabilization unit; the input end of the response sending unit is connected with a first port of the slave bus control module; the output end of the polling signal receiving unit is connected with a second port of the slave bus control module; the input end of the power supply sensing unit, the input end of the polling signal receiving unit and the output end of the response sending unit are respectively connected to the multiplexing line;

the grounding ends of the power supply switch module, the polling signal sending unit, the response receiving unit, the power supply sensing unit, the voltage stabilizing unit, the polling signal receiving unit and the response sending unit are connected with a ground wire;

the host machine judges whether the multiplex line is in an idle state or an occupied state according to the level of the third port of the bus control module; and the slave machine judges whether the multiplexing line is in an idle state or an occupied state according to the level of the second port of the bus control module.

As a preferable scheme, a power supply end of the polling signal sending unit is connected with a second power supply; a second input end of the response receiving unit is connected with a second power supply, and an output end of the response receiving unit is also connected with a third power supply;

the voltage stabilizing unit is constructed to include a primary voltage stabilizing unit and a secondary voltage stabilizing unit which are connected in sequence; the input end of the primary voltage stabilizing unit is connected with the output end of the power supply sensing unit, and the output end of the primary voltage stabilizing unit is also respectively connected with the second input end of the polling signal receiving unit and the power supply end of the response sending unit; the output end of the secondary voltage stabilizing unit is also connected with the output end of the polling signal receiving unit; the power supply sensing unit is also provided with a reference voltage end, and the reference voltage end is connected with the output end of the primary voltage stabilizing unit or the secondary voltage stabilizing unit.

Preferably, the voltage at the output end of the primary voltage stabilizing unit is equal to the voltage of the second power supply, and/or the voltage at the output end of the secondary voltage stabilizing unit is equal to the voltage of the third power supply.

As a preferred solution, the power supply switch module is implemented by using a first switch circuit controlled by a first switch device, where the first switch device includes at least one of a bipolar transistor and a field effect transistor; the power supply sensing unit is realized by adopting a second switch circuit controlled by a second switch device, and the second switch device comprises at least one of a bipolar transistor and a field effect transistor;

when the first switch circuit and the second switch circuit are both conducted, the bus system enters a power supply time period T1; when the first and second switch circuits are open, the bus system enters a status polling and reply period T2.

As a preferable scheme, the polling signal sending unit is implemented by using a third switch circuit controlled by a polling switch, and the polling switch includes at least one of a bipolar transistor and a field effect transistor; the response receiving unit is realized by adopting a first optical coupling circuit; the response sending unit is realized by adopting a fourth switch circuit controlled by a response switch, and the response switch comprises at least one of a bipolar transistor and a field effect transistor; the polling signal receiving unit is realized by adopting a second optical coupling circuit;

when the third switch circuit and the fourth switch circuit are cut off, the bus system is in an idle state in state polling and response states; when the third switch circuit or any one fourth switch circuit is conducted, the bus system is in an occupied state in a state polling state and a response state.

As a preferred scheme, the third switch circuit and the fourth switch circuit adopt the same circuit design; the first optical coupling circuit and the second optical coupling circuit adopt the same circuit design comprising photoelectric couplers.

As a preferred solution, the host bus control module is an independent processor or integrated in the host processor; and/or the slave bus control module is an independent processor or is integrated in a slave processor.

The invention has the following technical effects:

(1) the CRPB bus system disclosed by the invention adopts a polling response and power supply multiplexing mode, can meet the bus requirement by only 2 lines, and can realize that the polling period of the bus is controlled within 10 ms.

(2) The CRPB bus system disclosed by the invention adopts the photoelectric couplers at the receiving ends of the host and the slave, ensures that the output voltage of the receiving end only gets power from the power supply of the receiving end, and avoids the interference increase caused by remote power taking.

(3) The bus communication of the CRPB bus system disclosed by the invention adopts a current-driven circuit mode, has strong anti-interference capability and can reach a transmission distance of 1000 meters.

(4) The CRPB bus system disclosed by the invention has the advantages of simple structure, low cost, relative independence of each node and low failure rate.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of an RS-485 transmission bus in a master multi-slave electronic system;

FIG. 2 is a schematic diagram of the overall structure of a CRPB bus system in a master multi-slave electronic system 1;

FIG. 3 is a schematic diagram of the overall structure of the CRPB bus system in a master multi-slave electronic system 2;

FIG. 4 is a schematic circuit diagram of a CRPB bus system;

FIG. 5 is a schematic diagram of a power supply and voltage regulator circuit;

FIG. 6 is a block diagram of a status poll and reply module;

FIG. 7 is a schematic diagram of the power supply and poll reply timing sequences of the CRPB bus;

FIG. 8 is a schematic diagram of a poll reply timing sequence of the CRPB bus;

fig. 9 is a timing diagram of the poll reply/power bus.

Detailed Description

The invention is further explained below with reference to the figures and the specific embodiments.

Referring to fig. 2 to 6, the present invention discloses a polling Response Power bus system suitable for a remote master/slave electronic system, also called CRPB (circular query Power bus) bus system, which mainly includes a master bus circuit, a slave bus circuit and a bus harness, wherein the bus harness includes 2 lines, one is a bidirectional signal/Power multiplexing line (called "multiplexing line", "bus" or "CRPB bus"), and the other is a ground line. The ground wire is mainly used for connecting the grounding ends of the devices, and is not shown in other figures for simplifying the figure. It should be understood that, in practical applications, in a master multi-slave electronic system, there are usually more than two slaves, and for simplicity of illustration and description, the device numbers of the slaves in the embodiment are all uniformly indicated, and only one slave is shown in the circuit structure diagram.

In FIG. 4, part A is mainly used for power supply and voltage stabilization, wherein part A_{Master and slave}Supply switch module for the main unit, A_FromAnd the power supply and voltage stabilization module is used for a slave. Part B is mainly used for status polling and answering, wherein part B_{Master and slave}Polling signal sending and response receiving module for host computer, B_FromAnd the polling signal receiving and response sending module is a slave.

The host bus circuit mainly comprises a host bus processor, a power supply switch module and a polling signal sending and response receiving module, wherein the power supply switch module and the polling signal sending and response receiving module are connected with the host bus processor. The power supply switch module (also called power supply circuit) can be realized by a common MOS transistor switch circuit, a bipolar transistor (triode) switch circuit and the like, and is provided with at least four ports of an input end, an output end, a switch control end and a grounding end for supplying power to all slave computers. The input end of the power supply switch module is connected with a power supply V1, the output end is connected with a bus, the switch control end is connected with a port 1 of the host bus processor and receives a high level or low level signal output by the port 1 of the host bus processor, and the grounding end is connected with a ground wire. In this embodiment, the switching device in the power supply switching module mainly includes a P-type MOS transistor Q1 and an NPN-type transistor Q2, the power supply V1 is connected to the bus through the MOS transistor Q1, the port 1 of the host bus processor is connected to the base stage (i.e., the control end) of the transistor Q2, and the collector of the transistor Q2 is connected to the gate of the MOS transistor Q1 through R6. When the port 1 of the host bus processor outputs a high level, the triode Q2 and the MOS transistor Q1 are sequentially conducted, so that the power supply switch module is in an open state, and the power supply function is realized; otherwise, the system is in a closed state and is switched to a polling signal sending and response receiving function.

The polling signal sending and response receiving module comprises a polling signal sending unit and a response receiving unit. The polling signal transmitting unit is used for transmitting a polling signal to the bus, and can be implemented by a MOS transistor switch circuit, a bipolar transistor (triode) switch circuit, or the like, and is also called a host transmitting circuit, and has an input end, an output end, a power supply end, and a ground end. The input end of the polling signal sending unit is connected with port 2 of the host bus processor, the output end of the polling signal sending unit is connected with the bus, the power supply end of the polling signal sending unit is connected with the power supply V2, and the grounding end of the polling signal sending unit is connected with the ground wire. In this embodiment, the switch device in the polling signal sending unit mainly includes an NPN-type transistor Q6 and an N-type MOS transistor Q4, the port 2 of the host bus processor is connected to the bus through a resistor R14, a transistor Q6, a resistor R12, and a MOS transistor Q4 which are connected in sequence, when the port 2 outputs a low level, the transistor Q6 is turned off, the MOS transistor Q4 is turned on, the bus enters an occupied state, otherwise, the transistor is turned on, the MOS transistor Q4 is turned off, and the bus enters an idle state.

The response receiving unit can be realized by an optical coupling circuit, also called a host receiving circuit, and is used for receiving a slave response pulse signal from the bus, wherein the input end of the response receiving unit is connected with the bus, and the output end of the response receiving unit is connected with the port 3 of the bus processor. The optical coupling circuit is provided with an optical coupler which is mainly used for isolating the signal coupling relation of each voltage and avoiding the mutual interference of signals. The first input end of the photoelectric coupler U1 is connected with a power supply V2 output by the primary voltage stabilizing unit, the second input end of the photoelectric coupler U1 is connected with the multiplex line, the first output end of the photoelectric coupler U1 is connected with a power supply V3 output by the secondary voltage stabilizing unit, the second output end of the photoelectric coupler U1 is connected with the ground wire, and the port 3 of the host bus processor is arranged at the first output end. In this embodiment, the optical coupling circuit may include a photocoupler U1, a resistor R1, and a pull-up resistor R3, the photocoupler U1 includes a light emitting diode and a phototriode, the positive electrode of the light emitting diode is the first input end of the photocoupler U1, the positive electrode of the light emitting diode is connected in series with the voltage dividing resistor R1 and then connected to the power supply V2 output by the primary voltage stabilizing unit, the negative electrode of the light emitting diode is the second input end of the photocoupler U1, the collector electrode of the phototriode (i.e., the first output end of the photocoupler U1) is connected in series with the pull-up resistor R3 and then connected to the power supply V3 output by the secondary voltage stabilizing unit, and the emitter electrode of the phototriode (i.e., the second output end of the photocoupler U1) is grounded. In order to enhance the bus interference resistance, the voltage of the power supply V2 is relatively high, typically 12V. While the power supply V3 is the voltage that powers the processor, and is at a lower voltage value, typically 5V.

When the bus is in work, when all MOS tubes Q3 and Q4 connected with the bus are in a cut-off state, the light emitting diode of the photoelectric coupler connected with the bus is cut off and does not emit light, the corresponding phototriode is cut off, the collector of the phototriode outputs high level, and the IO ports (port 3 of the host and port 3 of the slave) of the processor read the value of 1. When any one of the MOS transistors Q3 and Q4 connected to the bus is turned on, the light emitting diode of the photocoupler connected to the bus emits light due to the on-state, the corresponding phototransistor is turned on, the collector of the phototransistor outputs a low level, and the IO port (port 3 of the host and port 3 of the slave) of the processor reads a value "0". Thus, the bus state may reach both the master bus processor and the slave processor.

The slave bus circuit mainly comprises a slave bus processor, a power supply and voltage stabilization module and a polling signal receiving and responding module. The power supply and voltage stabilization module, also called a slave power supply circuit, mainly comprises a power supply sensing unit and a voltage stabilization unit. The polling signal receiving and responding module has the functions of receiving polling pulses from the bus and responding, and mainly comprises a polling signal receiving unit and a responding and sending unit. The polling signal receiving and responding module can be realized by adopting a circuit structure which is the same as or similar to that of the polling signal sending and responding receiving module of the host.

The power supply sensing unit can also be implemented by a common switching circuit such as a MOS transistor and a bipolar transistor (triode), and has an input terminal, an output terminal, a ground terminal, and a reference voltage terminal. The input end of the power supply sensing unit is connected with the bus, the output end of the power supply sensing unit is connected with the voltage stabilizing unit, the grounding end of the power supply sensing unit is connected with the ground wire, the reference voltage end of the power supply sensing unit is connected with the power supply V4 or can be connected with the power supply V5, and the reference voltage end is mainly used for sensing whether the bus supplies power or not. And after being processed by the power supply sensing unit, the power supply V1 output by the host power supply switch module on the bus outputs a power supply V6. V6 is slightly lower than V1 because of the MOS transistor has a certain transistor voltage drop. In this embodiment, the switching device in the power supply sensing unit mainly includes a PNP transistor Q7, an NPN transistor Q9, and a P-type MOS transistor Q8. When the bus outputs a power supply V1, the triode Q7, the Q9 and the MOS transistor Q8 are sequentially conducted, the power supply V1 outputs the power supply V6 after passing through the MOS transistor Q8, and the power supply V6 serves as an input power supply of the voltage stabilizing unit.

The voltage stabilizing unit can adopt a secondary voltage stabilizing circuit and is provided with a primary voltage stabilizing unit and a secondary voltage stabilizing unit which are connected in sequence. In this embodiment, the output power V4 of the primary voltage stabilizing unit is used to supply power to the polling signal receiving unit and the response sending unit, and also to provide a reference voltage for the power supply sensing unit. The output power supply V5 of the secondary voltage stabilizing unit is used for supplying power to a phototriode (located in a photoelectric coupler) circuit of the polling signal receiving unit and the slave bus processor.

The polling signal receiving unit can be realized by adopting an optical coupling circuit and is used for receiving a polling pulse signal from the bus, the input end of the polling signal receiving unit is connected with the bus, and the output end of the polling signal receiving unit is connected with the port 2 of the slave bus processor. The first input end of the photoelectric coupler U2 is connected with a power supply V2 output by the primary voltage stabilizing unit, the second input end is connected with the bus, the first output end is connected with a power supply V3 output by the secondary voltage stabilizing unit, the second output end is connected with the ground wire, and the port 2 of the slave bus processor is arranged at the first output end. In this embodiment, the optical coupling circuit may include a photocoupler U2, a voltage dividing resistor R2, and a pull-up resistor R4, the photocoupler U2 includes a light emitting diode and a phototriode, the positive electrode of the light emitting diode is the first input terminal of the photocoupler U2, the positive electrode is connected in series with the voltage dividing resistor R2 and then connected to the power supply V2 output by the primary voltage stabilizing unit, the negative electrode is the second input terminal of the photocoupler U2, the collector of the phototriode is the first output terminal of the photocoupler U2, the collector of the phototriode is connected in series with the pull-up resistor R4 and then connected to the power supply V3 output by the secondary voltage stabilizing unit, and the emitter of the phototriode is the second output terminal of the photocoupler U2. The working principle of the response receiving unit is the same as that of the host bus circuit, and the slave bus processor can sense the state of the bus, which is not described in detail herein.

The response sending unit is used for sending the response pulse signal to the bus, can be realized by adopting an MOS tube switching circuit, and is provided with an input end, an output end, a power supply end and a grounding end, wherein the input end is connected with the port 1 of the slave bus processor, the output end is connected with the bus, the power supply end is connected with a power supply V4, and the grounding end is connected with a ground wire. In this embodiment, the switching device in the response sending unit includes an NPN transistor Q5 and an N-type MOS transistor Q3, the switch device is connected to the bus through a resistor R13, a transistor Q5, a resistor R11, and a MOS transistor Q3 which are connected in sequence from the port 1 of the slave bus processor, when the port 1 outputs a low level, the transistor Q5 is turned off, the MOS transistor Q3 is turned on, the bus enters an occupied state, otherwise, the transistor Q5 is turned on, the MOS transistor Q3 is turned off, and the bus enters an idle state.

It should be noted that the switching devices in the above unit circuit include devices without limitation to use of bipolar junction transistors (BJTs, also called triodes), field effect transistors (MOSFETs), etc., and can be configured according to requirements, and the overall circuit structure is basically unchanged.

In this embodiment, the master bus processor and the slave bus processor are both independent processors, wherein the master bus processor is electrically connected to the master processor through a parallel or serial interface, and the slave bus processor is electrically connected to the slave processor through a parallel or serial interface. In other embodiments, the master/slave bus processor may be a control module integrated with the master/slave processor.

The power supplies V1, V2 and V3 are arranged in a host bus circuit, wherein the power supply V1 is used for supplying power to the slave by the host, the power supply V2 is used for inquiring the state of the slave by the host, and the power supply V3 is used for the host bus processor C_MainThe power supply used. The power supplies V4, V5 and V6 are arranged in a slave bus circuit, wherein the power supply V6 is a power supply processed by the slave electricity sensing module by V1, is an input end of a slave voltage stabilizing circuit and is slightly lower than V1; the power supply V4 is a power supply obtained by stabilizing the voltage of V6 and is used as a power supply of the state polling and answering module, so the voltage of the power supply V4 is smaller than the voltage of V6, and the voltage of V4 can be set to be the same as the voltage of V2; the power supply V5 is obtained by stabilizing the power supply V4, and the voltage of V5 is smaller than the voltage of V4 as the power supply from the slave bus processor C. For example, the power V1 may be set to 24V, the power V2, V4 to 12V, and the power V3, V5 to 3.3V, but of course, the power V2 and the power V4, and the power V3 and the power V5 may be set differently according to requirements. It should be noted that, in practical application, the host is generally installed in a machine room, and power is conveniently supplied, while the slave is not easy to supply power, so that V2 and V3 can be obtained by stabilizing voltage of V1, and can also be supplied by other power sources.

As shown in FIG. 5, the host bus processor port 1 is the host bus processor C_{Master and slave}The IO port is used for controlling the switching state of the power supply and voltage stabilizing circuit. The working principle of the power supply and voltage stabilizing circuit is as follows:

when the host bus processor port 1 is at a low level, the transistor Q2 is turned off, the gate of the MOS transistor Q1 is at a high voltage, the MOS transistor Q1 is turned off, and the power supply V1 fails to reach the bus. At this point, the bus is available for status polling and acknowledgement. Particularly, the voltage of the gate of the MOS transistor Q1 is close to V1 by designing the values of the resistors R5, R6 and R8. For example, when V2 and V4 are 12V, the collector current of Q2 is set to be around 1mA, and therefore R5 may be 10 kilo-ohms, R6 may be 10 ohms, and R8 may be 10 kilo-ohms.

When the host bus processor port 1 is at high level, the transistor Q2 is turned on, the gate of the MOS transistor Q1 is at low voltage (negative with respect to the power supply V1), the MOS transistor Q1 is turned on, the power supply V1 reaches the bus through the MOS transistor Q1, and the status polling and response functions of the bus are suspended. Since the bus voltage is higher than the voltage of the power supply V4, the transistor Q7 is turned on, the transistor Q9 is also turned on, and the gate of the MOS transistor Q8 is turned on with a negative voltage (with respect to the power supply V1). The power supply V1 on the bus is slightly reduced to a power supply V6 after passing through the power supply sensing unit, the power supply V6 is stabilized into a power supply V4 through a voltage stabilizing circuit VR1, and the voltage of the power supply V4 is stabilized into a power supply V5 through a voltage stabilizing circuit VR 2. The significance of the fact that the voltage of the power supply V1 is greater than the voltage of the power supply V4 is that whether the power supply circuit is operating (i.e., whether the switch is closed) can be sensed. Because the power supply V2 and the power supply V4 are used for bus communication, the voltage value is greatly floated and cannot be directly used for a processor, and therefore, the voltage is stabilized twice, namely the power supply V4 is further stabilized to obtain the power supply V5 and then is supplied to the slave bus processor C_FromAnd (5) supplying power.

As shown in fig. 6, when the polling/responding switch tube connected to the bus is turned off, the light emitting diode in the photocoupler connected to the bus is not turned on, and the status of the CRPB bus is in an idle state. When one of the polling/response switch tubes connected to the bus is in a conducting state, all light emitting diodes in a photoelectric coupler connected to the bus are conducted, and at the moment, the state of the CRPB bus is in an occupied state. The polling/response switch tube on the bus mainly comprises a MOS tube Q4 in a main machine bus circuit, a MOS tube Q3 in a slave machine bus circuit and the like, wherein the MOS tube Q4 is a polling switch, and the MOS tube Q3 is a response switch.

When the CRPB bus is in an idle state, the bus can be brought into an occupied state by changing the level of the ports of the host or the slave (host bus processor port 2, slave bus processor port 1, etc.). Taking host control as an example, the specific process is as follows: the output high level of the port 2 of the host bus processor is changed into the output low level, the triode Q6 is cut off, the grid of the MOS tube Q4 is changed into high voltage, the MOS tube Q4 is conducted, and the bus enters an occupied state.

The state of the bus (idle or busy) can be sensed by the master or any of the slaves. If the bus is in an idle state, the light emitting diode in the photoelectric coupler U1 in the host does not emit light, and the phototriode in the photoelectric coupler U1 is not conducted, so that the port 3 of the host bus processor outputs high level; if the bus is in an occupied state, the light emitting diode in the photoelectric coupler U1 in the host emits light, so that the phototriode in the photoelectric coupler U1 is conducted, and the port 3 of the bus processor of the host outputs low level. Therefore, the host bus processor can judge whether the bus is in an idle state or an occupied state according to the level of the port 3 of the host bus processor.

Similarly, if the bus is in an idle state, the light emitting diode in the optoelectronic coupler U2 in the slave N does not emit light, and the phototriode in the optoelectronic coupler U2 is not turned on, so that a high level is output from the processor port 2 of the slave N; if the bus is in an occupied state, the light emitting diode in the photoelectric coupler U2 in the slave machine N emits light, so that the phototriode in the photoelectric coupler U2 is conducted, and a low level is output from the processor port 2 of the slave machine N. Therefore, the slave N processor can determine whether the bus is in an idle state or an occupied state according to the level of the port 2.

As shown in fig. 7, the timing of the CRPB bus divides time into two segments, T1 and T2, with timing T1 representing power supply time and T2 representing status poll and reply time. On the time axis, T2 is behind T1, and T1 is behind T2, which alternately appear and continuously circulate. At the power supply time T1, the master supplies power to all the slaves through the bus, and the status polling and answering functions of the bus are suspended; at the status polling and response time T2, the power supply circuit stops operating, and the master polls status via the bus and the slave responds.

Specifically, at power supply time T1, the master supplies power to all slaves via the bus, while the status polling and reply functions of the bus are suspended. As shown in connection with FIG. 5, host bus processor port 1 is high, causing Q1 to turn on and power supply V1 to the bus through Q1. Q7 is on from the slave, and Q9 and Q8 are also on accordingly. The power supply V1 is regulated to power supply V4 by VR1, and then regulated to power supply V5 by VR 2.

At the status polling and response time T2, the power supply circuit stops operating, and the master polls status via the bus and the slave responds. At the beginning of T2, port 1 and port 2 of all slave bus processors are high, making the bus idle. Subsequently, the host bus processor port 2 alternately outputs a low level (corresponding to the occupied state at this time) and a high level, so that the occupied state (low level) and the idle state (high level) alternately appear on the bus, and 1 low level and the next high level are called 1 pulse. The adjacent occupied state and idle state (the occupied state is before, and the idle state is after) are called a query cycle, and 1 pulse corresponds to one query cycle. In actual application, the system can be in a pre-occupation state and then in an idle state; or the idle state first and then the occupied state. The time of the occupied state and the time of the idle state can be properly adjusted according to the speed of the master/slave processor, in the embodiment, the time of the occupied state and the time of the idle state are consistent, but the time of the occupied state and the time of the idle state can also be different.

For the relationship between the pulse on the bus and the slave serial number, the sequence of the output pulse (inquiry period) on the bus determines the corresponding slave serial number, and the serial number output first is small and the serial number output later is large (or vice versa, that is, the serial number appearing first is large and the serial number appearing later is small). Taking the number of slaves as 100 as an example, and referring to fig. 7, the 1 st polling period (1 st pulse) corresponds to the slave No. 1; the 2 nd inquiry period (2 nd pulse) corresponds to the number 2 slave; … … the 100 th polling cycle (100 th pulse) corresponds to 100 slaves.

The host inquiry and slave response process comprises the following steps: the slave selects response or no response in the inquiry period corresponding to the self number. The acknowledgement and non-acknowledgement represent two states of the slave, e.g., presence or absence, true or false. The correspondence between the response, the non-response and the actual state can be set by itself. For example, a response corresponds to true and a no response corresponds to none or false, and vice versa.

In fig. 7, none of slaves nos. 1, 2, 3, 5, …, and 100 responded, and slave No. 4 responded. From the aspect of the shape of the bus signal, the slave No. 4 outputs a response pulse with a width smaller than that of the idle state in the idle state of the 4 th inquiry cycle. For example: the idle state is set to 10uS, and the width of the response pulse signal is set to 3 uS.

Fig. 8 lists waveforms of 4 signals, which obey the following relationship: the host bus processor port 2 and the slave 4 processor port 1 (both output) are in phase with each other to obtain a bus signal; the bus signal will reach both the master bus processor port 3 and the slave bus processor port 2 (both inputs). These 4 signals obey the following temporal relationship: 1. the host bus processor port 2 issues a polling pulse (first signal); 2. a polling pulse signal (third signal) appears on the bus; 3. receiving a polling pulse signal (first signal) from the bus processor port 2; 4. outputting a response pulse (second signal, recess signal) from the slave bus processor port 1; 5. the host bus processor port 3 receives the acknowledge pulse signal (fourth signal).

At the start of T2, the master bus processor port 2 outputs a polling signal which is counted by the slave bus processor No. 4 and compared with the local number when the polling signal arrives at the slave bus processor port 2 through the bus. When the count value reaches 4, the slave bus processor port 1 No. 4 outputs a response pulse, which is the same as the local number, and the bus signal is notched. The host bus processor port 3 receives the recess signal, and determines that the slave 4 has a response, thereby obtaining the status information of the slave.

Currently, an IO port of a mid-to-high processor (e.g., STM32 processor) typically executes an output instruction or an input instruction for several hundred ns (nanoseconds), so that a polling cycle can be set to within 10 μ s or 10 μ s so that the processor has enough time to read. The on-off time of switching devices such as a field effect transistor and a bipolar transistor is ns (generally tens of ns), and the requirement of a polling response time sequence is completely met. As shown in fig. 9, it is assumed that T1 is 6ms, T2 is 100 × 20 μ s — 2ms, one polling period is 20 μ s, and one polling response period is 6ms +2ms — 8ms, which completely meets the time characteristic requirement that the bus polling period is less than 10 ms.

For the application scenario with the communication distance not less than 200 meters, a master multi-slave bus system should have strong anti-interference capability, because in the case of a longer distance, the signal distortion caused by interference may cause the received value to be different from the actual transmitted value, which may cause the system to crash. According to the invention, two anti-interference measures are adopted, on one hand, photoelectric couplers are adopted at the receiving ends of the host and the slave, so that the output voltage of the receiving end is ensured to be only taken from the power supply of the receiving end, and the interference increase caused by long-distance electricity taking is avoided; on the other hand, the bus communication adopts a current-driven circuit mode, so that the bus communication has strong anti-interference capability and ensures stable and reliable communication. In practical application, the actual current can be set to be 10mA current per node, although the interference signal has a certain voltage amplitude, the power is small, the current-driven driving side is equivalent to a signal source with small internal resistance, when the interference signal is superposed on the signal source, most energy is consumed on the internal resistance, and the amplitude is greatly attenuated. Therefore, the current driving mode has strong anti-interference capability. For example, in fig. 6, the voltage of V4 is 12V, and the resistance of R2 is 1 kilo ohm, when the MOS transistor Q3 is turned on, the current flowing through the light emitting diode in the optocoupler U2 is about 10 mA. Due to the effect of the current, communication reliability is enhanced.

Finally, it should be noted that while the above describes exemplifying embodiments of the invention with reference to the accompanying drawings, the invention is not limited to the embodiments and applications described above, which are intended to be illustrative and instructive only, and not limiting. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto without departing from the scope of the invention as defined by the appended claims.

Claims

1. A CRPB bus system, comprising:

the status polling and reply period T2: the power supply switch module is closed, the host machine sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and the slave machine receives the polling pulse signal through a polling signal receiving unit and responds to the polling pulse signal according to the self state; the self state of the slave comprises a first state and a second state.

2. The CRPB bus system of claim 1, wherein the status poll and reply period T2: the host sends a polling pulse signal to the multiplexing line through a polling signal sending unit, and specifically includes: controlling a second port of a host bus control module connected with an input end of a polling signal sending unit to alternately output high and low levels, so that an occupied state and an idle state alternately appear on the multiplexing line to form a polling pulse signal; an inquiry period is formed by the adjacent occupied state and the idle state, each inquiry period corresponds to one slave machine number, and the inquiry periods of all the slave machines form a polling period;

the slave receives the polling pulse signal through the polling signal receiving unit and selects to send a response pulse signal to the multiplexing line or does not make any response through the response sending unit according to the self state in an idle state when the inquiry period is judged to correspond to the self number;

3. The CRPB bus system of claim 2, wherein the time widths of the busy state and the idle state are the same during the polling period; the occupied state is before and the idle state is after.

4. The CRPB bus system of any one of claims 1-3, wherein the power supply terminal of the power supply switch module is connected to a first power supply source, and the switch control terminal is connected to the first port of the host bus control module; the input end of the polling signal sending unit is connected with a second port of the host bus control module; the output end of the response receiving unit is connected with a third port of the host bus control module; the output end of the power supply switch module, the output end of the polling signal sending unit and the first input end of the response receiving unit are respectively connected to the multiplexing line;

grounding ends of the power supply switch module, the polling signal sending unit, the response receiving unit, the power supply sensing unit, the voltage stabilizing unit, the polling signal receiving unit and the response sending unit are connected with a ground wire;

5. The CRPB bus system as claimed in claim 4, wherein a power supply terminal of the polling signal sending unit is connected to a second power supply; a second input end of the response receiving unit is connected with a second power supply, and an output end of the response receiving unit is also connected with a third power supply;

6. The CRPB bus system of claim 5, wherein the voltage at the output of the primary regulator block is equal to the voltage of the second power supply, and/or the voltage at the output of the secondary regulator block is equal to the voltage of the third power supply.

7. The CRPB bus system of claim 4, wherein the power switch module is implemented using a first switch circuit controlled by a first switch device, the first switch device comprising at least one of a bipolar transistor and a field effect transistor; the power supply sensing unit is realized by adopting a second switch circuit controlled by a second switch device, and the second switch device comprises at least one of a bipolar transistor and a field effect transistor;

when the first switch circuit and the second switch circuit are both conducted, the bus system enters a power supply time period T1; when the first and second switch circuits are open, the bus system enters a status poll and reply period T2.

8. The CRPB bus system as claimed in claim 4, wherein the polling signal sending unit is implemented by a third switch circuit controlled by a polling switch, and the polling switch comprises at least one of a bipolar transistor and a field effect transistor; the response receiving unit is realized by adopting a first optical coupling circuit; the response sending unit is realized by adopting a fourth switch circuit controlled by a response switch, and the response switch comprises at least one of a bipolar transistor and a field effect transistor; the polling signal receiving unit is realized by adopting a second optical coupling circuit;

9. The CRPB bus system of claim 8, wherein the third and fourth switch circuits are of the same circuit design; the first optical coupler circuit and the second optical coupler circuit adopt the same circuit design comprising a photoelectric coupler.

10. The CRPB bus system of any one of claims 1 to 3, wherein the host bus control module is a separate processor or integrated in a host processor; and/or the slave bus control module is an independent processor or is integrated in a slave processor.