CN114650073B - Linearization correction method and device for radio frequency receiver - Google Patents
Linearization correction method and device for radio frequency receiver Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a linearization correction method and device of a radio frequency receiver. The invention comprises the following steps: the device comprises a radio frequency receiver, an active combiner, a second-order intermodulation component generator, an amplitude regulator, a phase regulator, a baseband multiplier and an analog switch; the input differential radio frequency signal is amplified by a main path and a correction branch circuit to obtain a differential linear baseband signal output; in the correction branch, an input radio frequency signal is converted into a second-order intermodulation product by a second-order intermodulation product generator, amplitude phase conditioning is carried out, and multiplication operation is carried out on the second-order intermodulation product and an output signal of a main path receiver to obtain a conditioned third-order intermodulation distortion component; the third order intermodulation distortion component is superimposed on the third order distortion component in the receiver output signal by an active combiner and cancelled in the final output signal. The invention suppresses the distortion in the signal, improves the linear fundamental frequency term, and realizes higher signal-to-noise ratio and communication effect.
Description
Technical Field
The present invention relates to a method and an apparatus for linearization correction, and more particularly, to a method and an apparatus for linearization correction of a radio frequency receiver.
Background
Communication circuits typically suffer from intermodulation distortion and intermodulation distortion.
Nonlinear DUTs (e.g., LNAs, PAs, turrets) when signals of multiple frequencies are input, interactions between the individual spectral components occur, creating new spectral components (spectral regeneration); when the amplifier works in a linear region with a small enough input signal, intermodulation distortion is not deteriorated and is kept at a relatively balanced level; as the power input to the DUT increases, the amplifier gradually enters the compression region, and intermodulation distortion will deteriorate rapidly.
The new frequency components are generated by the passage of signals of two or more different frequencies through an amplifier or loudspeaker, which distortion is typically caused by active devices (e.g. transistors, transistors) in the circuit. The magnitude of the distortion is related to the output power, and since these newly generated frequency components have no similarity to the original signal, less intermodulation distortion is also easily perceived by the human ear.
Intermodulation distortion (intermodulation distortion) refers to the sum and difference distortion of an input signal introduced by an amplifier. For example, intermodulation distortion components are generated after the mixed signal is input to the amplifier.
Intermodulation distortion refers to distortion caused by intermodulation of signals, and the term modulation refers to a technique used in communication technology to improve signal transmission efficiency. The original signal containing sound, image, text, etc. is "added" to the high frequency signal, and then the resultant signal is transmitted. This process and manner of adding the high and low frequency phases is referred to as modulation techniques, and the resultant signal is referred to as a modulated signal. The modulated signal contains all information of the low frequency signal in addition to the main characteristics of the high frequency signal.
The research on linearization technology of radio frequency receivers has been a technical focus of continuous attention, and as protocols of radio frequencies are crowded, interference in available frequency spectrums is more and more, and linear performance challenges of the front end of a monolithically integrated radio receiver are more and more serious. In the sub-6GHz frequency band, the main stream receiver architecture includes an LNA+MIXER+TIA architecture and a MIXER preamble architecture. Both structures have performance advantages and disadvantages. However, there is considerable room for improvement in both structures for small signal linearity. In principle, each module in the circuit contributes more or less non-linear components when doing a linear amplification process. Thus, linearization techniques of circuit elements in both receivers are becoming increasingly important if high-linearity capabilities at the system level are desired.
Retrospectively, representative of linearization techniques for mixer Circuits are literature [ W.Cheng, A.J.Annema, G.J.M.Wienk, and B.Nauta, "A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance," IEEE J.solid-State Circuits, vol.48, no.10, pp.2390-2402, oct.2013, doi:10.1109/JSSC.2013.2272339 ]. In this report, as shown in fig. 2, the source node of the mixer switch adopts a negative resistance topology, which can cancel the inherent IM3 component generated in the mixer. IIP3 results of 11.8dBm were found. The method not only suppresses third-order nonlinearity, but also significantly improves flicker noise of the current commutation mixer.
On the other hand, for low noise amplifier circuits, common linearization techniques include derivative superposition, post-distortion techniques, and the like. For example, documents [ b.guo, g.wen, and s.an, "6.8mW 15dBm IIP3 CMOS common-gate LNA employing post-linearisation technique," electron. Lett., vol.50, no.3, pp.149-151,2014 ] propose a post-distortion technique to improve IIP3, achieving a point frequency improvement effect better than 8dB, as shown in fig. 3. Thereafter, in order to enhance the linearization effect of the wideband, digital assist techniques have been introduced to adjust the distortion component as a function of the frequency of the input signal to balance the final linear output result signal [ representative literature, B.Guo, J.Chen, H.Chen, and x.wang, "a 0.1-1.4GHz inductorless low-noise amplifier with 13dBm IIP3 and 24dBm IIP2 in 180nm CMOS," mod. Phys. Lett. B, vol.32, no.02, p.1850009,2018 ], as shown in fig. 4 ]. Thereafter, the literature [ H.Yu, Y.Chen, C.C.Boon, P.—I.Mak, and R.P. Martins, "A0.096-mm $ {2} -1 $ -20-GHz Triple-Path Noise-gating on-Gate Common-Source LNA With Dual Complementary pMOS-nMOS Configuration," IEEE Trans. Microw.Thery tech., vol.68, no.1, pp.144-159, jan.2020, doi:10.1109/TMTT.2019.2949796 ], designs ultra wideband performance effects on the same circuit by means of advanced process lines. Note, however, that its IP3 linearity exhibits sharp fluctuations within the bandwidth and cannot linearly amplify signals within all pass bands.
In view of the design of an LNA+MIXER+TIA receiving system, the LNA module mainly contributes to a third-order distortion component (hereinafter referred to as IP 3); the second-order distortion component (hereinafter referred to as IP 2) is mainly derived from random mismatch of the mixer; the baseband TIA affects the second-order distortion component and the third-order distortion component at the same time, and enough feedback depth is needed to ensure the linear processing capability of the passive feedback network; in summary, based on the conventional isolated module linearization circuit technology, it is difficult to ensure that the circuits are cascaded and exhibit high linearity as a whole, because some complex nonlinear behavior may cause undesirable linear degradation behavior (such as second order interaction mechanism, cross modulation caused by capacitive memory characteristics at high frequencies) between the circuit modules.
Thus, the following technical situations can be summarized: the prior linearization technology is more innovative and improved in circuit module units. The overall linearity performance of the circuit after system integration cannot be guaranteed. The linearization of the circuit has the characteristics of point frequency or narrow band, and cannot meet the requirements of broadband communication today. Furthermore, for current direct conversion receivers, both IP2 and IP3 are linearity indicators to be considered. Whereas the prior art is more embodied in optimizing the design of IP 3. These limitations are all in need of new solutions.
Disclosure of Invention
Aiming at the problems in the background technology, the invention provides a linearization correction method and device of a radio frequency receiver, which aim to inhibit distortion in signals, promote linear fundamental frequency items and realize higher signal-to-noise ratio and communication effect.
The invention solves the technical problems and provides the following technical proposal:
a method for linearization correction of a radio frequency receiver, comprising the steps of:
step one: inputting the double-tone signals frf1 and frf2, setting the correction range of the amplitude of the double-tone signals to Prf [1, 2, 3 … N]Setting the phase correction range of the dual-tone signal as Deltaf [1, 2, 3 … M]The method comprises the steps of carrying out a first treatment on the surface of the Wherein Δf=f1-f 2 and the starting parameter is [ Prf i ,Δf j ]；
Step two: the correction branch switches sw 1-3 are disconnected, and only the fundamental frequency amplitude P1st and the third-order intermodulation distortion amplitude P3rd of the output end are measured when the main path works; calculating to obtain an initial value result of IP3;
step three: closing correction branch switches sw 1-3, and connecting an auxiliary path, and adjusting the amplitude of the linear feedforward branch by controlling a switch K5-9, a resistor R8-11 and a resistor R13-15; a correction probe for phase adjustment is performed by controlling the variable resistor R18 and the variable capacitor C9;
under the condition of enabling a correction branch, re-measuring the amplitude values P1st and P3rd of the final output end of the receiver, and obtaining an IP3 corrected result;
step four: combining the initial value result of the IP3 when the correction is not added before, and comparing the corrected result of the IP3 to obtain the effect delta IP3 of correcting and improving the front and back of the IP3;
repeating the third step until the correction effect reaches the expected value; and recorded at [ Prf i ,Δf j ]When inputting, the obtained correction cell information is [ A ] ij ,φ ij ]；
Step five: performing different signal powers Prf i Signal pitch Δf j The new round of correction and adjustment of the system is completed until all the input power and the baseband bandwidth range are covered;
the resulting matrix of stored values is [ A ] ij ] M,N And
the correction data is stored in a lookup table of the receiver back-end DSP for recall.
Preferably, the correction branch circuit includes an intermodulation distortion correction branch circuit for correcting third-order intermodulation distortion and an intermodulation distortion correction branch circuit for correcting second-order intermodulation distortion;
the intermodulation distortion correction branch circuit includes: a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier;
the intermodulation distortion correction branch includes: second-order intermodulation component generator, amplitude regulator, phase regulator.
Preferably, the device for realizing the linearization correction method of the radio frequency receiver comprises a main path for receiving and amplifying signals and a intermodulation distortion correction branch for correcting the signals;
the main path comprises an input end, a radio frequency receiver, an active combiner and an output end which are sequentially coupled;
the intermodulation distortion correction branch circuit comprises a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier which are sequentially coupled;
the input end comprises ports Vin+ and Vin-; the output end comprises ports Vout+ and Vout-;
the first input end of the radio frequency receiver is coupled with the port Vin+, and the second input end of the radio frequency receiver is coupled with the port Vin-;
the first input end of the active combiner is coupled to the first output end Vout1 of the radio frequency receiver, and the two input ends of the active combiner Lu Qidi are coupled to the second output end Vout2 of the radio frequency receiver; the first output end of the active complex Lu Qidi forms a port Vout+, and the second output end of the active complex Lu Qidi forms a port Vout-;
the first input end of the second-order intermodulation product generator is coupled with a port Vin+ through a switch K1; the second input end of the second-order intermodulation product generator is coupled with the port Vin-;
the second-order intermodulation product generator first output end is coupled to the amplitude regulator first input end, and the second-order intermodulation product generator second output end is coupled to the amplitude regulator second input end;
the first output end of the amplitude regulator is coupled to the first input end of the phase regulator, and the second output end of the amplitude regulator is coupled to the second input end of the phase regulator;
the first output end of the phase regulator is coupled to the first input end of the baseband multiplier, and the second output end of the phase regulator is coupled to the second input end of the baseband multiplier;
the forward input end Vin1 of the amplifier A2 is coupled to the first output end Vout1 of the radio frequency receiver, the reverse input end Vin2 of the amplifier A2 is coupled to the second output end Vout2 of the radio frequency receiver, the positive output end Vout3 of the amplifier A2 is coupled to the third input end of the baseband multiplier, and the reverse output end Vout4 of the amplifier A2 is coupled to the fourth input end of the baseband multiplier;
the first output end of the baseband multiplier is coupled with three input ends of an active complex Lu Qidi through a switch K3, and the second output end of the baseband multiplier is coupled with four input ends of the active complex Lu Qidi through a switch K4;
the input differential radio frequency signals are input by ports Vin+ and Vin-, and are amplified by a main path and a correction branch respectively, and differential linear baseband signal output is obtained at Vout+ and Vout-ports;
and in a correction branch, converting the input radio frequency signal into a second-order intermodulation product by a second-order intermodulation product generator, regulating the amplitude by an amplitude regulator, regulating the phase by a phase regulator, multiplying the regulated signal with a differential linear baseband signal output by a main path radio frequency receiver of an amplifier A2, superposing the regulated signal with the differential linear baseband signal output by the radio frequency receiver by an active combiner to obtain an output signal, and canceling the third-order distortion component after the superposition by the active combiner to finally ensure that the output signal only contains a linear fundamental frequency item.
Preferably, the active combiner comprises a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, and an amplifier A1;
one end of the resistor R23 is connected with the positive input end Vin3 of the amplifier A1, the other end of the resistor R23 forms a first input end of the active combiner, one end of the resistor R25 is connected with the negative input end Vin4 of the amplifier A1, and the other end of the resistor R25 forms an active combiner Lu Qidi;
one end of the resistor R26 is connected with the negative input end Vin4 of the amplifier A1, the other end of the resistor R24 forms three input ends of an active combination Lu Qidi, one end of the resistor R24 is connected with the positive input end Vin3 of the amplifier A1, and the other end of the resistor R24 forms four input ends of the active combination Lu Qidi;
one end of the resistor R27 is connected with the positive input end Vin3 of the amplifier A1, the other end of the resistor R28 is connected with the negative input end Vin4 of the amplifier A1, and the other end of the resistor R28 is connected with the positive output end Vout6 of the amplifier A1;
the negative output terminal Vout5 of the amplifier A1 forms an output terminal of the active combiner Lu Qidi, and the positive output terminal Vout6 of the amplifier A1 forms two output terminals of the active combiner Lu Qidi.
Preferably, the second order intermodulation product generator comprises: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6;
the first input end of the second-order intermodulation product generator is connected with the gate end of the NMOS tube M3 of the second-order intermodulation product generator and one end of the resistor R1 through a capacitor C1, and the second input end of the second-order intermodulation product generator is connected with the gate end of the NMOS tube M2 of the second-order intermodulation product generator and one end of the resistor R2 through a capacitor C2;
the source end of the NMOS tube M1 is connected with the drain end of the NMOS tube M2 and the drain end of the NMOS tube M3, the drain end of the NMOS tube M1 is connected with the gate end of the NMOS tube M4 through a capacitor C5, the drain end of the NMOS tube M1 is connected with a power supply voltage Vdd through a resistor R3 and a capacitor C3 which are connected in parallel, the gate end of the NMOS tube is connected with a bias voltage Vb2, and the source ends of the NMOS tube M2 and the NMOS tube M3 are grounded;
the drain end of the NMOS tube M4 is connected with a power supply voltage Vdd through a resistor R5 and a capacitor C4 which are connected in parallel, and the drain end of the NMOS tube M4 forms a first output end of the second-order intermodulation component generator through a capacitor C7; the source end of the NMOS tube M4 is grounded through a resistor R6 and a capacitor C6 which are connected in parallel, and the source end of the NMOS tube M4 forms a second output end of the second-order intermodulation component generator; the gate end of the NMOS tube M4 is connected with one end of a capacitor C5 and one end of a resistor R4, and the other end of the resistor R4 is connected with a bias voltage Vb 3;
the other ends of the resistors R1 and R2 are connected to the bias voltage Vb 1.
Preferably, the amplitude adjuster includes: NMOS tube M5, NMOS tube M6, NMOS tube M13, NMOS tube M14, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R9a, resistor R11a, capacitor C8, switch K5, switch K6, switch K7, switch K8, switch K9;
the first input end of the amplitude regulator is connected with the gate end of the NMOS tube M5, and the second input end of the amplitude regulator is connected with the gate end of the NMOS tube M6 through a capacitor C8;
the gate end of the NMOS tube M5 is connected with one end of a capacitor C7 and one end of a resistor R7, and the other end of the resistor R7 is connected with a bias voltage Vb 4;
the drain end of the NMOS tube M5 is connected with a power supply voltage Vdd through a resistor R9a, a resistor R9 and a resistor R8 in sequence, the source end of the NMOS tube M5 is connected with the drain end of the NMOS tube M13, and the source end of the NMOS tube M13 is grounded;
a switch K7 and a resistor R13 connected in series are connected in parallel with a switch K8 and a resistor R14 connected in series, and a switch K9 and a resistor R15 connected in series;
the drain end of the NMOS tube M13 is connected with one ends of the switch K7, the switch K8 and the switch K9, the drain end of the NMOS tube M14 is connected with one ends of the resistor R13, the resistor R14 and the resistor R15, the source end of the NMOS tube M14 is grounded, the source end of the NMOS tube M6 is connected with the drain end of the NMOS tube M14, and the gate ends of the NMOS tube M13 and the NMOS tube M14 are connected with the bias voltage Vb 0;
the gate end of the NMOS tube M6 is connected with one end of a capacitor C8 and one end of a resistor R12, and the other end of the resistor R12 is connected with a bias voltage Vb 5;
the drain end of the NMOS tube M6 is connected with a power supply voltage Vbb through a resistor R11a, a resistor R11 and a resistor R10 in sequence, one end of a switch K5 is connected with one ends of a resistor R8 and a resistor R9, and the other end of the switch K5 is connected with one ends of the resistor R10 and the resistor R11;
one end of the switch K6 is connected with one ends of the resistor R9 and the resistor R9a, and the other end of the switch K6 is connected with one ends of the resistor R11 and the resistor R11 a;
one ends of the resistor R11 and the resistor R11a constitute a first output end of the amplitude adjuster, and one ends of the resistor R9 and the resistor R9a constitute a second output end of the amplitude adjuster.
Preferably, the phase adjuster includes: resistor R16, resistor R17, resistor R18, and capacitor C9;
a resistor R16 and a resistor R17 which are connected in series are connected in parallel with a resistor R18 and a capacitor C9 which are connected in series;
one end of the resistor R16 and one end of the resistor R18 form a first input end of the phase adjuster, and one end of the resistor R17 and one end of the capacitor C9 form a second input end of the phase adjuster;
one end of the resistor R18 and one end of the capacitor C9 are connected with one end of the resistor R20 through the capacitor C11 to form a first output end of the phase regulator;
one end of the resistor R16 and one end of the resistor R17 are connected with one end of the resistor R19 through a capacitor C10 to form a second output end of the phase regulator;
the other end of the resistor R19 and the other end of the resistor R20 are connected to the bias voltage Vb 6.
Preferably, the baseband multiplier includes: NMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, NMOS tube M15, NMOS tube M16, resistor R19, resistor R20, resistor R21, resistor R22;
the gate end of the NMOS tube M9 and the gate end of the NMOS tube M10 are connected to form a first input end of the baseband multiplier;
the gate end of the NMOS tube M8 and the gate end of the NMOS tube M11 are connected to form a second input end of the baseband multiplier;
the drain end of the NMOS tube M9 is connected with the drain end of the NMOS tube M11 through a resistor R22 and is connected with the power supply voltage Vbb, the drain end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 through a resistor R21 and is connected with the power supply voltage Vbb, and the drain end of the NMOS tube M7 is connected with the power supply voltage Vbb;
the drain end of the NMOS tube M9 is connected with the drain end of the NMOS tube M11 to form a first output end of the baseband multiplier;
the drain end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 to form a second output end of the baseband multiplier;
the gate end of the NMOS tube M7 is connected with the positive-phase output end Vout3 of the amplifier A2, the drain end of the NMOS tube M12 is connected with the power supply voltage Vbb, and the gate end of the NMOS tube M12 is connected with the negative-phase output end Vout4 of the amplifier A2;
the source end of the NMOS tube M7, the source end of the NMOS tube M8 and the source end of the NMOS tube M9 are connected with the drain end of the NMOS tube M15;
the source end of the NMOS tube M10, the source end of the NMOS tube M11 and the source end of the NMOS tube M12 are connected with the drain end of the NMOS tube M16;
the source terminal of the NMOS tube M15 is grounded, the source terminal of the NMOS tube M16 is grounded, and the gate terminals of the NMOS tube M15 and the NMOS tube M16 are connected with bias voltage Vb 0.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. the invention uses an extra parallel correction branch to counteract nonlinearity on the main path, the circuit provided by the invention covers the main path and the correction branch, and the main path comprises a radio frequency receiver and an active combiner; the correction branch comprises a second-order intermodulation component generator, an amplitude regulator, a phase regulator and a baseband multiplier. It employs an additional parallel correction branch to counteract the non-linearities on the main path. Nonlinear components of the same magnitude and opposite sign as the main path are generated on the correction branches. The nonlinear signal component of the receive path is cancelled by linear superposition of the final stage combiner, resulting in a linear signal at the output.
2. The design is flexible to use, because the correction branch operating frequency is baseband, the consumed power is not high, and the correction branch operating frequency is not sensitive to parasitic effects like a radio frequency circuit.
3. Unlike available module unit linearizing technology, the present invention makes linearizing correction to the front end of the whole receiver. The invention does not depend on the topology structure in the radio frequency receiver and the radio frequency coverage area, and has wide applicability.
4. Unlike traditional IP3 optimizing technology, the invention can realize simultaneous optimization of IP2 and IP3 and adapt to the application requirement of the current direct conversion receiver.
5. Different from the linearization narrowband characteristic of the traditional circuit, the invention can optimally adjust the correction branch circuit in a proper state by means of a digital control technology so as to obtain the linearization effect in a broadband range. And is better suited to today's broadband communication needs.
Drawings
FIG. 1 is a diagram showing the steps of a linearization correction technique according to the present invention.
Fig. 2 is a mixer linearization architecture based on negative resistance technology.
Fig. 3 is a low noise amplifier linearization architecture based on post-distortion techniques.
Fig. 4 is a broadband low noise amplifier linearization architecture based on a numerical assist technique.
Fig. 5 is a diagram showing a specific implementation structure of the linearization correction circuit according to the present invention.
Fig. 6 is a schematic block diagram of linearization correction proposed by the present invention.
Fig. 7 is a phase compensation network structure diagram and a transfer amplitude-phase characteristic diagram.
Fig. 8 is a graph comparing changes in receiver noise figure before and after using the correction branch.
Fig. 9 is a graph comparing changes in receiver linearity IP3 before and after the use of the correction branch.
Fig. 10 is a graph comparing changes in receiver linearity IP2 before and after the use of the correction branch.
Detailed Description
In order to make the technical means, features and effects achieved by the present invention easier to understand, the technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the specific embodiments and the drawings in the embodiments of the present invention.
Referring to fig. 1-10, for those skilled in the art to better understand the principles of the present invention, the working principle of the linearization circuit of the radio frequency receiver proposed by the present invention is illustrated as follows:
fig. 6 shows a simplified block diagram of a linearization correction solution. It can be seen that the linearization scheme is implemented by adding an auxiliary path in parallel with the original receiver. Along the main path of signal transmission, is the main channel of the receiver. Specifically, for a dual-tone radio frequency input signal, frf1 (i.e., flo+f1) and frf2 (i.e., flo+f2), there is a large amount of nonlinear spectrum generation at the output side of the receiver due to the nonlinear factor of the channel. As shown, the spectrum falling within the band can be seen to have third order intermodulation distortion components, and second order intermodulation distortion components. The second order intermodulation distortion components f1+f2 falling outside the band are typically caused by the baseband circuit contribution of the latter stage of the mixer; the 2flo+f1+f2 distortion component is in turn contributed by the radio frequency low noise amplifier. Irrespective of the effect of the out-of-band distortion component, we need to compensate for the in-band second order third order distortion component to improve the linearity of the receiver.
Note that in the auxiliary path, frf1 and frf2 are for the dual tone radio frequency input signal. Intermodulation products f1-f2 and 2flo+f1-f2 can be obtained by the second order intermodulation product intermodulation generation circuit. Due to the low-pass filtering characteristic of the baseband channel, the sum frequency term 2flo+f1-f2 is effectively suppressed and ignored. The difference frequency terms f1-f2 are multiplied by the amplitude and phase adjustment of the later stage and the multiplier unit circuit, and the other group of input signals of the multiplier come from the fundamental frequency terms f1 and f2 of the receiver. As a result, the multiplier output can obtain the output spectrum shown in fig. 5. In principle, the phases of the fIM3, L fIM3, H component and the fIM3, L fIM3, H component output by the receiver are reversed and the amplitudes are equal, so that the fIM3, L fIM3, H component is eliminated through the output of the final stage combiner (using an operational amplifier). It is also noted that the output frequency of the multiplier also has byproducts f1, f2, so it is envisioned that the addition of auxiliary paths may also increase the gain of the circuit appropriately. The function of the amplifier A2 is to adjust the amplitude, so that the main path baseband signal participates in the multiplier operation with a constant amplitude, and extra nonlinear products are avoided.
Similar to the nonlinear compensation principle of the third-order intermodulation, the nonlinear compensation of the second-order intermodulation can be correspondingly realized. And the auxiliary path is observed again, and is different from a compensation channel of the third-order intermodulation, the second-order intermodulation does not need the participation of a multiplier, and only the adjustment of the amplitude phase can be used for adjusting and controlling the second-order intermodulation component, so that the in-band intermodulation components f1-f2 of the main path are eliminated through the superposition of the final-stage combiner.
In the following, taking IP3 correction as an example, fig. 1 illustrates a basic step flow of the operation of the correction circuit, and similarly, IP2 correction may be obtained by referring to the description thereof, which is omitted.
The two tone signals frf1 and frf2 are first input, and the amplitude correction range Prf [1 … N ] thereof is set]And a range of the two-tone pitch of Δf (f 1-f 2) [1 … M]. And the initiation parameter is [ Prf i ,Δf j ]。
The correction branch switches sw 1-3 are turned off, only the fundamental frequency amplitude P1st of the output end and the third-order intermodulation distortion amplitude P3rd are measured when the main path works,
closing the correction branch switches sw 1-3 to perform amplitude and phase adjustment correction of the linear feedforward branch,
the magnitudes P1st and P3rd of the final output of the receiver are measured again,
and combining the results when the correction is not added before, and comparing the effect of the front-back correction promotion of the IP 3. If the comparison result does not reach the expected value, continuing to adjust the linear feedforward branch until the correction effect reaches the expected value. And recorded at [ Prf i ,Δf j ]When inputting, the obtained correction cell information is [ A ] ij ,φ ij ]The amplitude and phase circuit control mapping relation is included: a01&φ01，A02&Phi 02, resistance, capacitance tuning control in a2 cell.
Performing different signal powers Prf i Signal pitch Δf j Until all ranges are covered. The correction flow is ended and the obtained stored numerical matrix is [ A ] ij ] M,N ，
As shown in fig. 6, the numerical matrix [ a ] is corrected ij ] M,N ，
Stored in the receiver's dsp in the form of a lookup table for recall. In the actual receiving process of the receiver at a specific position of a certain cell, when the base station distributes pilot frequency information for the terminal, the terminal simultaneously obtains the input power level prf of the signal sent by the base station to the antenna port of the terminal i Information, combined with the allocated channel condition, determines the actual local oscillation frequency and baseband bandwidth deltaf j . Thereafter, the terminal DSP reads the correction data A in the look-up table ij And phi ij Corresponding to a specific input power prf i And a frequency spacing Δf j Mapping into actual amplitude, phase circuit control information: the module circuits a01 and phi 01 in fig. 6, and the module circuits a02 and phi 02, the resistor, capacitor tuning control in the a2 cell. In this way, the controlled auxiliary path can compensate and eliminate distortion components in real time when the main path receives communication data, and ensures high dynamic range communication receiving quality.
From the above technical steps, it can be seen that the receiver of the main path is regarded as a black box, the nonlinear relation among the internal circuits of the receiver is not concerned, and the branching component of the output is quantitatively obtained and eliminated by the aid of the auxiliary path. Therefore, the invention can not depend on the topology structure in the radio frequency receiver and the radio frequency coverage area, and has wide applicability. In the above operation practice, the correction parameters may be correspondingly simplified or refined according to the actually obtained receiver nonlinear characteristics. For example, for a sub-6GHz receiver, whose baseband frequency is typically within 20MHz, the nonlinear behavior is less sensitive to changes in frequency spacing Δf, and thus the number of samples of Δf (f 1-f 2) [1 … M ] can be significantly reduced. The amplitude correction range Prf [1 … N ] is also taught, and in the small signal range, the increase of P3rd is quite linear, so that the sampling point can be reduced, after Prf-30 dBm, the nonlinear change is complex, the high-order product P5rd can be added, and at this time, the sampling point range of Prf near the power level can be increased, so as to obtain a good overall correction effect.
Referring again to fig. 5, the second order intermodulation product generating circuit is generated using transistor pair M23. For a structure like this, after differential signal input, the fundamental frequency is cancelled, the even term is reserved, f1-f2 in the even term is reserved and transmitted to the post-processing due to the low-pass filtering effect of R3C3 at the load, and other Gao Jieou terms are filtered.
Due to the nonlinear complexity of the main path and the auxiliary path and the delay difference of signal transmission, the phases of the fIM3, L fIM3 and H components obtained by the compensation path and the fIM3, L fIM3 and H components output by the main path receiver are difficult to achieve accurate 180-phase reversal, amplitude matching is difficult to achieve, and the effect of the method is degraded. It is necessary to introduce an amplitude, phase adjustment unit.
The amplitude adjustment circuit shown in fig. 5 is a differential structure amplifier, and a switch array is designed at the load and at the source to adjust the gain amplitude of the amplifier. The gain expression may be abbreviated as
g m56 R 8～11,16～17 /(1+g m56 R 13～15 )；
Where gm56 is the transconductance of transistor M56, R8-11,16-17 is the load equivalent resistance R13-15 is the source equivalent degeneration resistance. K5-K9 is realized by adopting a mos tube working in a three-stage tube region, and the magnitude control of the equivalent resistance of the mos tube can be realized through the tuning of the grid bias voltage. By combining the switch array section bit control mode of R8-11R 13-15, the wide-range control tuning of the gain can be obtained.
Here, the required phi can be obtained by regulating the R16-18C9 network through the passive phase shift network shown in FIG. 7 ij Offset [ ]Typically less than 90 degrees). For different prfs i ,Δf j Only tuning R18C9 is required to obtain a product of ω ij Phi required at the position ij Offset amount. The network amplitude is constant, and the amplitude is not affected in the phase adjustment process. So that we can achieve independent tuning of the two parameters of amplitude, phase.
Fig. 5 shows the multiplier based on an active mixer architecture but modified. The main path receiver signal is connected with one path of signal in a source follower mode through M7/M12, and the grid electrode of the M8-11 transistor pair is connected with the other path of auxiliary path signal. Here, the M8-11 transistor pair operates in a small signal amplified state without periodic switching of current. The power consumption requirement of the front-stage circuit is reduced without the high intensity of auxiliary path signals; more importantly, the small signal operation of the multiplier reduces the nonlinear behavior generated by the current hard switching in the traditional structure and powerfully ensures the offset effect of the auxiliary path.
The final stage combiner is a multi-input operational amplifier structure, and the operational amplifier unit is required to provide enough gain bandwidth products to ensure that the combiner performs linear superposition summation operation within the bandwidth of the receiver. The analog switches K1-6 in fig. 5 are implemented using MOS operating in the triode region, and the control of the high and low levels of the gates enables the switching of the switches. The structure of the variable gain amplifier A2 is similar to the differential pair structure of amplitude adjustment, and a diagram is not given here alone. The correction characteristics of the auxiliary path channel are not dependent on the structural characteristics of the rf receiver and the rf frequency range. However, it should be noted that the baseband frequency range constitutes a limitation of the use of the present invention. In other words, the circuits of the auxiliary path all operate at baseband frequencies, which necessarily has a compromise of gain and bandwidth. On the premise of matching the baseband bandwidth of the radio frequency receiver, the power consumption and the gain of the auxiliary path are required to be optimally designed. In addition, for the other branch structure for correcting IP2 in the auxiliary path shown in fig. 6, an amplitude adjuster and a phase adjuster structure are used, which are the same as those shown in fig. 5. However, since the second-order distortion component and the third-order distortion component in the main path generally have significant differences in amplitude and phase information, an additional amplitude and phase adjustment branch needs to be designed in the auxiliary path to compensate for the second-order distortion.
The embodiment realizes the linearization correction circuit of the radio frequency receiver by adopting a 65nm standard CMOS process design and adopts 1.2/1.8V dual-voltage power supply. The radio frequency receiver to be corrected adopts an LNA+MIXER+TIA current mode structure, the baseband bandwidth is 20MHz, and the radio frequency bandwidth is 0.5-4GHz. The rf receiver was removed and the remaining circuitry of fig. 5 had a power consumption of 18.6mW. The electrical properties obtained by simulation are as follows, and the noise figure results at the local oscillation frequency of 0.5-4GHz are shown in fig. 8, and it can be seen that the noise figure degradation caused by the introduction of the auxiliary path can be controlled within the average level of 0.3 dB. Fig. 9 shows the output of IP3 at a frequency of 0.5-4GHz, where the input signal power prf= -30dBm, where the intermediate frequency is at 10MHz and the duplex frequency spacing Δf is chosen to be 2MHz, it can be seen that the IP3 is significantly improved over the entire wideband range with an improvement of about 13.5dB after the auxiliary path is used. Also over the entire wideband, the IP2 improvement effect is shown in fig. 10, with IP2 achieving an improvement of approximately 20 dB. In addition, by adjusting Δf within the baseband bandwidth and performing the correction steps of the auxiliary path in the illustration, a high robustness result of IP3 with Δf can be obtained, and on the other hand, increasing the input signal power prf to-15 dBm can also correspondingly obtain a similar linearity correction boost performance, and no separate illustration is given here. In general, the present invention provides a technique for linearization correction of a radio frequency receiver circuit. The method has the characteristics of good applicability and flexible use, and can be widely applied to 5G wireless communication equipment.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (8)
1. A method for linearization correction of a radio frequency receiver, characterized by: the method comprises the following steps:
step one: inputting the double-tone signals frf1 and frf2, setting the correction range of the amplitude of the double-tone signals to Prf [1, 2, 3 … N]Setting the phase correction range of the dual-tone signal as Deltaf [1, 2, 3 … M]The method comprises the steps of carrying out a first treatment on the surface of the Wherein Δf=f1-f 2 and the starting parameter is [ Prf i ,Δf j ]；
Step two: the correction branch switches sw1, sw2 and sw3 are disconnected, and only the fundamental frequency amplitude P1st and the third-order intermodulation distortion amplitude P3rd of the output end are measured when the main path works; calculating to obtain an initial value result of IP3;
step three: closing correction branch switches sw1, sw2 and sw3, and enabling an auxiliary path to be connected, wherein at the moment, amplitude adjustment of a linear feedforward branch is performed by controlling switches K5, K6, K7, K8, K9, resistors R8, R9, R10 and R11 and resistors R13, R14 and R15; a correction probe for phase adjustment is performed by controlling the variable resistor R18 and the variable capacitor C9;
under the condition of enabling a correction branch, re-measuring the amplitude values P1st and P3rd of the final output end of the receiver, and obtaining an IP3 corrected result;
step four: combining the initial value result of the IP3 when the correction is not added before, and comparing the corrected result of the IP3 to obtain the effect delta IP3 of correcting and improving the front and back of the IP3;
repeating the third step until the correction effect reaches the expected value; and recorded at [ Prf i ,Δf j ]When inputting, the obtained correction cell information is [ A ] ij ,φ ij ]；
Step five: performing different signal powers Prf i Signal pitch Δf j The new round of correction and adjustment of the system is completed until all the input power and the baseband bandwidth range are covered;
the resulting matrix of stored values is [ A ] ij ] M,N And
the correction data is stored in a lookup table of the receiver back-end DSP for recall.
2. The method for linearization correction of a radio frequency receiver of claim 1, wherein: the correction branch circuit comprises an intermodulation distortion correction branch circuit for correcting third-order intermodulation distortion and an intermodulation distortion correction branch circuit for correcting second-order intermodulation distortion;
the intermodulation distortion correction branch circuit includes: a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier;
the intermodulation distortion correction branch includes: second-order intermodulation component generator, amplitude regulator, phase regulator.
3. A linearization correction device for a radio frequency receiver, characterized in that: apparatus for implementing the method of any one of claims 1 or 2, comprising a main path for receiving and amplifying the signal and an intermodulation distortion correction branch for correcting the signal;
the main path comprises an input end, a radio frequency receiver, an active combiner and an output end which are sequentially coupled;
the intermodulation distortion correction branch circuit comprises a second-order intermodulation component generator, an amplitude regulator, a phase regulator, an amplifier A2 and a baseband multiplier which are sequentially coupled;
the input end comprises ports Vin+ and Vin-; the output end comprises ports Vout+ and Vout-;
the first input end of the radio frequency receiver is coupled with the port Vin+, and the second input end of the radio frequency receiver is coupled with the port Vin-;
the first input end of the active combiner is coupled to the first output end Vout1 of the radio frequency receiver, and the two input ends of the active combiner Lu Qidi are coupled to the second output end Vout2 of the radio frequency receiver; the first output end of the active complex Lu Qidi forms a port Vout+, and the second output end of the active complex Lu Qidi forms a port Vout-;
the first input end of the second-order intermodulation product generator is coupled with a port Vin+ through a switch K1; the second input end of the second-order intermodulation product generator is coupled with the port Vin-;
the second-order intermodulation product generator first output end is coupled to the amplitude regulator first input end, and the second-order intermodulation product generator second output end is coupled to the amplitude regulator second input end;
the first output end of the amplitude regulator is coupled to the first input end of the phase regulator, and the second output end of the amplitude regulator is coupled to the second input end of the phase regulator;
the first output end of the phase regulator is coupled to the first input end of the baseband multiplier, and the second output end of the phase regulator is coupled to the second input end of the baseband multiplier;
the forward input end Vin1 of the amplifier A2 is coupled to the first output end Vout1 of the radio frequency receiver, the reverse input end Vin2 of the amplifier A2 is coupled to the second output end Vout2 of the radio frequency receiver, the positive output end Vout3 of the amplifier A2 is coupled to the third input end of the baseband multiplier, and the reverse output end Vout4 of the amplifier A2 is coupled to the fourth input end of the baseband multiplier;
the first output end of the baseband multiplier is coupled with three input ends of an active complex Lu Qidi through a switch K3, and the second output end of the baseband multiplier is coupled with four input ends of the active complex Lu Qidi through a switch K4;
the input differential radio frequency signals are input by ports Vin+ and Vin-, and are amplified by a main path and a correction branch respectively, and differential linear baseband signal output is obtained at Vout+ and Vout-ports;
and in a correction branch, converting the input radio frequency signal into a second-order intermodulation product by a second-order intermodulation product generator, regulating the amplitude by an amplitude regulator, regulating the phase by a phase regulator, multiplying the regulated signal with a differential linear baseband signal output by a main path radio frequency receiver of an amplifier A2, superposing the regulated signal with the differential linear baseband signal output by the radio frequency receiver by an active combiner to obtain an output signal, and canceling the third-order distortion component after the superposition by the active combiner to finally ensure that the output signal only contains a linear fundamental frequency item.
4. A linearization correction device for a radio frequency receiver as in claim 3, wherein: the active combiner comprises a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28 and an amplifier A1;
one end of the resistor R23 is connected with the positive input end Vin3 of the amplifier A1, the other end of the resistor R23 forms a first input end of the active combiner, one end of the resistor R25 is connected with the negative input end Vin4 of the amplifier A1, and the other end of the resistor R25 forms an active combiner Lu Qidi;
one end of the resistor R26 is connected with the negative input end Vin4 of the amplifier A1, the other end of the resistor R24 forms three input ends of an active combination Lu Qidi, one end of the resistor R24 is connected with the positive input end Vin3 of the amplifier A1, and the other end of the resistor R24 forms four input ends of the active combination Lu Qidi;
one end of the resistor R27 is connected with the positive input end Vin3 of the amplifier A1, the other end of the resistor R28 is connected with the negative input end Vin4 of the amplifier A1, and the other end of the resistor R28 is connected with the positive output end Vout6 of the amplifier A1;
the negative output terminal Vout5 of the amplifier A1 forms an output terminal of the active combiner Lu Qidi, and the positive output terminal Vout6 of the amplifier A1 forms two output terminals of the active combiner Lu Qidi.
5. A linearization correction device for a radio frequency receiver as in claim 3, wherein: the second order intermodulation product generator comprises: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5 and resistor R6;
the first input end of the second-order intermodulation product generator is connected with the gate end of the NMOS tube M3 of the second-order intermodulation product generator and one end of the resistor R1 through a capacitor C1, and the second input end of the second-order intermodulation product generator is connected with the gate end of the NMOS tube M2 of the second-order intermodulation product generator and one end of the resistor R2 through a capacitor C2;
the source end of the NMOS tube M1 is connected with the drain end of the NMOS tube M2 and the drain end of the NMOS tube M3, the drain end of the NMOS tube M1 is connected with the gate end of the NMOS tube M4 through a capacitor C5, the drain end of the NMOS tube M1 is connected with a power supply voltage Vdd through a resistor R3 and a capacitor C3 which are connected in parallel, the gate end of the NMOS tube is connected with a bias voltage Vb2, and the source ends of the NMOS tube M2 and the NMOS tube M3 are grounded;
the drain end of the NMOS tube M4 is connected with a power supply voltage Vdd through a resistor R5 and a capacitor C4 which are connected in parallel, and the drain end of the NMOS tube M4 forms a first output end of the second-order intermodulation component generator through a capacitor C7; the source end of the NMOS tube M4 is grounded through a resistor R6 and a capacitor C6 which are connected in parallel, and the source end of the NMOS tube M4 forms a second output end of the second-order intermodulation component generator; the gate end of the NMOS tube M4 is connected with one end of a capacitor C5 and one end of a resistor R4, and the other end of the resistor R4 is connected with a bias voltage Vb 3;
the other ends of the resistors R1 and R2 are connected to the bias voltage Vb 1.
6. A linearization correction device for a radio frequency receiver as in claim 3, wherein: the amplitude adjuster includes: NMOS tube M5, NMOS tube M6, NMOS tube M13, NMOS tube M14, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, resistor R9a, resistor R11a, capacitor C8, switch K5, switch K6, switch K7, switch K8, switch K9;
the first input end of the amplitude regulator is connected with the gate end of the NMOS tube M5, and the second input end of the amplitude regulator is connected with the gate end of the NMOS tube M6 through a capacitor C8;
the gate end of the NMOS tube M5 is connected with one end of a capacitor C7 and one end of a resistor R7, and the other end of the resistor R7 is connected with a bias voltage Vb 4;
the drain end of the NMOS tube M5 is connected with a power supply voltage Vdd through a resistor R9a, a resistor R9 and a resistor R8 in sequence, the source end of the NMOS tube M5 is connected with the drain end of the NMOS tube M13, and the source end of the NMOS tube M13 is grounded;
a switch K7 and a resistor R13 connected in series are connected in parallel with a switch K8 and a resistor R14 connected in series, and a switch K9 and a resistor R15 connected in series;
the drain end of the NMOS tube M13 is connected with one ends of the switch K7, the switch K8 and the switch K9, the drain end of the NMOS tube M14 is connected with one ends of the resistor R13, the resistor R14 and the resistor R15, the source end of the NMOS tube M14 is grounded, the source end of the NMOS tube M6 is connected with the drain end of the NMOS tube M14, and the gate ends of the NMOS tube M13 and the NMOS tube M14 are connected with the bias voltage Vb 0;
the gate end of the NMOS tube M6 is connected with one end of a capacitor C8 and one end of a resistor R12, and the other end of the resistor R12 is connected with a bias voltage Vb 5;
the drain end of the NMOS tube M6 is connected with a power supply voltage Vbb through a resistor R11a, a resistor R11 and a resistor R10 in sequence, one end of a switch K5 is connected with one ends of a resistor R8 and a resistor R9, and the other end of the switch K5 is connected with one ends of the resistor R10 and the resistor R11;
one end of the switch K6 is connected with one ends of the resistor R9 and the resistor R9a, and the other end of the switch K6 is connected with one ends of the resistor R11 and the resistor R11 a;
one ends of the resistor R11 and the resistor R11a constitute a first output end of the amplitude adjuster, and one ends of the resistor R9 and the resistor R9a constitute a second output end of the amplitude adjuster.
7. A linearization correction device for a radio frequency receiver as in claim 3, wherein: the phase adjuster includes: resistor R16, resistor R17, resistor R18, and capacitor C9;
a resistor R16 and a resistor R17 which are connected in series are connected in parallel with a resistor R18 and a capacitor C9 which are connected in series;
one end of the resistor R16 and one end of the resistor R18 form a first input end of the phase adjuster, and one end of the resistor R17 and one end of the capacitor C9 form a second input end of the phase adjuster;
one end of the resistor R18 and one end of the capacitor C9 are connected with one end of the resistor R20 through the capacitor C11 to form a first output end of the phase regulator;
one end of the resistor R16 and one end of the resistor R17 are connected with one end of the resistor R19 through a capacitor C10 to form a second output end of the phase regulator;
the other end of the resistor R19 and the other end of the resistor R20 are connected to the bias voltage Vb 6.
8. A linearization correction device for a radio frequency receiver as in claim 3, wherein: the baseband multiplier includes: NMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, NMOS tube M15, NMOS tube M16, resistor R19, resistor R20, resistor R21, resistor R22;
the gate end of the NMOS tube M9 and the gate end of the NMOS tube M10 are connected to form a first input end of the baseband multiplier;
the gate end of the NMOS tube M8 and the gate end of the NMOS tube M11 are connected to form a second input end of the baseband multiplier;
the drain end of the NMOS tube M9 is connected with the drain end of the NMOS tube M11 through a resistor R22 and is connected with the power supply voltage Vbb, the drain end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 through a resistor R21 and is connected with the power supply voltage Vbb, and the drain end of the NMOS tube M7 is connected with the power supply voltage Vbb;
the drain end of the NMOS tube M9 is connected with the drain end of the NMOS tube M11 to form a first output end of the baseband multiplier;
the drain end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 to form a second output end of the baseband multiplier;
the gate end of the NMOS tube M7 is connected with the positive-phase output end Vout3 of the amplifier A2, the drain end of the NMOS tube M12 is connected with the power supply voltage Vbb, and the gate end of the NMOS tube M12 is connected with the negative-phase output end Vout4 of the amplifier A2;
the source end of the NMOS tube M7, the source end of the NMOS tube M8 and the source end of the NMOS tube M9 are connected with the drain end of the NMOS tube M15;
the source end of the NMOS tube M10, the source end of the NMOS tube M11 and the source end of the NMOS tube M12 are connected with the drain end of the NMOS tube M16;
the source terminal of the NMOS tube M15 is grounded, the source terminal of the NMOS tube M16 is grounded, and the gate terminals of the NMOS tube M15 and the NMOS tube M16 are connected with bias voltage Vb 0.
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