CN114649216A - Method for manufacturing a semiconductor device, assembly used and corresponding semiconductor device - Google Patents

Abstract

Methods of manufacturing semiconductor devices, assemblies used, and corresponding semiconductor devices are disclosed. The leadframe includes a pattern of conductive structures, with one or more sacrificial connecting structures bridging between a pair of conductive structures. A sacrificial connection structure or structures are formed at one of the first and second surfaces of the leadframe and have a thickness between the first and second surfaces that is less than the thickness of the leadframe. A filling of electrically insulating material is molded between the electrically conductive structures of the lead frame, wherein the electrically insulating material is molded between the connection structure and the other surface of the lead frame. The sacrificial connection structure counteracts deformation and displacement of the components during formation and pre-molding of the lead frame.

Description

Method for manufacturing a semiconductor device, assembly used and corresponding semiconductor device

Cross reference to related applicationsFork guide

The disclosures in italian application No. 102020000031553, filed on 12/18/2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law, are claimed for priority.

Technical Field

The present description relates to semiconductor devices.

For example, one or more embodiments may be applied to a semiconductor device such as an Integrated Circuit (IC).

Background

Various types of semiconductor devices may benefit from the use of a pre-molded leadframe.

Quad flat no lead (QFN) packages, which have peripheral pads on the bottom of the package to provide electrical connections to a substrate such as a Printed Circuit Board (PCB), are examples of such devices.

A pre-molded leadframe comprising a resin/plastic material surrounding a metal lead and a pad/paddle to which a semiconductor chip or die (die) is attached; a molding compound (e.g., epoxy) is then molded onto the chip or die attached to the pre-molded lead frame.

For example, in the case of QFN packages, a metal (e.g., copper) leadframe is etched at the top and bottom using photolithographic techniques in order to create the desired pattern of one or more pads/pads along with leads connected to the bar (bar).

The lead frame thus etched is completely filled with plastic resin in a pre-molding step. This may involve using standard molding techniques to fill in the voids in the lead frame.

After molding, a matte and dauber process may be applied to obtain clean top and bottom copper surfaces, with the pre-molded resin encapsulating the components of the leadframe in a stable planar structure.

During the (pre) molding process, resin flows through the open spaces to penetrate the leadframe thickness. The structures in the lead frame should be maintained in the desired position to avoid any displacement or deformation during the filling process.

To this end, the components (e.g., pads) of the lead frame may be supported/fixed by tie bars. These tie bars may be located, for example, at the corners of the pads in order to save space and leave available remaining space for the signal leads.

For example, if there are two or more pads/pads in the leadframe, it is almost impossible to reliably "lock" all pads/pads through multiple connections. It was observed that the pads or solder plates with (only) two connections could undesirably move during the molding process.

In the case of complex designs with more pads/solder plates, it is practically impossible to provide sufficient connections to the outer bars. For example, in a circuit layout that includes discrete components, the die pads connected by the posts may not be as electrically isolated as desired, e.g., the drain and collector are often shorted.

Furthermore, the locations for forming the additional tie bars consume valuable area and may cause certain leads in the lead frame to become unusable and thus lost.

In summary, conventional methods of handling undesired displacements or deformations during pre-molding, with the risk of loss of electrical insulation between the frame clamps, present for example: the disadvantages that the pin count may be reduced and the package size may be increased; design constraints in the case of multi-die pads; and an electrically shorted die pad.

There is a need in the art to provide an improved solution that overcomes the drawbacks of the prior art solutions discussed above.

Disclosure of Invention

One or more embodiments may be directed to a method.

One or more embodiments may relate to components for use in such methods. A pre-molded leadframe including half-etched temporary tie bars between pads may be an example of such an assembly.

One or more embodiments may relate to a corresponding semiconductor device that may be produced using such an assembly.

One or more embodiments may involve temporary (sacrificial) connections that are half-etched on the bottom (or back) side of the leadframe. These connections help to hold the leadframe structure together during etching and pre-molding, reducing the risk of deformation and undesired displacement.

In one or more embodiments, the die pads can only be temporarily shorted and physical separation can be achieved during the etching step to remove tie bars.

One or more embodiments effectively reduce distortion and promote greater leadframe stability during premolding, saving space for additional pads.

One or more embodiments do not negatively impact package size and/or the number of available signal leads; multiple pads/solder plates can be accommodated without design limitations.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

fig. 1A and 1B are perspective views of a leadframe according to embodiments of the present description prior to pre-molding;

fig. 2A and 2B are perspective views of a leadframe after pre-molding according to embodiments of the present description;

FIG. 3 is a cross-sectional view taken along line II-II of FIG. 2B, enlarged and reproduced;

FIG. 4 is a cross-sectional view substantially corresponding to FIG. 3 showing the result of the etching step; and

fig. 5A and 5B are perspective views of a semiconductor device to which the embodiment of the present specification can be applied.

It will be appreciated that for clarity and ease of understanding, various numbers may not be drawn to scale.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various examples according to the described embodiments. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to not obscure aspects of the embodiments.

Reference to "an embodiment" or "one embodiment" within the framework of the specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in one embodiment," and the like, that may be present in various points of the specification do not necessarily refer to exactly one and the same embodiment. Furthermore, in one or more embodiments, particular conformations, structures or characteristics may be combined in any suitable manner.

The headings/references used herein are provided for convenience only and thus do not define the scope of protection or the scope of the embodiments.

Moreover, throughout the drawings, like parts or elements are denoted by like reference numerals, and the corresponding description will not be repeated for each drawing for the sake of brevity.

The name lead frame is currently used to refer to the metal frame that provides support for the semiconductor chip or die (see, for example, the united states patent and trademark office's united states nomenclature of USPC), as well as the electrical leads that couple the semiconductor chip or die to other electrical elements or contacts.

Basically, the leadframe includes an array of conductive structures (leads) extending from peripheral locations inward in the direction of the semiconductor chip or die, thereby forming an array of conductive structures from a die pad having at least one semiconductor chip or die attached thereto. This may be by a die attach adhesive (e.g., a die attach film or DAF).

Electrical coupling of the leads in the leadframe to the semiconductor chip or die may be by wires forming a wire bonding pattern around the chip or die.

The leadframe and the semiconductor die (also referred to as semiconductor chip at present) mounted thereon are one of the main components of the plastic package of the semiconductor device. It is made of an electrically conductive material (metal such as copper) and uses different intervening materials: glue, tape, solder paste are configured and shaped to support the die attached thereto.

Various types of semiconductor devices may benefit from the use of a pre-molded leadframe. The pre-molded lead frame includes a resin/plastic material surrounding the metal leads and a die paddle to which a semiconductor chip or die may be attached; a molding compound (e.g., epoxy) is then molded onto the chip or die attached to the pre-molded lead frame.

Fig. 1A and 1B are perspective views of a "bare" lead frame 10 (prior to pre-molding). Fig. 1A shows a view from the top or front side (the side on which the semiconductor die is mounted), and fig. 1B shows a view from the bottom or back side.

As shown in fig. 1A and 1B (by way of example only), a leadframe 10 may include an array of leads 12 and at least one die pad 14, and one (or more) semiconductor chip ICs (shown in dashed outline) may be mounted on the die pad 14.

As shown by way of example herein, the leadframe 10 (used in semiconductor devices such as electronic fuses-e.g., efuses for short) may include other pads or pads 14', 14 "that are configured to be coupled to (power) connections, such as so-called ribbons (ribbons) for semiconductor chip ICs (shown in phantom).

Those skilled in the art will readily appreciate that the description provided herein with respect to die pad 14 also applies to pads or solder plates, such as 14' and/or 14 ".

A conventional technique for producing lead frames (e.g., 10) is photolithography. The original (e.g., copper) sheet in panel or reel form is top/bottom covered with resist developed by masking and etching. The exposed metal is etched away and the resist is finally removed. The lead 12 and the pads/ pads 14, 14' and 14 "can be formed simultaneously using this technique.

A semiconductor die, such as the integrated circuit IC shown in the figure, is attached to a pad such as 14 and gold, silver or copper wire (not visible in the figure for simplicity) is provided during the wire bonding process to connect the die to the wire/pad. And after wire bonding, completing the packaging process by a packaging/solder electroplating step.

In those types of semiconductor devices that use a premolded lead frame, the "bare" lead frame of fig. 1A and 1B is subjected to a premolding process, with the result that the lead frame 10 becomes a premolded lead frame.

Such a pre-molded lead frame can be seen in fig. 2A and 2B, where: fig. 2A shows the pre-molded lead frame 10 viewed from the top or front side, and fig. 2B shows the pre-molded lead frame 10 viewed from the bottom or back side. The pre-molded lead frame 10 is "completely filled" with a resin/plastic material 16 (e.g., epoxy) that penetrates (and cures in) the space around the metal leads 12 and the pads or pads 14, 14', 14 ".

Subsequently, a molding compound is molded onto the (pre-molded) leadframe 10, with the chip or die 14 attached to the leadframe 10. For simplicity, such molding compound (e.g., epoxy, different from or the same as the pre-mold resin 16) is not visible in fig. 2A, but is represented by dashed line 18 in fig. 5A and 5B, as described below.

In general, the pre-molded leadframe technique as discussed previously is conventional in the art, making it unnecessary to provide a more detailed description here.

During the pre-molded lead frame manufacturing process (see fig. 2A and 2B in comparison to fig. 1A and 1B), the etched lead frame is completely filled with resin (e.g., 16) that penetrates into the empty space through the thickness of the bare lead frame, as shown in fig. 1A and 1B.

As previously mentioned, the various structures (leads 12, pads or paddles 14, 14', 14 ", including die pad 14) should desirably maintain their position, avoiding displacement or deformation during leadframe formation and during pre-mold resin filling.

In one or more embodiments, a temporary (sacrificial) connection may be provided, as illustrated at 100 in fig. 1A, 1B, and 2B. As shown, these connections may be provided, for example, between a solder board or pad and another solder board or pad, and between a solder board or pad and a lead. At least in principle, also inter-lead connections can be considered.

In one or more embodiments, the connection 100 may be provided as a half-etch formation of the bottom or back side of the lead frame during the etching process that results in the "bare" lead frame 10 of fig. 1A and 1B.

As can be seen in the cross-sectional view of fig. 3, the connector 100 bridges between two conductive portions (in the case shown in fig. 3, the die pad 14 and the adjacent paddle 14 ") that are half-etched in the leadframe 10, without extending to the entire depth or height of the leadframe 10.

That is, as shown in fig. 3 (where the lead frame is shown from the bottom side up, i.e., viewed from its bottom or back side), a quantity of pre-molded resin 16 remains between the connector 100 (which is essentially a rod) and the top or front side of the lead frame (facing down in fig. 3).

In accordance with the current language of the art, the name "half-etched" is used herein to denote a connector 100 that does not extend to the entire depth or height of the lead frame 10 (as measured between opposing surfaces of the lead frame 10), but this does not mean that the connector 100 must have a thickness/height that is equal to or close to 50% of the thickness/height of the lead frame 10. As shown in fig. 1A and 1B, the half-etching of the leadframe is provided from (i.e., at) the top/front side and the bottom/back side. The resin/plastic material 16 filling the space around the metal leads 12 and the pads or pads 14, 14', 14 "fills the half-etched openings extending from the top/front side and the half-etched openings extending from the bottom/back side, respectively, and after curing will have a front surface coplanar with the top/front side of the leadframe and a back surface coplanar with the bottom/back side of the leadframe. See fig. 2A and 2B.

Depending on the application/process, the thickness/height of the connector 100 may be selected to facilitate subsequent removal of the connector 100 (as schematically shown in dashed lines at SE in fig. 3).

As shown in fig. 4, the removal (e.g., etching) of the connection 100 results in the formation of a recess at the location where the connection 100 is provided.

The removal of the connection 100 may involve, for example, a (further) etching step of the leadframe 10.

Such (selective) etching-as indicated by SE in fig. 3-may also be applied to the leadframe 10 for other purposes that are not of particular interest for the features of the embodiments discussed herein.

As discussed, the connector 100 helps to keep the leadframe structure stronger and more robust during formation of the leadframe 10 (e.g., by etching) and during pre-molding, reducing the risk of undesired deformation and displacement of components.

As can be appreciated by comparing fig. 3 and 4, the removal of the connector 100 re-establishes electrical isolation between adjacent conductive portions of the leadframe (as shown by die pad 14 and paddle 14 "in fig. 3 and 4) that were previously connected (mechanically and electrically) by the connector 100.

Fig. 5A and 5B are perspective views of a semiconductor device 20 (electronic fuse-in short an e-fuse or eFuse), which semiconductor device 20 includes a pre-molded leadframe 10 processed as previously described. Specifically, fig. 5A shows device 20 viewed from the top or front side, and fig. 5B shows device 20 viewed from the bottom or back side.

As shown by way of example herein, the leadframe 10 may include other pads or pads 14', 14 "configured to receive (power) connections, such as a so-called tape or clip (clip) R coupled to a semiconductor chip IC (shown in dashed outline).

Facing upward in fig. 5A, the molding compound 18 is molded onto a (pre-molded) leadframe 10, the leadframe 10 having a chip IC and a top or front surface electrical contact (tape) R disposed thereon. The outline of the molding compound 18 (e.g., an epoxy, different from or the same as the pre-mold resin 16) is shown in dashed lines in fig. 5A and 5B.

Of course, the electronic fuse is referred to as the semiconductor device 20 applicable to the embodiment only as an example, and is not construed in a limiting sense of the embodiment.

The bottom or back side up representation of the leadframe 10 in fig. 5B shows a possible "residue" 100' of the removal of the connector 100 that remains in the final device 20.

The residue 100 'of the two connections between the pads/pads 14 and 14' is illustrated in fig. 5B, and it will be further understood that such residue may be present at any location where the ("half-etched") connection 100 is initially present and subsequently removed.

These residues 100 'may include recesses or grooves in the bottom or back side of leadframe 12 (and device 20) at those locations where connectors 100 were originally provided, which are subsequently removed (e.g., "etched away") to provide electrical insulation between the conductive structures of leadframe 10, such as 14 and 14' in fig. 3 and 4.

Note that in some embodiments, the residue 100' may include recesses or grooves that are then at least partially filled with other materials, such as electroplating.

In any case, the residues 100' are still present and their presence can be detected in the final complete device, as a "proof" of the supply and subsequent removal of the connection 100, i.e. as evidence of the removal of the connection.

As shown in fig. 4, the residue 100 'may include the mutually protruding portions of the conductive structures of the leadframe 10, e.g., 14 and 14', which initially serve as end abutments of the bridge structure of the connector 100.

Accordingly, one or more embodiments effectively reduce undesirable deformation and displacement of the leadframe during leadframe formation (e.g., by etching) and pre-molding, while saving space for additional pads/pads and signal leads, without special restrictions in design, facilitating the fabrication of smaller packages.

In summary, one or more embodiments may relate to a method (e.g., 20) of manufacturing a semiconductor device, wherein the method includes: at least one semiconductor chip (e.g., IC) is arranged onto at least one semiconductor chip mounting region (e.g., chip mounting pad 14) in a first (e.g., top or front) surface of a leadframe (e.g., 10) that includes a pattern of conductive structures (e.g., leads 12 and pads/ pads 14, 14', 14 ") and has a second (e.g., bottom or back) surface opposite the first surface and a leadframe thickness between the first and second surfaces (i.e., measured in a direction perpendicular to the general plane of the leadframe).

A method as exemplified herein may comprise: at least one (sacrificial) connection structure (e.g., 100) is formed (provided) that extends in a bridge between a pair of conductive structures (e.g., see 14, 14' in fig. 3) in a pattern of the conductive structures, wherein the at least one connection structure is formed at one of the first and second surfaces of the leadframe (e.g., between the first and second surfaces) and has a thickness between the first and second surfaces that is less than the thickness of the leadframe. Then, a filler (e.g., 16) of electrically insulating material is molded between the conductive structures in the pattern of conductive structures, wherein the insulating material from the filler is molded (and thus penetrates) between the at least one connection structure and another of the first and second surfaces (e.g., second surfaces) of the leadframe. The at least one (sacrificial) connection structure between the pair of conductive structures in the pattern of conductive structures is then eliminated (see e.g. SE in fig. 3).

A method as exemplified herein can include forming at least one connection structure at a second (e.g., bottom or back) surface of a leadframe.

A method as exemplified herein can include forming or providing (e.g., by etching) at least one connection structure in a leadframe along with the pattern of conductive structures.

The method as exemplified herein may comprise forming (providing) a pattern of the at least one connection structure and the electrically conductive structure by etching a metallic material.

A method as exemplified herein can include forming (providing) at least one connection structure between a first surface and a second surface having a thickness of about half of the leadframe thickness.

As used herein, the term "approximately" means a technical feature that is produced within the technical tolerances of the method used to manufacture it.

A leadframe (e.g., 10), as exemplified herein, facilitates being provided as an assembly for a method, as exemplified herein.

As shown in fig. 1A and 1B, such an assembly may be provided as a "bare" (e.g., metal only) leadframe having a first surface including at least one semiconductor chip mounting region (e.g., 14) and a second surface opposite the first surface, the leadframe having a leadframe thickness between the first and second surfaces. The lead frame includes: a pattern of conductive structures (e.g., 12, 14', 14 "); and at least one connection structure (e.g., 100) extending in a bridge between a pair of conductive structures (e.g., 14') in the pattern of conductive structures, wherein the at least one connection structure is located at one of the first and second surfaces of the leadframe (e.g., at the first and second surfaces) and has a thickness between the first and second surfaces that is less than the leadframe thickness.

Advantageously, the at least one connection structure may be located at a second surface of the leadframe (10).

Advantageously, the at least one connection structure may have a thickness of about half the thickness of the leadframe between the first and second surfaces of the leadframe.

The expression "approximately" here likewise denotes a technical feature which is produced within the technical tolerances of the production method.

As illustrated in fig. 2A and 2B, the assemblies discussed herein may likewise be provided as a "pre-molded" (e.g., metal plus pre-molded resin) leadframe, including a filler (e.g., 16) of electrically insulating material molded between the electrically conductive structures in the pattern of electrically conductive structures, wherein electrically insulating material from the filler is molded between the at least one connection structure and the other of the first and second surfaces (e.g., bottom or back surfaces) of the leadframe (10).

A semiconductor device as exemplified herein (see, e.g., 20 in fig. 5A and 5B) may include: at least one semiconductor chip (e.g., IC) is disposed on at least one semiconductor chip mounting region (e.g., 14) in a first (e.g., top or front) surface of the leadframe, the leadframe including a pattern of conductive structures and having a second surface opposite the first surface and a leadframe thickness between the first and second surfaces. The device further comprises a filling (e.g. 16) of electrically insulating material moulded between the electrically conductive structures in the pattern of said electrically conductive structures. At one (e.g., bottom or back) of the first and second surfaces of the leadframe, there is at least one groove (e.g., 100') that extends in a bridge between a pair of (e.g., see 14, 14' in fig. 4) of the pattern of conductive structures, wherein the at least one groove (resulting from the elimination of a connection such as 100) has a depth between the first and second surfaces that is less than the thickness of the leadframe, and the pair of conductive structures in the pattern of conductive structures are electrically isolated from each other at the groove.

In a semiconductor device as exemplified herein, at least one recess (e.g., 100') can be located at the second surface of the leadframe.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described, by way of example only, without departing from the scope of the embodiments.

The claims are an integral part of the technical disclosure provided herein in connection with the examples.

The scope of protection is determined by the appended claims.

Claims (18)

1. A method, comprising:

processing a sheet to form a leadframe, the sheet comprising a first surface, a second surface opposite the first surface, and a leadframe thickness between the first surface and the second surface, the leadframe comprising a semiconductor chip mounting area, a pattern of conductive structures, and at least one connection structure that extends in a bridge between a pair of the conductive structures in the pattern of conductive structures;

wherein the at least one connection structure is located at one of the first and second surfaces, having a structure thickness less than the leadframe thickness;

molding a filler of electrically insulating material between electrically conductive structures in the pattern of electrically conductive structures, wherein electrically insulating material from the filler is present between the at least one connection structure and the other of the first and second surfaces of the leadframe; and

eliminating the at least one connection structure between the pair of conductive structures in the pattern of conductive structures.

2. The method of claim 1, wherein processing the sheet comprises: performing a first half-etch from the first surface of the sheet and a second half-etch from the second surface of the sheet to form the leadframe, and wherein molding comprises: filling an opening provided by the first half-etch and the second half-etch with the electrically insulating material, and curing the electrically insulating material filling the opening to have a first surface coplanar with the first surface of the treated sheet and a second surface coplanar with the second surface of the treated sheet.

3. The method of claim 1, further comprising: mounting a semiconductor chip to the semiconductor chip mounting region.

4. The method of claim 1, wherein the semiconductor chip mounting region is present at the first surface and the at least one connection structure is present at the second surface.

5. The method of claim 1, wherein the at least one connection structure is formed in the leadframe with a pattern of the conductive structures.

6. The method of claim 1, wherein processing comprises: etching the metallic material of the sheet to form a pattern of the at least one connection structure and the conductive structure.

7. The method of claim 1, wherein the at least one connection structure thickness is about half of the leadframe thickness.

8. A leadframe having a first surface and a second surface opposite the first surface, and a leadframe thickness between the first surface and the second surface, the leadframe comprising:

a semiconductor chip mounting region located at the first surface;

a pattern of conductive structures;

at least one connecting structure extending in a bridge between a pair of conductive structures in the pattern of conductive structures;

wherein the at least one connection structure is located at one of the first and second surfaces of the leadframe and has a structure thickness that is less than the leadframe thickness; and

a filler of electrically insulating material molded between electrically conductive structures in the pattern of electrically conductive structures, electrically insulating material from the filler being molded between the at least one connection structure and the other of the first and second surfaces of the leadframe, and the filler having a first surface coplanar with the first surface of the leadframe and a second surface coplanar with the second surface of the leadframe.

9. The leadframe of claim 8, wherein the at least one connection structure is located at the second surface of the leadframe.

10. The leadframe of claim 8, wherein the at least one connection structure thickness is about half the leadframe thickness.

11. The leadframe of claim 8 wherein the semiconductor chip mounting area, the pattern of conductive structures, and the at least one connection structure are defined by a first half-etched opening extending from the first surface and a second half-etched opening extending from the second surface.

12. A semiconductor device, comprising:

a leadframe having a first surface, a second surface opposite the first surface, and a leadframe thickness between the first surface and the second surface, and comprising: a semiconductor chip mounting region on the first surface; and a pattern of conductive structures;

a filler of a first electrically insulating material molded between the electrically conductive structures in the pattern of electrically conductive structures;

a semiconductor chip mounted to the semiconductor chip mounting region; and

at least one groove at one of the first and second surfaces of the leadframe, the at least one groove bridging between a pair of the conductive structures in the pattern of conductive structures;

wherein the at least one groove has a depth that is less than the leadframe thickness between the first surface and the second surface, and the pair of conductive structures in the pattern of conductive structures are electrically insulated from each other at the groove.

13. The semiconductor device of claim 12, further comprising a fill of a second electrically insulating material molded over the semiconductor chip and onto the first surface of the leadframe and first fill.

14. The semiconductor device of claim 12, further comprising mutually protruding portions of the conductive structures at the recess, the mutually protruding portions forming end abutments of at least one connecting structure that would otherwise bridge between the pair of conductive structures in the pattern of conductive structures.

15. The semiconductor device of claim 14, wherein the mutually protruding portions are located at one of the first and second surfaces of the leadframe and have a partial thickness less than the leadframe thickness.

16. The semiconductor device of claim 12, wherein the at least one groove is located at the second surface of the leadframe.

17. The semiconductor device of claim 12, wherein the first filler has a first surface coplanar with the first surface of the leadframe and has a second surface coplanar with the second surface of the leadframe.

18. The semiconductor device of claim 12, wherein the pattern of the semiconductor chip mounting area and the conductive structure is defined by a first half-etched opening extending from the first surface and a second half-etched opening extending from the second surface, the first half-etched opening and the second half-etched opening being filled with the first filler.

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