CN114646870A - Time sequence calibration method and system - Google Patents
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
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Abstract
The invention discloses a time sequence calibration method and a time sequence calibration system, wherein the time sequence calibration method is used for carrying out time sequence calibration on test signals in a plurality of test channels of a digital test machine, and comprises the following steps: gating any two test channels of the digital test machine to output test signals; comparing the test signals output by the two gated test channels by adopting a window comparator, and outputting a comparison result to the FPGA; the test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer to be used as a sampling clock; the FPGA acquires an output result of the window comparator according to the sampling clock and sends result information to the control terminal; and the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to finish the time sequence calibration of the test channel.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a time sequence calibration method and a time sequence calibration system.
Background
The digital chip tester usually supports a pattern test, and is used for judging whether the chip functions are normal or not by the digital chip through testing the pattern, so as to realize rapid test when the digital chip is produced in large scale.
The digital chip tester generally supports hundreds of test channels, and digital signals output by each test channel need to be output to pins of the digital chip to be tested at the same time, that is, the digital signals need to be edge-aligned, so as to ensure that the time sequence between signals output to the pins of the digital chip to be tested is correct. To ensure that the edges of the digital signals output by all the test channels of all the digital chip testers are aligned, the digital chip testers need to calibrate the time sequence of the digital signals.
The existing method generally judges whether the test edges of the test channels are aligned one by one through a high-speed oscilloscope, and the method needs an additional high-speed oscilloscope, so that the cost is high and the use is inconvenient; or the signals after the clocks are output through the two channels are subjected to phase comparison, and then whether the edges are aligned is measured and calculated in a voltage acquisition mode after the phase comparison signals are charged through a capacitor.
Disclosure of Invention
It is an object of the present invention to provide a timing calibration method and system to solve at least one of the problems of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a first aspect of the present invention provides a timing calibration method for performing timing calibration on test signals in a plurality of test channels of a digital test machine, the method including:
gating any two test channels of the digital test machine to output test signals;
comparing the test signals output by the two gated test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer to be used as a sampling clock;
the FPGA acquires an output result of the window comparator according to the sampling clock and sends result information to the control terminal;
and the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to finish the time sequence calibration of the test channel.
Optionally, the method further comprises: and taking the test channel where the sampling clock is positioned as a calibration reference channel, and sequentially gating one of the other multiple test channels to be communicated with the window comparator to be used as a calibrated channel for timing calibration.
Optionally, the multiple excitation signal test channels of the digital test machine are connected to an input end of a relay network, a first output end of the relay network is connected to a first input end of the window comparator, a second output end of the relay network is connected to a second input end of the window comparator and an input end of the clock buffer, an output end of the window comparator is connected to a first input end of the FPGA, an output end of the clock buffer is connected to a second input end of the FPGA, and an output end of the FPGA is connected to the control terminal.
Optionally, the control terminal controls a relay in the relay network to be opened or closed, so that the two gated excitation signal test channels are respectively output to the first output end and the second output end of the relay network.
Optionally, if the clock signal edge generated by the calibrated channel is not aligned with the clock signal edge generated by the reference channel, the control system controls the excitation signal test channel of the digital testing machine to adjust the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the clock signal edge generated by the reference channel.
Optionally, the clock phase of the calibrated channel output is adjusted using a binary search method.
Optionally, if the phase of the calibrated channel is detected to be advanced with respect to the phase of the reference channel, the calibrated channel is output with a delay of N nS, if the phase of the calibrated channel is detected to be delayed with respect to the phase of the reference channel, the calibrated channel is output with a delay of N/2nS, if the phase of the calibrated channel is detected to be delayed with respect to the phase of the reference channel, the phase of the calibrated channel is advanced with respect to the phase of the reference channel within a range of 0 to N/2nS, and if the phase of the calibrated channel is detected to be advanced with respect to the phase of the reference channel, the phase of the calibrated channel is advanced with respect to the phase of the reference channel within a range of N/2 to N nS, where N > 0.
A second aspect of the present invention provides a timing calibration system for performing the above timing calibration method, the system comprising: the system comprises a digital test machine, a control terminal and a time sequence calibration board card;
the timing calibration board card comprises: the system comprises a relay network, a window comparator, a clock buffer and an FPGA;
the digital testing machine comprises a plurality of excitation signal testing channels;
the relay network is used for gating any two excitation signal test channels of the plurality of excitation signal test channels of the digital test machine and respectively outputting the two excitation signal test channels to the window comparator;
the window comparator is used for comparing the clock signals output by the two gated excitation signal test channels, judging whether the edges of the two clock signals are aligned or not, and outputting a judgment result to the FPGA;
the clock buffer is used for buffering a clock signal output by one of the gated excitation signal test channels and outputting the clock signal to the FPGA as a sampling clock;
the FPGA is used for acquiring a comparison result of the window comparator according to the sampling clock and sending the result to the control terminal;
the control terminal is used for controlling the excitation signal testing channels to generate clock signals, judging whether the edges of the clock signals generated by the two excitation signal testing channels are aligned or not, and carrying out time sequence calibration.
Optionally, the relay network and the window comparator support an operating frequency of 100-800 MHz.
Optionally, the control terminal controls one of the relay network gating test channels to communicate with the input end of the clock buffer and the second input end of the high-speed window comparator to be used as a calibration reference channel, and sequentially gates one of the other excitation signal test channels to communicate with the first input end of the window comparator to be used as a calibrated channel to perform timing calibration.
The invention has the following beneficial effects:
the technical scheme of the invention provides a time sequence calibration method and a time sequence calibration system, and the system can realize time sequence calibration without external oscilloscopes and other instruments and is convenient to use. The time sequence calibration method can quickly realize the time sequence calibration of the test channels of the digital test machine by utilizing the high-speed relay network and the high-speed window comparator in the time sequence calibration board, improves the time sequence calibration efficiency, and meets the calibration precision requirement because the calibration precision of all the test channels can reach within 50 ps.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating a timing calibration system according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a timing calibration method according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a timing calibration system, which includes a digital test machine 1, a control terminal 2, and a timing calibration board 3.
The digital testing machine 1 comprises a plurality of testing channels, each testing channel correspondingly transmits a testing vector (Pattern), and the testing vectors are used as testing signals and sent to pins of a product to be tested by the digital testing machine. A typical digital testing machine 1 includes 512, 768, 1024 test channels. That is, 512 test vectors are transmitted correspondingly in 512 test channels.
The control terminal 2 may be a computer or a cloud server, and is mainly used for controlling the timing calibration process.
The timing calibration board 3 includes: a high-speed relay network 31, a high-speed window comparator 32, a clock buffer 33, and an FPGA 34.
The high-speed relay network 31 is configured to gate any two test channels of the digital test machine, so that two test vectors in the two gated test channels are output to the high-speed window comparator 32, respectively. In one specific example, the high speed relay network 31 and the high speed window comparator 32 support a maximum of 800MHz operating frequency.
The high-speed window comparator 32 is configured to compare the test vector signals output by the two gated test channels, determine whether edges of the two test vector signals are aligned, and output a determination result to the FPGA 34;
the clock buffer 33 is used for buffering a test vector signal generated by one of the test channels and outputting the buffered test vector signal to the FPGA34 as a sampling clock;
the FPGA34 is configured to collect a comparison result of the high-speed window comparator 32 according to the sampling clock, and send the result to the control terminal 2.
The control terminal 2 is used for controlling the excitation signal test channels to generate clock signals, judging whether the edges of the clock signals generated by the two excitation signal test channels are aligned, and performing timing calibration.
In one possible implementation manner, the relay network and the window comparator support 100-800 MHz working frequency.
In a possible implementation manner, the control terminal controls one of the relay network gating test channels to be communicated with the input end of the clock buffer and the second input end of the window comparator to serve as a calibration reference channel, and sequentially gates one of the other multiple excitation signal test channels to be communicated with the first input end of the high-speed window comparator to serve as a calibrated channel for timing calibration.
As shown in fig. 2, another embodiment of the present invention provides a timing calibration method for performing timing calibration on test signals in a plurality of test channels of a digital test machine, the method comprising:
gating any two test channels of the digital test machine to output test signals;
comparing the test signals output by the two gated test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer to be used as a sampling clock;
the FPGA acquires an output result of the window comparator according to the sampling clock and sends result information to the control terminal;
and the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA so as to finish the time sequence calibration of the test channel. In a possible implementation manner, the multiple excitation signal test channels of the digital test machine 1 are connected to the input end of the high-speed relay network 31, the first output end of the high-speed relay network 31 is connected to the first input end of the high-speed window comparator 32, the second output end of the high-speed relay network 31 is connected to the second input end of the high-speed window comparator 32 and the input end of the clock buffer bufe 33, the output end of the high-speed window comparator 32 is connected to the first input end of the FPGA34, the output end of the clock buffer 33 is connected to the second input end of the FPGA34, and the output end of the FPGA34 is connected to the control terminal 2.
In a possible implementation manner, the control terminal 2 controls the relays in the high-speed relay network 31 to open or close, so that the two gated excitation signal test channels are respectively output to the first output terminal and the second output terminal of the high-speed relay network 31.
In a specific example, at least 512 test channels included in the digital test machine 1 are all connected to the input end of the high-speed relay network 31, 512 test channels correspondingly transmit 512 test vectors (Pattern), the high-speed relay network 31 arbitrarily selects two test channels from the at least 512 test channels included in the digital test machine 1 to output, two output ends of the high-speed relay network 31 are both connected to the input end of the high-speed window comparator 32, meanwhile, the output end of one of the high-speed relay networks 31 is connected to the input end of the clock buffer 33, the output end of the high-speed window comparator 32 is connected to the FPGA, the output end of the clock buffer 33 is connected to the FPGA, the FPGA samples the comparison result of the high-speed window comparator 32 by using the sampling clock output by the clock buffer 33, and then transmits the sampling result to the control terminal 2, for example, the control terminal 2 is a computer, the computer determines whether the two test channels tested this time are aligned, and performing timing calibration.
In a possible implementation manner, the control terminal 2 controls the high-speed relay network 31 to gate one of the test channels to communicate with the input terminal of the clock buffer 33 and the second input terminal of the high-speed window comparator 32 to serve as a calibration reference channel, which is called channel 2, and sequentially gates one of the other multiple excitation signal test channels to communicate with the first input terminal of the high-speed window comparator to serve as a calibrated channel, which is called channel 1, for timing calibration.
In a specific example, the control terminal 2 gates other excitation signal test channels that are not gated by the high-speed window comparator 32 in sequence, and performs timing calibration on the calibrated channel 1 according to the reference channel 2.
In one particular example, two stimulus signal test channels gated in a computer controlled digital tester generate a clock signal, for example a 100MHz clock signal.
In one possible implementation, the method further comprises: and taking the test channel where the sampling clock is positioned as a calibration reference channel, and sequentially gating one of the other multiple test channels to be communicated with the window comparator to be used as a calibrated channel to carry out time sequence calibration.
In a possible implementation manner, if the clock signal edge generated by the calibrated channel is not aligned with the clock signal edge generated by the reference channel, the control system controls the excitation signal test channel of the digital testing machine to adjust the clock phase output by the calibrated channel until the clock phase of the calibrated channel is aligned with the clock signal edge generated by the reference channel.
In one specific example, when the output result of the high-speed window comparator is random 0 and 1, the edge of the clock signal generated by the calibrated channel and the reference channel is aligned; when the output result of the high-speed window comparator is a fixed 0 or 1, the edges of the clock signals generated by the calibrated channel and the reference channel are not aligned, so that whether the edges of the clock signals generated by the calibrated channel and the reference channel are aligned or not can be judged, and the timing calibration is realized.
When the clock signal edges generated by the calibrated channel and the reference channel are not aligned, the control system 2 controls the digital test machine 1 to adjust the clock phase output by the calibrated channel until the clock signal edges generated by the calibrated channel and the reference channel are aligned, wherein the clock phase output by the calibrated channel is adjusted by using a binary search method so that the clock signal edges generated by the calibrated channel and the reference channel are aligned.
In one possible implementation, if the phase of the calibrated channel is detected to be advanced with respect to the phase of the reference channel, the calibrated channel output is delayed by N nS, if the phase of the calibrated channel is detected to be delayed with respect to the phase of the reference channel, the calibrated channel output is delayed by N/2nS, if the phase of the calibrated channel is detected to be delayed with respect to the phase of the reference channel, the phase of the calibrated channel is advanced with respect to the phase of the reference channel by 0 to N/2nS, and if the phase of the calibrated channel is detected to be advanced with respect to the phase of the reference channel, the phase of the calibrated channel is advanced with respect to the phase of the reference channel by N/2 to N nS, where N > 0.
In one specific example, channel 1 is a calibrated channel, i.e., a channel in which one of the other multiple stimulus signal test channels communicates with the first input terminal of the high-speed window comparator; the channel 2 is a reference channel, namely a channel through which one of two gated excitation signal test channels is communicated with the input end of the clock buffer and the second input end of the high-speed window comparator by the high-speed relay network, when neither the channel 1 nor the channel 2 has output delay, the phase of the channel 1 is measured to be ahead of that of the channel 2, the output delay of the channel 1 is increased by 5nS, then the phase lag of the channel 1 is measured to be behind that of the channel 2, the output delay of the channel 1 is modified to be 2.5nS, then if the phase lag of the channel 1 is measured to be behind that of the channel 2, the phase of the channel 1 is advanced to be within the range of 0-2.5 nS than that of the channel 2, if the phase lag of the channel 1 is measured to be ahead of that of the channel 2, the phase of the channel 1 is advanced to be within the range of 2.5-5 nS, and then the actual phase difference is found out by sequentially carrying out halving judgment and finding according to the range.
The test system provided by the invention does not need to be connected with a digital chip to be tested in calibration, and the digital test machine is connected with the digital chip to be tested after the calibration is finished.
In one specific example, the calibration accuracy of the reference channel and all calibrated channels of the test system of the present invention is 50ps, which is primarily related to the parameters of the high speed window comparator.
It should be noted that the principle and the working flow of the timing calibration system provided in this embodiment are similar to those of the timing calibration method, and reference may be made to the above description for relevant points, which are not described herein again.
The time sequence calibration system and method provided by the embodiment of the invention do not need external oscilloscopes and other instruments, utilize the high-speed window comparator, can quickly realize the time sequence calibration of the pattern test channel of the digital test machine, improve the time sequence calibration efficiency, and meet the calibration precision requirement, wherein the calibration precision can reach within 50 ps.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (10)
1. A method of timing calibration for timing calibration of test signals in a plurality of test channels of a digital test machine, the method comprising:
gating any two test channels of the digital test machine to output test signals;
comparing the test signals output by the two gated test channels by adopting a window comparator, and outputting a comparison result to the FPGA;
the test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer to be used as a sampling clock;
the FPGA acquires an output result of the window comparator according to the sampling clock and sends result information to the control terminal;
and the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output result of the FPGA so as to finish the time sequence calibration of the test channel.
2. The timing calibration method of claim 1, further comprising: and taking the test channel where the sampling clock is positioned as a calibration reference channel, and sequentially gating one of the other multiple test channels to be communicated with the window comparator to be used as a calibrated channel for timing calibration.
3. The timing calibration method according to claim 1, wherein a plurality of excitation signal test channels of the digital tester are connected to an input terminal of a relay network, a first output terminal of the relay network is connected to a first input terminal of the window comparator, a second output terminal of the relay network is connected to a second input terminal of the window comparator and an input terminal of the clock buffer, an output terminal of the window comparator is connected to a first input terminal of the FPGA, an output terminal of the clock buffer is connected to a second input terminal of the FPGA, and an output terminal of the FPGA is connected to the control terminal.
4. The timing calibration method according to claim 3, wherein the control terminal controls the relays in the relay network to open or close, so that the two enabled excitation signal test channels are respectively output to the first output terminal and the second output terminal of the relay network.
5. The timing calibration method of claim 2, wherein if the edges of the clock signals generated by the calibrated channel are not aligned with the edges of the clock signals generated by the reference channel, the control system controls the digital tester excitation signal test channel to adjust the clock phase of the output of the calibrated channel until the clock phase of the calibrated channel is aligned with the edges of the clock signals generated by the reference channel.
6. The timing calibration method of claim 5, wherein the clock phase of the calibrated channel output is adjusted using a binary search method.
7. The timing calibration method of claim 6, wherein the calibrated channel output is delayed by N nS if the calibrated channel is phase-advanced with respect to the reference channel, wherein the calibrated channel output is adjusted to N/2nS if the calibrated channel is phase-delayed with respect to the reference channel, wherein the calibrated channel is phase-advanced with respect to the reference channel by 0-N/2 nS if the calibrated channel is phase-delayed with respect to the reference channel, and wherein the calibrated channel is phase-advanced with respect to the reference channel by N/2-N nS if the calibrated channel is phase-advanced with respect to the reference channel, wherein N > 0.
8. A timing calibration system for performing the timing calibration method of any one of claims 1-7, the system comprising: the system comprises a digital test machine, a control terminal and a time sequence calibration board card;
the timing calibration board card comprises: the system comprises a relay network, a window comparator, a clock buffer and an FPGA;
the digital testing machine comprises a plurality of excitation signal testing channels;
the relay network is used for gating any two excitation signal test channels of the plurality of excitation signal test channels of the digital test machine and respectively outputting the two excitation signal test channels to the window comparator;
the window comparator is used for comparing the clock signals output by the two gated excitation signal test channels, judging whether the edges of the two clock signals are aligned or not, and outputting a judgment result to the FPGA;
the clock buffer is used for buffering a clock signal output by one of the gated excitation signal test channels and outputting the clock signal to the FPGA as a sampling clock;
the FPGA is used for acquiring a comparison result of the window comparator according to the sampling clock and sending the result to the control terminal;
the control terminal is used for controlling the excitation signal testing channels to generate clock signals, judging whether the edges of the clock signals generated by the two excitation signal testing channels are aligned or not, and carrying out time sequence calibration.
9. The timing calibration system of claim 8, wherein the relay network and the window comparator support 100-800 MHz operating frequency.
10. The timing calibration system of claim 8, wherein the control terminal controls the relay network to gate one of the test channels to communicate with the clock buffer input and the second input of the window comparator to serve as a calibration reference channel, and to sequentially gate one of the other multiple excitation signal test channels to communicate with the first input of the window comparator to serve as a calibrated channel for timing calibration.
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| CN202210115782.8A CN114646870B (en) | 2022-02-07 | 2022-02-07 | Time sequence calibration method and system |
| PCT/CN2022/127520 WO2023147732A1 (en) | 2022-02-07 | 2022-10-26 | Timing calibration method and system |
| TW111141229A TWI826083B (en) | 2022-02-07 | 2022-10-28 | Timing calibration method and system |
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| CN202210115782.8A CN114646870B (en) | 2022-02-07 | 2022-02-07 | Time sequence calibration method and system |
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| WO2023147732A1 (en) * | 2022-02-07 | 2023-08-10 | 苏州华兴源创科技股份有限公司 | Timing calibration method and system |
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|---|---|
| TW202332927A (en) | 2023-08-16 |
| CN114646870B (en) | 2024-03-12 |
| WO2023147732A1 (en) | 2023-08-10 |
| TWI826083B (en) | 2023-12-11 |
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