CN114639741A - Packaging structure and packaging method of image sensing chip - Google Patents

Abstract

The invention discloses a packaging structure and method for an image sensor chip. The method includes: providing a wafer, the wafer includes a plurality of chips to be packaged distributed in an array, and each of the chips to be packaged has opposite a first surface and a second surface, the first surface has a sensing area and a welding pad, the welding pad is electrically coupled with the sensing area; a transparent cover plate is provided, the transparent cover plate has an opposite third surface and a fourth surface; a filter coating is formed on the third surface of the transparent cover plate; the fourth surface of the transparent cover plate is relatively combined with the first surface of the chip to be packaged, and the transparent cover plate covers all the chips to be packaged ; Cutting the wafer, the transparent cover plate and the filter coating to form a plurality of independent packaging structures. The invention adopts the wafer-level packaging method, which has low technical difficulty and low cost, and does not use blue glass, so the problem of warpage caused by inconsistent thermal expansion coefficients will not occur.

Description

Image sensor chip packaging structure and packaging method

technical field

The present invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and packaging method of an image sensor chip.

Background technique

With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which has brought great convenience to people's daily life and work, and has become an indispensable and important part of the current people. tool.

As a chip that converts optical image signals into electronic signals, an image sensor chip has a sensing area. In the prior art, blue glass is usually used as a filter unit to package a single chip. This method has technical difficulties in packaging. high cost, and the use of blue glass has the problem of high CTE (coefficient of thermal expansion).

The information disclosed in this Background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an image sensor chip packaging structure and packaging method, which can overcome the problems of high packaging technology difficulty and high cost in the prior art.

To achieve the above purpose, embodiments of the present invention provide a packaging method for an image sensor chip, including:

A wafer is provided, the wafer includes a plurality of chips to be packaged distributed in an array, each of the chips to be packaged respectively has a first surface and a second surface opposite to each other, the first surface has a sensing area and a bonding pad, the bonding pad is electrically coupled to the sensing region;

providing a transparent cover having opposing third and fourth surfaces;

forming a filter coating on the third surface of the transparent cover;

combining the fourth surface of the transparent cover plate with the first surface of the chip to be packaged, the transparent cover plate covering all the chips to be packaged;

The wafer, the transparent cover and the filter coating are cut to form a plurality of independent packaging structures.

In one or more embodiments of the present invention, the filter coating adopts polytetrafluoroethylene or trimethylbenzene.

In one or more embodiments of the present invention, after the filter coating is formed on the third surface of the transparent cover plate, the method further includes:

An encapsulation protective layer is formed on the surface of the filter coating.

In one or more embodiments of the present invention, the encapsulation protective layer is an oxide or nitride, preferably a silicon dioxide protective layer.

In one or more embodiments of the present invention, in the encapsulation structure, the encapsulation protection layer is retained.

In one or more embodiments of the present invention, the thickness of the filter coating is 3 μm˜5 μm.

In one or more embodiments of the present invention, the method for relatively combining the fourth surface of the transparent cover plate with the first surface of the chip to be packaged includes:

A support structure is formed on the fourth surface of the transparent cover plate or the first surface of the chip to be packaged, and the support structure is supported between the first surface of the chip to be packaged and the fourth surface of the transparent cover plate, so that the chip to be packaged The sensing area is located in the groove enclosed by the support structure and the transparent cover.

In one or more embodiments of the present invention, the method of forming a support structure on the fourth surface of the transparent cover plate includes:

forming a layer of epoxy resin material or silicon material on the fourth surface of the transparent cover plate;

The epoxy resin material is exposed and developed to form the support structure.

In one or more embodiments of the present invention, before cutting the wafer, the transparent cover plate and the filter coating, the method further includes:

A via hole is formed on the second surface of each chip to be packaged through the wafer, and the via hole is used to expose the bonding pad;

forming an insulating layer on the second surface of the chip to be packaged and the sidewall of the via hole;

A redistribution circuit layer is formed on the surface of the insulating layer, and the redistribution circuit layer is electrically connected to the pad;

A solder resist layer with openings is formed on the surface of the redistribution circuit layer and the surface of the insulating layer, and the openings expose a part of the redistribution circuit layer;

Soldering bumps electrically connected to the redistribution circuit layer are formed in the openings.

In order to achieve the above object, the embodiments of the present invention provide a package structure of an image sensor chip, which is fabricated by any of the methods described above.

Compared with the prior art, the present invention adopts the wafer-level packaging method to make a transparent cover plate on one side of the sensing area of the chip, and at the same time, a layer of filter coating is made on the optical surface of the transparent cover plate, and then the wafer and the The transparent cover plate is used to form a plurality of independent packaging structures. The packaging method has low technical difficulty and low cost, and does not use blue glass, so the problem of warpage caused by inconsistent thermal expansion coefficients will not occur.

Description of drawings

FIGS. 1 a to 1 j are schematic diagrams of intermediate structures fabricated by a package structure according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprising" or its conjugations such as "comprising" or "comprising" and the like will be understood to include the stated elements or components, and Other elements or other components are not excluded.

The development trend of electronic devices is miniaturization and portability. A major factor determining the miniaturization and portability of electronic devices is the packaging design of chips in electronic devices. The traditional chip packaging method is usually to use wire bonding (WireBonding) for packaging, but with the rapid development of integrated circuits, the longer leads make the product size unable to meet the ideal requirements. Therefore, Wafer Level Packaging (WLP: Wafer Level Packaging) Package) has gradually replaced wire bonding packaging as a more commonly used packaging method. Wafer-level packaging technology is a technology in which the entire wafer is packaged and tested and then cut into a single chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level packaging has the following advantages: it can process multiple wafers at the same time, and the packaging efficiency is high; the whole wafer is tested before cutting, which reduces the testing process in packaging and reduces the testing cost; packaged chips have light, Small, short, thin advantages.

As a chip that converts optical image signals into electronic signals, the image sensor chip has a sensing area. When using the existing wafer-level chip packaging technology to package the image sensor chip, in order to protect the sensing area of the image sensor It is usually necessary to form an encapsulation cover at the position of the photosensitive area to protect the photosensitive area from damage and contamination. Considering the normal transmission of light, the package cover is usually a transparent substrate. The transparent substrate can be used as a support in the process of forming the image sensor chip package, so that the process can be carried out smoothly. After the wafer-level chip packaging is completed, the transparent substrate will continue to remain, and the sensing area will continue to be protected from damage and contamination during subsequent use of the image sensor chip.

As shown in FIGS. 1 a to 1 j , a method for packaging an image sensor chip according to a preferred embodiment of the present invention includes the following steps.

Step S01 , as shown in FIG. 1 a , a wafer 100 is provided, the wafer 100 includes a plurality of chips 10 to be packaged distributed in an array and a scribe line area 20 between adjacent chips 10 to be packaged. After the wafer 100 is subsequently diced along the dicing line area 20 , a plurality of independent die can be formed, and each die corresponds to a package structure of an image sensor chip.

Fig. 1b is a cross-sectional view of AA' in Fig. 1a, and Fig. 1b exemplarily provides two chips 10 to be packaged. Each of the chips 10 to be packaged has a first surface 11 and a second surface 12 opposite to each other, the first surface 11 has a sensing area 111 and a bonding pad 112 , and the bonding pad 112 is electrically coupled to the sensing area 111 . .

Step S02 , as shown in FIG. 1 c , a transparent cover plate 30 is provided, and the transparent cover plate 30 has an opposite third surface 31 and a fourth surface 32 .

The transparent cover plate 30 is mainly used to protect the sensing area 111 and allow external light to enter the sensing area 111 , and is also used as a support for the filter coating. The size and shape of the transparent cover plate 30 correspond to those of the wafer, and by providing one transparent cover plate 30 , all the sensing regions 111 in the chips 10 to be packaged can be covered.

In one embodiment, the transparent cover plate 30 is light-transmitting glass, which may be organic glass or inorganic glass.

Step S03 , as shown in FIG. 1 c , a filter coating 40 is formed on the third surface 31 of the transparent cover plate 30 .

Since any object above absolute zero (-237°C) emits infrared light (infrared light), that is to say, the sensing area 111 can sense visible light and infrared light at the same time. According to the law of refraction and distance from light, it can be obtained: wavelength The longer, the smaller the refractive index; the shorter the wavelength, the greater the refractive index. Therefore, when the visible light and the infrared light enter the sensing area 111 at the same time, the visible light and the infrared light will be imaged on different target surfaces, the visible light image is a color image, and the infrared light image is a black and white image. , the infrared light will form a virtual image on the target surface, thereby affecting the color and quality of the image. Therefore, a filter coating 40 needs to be formed on the surface of the transparent cover 30 to filter out the infrared light in the light to solve the problem of image color distortion.

In one embodiment, the filter coating is an IR coating (Infrared Radiation) or an AR coating (Anti-Refletance), and the filter coating can filter out infrared light. effect.

In another embodiment, the filter coating is made of organic compounds, such as PTFE (polytetrafluoroethylene) or trimethylbenzene.

The filter coating 40 is formed by spraying or spin coating, and the size of the filter coating 40 is consistent with the size of the transparent cover plate 30 .

In a preferred embodiment, the thickness of the filter coating is 3 μm˜5 μm.

Step S04 , as shown in FIG. 1 f , the fourth surface 32 of the transparent cover plate 30 and the first surface 11 of the chip 10 to be packaged are relatively combined, and the transparent cover plate 30 covers all the chips 10 to be packaged.

Step S05, cutting the wafer 100, the transparent cover plate 30 and the filter coating 40 layers to form a plurality of independent packaging structures.

1d, in the above step S03, after the filter coating 40 is formed on the third surface 31 of the transparent cover plate 30, the method further includes: further forming an encapsulation protection layer 50 on the surface of the filter coating 40 .

The encapsulation protective layer 50 can be made of oxide or nitride, preferably a silicon dioxide protective layer, to protect the optical surface of the clear cover plate 30 during the encapsulation process. The strength also needs to be considered, and the thickness is preferably 0.5 μm to 1 μm, for example, it can be 0.6 μm, 0.7 μm, 0.8 μm or 0.9 μm. After the encapsulation and dicing are completed, the encapsulation protection layer 50 may remain in the encapsulation structure without being removed.

In one embodiment, the encapsulation protection layer 50 is formed by sputtering.

Referring to FIG. 1e , in the above-mentioned step S04 , the method for relatively combining the fourth surface 32 of the transparent cover plate 30 with the first surface 11 of the chip 10 to be packaged includes: forming on the fourth surface 32 of the transparent cover plate 30 The support structure 60 is supported between the first surface 11 of the chip to be packaged 10 and the fourth surface 32 of the transparent cover 30 so that the sensing area 111 of the chip to be packaged 10 is located between the support structure 60 and the transparent cover 30 Inside the groove 61 enclosed by the cover plate 30 .

In one embodiment, the method for forming the support structure 60 on the fourth surface 32 of the transparent cover plate 30 includes: firstly forming a layer of epoxy resin material on the fourth surface 32 of the transparent cover plate 30; The material is exposed and developed to form the support structure 60 .

In one embodiment, the support structure 60 may also be formed on the first surface 11 of the chip 10 to be packaged first, and then combined with the transparent cover plate 30 .

In the step S04, as shown in FIG. 1g, after completing the relative bonding between the fourth surface 32 of the transparent cover 30 and the first surface 11 of the chip 10 to be packaged, the method further includes: starting from the second surface of the chip 10 to be packaged. 12 The chip 10 to be packaged is thinned, so as to reduce the thickness of the package structure and facilitate the etching of the subsequent via holes, and the thinning method may adopt processes such as mechanical grinding and chemical grinding.

In the step S05, before cutting the wafer 100, the transparent cover plate 30 and the filter coating 40 layer, the following steps are further included.

Step S051 , as shown in FIG. 1 h , a via hole 13 penetrating the wafer is formed on the second surface 12 of each of the chips 10 to be packaged, and the via hole 13 is used to expose the bonding pad 112 .

The shape of the via hole 13 can be an inverted trapezoidal hole with a diameter gradually increasing from the second surface 12 to the first surface 11 of the chip 10 to be packaged, or a straight hole with the same diameter from the second surface 12 to the first surface 11 , as shown in Figure 1h.

The cross-sectional shape of the via hole 13 may be circular, square or triangular, which is not limited in this case.

Step S052 , as shown in FIG. 1 i , an insulating layer 70 is formed on the second surface 12 of the chip 10 to be packaged and the sidewalls of the via hole 13 .

The insulating layer 70 is used to achieve electrical insulation, and its material can be silicon oxide, silicon nitride, silicon oxynitride or insulating resin.

Step S053 , as shown in FIG. 1 j , a redistribution circuit layer 80 is formed on the surface of the insulating layer 70 , and the redistribution circuit layer 80 is electrically connected to the bonding pad 112 .

The redistribution line layer 80 is a metal layer, which may be formed by depositing a metal thin film and then etching.

Step S054 , a solder resist layer 90 having openings is formed on the surface of the redistribution circuit layer 80 and the surface of the insulating layer 70 , and the openings expose a part of the redistribution circuit layer 80 .

The solder resist layer 90 also fills the via holes 13 , and the material of the solder resist layer 90 may be an insulating dielectric material such as silicon oxide, silicon nitride, etc., for protecting the redistribution circuit layer 80 .

Step S055 , forming solder bumps 110 electrically connected to the redistribution circuit layer 80 in the opening.

The solder bumps 110 may be connection structures such as solder balls and metal posts, and the material may be metal materials such as copper, aluminum, gold, tin, or lead.

In step S03 and step S04 , the fourth surface 32 of the transparent cover plate 30 and the first surface 11 of the chip 10 to be packaged may be relatively combined first, and then a filter coating is formed on the third surface 31 of the transparent cover plate 30 Layer 40.

This embodiment also discloses a package structure of an image sensor chip, which is fabricated by the above method. In this packaging structure, a layer of PTFE or trimethylbenzene filter material is formed on the surface of the transparent cover plate 30, and then the wafer and the transparent cover plate are simultaneously cut to form multiple independent packaging structures. The packaging method has low technical difficulty. , The cost is low, and blue glass is not used, and the problem of warpage caused by inconsistent thermal expansion coefficients will not occur.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many changes and modifications are possible in light of the above teachings. The exemplary embodiments were chosen and described for the purpose of explaining certain principles of the invention and their practical applications, to thereby enable others skilled in the art to make and utilize various exemplary embodiments and various different aspects of the invention. Choose and change. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims (10)

1. A packaging method for an image sensor chip, comprising: A wafer is provided, the wafer includes a plurality of chips to be packaged distributed in an array, each of the chips to be packaged respectively has a first surface and a second surface opposite to each other, the first surface has a sensing area and a bonding pad, the bonding pad is electrically coupled to the sensing region; providing a transparent cover having opposing third and fourth surfaces; forming a filter coating on the third surface of the transparent cover; combining the fourth surface of the transparent cover plate with the first surface of the chip to be packaged, the transparent cover plate covering all the chips to be packaged; The wafer, the transparent cover and the filter coating are cut to form a plurality of independent packaging structures. 2 . The packaging method of an image sensor chip according to claim 1 , wherein the filter coating is made of polytetrafluoroethylene or trimethylbenzene. 3 . 3. The method for packaging an image sensor chip according to claim 2, wherein after forming the filter coating on the third surface of the transparent cover plate, the method further comprises: An encapsulation protective layer is formed on the surface of the filter coating. 4 . The method for packaging an image sensor chip according to claim 3 , wherein the packaging protective layer is an oxide or a nitride, preferably a silicon dioxide protective layer. 5 . 5 . The packaging method of the image sensor chip according to claim 4 , wherein, in the packaging structure, the packaging protection layer is retained. 6 . 6 . The method for packaging an image sensor chip according to claim 2 , wherein the filter coating has a thickness of 3 μm˜5 μm. 7 . 7 . The packaging method of an image sensor chip according to claim 1 , wherein the method for relatively combining the fourth surface of the transparent cover plate with the first surface of the chip to be packaged comprises: 8 . A support structure is formed on the fourth surface of the transparent cover plate or the first surface of the chip to be packaged, and the support structure is supported between the first surface of the chip to be packaged and the fourth surface of the transparent cover plate, so that the chip to be packaged The sensing area is located in the groove enclosed by the support structure and the transparent cover. 8. The method for packaging an image sensor chip according to claim 7, wherein the method for forming a support structure on the fourth surface of the transparent cover plate comprises: A layer of epoxy resin material or silicon material is formed on the fourth surface of the transparent cover plate; The epoxy resin material is exposed and developed to form the support structure. 9. The method for packaging an image sensor chip according to claim 1, wherein before cutting the wafer, the transparent cover plate and the filter coating, the method further comprises: A via hole is formed through the wafer on the second surface of each of the chips to be packaged, and the via hole is used to expose the bonding pad; forming an insulating layer on the second surface of the chip to be packaged and the sidewall of the via hole; A redistribution circuit layer is formed on the surface of the insulating layer, and the redistribution circuit layer is electrically connected to the pad; A solder resist layer with openings is formed on the surface of the redistribution circuit layer and the surface of the insulating layer, and the openings expose a part of the redistribution circuit layer; Soldering bumps electrically connected to the redistribution circuit layer are formed in the openings. 10. A package structure of an image sensor chip, manufactured by the method according to any one of claims 1 to 9.

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