CN114639741A - Packaging structure and packaging method of image sensing chip - Google Patents
Packaging structure and packaging method of image sensing chip Download PDFInfo
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- CN114639741A CN114639741A CN202210260164.2A CN202210260164A CN114639741A CN 114639741 A CN114639741 A CN 114639741A CN 202210260164 A CN202210260164 A CN 202210260164A CN 114639741 A CN114639741 A CN 114639741A
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02016—Circuit arrangements of general character for the devices
- H01L31/02019—Circuit arrangements of general character for the devices for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a packaging structure and a method of an image sensing chip, wherein the method comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of chips to be packaged which are distributed in an array mode, each chip to be packaged is provided with a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, and the welding pad is electrically coupled with the induction area; providing a transparent cover plate, wherein the transparent cover plate is provided with a third surface and a fourth surface which are opposite; forming a light filtering coating on the third surface of the transparent cover plate; oppositely combining the fourth surface of the transparent cover plate and the first surface of the chip to be packaged, wherein the transparent cover plate covers all the chips to be packaged; and cutting the wafer, the transparent cover plate and the filtering coating to form a plurality of independent packaging structures. The invention adopts a wafer level packaging method, has low technical difficulty and low cost, does not adopt blue glass, and can not generate the problem of warping caused by inconsistent thermal expansion coefficients.
Description
Technical Field
The present invention relates to the field of semiconductor packaging technology, and more particularly, to a packaging structure and a packaging method for an image sensor chip.
Background
With the continuous development of scientific technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The image sensing chip is used as a chip for converting optical image signals into electronic signals, and has a sensing area, in the prior art, blue glass is usually used as a filtering unit to package a single-particle chip, the method has the problems of high difficulty and high cost of the packaging technology, and the problem of high CTE (coefficient of thermal expansion) is caused by the adoption of the blue glass.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a packaging structure and a packaging method of an image sensing chip, which can solve the problems of high difficulty and high cost of the packaging technology in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a method for packaging an image sensor chip, including:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged which are distributed in an array manner, each chip to be packaged is respectively provided with a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, and the welding pad is electrically coupled with the induction area;
providing a transparent cover plate, wherein the transparent cover plate is provided with a third surface and a fourth surface which are opposite;
forming a light filtering coating on the third surface of the transparent cover plate;
oppositely combining the fourth surface of the transparent cover plate and the first surface of the chip to be packaged, wherein the transparent cover plate covers all the chips to be packaged;
and cutting the wafer, the transparent cover plate and the filtering coating to form a plurality of independent packaging structures.
In one or more embodiments of the present invention, the optical filter coating layer uses polytetrafluoroethylene or trimethylbenzene.
In one or more embodiments of the present invention, after forming the filter coating on the third surface of the transparent cover plate, the method further includes:
and forming a packaging protective layer on the surface of the light filtering coating.
In one or more embodiments of the present invention, the encapsulation protection layer is an oxide or nitride, preferably a silicon dioxide protection layer.
In one or more embodiments of the present invention, in the packaging structure, the packaging protection layer is remained.
In one or more embodiments of the present invention, the thickness of the optical filter coating layer is 3 μm to 5 μm.
In one or more embodiments of the present invention, the method for oppositely bonding the fourth surface of the transparent cover plate and the first surface of the chip to be packaged comprises:
and forming a supporting structure on the fourth surface of the transparent cover plate or the first surface of the chip to be packaged, wherein the supporting structure is supported between the first surface of the chip to be packaged and the fourth surface of the transparent cover plate, so that the sensing area of the chip to be packaged is positioned in a groove formed by the supporting structure and the transparent cover plate in an enclosing manner.
In one or more embodiments of the present invention, a method of forming a support structure on a fourth surface of a transparent cover plate includes:
forming a layer of epoxy resin material or silicon material on the fourth surface of the transparent cover plate;
and exposing and developing the epoxy resin material to form the supporting structure.
In one or more embodiments of the present invention, before dicing the wafer, the transparent cover plate and the filter coating, the method further includes:
forming a through hole penetrating through the wafer on the second surface of each chip to be packaged, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip to be packaged and the side wall of the through hole;
forming a redistribution circuit layer on the surface of the insulating layer, wherein the redistribution circuit layer is electrically connected with the welding pad;
forming a solder mask layer with an opening on the surface of the redistribution circuit layer and the surface of the insulating layer, wherein part of the redistribution circuit layer is exposed out of the opening;
and forming a welding bulge electrically connected with the redistribution circuit layer in the opening.
In order to achieve the above object, an embodiment of the present invention provides a package structure of an image sensor chip, which is manufactured by any one of the above methods.
Compared with the prior art, the wafer level packaging method is adopted, the transparent cover plate is manufactured on one side of the sensing area of the chip, the optical surface of the transparent cover plate is simultaneously provided with the filtering coating, and then the wafer and the transparent cover plate are simultaneously cut to form a plurality of independent packaging structures.
Drawings
Fig. 1a to 1j are schematic intermediate structures of a package structure according to an embodiment of the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The trend in development of electronic devices is miniaturization and portability. One of the main factors that determine the miniaturization and portability of electronic devices is the package design of the chip in the electronic device. The conventional chip packaging method generally adopts wire bonding (WireBonding) for packaging, but with the rapid development of integrated circuits, the product size cannot meet the ideal requirements due to the longer lead, so that Wafer Level Packaging (WLP) gradually replaces wire bonding packaging to become a more common packaging method. The wafer level packaging technology is a technology of cutting a whole wafer into single chips after packaging test, and the size of the packaged chips is completely consistent with that of bare chips. The wafer level package has the following advantages: a plurality of wafers can be processed simultaneously, and the packaging efficiency is high; the whole wafer is tested before cutting, so that the test process in packaging is reduced, and the test cost is reduced; the packaged chip has the advantages of light weight, small size, short length and thinness.
When the image sensor chip is packaged by using the conventional wafer-level chip packaging technology, a package cover is usually required to be formed at the photosensitive area to protect the photosensitive area of the image sensor from being damaged and polluted. The encapsulation cover is typically a transparent substrate, allowing for the normal transmission of light. The transparent substrate can be used as a support in the formation process of the image sensing chip package, so that the manufacturing process can be smoothly carried out. After the wafer-level chip packaging is completed, the transparent substrate can still be kept, and the sensing area is continuously protected from being damaged and polluted in the use process of the subsequent image sensing chip.
As shown in fig. 1a to 1j, a method for packaging an image sensor chip according to a preferred embodiment of the present invention includes the following steps.
Step S01, referring to fig. 1a, a wafer 100 is provided, where the wafer 100 includes a plurality of chips 10 to be packaged distributed in an array and scribe line regions 20 located between adjacent chips 10 to be packaged. After the wafer 100 is subsequently diced along the scribe line region 20, a plurality of independent dies may be formed, where each die corresponds to a package structure of an image sensor chip.
Fig. 1b is a cross-sectional view of a-a' in fig. 1a, and 2 chips 10 to be packaged are exemplarily provided in fig. 1 b. Each chip 10 to be packaged has a first surface 11 and a second surface 12 opposite to each other, the first surface 11 has a sensing region 111 and a pad 112, and the pad 112 is electrically coupled to the sensing region 111.
Step S02, referring to fig. 1c, a transparent cover 30 is provided, wherein the transparent cover 30 has a third surface 31 and a fourth surface 32 opposite to each other.
The transparent cover 30 is mainly used to protect the sensing region 111 and provide external light into the sensing region 111, and also serves as a support for the filter coating. The size and shape of the transparent cover 30 correspond to the wafer, and the shielding of the sensing regions 111 in all the chips 10 to be packaged can be realized by providing one transparent cover 30.
In one embodiment, the transparent cover 30 is a transparent glass, which may be organic glass or inorganic glass.
Step S03, referring to fig. 1c, forms the filter coating 40 on the third surface 31 of the transparent cover 30.
Since any object above absolute zero (-237 ℃) emits infrared (infrared) light to the outside, that is, the sensing region 111 can sense visible light and infrared light at the same time, the refraction distance sum law of light can be obtained as follows: the longer the wavelength, the smaller the refractive index; the shorter the wavelength, the larger the refractive index. Therefore, after visible light and infrared light entered the sensing area 111 simultaneously, visible light and infrared light can form images at different target surfaces, the formation of image of visible light is the color graph, the formation of image of infrared light is black and white formation of image, after the image that forms with visible light is debugged, infrared light can form the virtual image at the target surface to influence the colour and the quality of image, consequently, need the surface formation filter coating 40 of transparent cover plate 30, filter the infrared light in the light, solve the problem of image color distortion.
In one embodiment, the filter coating is an IR coating (Infrared filtering coating) or an AR coating (Anti-reflection coating), which functions to filter out Infrared light.
In another embodiment, the filter coating is an organic compound, such as PTFE (polytetrafluoroethylene) or trimethylbenzene.
The filter coating 40 is formed by a spray coating or spin coating process, and the size of the filter coating 40 is consistent with that of the transparent cover plate 30.
In a preferred embodiment, the thickness of the filter coating is 3 μm to 5 μm.
Step S04, referring to fig. 1f, oppositely combining the fourth surface 32 of the transparent cover plate 30 and the first surface 11 of the chip 10 to be packaged, where the transparent cover plate 30 covers all the chips 10 to be packaged.
Step S05, dicing the wafer 100, the transparent cover plate 30 and the filter coating 40 to form a plurality of independent package structures.
Referring to fig. 1d, in step S03, after the filter coating 40 is formed on the third surface 31 of the transparent cover 30, the method further includes: an encapsulation protection layer 50 is further formed on the surface of the filter coating layer 40.
The encapsulation protection layer 50 may be an oxide or nitride, preferably a silicon dioxide protection layer, for protecting the optical surface of the exposed cover plate 30 during the encapsulation process, and has a thickness considering light transmittance and strength, and a thickness of 0.5 μm to 1 μm, such as 0.6 μm, 0.7 μm, 0.8 μm or 0.9 μm. After the encapsulation and dicing are completed, the encapsulation protection layer 50 may remain in the encapsulation structure without being removed.
In one embodiment, the package protection layer 50 is formed by sputtering.
Referring to fig. 1e, in the above step S04, the method for oppositely bonding the fourth surface 32 of the transparent cover plate 30 and the first surface 11 of the chip 10 to be packaged includes: a supporting structure 60 is formed on the fourth surface 32 of the transparent cover plate 30, and the supporting structure 60 is supported between the first surface 11 of the chip 10 to be packaged and the fourth surface 32 of the transparent cover plate 30, so that the sensing region 111 of the chip 10 to be packaged is located in the groove 61 enclosed by the supporting structure 60 and the transparent cover plate 30.
In one embodiment, the method of forming the support structure 60 on the fourth surface 32 of the transparent cover 30 includes: firstly, forming a layer of epoxy resin material on the fourth surface 32 of the transparent cover plate 30; the epoxy material is then exposed and developed to form the support structure 60.
In an embodiment, the supporting structure 60 may be formed on the first surface 11 of the chip 10 to be packaged, and then combined with the transparent cover 30.
In step S04, referring to fig. 1g, after the fourth surface 32 of the transparent cover 30 and the first surface 11 of the chip 10 to be packaged are bonded to each other, the method further includes: thinning the chip 10 to be packaged from the second surface 12 of the chip 10 to be packaged so as to reduce the thickness of the packaging structure and facilitate the subsequent etching of the via hole, wherein the thinning mode can adopt processes such as mechanical grinding, chemical grinding and the like.
In step S05, before dicing the wafer 100, the transparent cover plate 30 and the filter coating 40, the following steps are further included.
Step S051, referring to fig. 1h, forming a through hole 13 penetrating through the wafer on the second surface 12 of each chip 10 to be packaged, wherein the through hole 13 is used for exposing the welding pad 112.
The shape of the via hole 13 may be an inverse trapezoid hole with gradually increasing aperture from the second surface 12 to the first surface 11 of the chip 10 to be packaged, or a straight hole with the same aperture size from the second surface 12 to the first surface 11, as shown in fig. 1 h.
The cross-sectional shape of the via hole 13 may be circular, square or triangular, but the present disclosure is not limited thereto.
Step S052, referring to fig. 1i, forms an insulating layer 70 on the second surface 12 of the chip 10 to be packaged and the sidewall of the via hole 13.
The insulating layer 70 is used to realize electrical insulation, and the material thereof may be silicon oxide, silicon nitride, silicon oxynitride, or insulating resin.
Step S053, referring to fig. 1j, a redistribution line layer 80 is formed on the surface of the insulating layer 70, and the redistribution line layer 80 is electrically connected to the pad 112.
The redistribution layer 80 is a metal layer, and may be formed by metal film deposition and then etching.
Step S054 is to form a solder mask 90 having an opening exposing a portion of the redistribution line layer 80 on the surface of the redistribution line layer 80 and the surface of the insulation layer 70.
The via hole 13 is further filled with the solder resist layer 90, and the material of the solder resist layer 90 may be an insulating dielectric material such as silicon oxide, silicon nitride, etc. for protecting the redistribution line layer 80.
Step S055, forming a solder bump 110 electrically connected to the redistribution layer 80 in the opening.
The solder bump 110 may be a solder ball, a metal pillar, or other connecting structure, and the material may be a metal material such as copper, aluminum, gold, tin, or lead.
In step S03 and step S04, the fourth surface 32 of the transparent cover 30 and the first surface 11 of the chip 10 to be packaged may be bonded to each other, and then the filter coating 40 is formed on the third surface 31 of the transparent cover 30.
The embodiment also discloses a packaging structure of the image sensing chip, which is manufactured by adopting the method. In the packaging structure, a layer of PTFE or trimethylbenzene filtering material is formed on the surface of the transparent cover plate 30, and then the wafer and the transparent cover plate are simultaneously cut to form a plurality of independent packaging structures.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A method for packaging an image sensor chip, comprising:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged which are distributed in an array manner, each chip to be packaged is respectively provided with a first surface and a second surface which are opposite, the first surface is provided with an induction area and a welding pad, and the welding pad is electrically coupled with the induction area;
providing a transparent cover plate, wherein the transparent cover plate is provided with a third surface and a fourth surface which are opposite;
forming a light filtering coating on the third surface of the transparent cover plate;
oppositely combining the fourth surface of the transparent cover plate and the first surface of the chip to be packaged, wherein the transparent cover plate covers all the chips to be packaged;
and cutting the wafer, the transparent cover plate and the filtering coating to form a plurality of independent packaging structures.
2. The method of claim 1, wherein the filter coating is polytetrafluoroethylene or trimethylbenzene.
3. The method of claim 2, wherein after forming the filter coating on the third surface of the transparent cover, further comprising:
and forming a layer of packaging protective layer on the surface of the filtering coating.
4. The method for packaging an image sensor chip as claimed in claim 3, wherein the protective layer is an oxide or nitride, preferably a silicon dioxide protective layer.
5. The method of claim 4, wherein the passivation layer is retained in the package structure.
6. The method of claim 2, wherein the thickness of the filter coating is 3 μm to 5 μm.
7. The method for packaging an image sensor chip as claimed in claim 1, wherein the step of oppositely bonding the fourth surface of the transparent cover plate and the first surface of the chip to be packaged comprises:
and forming a supporting structure on the fourth surface of the transparent cover plate or the first surface of the chip to be packaged, wherein the supporting structure is supported between the first surface of the chip to be packaged and the fourth surface of the transparent cover plate, so that the sensing area of the chip to be packaged is positioned in a groove formed by the supporting structure and the transparent cover plate in an enclosing manner.
8. The method of claim 7, wherein the step of forming the support structure on the fourth surface of the transparent cover comprises:
forming a layer of epoxy resin material or silicon material on the fourth surface of the transparent cover plate;
and exposing and developing the epoxy resin material to form the supporting structure.
9. The method of claim 1, further comprising, before the dicing the wafer, the transparent cover plate, and the filter coating layer:
forming a through hole penetrating through the wafer on the second surface of each chip to be packaged, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip to be packaged and the side wall of the through hole;
forming a redistribution circuit layer on the surface of the insulating layer, wherein the redistribution circuit layer is electrically connected with the welding pad;
forming a solder mask layer with an opening on the surface of the redistribution circuit layer and the surface of the insulating layer, wherein part of the redistribution circuit layer is exposed out of the opening;
and forming a welding bulge electrically connected with the redistribution circuit layer in the opening.
10. A package structure of an image sensor chip, manufactured by the method of any one of claims 1 to 9.
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| CN202210260164.2A CN114639741A (en) | 2022-03-16 | 2022-03-16 | Packaging structure and packaging method of image sensing chip |
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| CN202210260164.2A CN114639741A (en) | 2022-03-16 | 2022-03-16 | Packaging structure and packaging method of image sensing chip |
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Cited By (1)
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| CN117936636A (en) * | 2023-12-29 | 2024-04-26 | 成都阜时科技有限公司 | Light sensing chip, preparation method thereof, laser radar and electronic equipment |
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| WO2017177631A1 (en) * | 2016-04-12 | 2017-10-19 | 华天科技（昆山）电子有限公司 | Image sensing chip packaging structure and manufacturing method therefor |
| US20200044099A1 (en) * | 2018-08-02 | 2020-02-06 | Xintec Inc. | Chip package and method for forming the same |
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- 2022-03-16 CN CN202210260164.2A patent/CN114639741A/en active Pending
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| WO2017177631A1 (en) * | 2016-04-12 | 2017-10-19 | 华天科技（昆山）电子有限公司 | Image sensing chip packaging structure and manufacturing method therefor |
| CN106449546A (en) * | 2016-09-26 | 2017-02-22 | 苏州晶方半导体科技股份有限公司 | Image sensor chip packaging structure and packaging method thereof |
| US20200044099A1 (en) * | 2018-08-02 | 2020-02-06 | Xintec Inc. | Chip package and method for forming the same |
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