CN114743955A - Packaging structure and manufacturing method thereof - Google Patents

Packaging structure and manufacturing method thereof Download PDF

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Publication number
CN114743955A
CN114743955A CN202210417792.7A CN202210417792A CN114743955A CN 114743955 A CN114743955 A CN 114743955A CN 202210417792 A CN202210417792 A CN 202210417792A CN 114743955 A CN114743955 A CN 114743955A
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China
Prior art keywords
layer
chip unit
metal layer
light shielding
forming
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CN202210417792.7A
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Chinese (zh)
Inventor
李瀚宇
林焱
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China Wafer Level CSP Co Ltd
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China Wafer Level CSP Co Ltd
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Priority to CN202210417792.7A priority Critical patent/CN114743955A/en
Publication of CN114743955A publication Critical patent/CN114743955A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/042—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
    • H01L31/02164—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors for shielding light, e.g. light blocking layers, cold shields for infrared detectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a packaging structure and a packaging method, wherein the packaging structure comprises: the chip unit is provided with a first surface and a second surface which are opposite, and the first surface is provided with a sensing area and a welding pad which is electrically connected with the sensing area; a cover plate disposed opposite to the first surface of the chip unit; and the light shielding layer covers the second surface of the chip unit and is selected from TiN, Ge, TiW or TaN. The light-shielding material is selected from TiN, Ge, TiW or TaN and the like, has better stability, low luminous flux and thermal shock resistance. Particularly, when the light shielding material is TiN, dry etching can be adopted to sequentially etch the TiN and the insulating layer in the etching of the exposed welding pad, the gas adopted in the dry etching is the same, and the insulating layer and the light shielding layer can be removed in the same etching process.

Description

Packaging structure and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor packaging technology, and more particularly, to a package structure and a method for fabricating the same.
Background
An image sensor chip, which is a chip that can convert an optical image into an electronic signal, has a sensing area. Since silicon has better light transmission capability in 1000-7000nm infrared band and far infrared band, near infrared light (750-1400nm), short wavelength infrared light (1400-3000nm) and medium wavelength infrared light (3000-8000nm) can transmit through the silicon layer. Therefore, under a specific light source, infrared light on the back surface of the chip can interfere with the front sensing area through the transparent Si layer, and distortion is caused.
In order to solve the problem, in the prior art, a metal light shielding layer is usually disposed on the back surface of silicon to prevent external light from passing through the silicon material and affecting the imaging quality of the chip. In the prior art, the metal light shielding layer is made of Al, and as the service life of the chip is longer and longer, the metal Al is easy to migrate, so that the short circuit of a chip circuit is caused, and the use failure of the chip is caused.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a packaging structure and a manufacturing method thereof, which can solve the problems that in the prior art, due to the adoption of metal Al, Al migration is easy to occur, so that the circuit of a chip is short-circuited, the use of the chip is invalid and the like.
To achieve the above object, an embodiment of the present invention provides a package structure, including:
the chip unit is provided with a first surface and a second surface which are opposite, and the first surface is provided with an induction area and a welding pad which is electrically connected with the induction area;
a cover plate disposed opposite to the first surface of the chip unit;
and the light shielding layer covers the second surface of the chip unit and is selected from TiN, Ge, TiW or TaN.
In one or more embodiments of the present invention, the package structure further includes:
a via hole penetrating the chip unit from the second surface of the chip unit, the via hole exposing the pad;
an insulating layer covering the second surface of the chip unit and the surface of the side wall of the via hole;
the metal layer is positioned on the surface of the insulating layer and electrically connected with the welding pad;
the solder mask is positioned on the surface of the metal layer and in the through hole, and is provided with an opening for exposing part of the metal layer;
and filling the opening and exposing the welding bump outside the surface of the solder resist layer.
In one or more embodiments of the present invention, the light shielding layer is formed between the insulating layer and the metal layer.
In one or more embodiments of the present invention, the light shielding layer is formed on a surface of the solder resist layer.
In one or more embodiments of the present invention, the light-shielding layer has a thickness of 0.1 to 0.13 um.
In order to achieve the above object, an embodiment of the present invention further provides a method for manufacturing a package structure, including:
providing a chip unit, wherein the chip unit is provided with a first surface and a second surface which are opposite, and the first surface is provided with a sensing area and a welding pad which is electrically connected with the sensing area;
providing a cover plate, and oppositely combining the cover plate and the first surface of the chip unit;
and covering a shading layer on the second surface of the chip unit, wherein the shading layer is selected from TiN, Ge, TiW or TaN.
In one or more embodiments of the present invention, further comprising:
forming a through hole penetrating through the chip unit on the second surface of the chip unit, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip unit and the side wall of the through hole;
forming a light-shielding layer on the surface of the insulating layer;
etching part of the shading layer and the insulating layer to expose the welding pad;
forming a metal layer on the surface of the light shielding layer, wherein the metal layer is electrically connected with the welding pad;
forming a solder mask layer on the surface of the metal layer and in the via hole, wherein the solder mask layer is provided with an opening for exposing part of the metal layer;
and forming a welding bulge which is electrically connected with the metal layer in the opening.
In one or more embodiments of the present invention, the light shielding layer is made of a TiN material, and in the same dry etching process, a portion of the TiN material and the insulating layer are sequentially removed to expose the pad.
In one or more embodiments of the present invention, further comprising:
forming a through hole penetrating through the chip unit on the second surface of the chip unit, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip unit and the side wall of the through hole;
etching part of the insulating layer to expose the welding pad;
forming a metal layer on the surface of the insulating layer, wherein the metal layer is electrically connected with the welding pad;
forming a solder mask layer on the surface of the metal layer and in the via hole, wherein the solder mask layer is provided with an opening for exposing part of the metal layer;
and forming a welding bulge electrically connected with the metal layer in the opening.
And forming a light shielding layer on the surface of the solder mask layer.
In one or more embodiments of the present invention, the light-shielding layer has a thickness of 0.1 to 0.13 um.
Compared with the prior art, the shading material is selected from TiN, Ge, TiW or TaN and the like, has better stability, low luminous flux and thermal shock resistance. Particularly, when the light shielding material is TiN, dry etching can be adopted to sequentially etch the TiN and the insulating layer in the etching of the exposed welding pad, the gas adopted in the dry etching is the same, and the insulating layer and the light shielding layer can be removed in the same etching process.
Drawings
Fig. 1 to 9 are intermediate structure schematic diagrams of a package structure according to embodiment 1 of the present invention;
fig. 10 is a schematic diagram of a package structure according to embodiment 2 of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Example 1
As shown in fig. 1, a package structure 100 according to a preferred embodiment of the present invention includes a chip unit 10, a cover plate 20, and a light shielding layer 30. The chip unit 10 has a first surface 11 and a second surface 12 opposite to each other, the first surface 11 has a sensing region 111 and a pad 112 electrically connected to the sensing region 111; the cover plate 20 is disposed opposite to the first surface 11 of the chip unit 10; the light shielding layer 30 covers the second surface 12 of the chip unit 10, and the light shielding layer 30 is selected from TiN, Ge, TiW or TaN.
The light shielding layer 30 covers the second surface 12 (back surface) of the chip unit 10, and since the light shielding layer 30 is opaque, light cannot pass through the Si material through the second surface 12, and thus interference to the sensing region 111 is avoided.
The shading layer 30 is selected from TiN, Ge, TiW or TaN, and has stable performance, low luminous flux and thermal shock resistance. When the light shielding layer 30 is made of TiN, dry etching may be used to sequentially etch TiN and the insulating layer (SiO) in the process of exposing the pad2) The same gas is used for dry etching, and the insulating layer and the light shielding layer 30 can be removed in the same etching process. When other materials such as Tiw or Ge are used for the light shielding layer 30, wet etching may be used in the process of exposing the bonding pad 112. When TaN is used as the light-shielding layer 30, it also has the ability to prevent thermal shock and metal migration.
In one embodiment, the chip unit 10 is an image sensor chip unit, and the sensing region 111 is connected to an external circuit through a pad 112 electrically connected thereto, and transmits a corresponding electrical signal. The sensing region 111 is an optical sensing region and may be formed by arranging a plurality of photodiode arrays, and the photodiodes may convert optical signals irradiated to the sensing region 111 into electrical signals, and transmit the electrical signals to an external circuit through the bonding pads 112.
In other embodiments, the sensing region of the chip unit 10 may also be a physical sensor that utilizes physical quantity changes such as heat, light, and pressure to measure, such as other optoelectronic devices, radio frequency devices, surface acoustic wave devices, and pressure sensing devices, or a micro-electromechanical system, a micro-fluidic system, and the like.
The cover plate 20 is made of a transparent material, which may be inorganic glass or organic glass.
A supporting structure 80 is disposed between the cover plate 20 and the chip unit 10, and the sensing region 111 of the chip unit 10 is located in a cavity defined by the supporting structure 80 and the first surface 11 of the chip unit 10.
In some embodiments, the material of the support structure 80 is a wet film or a dry film photoresist, and is formed by spraying, spin coating, or pasting, and the support structure 80 is formed after the support structure material layer is exposed and developed to be patterned.
In some embodiments, the support structure 80 may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and is formed by a deposition process, and then patterned by a photolithography and etching process to form the support structure 80.
In other embodiments, the support structure 80 may be formed by etching the cover plate 20. Specifically, a patterned photoresist layer may be formed on the cover plate 20, and then the cover plate 20 is etched by using the patterned photoresist layer as a mask, so as to form a support structure 80 in the cover plate 20, where the support structure 80 is a raised portion on the cover plate 20.
The second surface 12 of the chip unit 10 forms a via hole 13 penetrating through the chip unit 10, and the via hole 13 exposes the pad 112.
The second surface 12 of the chip unit 10 and the sidewall surface of the via hole 13 are formed with an insulating layer 40, and an opening exposing the pad 112 is formed at a position of the insulating layer 40 corresponding to the pad 112. In one embodiment, the material of the insulating layer 40 may be silicon oxide, silicon nitride, silicon oxynitride, or insulating resin.
The light shielding layer 30 is formed on the surface of the insulating layer 40, and an opening exposing the pad 112 is formed at a position corresponding to the pad 112.
In this embodiment, the light shielding layer 30 is formed on the surface of the insulating layer 40 and extends along the inner wall of the via hole 13, so that not only light from the second surface 12 of the chip unit 10 can be blocked, but also light from the side surface of the chip unit 10 can be blocked, and thus three-dimensional shielding is achieved.
The thickness of the light-shielding layer 30 is preferably 0.1 to 0.13 um. If the light shielding layer 30 is too thick, stress and subsequent etching problems are affected, the cost is high, and if the light shielding layer 30 is too thin, the light shielding effect is affected.
A metal layer 50 is formed on the surface of the light shielding layer 30, and the metal layer 50 is electrically connected to the pad 112.
The surface of the metal layer 50 and the inside of the via hole 13 are also covered with a solder resist layer 60, and the solder resist layer 60 has an opening for exposing a part of the metal layer 50. The solder resist layer 60 is made of an insulating dielectric material such as silicon oxide or silicon nitride, and is used for protecting the metal layer 50.
The solder mask 60 has an opening therein with a solder bump 70, and the solder bump 70 is electrically connected to the metal layer 50 and protrudes out of the surface of the solder mask 60. The solder bump 70 may be a solder ball, a metal pillar, or other connecting structure, and the material may be a metal material such as copper, aluminum, gold, tin, or lead.
Correspondingly, the embodiment of the invention provides a packaging method for forming the packaging structure shown in fig. 1. Fig. 2 to 9 are schematic diagrams of intermediate structures formed in a packaging process of a packaging method according to an embodiment of the invention.
Step s01, referring to fig. 2 and 3, provides a wafer 200 including a plurality of chip units 10 distributed in an array. Fig. 3 is a cross-sectional view of fig. 2 in the direction of a-a' showing two chip units 10 with a dicing channel 201 between the chip units 10 to facilitate a dicing process in a subsequent dicing process.
Each chip unit 10 has a first surface 11 and a second surface 12 opposite to each other, and the first surface 11 has a sensing region 111 and a pad 112 electrically connected to the sensing region 111.
Step s02, referring to fig. 4, a cover plate 20 is provided, and a supporting structure 80 is formed on a side surface of the cover plate 20, wherein a cavity 21 defined between the supporting structure 80 and the surface of the cover plate 20 corresponds to the sensing region 111 of the chip unit 10.
Since the light is required to reach the sensing region 111 through the cover plate 20, the cover plate 20 has high light transmittance and is a transparent material. Both surfaces of the cover plate 20 are flat and smooth, and do not scatter or diffuse incident light. In one embodiment, the material of the cover plate 20 may be inorganic glass, organic glass, or other light-transmitting material with a specific strength.
In some embodiments, the material of the supporting structure 80 is a wet film or a dry film photoresist, and is formed by spraying, spin coating, or pasting, and the supporting structure 80 is formed after the supporting structure material layer is exposed and developed to be patterned.
In some embodiments, the support structure 80 may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., and is formed by a deposition process, and then patterned by a photolithography and etching process to form the support structure 80.
In other embodiments, the support structure 80 may be formed by etching the cover plate 20. Specifically, a patterned photoresist layer may be formed on the cover plate 20, and then the cover plate 20 is etched by using the patterned photoresist layer as a mask, so as to form a support structure 80 in the cover plate 20, where the support structure 80 is a protruding portion on the cover plate 20.
Step s03, referring to fig. 5, the side of the cover plate 20 having the supporting structure 80 is opposed to and bonded to the first surface 11 of the chip unit 10, so that the supporting structure 80 is supported between the cover plate 20 and the first surface 11 of the chip unit 10, and the sensing region 111 is located in the cavity 21.
In order to facilitate the subsequent etching of the via hole, the chip unit 10 is thinned from the second surface 12 of the chip unit 10, and the thinning manner may be mechanical grinding, chemical mechanical grinding process, or the like.
Step s04, referring to fig. 6, a via hole 13 penetrating through the chip unit 10 is formed on the second surface 12 of the chip unit 10, and the via hole 13 is used for exposing the pad 112.
In an embodiment, the via 13 may be a trapezoid hole, and the aperture of the via 13 gradually increases in a direction from the first surface 11 to the second surface 12 of the via 13. In other embodiments, the vias 13 may also be straight holes, and the apertures of the vias 13 are the same in the direction from the first surface 11 to the second surface 12 of the vias 13. The cross section of the via 13 may be circular, triangular, square, or the like.
At step s05, referring to fig. 7, the insulating layer 40 is formed on the second surface 12 of the chip unit 10 and the sidewalls of the via hole 13 (including the bottom of the via hole 13, the insulating layer 40 covers the pad 112). The material of the insulating layer 40 may be silicon oxide, silicon nitride, silicon oxynitride, or insulating resin.
In step s06, referring to fig. 8, a light shielding layer 30 is formed on the surface of the insulating layer 40, and the thickness of the light shielding layer 30 is preferably 0.1 to 0.13 um. The material of the light shielding layer 30 is selected from TiN materials.
In step s07, referring to fig. 9, in the same dry etching process, part of the light shielding layer 30 and the insulating layer 40 are sequentially removed to form an opening exposing the pad 112.
Because the light-shielding layer 30 is made of TiN, the insulating layer 40 is made of SiO2The two materials can be etched by a dry method, and the etching gases are the same, so that the light shielding layer 30 and the insulating layer 40 can be etched in sequence in the same etching process, the process is simple, and the cost is low.
Next, a metal layer 50 is formed on the surface of the light shielding layer 30, and the metal layer 50 is electrically connected to the pad 112. The metal layer 50 serves as a redistribution layer for guiding the bonding pad 112 to the second surface 12 of the chip unit 10 and connecting with an external circuit, and the metal layer 50 may be formed by depositing and etching a metal film.
Next, referring to fig. 1, a solder mask layer 60 is formed on the surface of the metal layer 50 and in the via hole 13, and the solder mask layer 60 has an opening exposing a portion of the metal layer 50. The solder resist layer 60 is made of an insulating dielectric material such as silicon oxide or silicon nitride, and is used for protecting the metal layer 50.
Next, a solder bump 70 electrically connected to the metal layer 50 is formed in the opening of the solder resist layer 60. The solder bump 70 may be a solder ball, a metal pillar, or other connecting structure, and the material may be a metal material such as copper, aluminum, gold, tin, or lead.
In step s08, the wafer 200, the cover plate 20 and the light-shielding material layer 30 are diced along the scribe line regions 201 of the wafer 200 to form a plurality of independent package structures.
The cutting can be performed by a slicing knife or a laser cutting, and the slicing knife can be performed by a metal knife or a resin knife.
Example 2
As shown in fig. 10, a package structure 300 according to a second embodiment of the present invention includes a chip unit 310, a cover plate 320, and a light shielding layer 330. The chip unit 310 has a first surface 311 and a second surface 312 opposite to each other, the first surface 311 has a sensing region 3111 and a pad 3112 electrically connected to the sensing region 3111; the cover plate 320 is disposed opposite to the first surface 311 of the chip unit 310; the light shielding layer 330 covers the second surface 312 of the chip unit 310, and the light shielding layer 330 is selected from TiN, Ge, TiW or TaN.
A supporting structure 380 is disposed between the cover plate 320 and the chip unit 310, and the sensing region 3111 of the chip unit 310 is located in a cavity defined by the supporting structure 380 and the first surface 311 of the chip unit 310.
The second surface 312 of the chip unit 310 forms a via 313 penetrating through the chip unit 310, and the via 313 exposes the pad 3112.
The second surface 312 of the chip unit 310 and the sidewall surface of the via 313 are formed with an insulating layer 340, and an opening exposing the pad 3112 is formed at a position of the insulating layer 340 corresponding to the pad 3112.
A metal layer 350 is formed on the surface of the insulating layer 340, and the metal layer 350 is electrically connected to the pad 3112.
The surface of the metal layer 350 and the inside of the via hole 313 are also covered with a solder resist layer 360, and the solder resist layer 360 is provided with an opening for exposing a part of the metal layer 350.
The solder mask layer 360 has a hole therein with a solder bump 370, and the solder bump 370 is electrically connected to the metal layer 350 and protrudes out of the surface of the solder mask layer 360.
The main difference from embodiment 1 is that the light shielding layer 330 of the present embodiment is formed on the surface of the solder resist layer 360. Compared with embodiment 1, this solution cannot block the light from the side of the chip unit 310.
Other structures and manufacturing methods are the same as those in embodiment 1, and are not described again.
Example 3
In this embodiment, compared to embodiment 1, the material of the light-shielding layer 30 is selected from Ge, TiW or TaN. In the corresponding manufacturing process, it is necessary to etch the light-shielding layer 30 by using a wet etching process to form an opening exposing the pad 112, and etch the insulating layer 40 by using a dry etching process to form an opening exposing the pad 112 on the insulating layer 40. Etching was performed by two processes, and both time and cost were increased correspondingly as compared with the etching performed by one process of example 1.
The structure and other manufacturing methods are the same as those of embodiment 1, and are not described again.
The foregoing description of specific exemplary embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A package structure, comprising:
the chip unit is provided with a first surface and a second surface which are opposite, and the first surface is provided with an induction area and a welding pad which is electrically connected with the induction area;
a cover plate disposed opposite to the first surface of the chip unit;
and the light shielding layer covers the second surface of the chip unit and is selected from TiN, Ge, TiW or TaN.
2. The package structure of claim 1, wherein the package structure further comprises:
a via hole penetrating the chip unit from the second surface of the chip unit, the via hole exposing the pad;
an insulating layer covering the second surface of the chip unit and the surface of the side wall of the via hole;
the metal layer is positioned on the surface of the insulating layer and electrically connected with the welding pad;
the solder mask is positioned on the surface of the metal layer and in the through hole, and is provided with an opening for exposing part of the metal layer;
and filling the opening and exposing the welding bump outside the surface of the solder resist layer.
3. The package structure of claim 2, wherein the light shielding layer is formed between the insulating layer and the metal layer.
4. The package structure of claim 2, wherein the light shielding layer is formed on a surface of the solder resist layer.
5. The package structure of claim 1, wherein the light-shielding layer has a thickness of 0.1-0.13 um.
6. A method for manufacturing a package structure, comprising:
providing a chip unit, wherein the chip unit is provided with a first surface and a second surface which are opposite, and the first surface is provided with a sensing area and a welding pad which is electrically connected with the sensing area;
providing a cover plate, and oppositely combining the cover plate and the first surface of the chip unit;
and covering a shading layer on the second surface of the chip unit, wherein the shading layer is selected from TiN, Ge, TiW or TaN.
7. The method for manufacturing the package structure according to claim 6, further comprising:
forming a through hole penetrating through the chip unit on the second surface of the chip unit, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip unit and the side wall of the through hole;
forming a light shielding layer on the surface of the insulating layer;
etching part of the shading layer and the insulating layer to expose the welding pad;
forming a metal layer on the surface of the light shielding layer, wherein the metal layer is electrically connected with the welding pad;
forming a solder mask layer on the surface of the metal layer and in the via hole, wherein the solder mask layer is provided with an opening for exposing part of the metal layer;
and forming a welding bulge electrically connected with the metal layer in the opening.
8. The method for manufacturing the package structure according to claim 7, wherein the light shielding layer is made of TiN,
and in the same dry etching process, removing part of the TiN material and the insulating layer in sequence to expose the welding pad.
9. The method for manufacturing the package structure according to claim 6, further comprising:
forming a through hole penetrating through the chip unit on the second surface of the chip unit, wherein the through hole is used for exposing the welding pad;
forming an insulating layer on the second surface of the chip unit and the side wall of the through hole;
etching part of the insulating layer to expose the welding pad;
forming a metal layer on the surface of the insulating layer, wherein the metal layer is electrically connected with the welding pad;
forming a solder mask layer on the surface of the metal layer and in the via hole, wherein the solder mask layer is provided with an opening for exposing part of the metal layer;
and forming a welding bulge electrically connected with the metal layer in the opening.
And forming a light shielding layer on the surface of the solder mask layer.
10. The method of claim 6, wherein the light-shielding layer has a thickness of 0.1-0.13 um.
CN202210417792.7A 2022-04-20 2022-04-20 Packaging structure and manufacturing method thereof Pending CN114743955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210417792.7A CN114743955A (en) 2022-04-20 2022-04-20 Packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210417792.7A CN114743955A (en) 2022-04-20 2022-04-20 Packaging structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114743955A true CN114743955A (en) 2022-07-12

Family

ID=82283942

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210417792.7A Pending CN114743955A (en) 2022-04-20 2022-04-20 Packaging structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114743955A (en)

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