CN114639727A - Separate grid MOSFET device structure for improving EMI - Google Patents
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- 210000000746 body region Anatomy 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 65
- 229920005591 polysilicon Polymers 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 35
- 208000032365 Electromagnetic interference Diseases 0.000 claims 8
- 238000000034 method Methods 0.000 abstract description 8
- 238000000926 separation method Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention relates to a split gate MOSFET device structure for improving EMI, which comprises a first conduction type new substrate, a first conduction type epitaxial layer positioned on the first conduction type substrate, a first groove formed in the first conduction type epitaxial layer, a second conduction type body region and a first conduction type source region. On the basis of the existing split gate device, the second groove perpendicular to the first groove is added, the number of conductive channels is increased, the on-resistance is reduced, the on-loss is further reduced, the input capacitance Ciss is increased, and the problem of electromagnetic interference generated by the device in the rapid switching process is effectively solved.
Description
Technical Field
The invention relates to a power semiconductor device, in particular to a split gate MOSFET device structure for improving EMI, belonging to the technical field of power semiconductor devices.
Background
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a Field Effect Transistor that can be widely used, and the characteristics of the device are constantly close to the one-dimensional limit of silicon materials;
currently, power MOSFETs are mainly studied for the purpose of reducing power consumption, and semiconductor device power consumption includes conduction loss and switching loss. With the continuous improvement and innovation of devices, a Split-Gate Trench device structure (MOSFET) with extremely low conduction loss and extremely low switching loss is provided in the field, as shown in fig. 1, the one-dimensional limit of a silicon material can be broken in a medium-low voltage range, and the MOSFET has lower conduction resistance, so that lower conduction loss can be realized, and the device characteristics are greatly improved; however, in the application process, as the switching speed of the split gate type trench device is faster and faster, the problem of electromagnetic interference (i.e. EMI) is easily caused in the switching circuit.
Disclosure of Invention
The invention aims to provide a structure of a split gate MOSFET device for improving EMI (metal oxide semiconductor field effect transistor) aiming at an EMI phenomenon of the existing split gate type groove device in an application process, wherein a second groove which is vertical to a first groove is added on the basis of the existing split gate device, the number of conductive channels is increased, the on-resistance is reduced, the on-loss is further reduced, the input capacitance Ciss is increased, and the problem of the electromagnetic interference generated by the device in a rapid switching process is effectively solved.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a split gate MOSFET device structure for improving EMI comprises a first conduction type new substrate, a first conduction type epitaxial layer positioned on the first conduction type substrate, a first groove formed in the first conduction type epitaxial layer, a second conduction type body region and a first conduction type source region, and is characterized in that the first conduction type epitaxial layer further comprises a second groove vertically distributed with the first groove, and the depth of the second groove is smaller than that of the second groove.
Furthermore, first grid polycrystalline silicon and separation grid polycrystalline silicon are filled in the first groove, the first grid polycrystalline silicon and the separation grid polycrystalline silicon are isolated through a first insulating layer, the separation grid polycrystalline silicon is isolated from the first conduction type epitaxial layer through a second insulating layer, and the first grid polycrystalline silicon is isolated from the second conduction type epitaxial layer through a first grid oxide layer;
second grid polycrystalline silicon is filled in the second groove and connected with the first grid polycrystalline silicon, the second grid polycrystalline silicon is isolated from the second conductive type epitaxial region through a second grid oxide layer, and the second grid polycrystalline silicon is isolated from the first conductive type epitaxial layer through a third insulating layer.
Further, an insulating medium layer covers the first conductive type epitaxial layer, a source metal covers the insulating medium layer, the first grid polycrystalline silicon in the first groove is isolated from the source metal through the insulating medium layer, the second grid polycrystalline silicon in the second groove is isolated from the source metal through the insulating medium layer, and the source metal is electrically connected with the separation grid polycrystalline silicon in the first groove.
Furthermore, the source metal penetrates through the insulating medium layer and is in ohmic contact with the second conductive type body region and the first conductive type source region respectively, the first conductive type source region is located on two sides of the first groove and the second groove and is adjacent to the first conductive type source region, and the second conductive type body region is located between the first groove and the second groove and between the first groove and the second groove.
Further, a drain metal is formed on a lower surface of the first conductive type substrate, the drain metal being in ohmic contact with the first conductive type substrate.
Further, the depth of the second trench must be smaller than the depth of the second conductive-type body region.
Further, the depth of the second trench does not exceed the depth of the first conductive type source region.
Further, the thicknesses of the first gate oxide layer and the second gate oxide layer are the same.
Further, for the MOSFET structure of the N-type separation gate, the first conduction type is N-type conduction, and the second conduction type is P-type conduction; for a MOSFET structure with a P-type split gate, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Compared with the prior art, the invention has the following advantages:
1) according to the invention, the second grooves which are vertically distributed with the first grooves are arranged, so that the channels of the on-resistance can be increased, the channels of the on-resistance comprise a first conductive channel which is formed in the second conductive type body region by the first grooves through the first gate oxide layer and a second conductive channel which is formed in the second conductive type body region by the second grooves through the second gate oxide layer, and the on-resistance of the device during the on-state can be reduced by increasing the conductive channels, so that the on-loss is reduced;
2) according to the invention, the second grid polysilicon is arranged in the second groove, the second grid polysilicon is connected with the first grid polysilicon and leads out the grid (not shown in the figure) through the grid metal, the area of the grid is increased by the arrangement of the second grid polysilicon, further, the input capacitance Ciss is increased, Ciss = Cgs + Cgd, and the electromagnetic interference EMI problem of the device in the rapid switching process can be effectively resisted.
Drawings
Fig. 1 is a schematic diagram of a prior art split-gate MOSFET device.
Fig. 2 is a schematic structural view of a first trench and a second trench of the present invention.
FIG. 3 is a schematic diagram of a structure for forming a source contact hole according to the present invention.
Fig. 4 is a schematic diagram of the structure of a split gate MOSFET device of the present invention.
Description of reference numerals: 1-a first conductivity type substrate; 2-a first conductivity type epitaxial layer; 3-a first trench; 4-a second conductivity type body region; 5-a first conductivity type source region; 6-a second trench; 7-first gate polysilicon; 8-separation gate polysilicon; 9-a first insulating layer; 10-a second insulating layer; 11-a first gate oxide layer; 12-second gate polysilicon; 13-a second gate oxide layer; 14-an insulating dielectric layer; 15-source metal; 16-drain metal.
Detailed Description
The present invention will be further described with reference to the following specific examples.
Taking an N-type split gate MOSFET device as an example, the first conductivity type is N-type, and the second conductivity type is P-type;
example 1:
as shown in fig. 2, a split-gate MOSFET device structure for improving EMI comprises a first conductivity type new substrate 1, an N-type epitaxial layer 2 on the N-type substrate 1, a first trench 3 formed in the N-type epitaxial layer 2, a P-type body region 4, and an N-type source region 5, and further comprises a second trench 6 vertically distributed with respect to the first trench 3 in the N-type epitaxial layer 2, and the depth of the second trench 6 is smaller than the depth of the second trench 6;
the first groove 3 is filled with first grid polysilicon 7 and separation grid polysilicon 8, the first grid polysilicon 7 and the separation grid polysilicon 8 are isolated by a first insulating layer 9, the separation grid polysilicon 8 is isolated from the N-type epitaxial layer 2 by a second insulating layer 10, and the first grid polysilicon 7 is isolated from the P-type body region 4 by a first grid oxide layer 11;
As shown in fig. 3, an insulating dielectric layer 14 covers the N-type epitaxial layer 2, a source metal 15 covers the insulating dielectric layer 14, the first gate polysilicon 7 in the first trench 3 is isolated from the source metal 15 by the insulating dielectric layer 14, the second gate polysilicon 12 in the second trench 6 is isolated from the source metal 15 by the insulating dielectric layer 14, and the source metal 15 is electrically connected to the split gate polysilicon 8 in the first trench 3, which is not shown in the figure and is well known to those skilled in the art;
the source metal 15 penetrates through the insulating medium layer 14 and is in ohmic contact with the P-type body region 4 and the N-type source region 5 respectively, the N-type source region 5 is located on two sides of the first groove 3 and the second groove 6 and is adjacent to the first groove 3 and the second groove 6, and the P-type body region 4 is located between the first groove 3 and the second groove 6 and between the first groove 3 and the second groove 6;
and forming a drain metal 16 on the lower surface of the N-type substrate 1, wherein the drain metal 16 is in ohmic contact with the N-type substrate 1.
In the embodiment of the present invention, the depth of the second trench 6 must be smaller than the depth of the P-type body region 4, and the depth of the second trench 6 does not exceed the depth of the N-type source region 5.
1-a first conductivity type substrate; 2-a first conductivity type epitaxial layer; 3-a first trench; 4-a second conductivity type body region; 5-a first conductivity type source region; 6-a second trench; 7-first gate poly; 8-separation gate polysilicon; 9-a first insulating layer; 10-a second insulating layer; 11-a first gate oxide layer; 12-second gate polysilicon; 13-a second gate oxide layer; 14-an insulating dielectric layer; 15-source metal; 16-drain metal.
The method for manufacturing the structure of the split-gate MOSFET device for improving EMI in embodiment 1 above includes the following steps:
providing an N-type heavily doped substrate 1, and growing an N-type epitaxial layer 2 on the N-type heavily doped substrate 1;
etching the N-type epitaxial layer 2 to obtain a first groove 3 and a second groove 6 which is vertically distributed with the first groove 3;
in the present invention, the depth of the first trench 3 is greater than the depth of the second trench 6;
growing a thick oxide layer in the first trench 3 by thermal oxidation, continuously depositing polycrystalline silicon on the thick oxide layer, etching the polycrystalline silicon, and obtaining a separation gate polycrystalline silicon 8 and a second insulating layer 10 at the bottom of the first trench 3;
continuing growing an oxide layer in the first trench 3 by thermal oxidation, and etching the oxide layer to obtain a first insulating layer 9 on the split gate polysilicon 8, a first gate oxide layer 11 on the side wall of the first trench 3 and a second gate oxide layer 13 at the bottom of the second trench 6;
in the process of etching the oxide layer in the above steps, the ratio of horizontal etching to vertical etching is controlled, so that the thickness of the first insulating layer 9 is larger than that of the first gate oxide layer 11, and the thickness of the first gate oxide layer 11 is the same as that of the second gate oxide layer 13;
depositing polycrystalline silicon in the first trench 3 and the second trench 6 continuously, and etching the polycrystalline silicon to obtain first grid polycrystalline silicon 7 in the first trench 3 and second grid polycrystalline silicon 12 in the second trench 6;
injecting P-type impurities and N-type impurities into the surface of the N-type epitaxial layer 2 in sequence, pushing a well, and forming a P-type body region 4 and an N-type source region 5 in sequence, as shown in FIG. 2;
depositing an insulating medium layer 14 on the surface of the N-type epitaxial layer 2, etching the insulating medium layer 14, and forming a source contact hole penetrating through the N-type source region 5 above the P-type body region 4; as shown in fig. 3;
step eight, filling metal in the source contact hole to form source metal 15; the source metal 15 is in ohmic contact with the P-type body region 4 and the N-type source region 5 respectively;
meanwhile, the source metal 15 is also in ohmic contact with the leading-out end of the separation gate polysilicon 8, and a gate metal is also formed, and the gate metal is in ohmic contact with the first gate polysilicon 7 and the second gate polysilicon 12 respectively, as shown in the above figures, which is well known by those skilled in the art and is not described again;
and step nine, depositing metal on the lower surface of the N-type heavily doped substrate 1 to form drain metal 16, thus completing the manufacture of the split gate MOSFET device for improving EMI, as shown in FIG. 4.
According to the invention, the second grooves 6 which are vertically distributed with the first grooves 3 are arranged, so that the channels of the conduction resistance can be increased, the channels of the conduction resistance comprise a first conductive channel which is formed on the second conductive type body region 4 by the first grooves 3 through the first gate oxide layer 11 and a second conductive channel which is formed on the second conductive type body region 4 by the second grooves 6 through the second gate oxide layer 13, the conduction resistance of the device during conduction can be reduced by increasing the conductive channels, and the conduction loss is further reduced;
in the invention, the second gate polysilicon 12 is arranged in the second trench 6, the second gate polysilicon 12 is connected with the first gate polysilicon 7, and the gates (not shown in the figure and well known to those skilled in the art) are all led out through gate metal, and the area of the gate is increased by arranging the second gate polysilicon 12, so that the input capacitance Ciss is increased, Ciss = Cgs + Cgd, and the electromagnetic interference EMI problem of the device in the rapid switching process can be effectively resisted.
It is also noted that the term "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a good or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such good or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a commodity or system that includes the element.
The foregoing description shows and describes several preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A split-gate MOSFET device structure for improving EMI (electro magnetic interference) comprises a first conduction type new substrate (1), a first conduction type epitaxial layer (2) positioned on the first conduction type substrate (1), a first groove (3) formed in the first conduction type epitaxial layer (2), a second conduction type body region (4) and a first conduction type source region (5), and is characterized in that a second groove (6) vertically distributed with the first groove (3) is further included in the first conduction type epitaxial layer (2), and the depth of the second groove (6) is smaller than that of the second groove (6).
2. The structure of claim 1, wherein the first trench (3) is filled with a first gate polysilicon (7) and a split gate polysilicon (8), the first gate polysilicon (7) and the split gate polysilicon (8) are isolated by a first insulating layer (9), the split gate polysilicon (8) is isolated from the epitaxial layer (2) of the first conductivity type by a second insulating layer (10), and the first gate polysilicon (7) is isolated from the body region (4) of the second conductivity type by a first gate oxide layer (11);
second grid polysilicon (12) is filled in the second groove (6), the second grid polysilicon (12) is connected with the first grid polysilicon (7), the second grid polysilicon (12) is isolated from the second conduction type body region (4) through a second grid oxide layer (13), and the second grid polysilicon (12) is isolated from the first conduction type epitaxial layer (2) through a third insulating layer.
3. The split-gate MOSFET device structure for improving EMI as claimed in claim 2, wherein the first conductivity type epitaxial layer (2) is covered with an insulating dielectric layer (14), the insulating dielectric layer (14) is covered with a source metal (15), the first gate polysilicon (7) in the first trench (3) is isolated from the source metal (15) by the insulating dielectric layer (14), the second gate polysilicon (12) in the second trench (6) is isolated from the source metal (15) by the insulating dielectric layer (14), and the source metal (15) is electrically connected to the split-gate polysilicon (8) in the first trench (3).
4. The structure of claim 3, wherein the source metal (15) is in ohmic contact with the second conductivity type body region (4) and the first conductivity type source region (5) through the insulating dielectric layer (14), the first conductivity type source region (5) is located on both sides of and adjacent to the first trench (3) and the second trench (6), and the second conductivity type body region (4) is located between the first trenches (3), between the second trenches (6), between the first trenches (3) and between the second trenches (6).
5. The EMI improved split-gate MOSFET device structure of claim 1 wherein a drain metal (16) is formed on the lower surface of said first conductivity type substrate (1), said drain metal (16) being in ohmic contact with said first conductivity type substrate (1).
6. An EMI improved split-gate MOSFET device structure as claimed in claim 1, characterized in that the depth of said second trench (6) must be less than the depth of said second conductivity type body region (4).
7. An EMI improved split-gate MOSFET device structure as claimed in claim 1 in which the depth of said second trench (6) does not exceed the depth of said first conductivity type source region (5).
8. The EMI improved split-gate MOSFET device structure of claim 1 wherein said first gate oxide layer (11) and said second gate oxide layer (13) are the same thickness.
9. The EMI improved split-gate MOSFET device structure of claim 1 wherein for an N-type split-gate MOSFET structure, said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity; for a MOSFET structure with a P-type split gate, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102007584A (en) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | Semiconductor device structures and related processes |
| US20150349110A1 (en) * | 2014-05-30 | 2015-12-03 | Texas Instruments Incorporated | Mosfet having dual-gate cells with an integrated channel diode |
| CN110491935A (en) * | 2019-08-31 | 2019-11-22 | 电子科技大学 | Separate gate VDMOS device and manufacturing method with high gully density |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102007584A (en) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | Semiconductor device structures and related processes |
| US20150349110A1 (en) * | 2014-05-30 | 2015-12-03 | Texas Instruments Incorporated | Mosfet having dual-gate cells with an integrated channel diode |
| CN110491935A (en) * | 2019-08-31 | 2019-11-22 | 电子科技大学 | Separate gate VDMOS device and manufacturing method with high gully density |
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