CN114639605A - Preparation method of array type round hole shape of high-density gene chip - Google Patents
Preparation method of array type round hole shape of high-density gene chip Download PDFInfo
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- CN114639605A CN114639605A CN202111437530.9A CN202111437530A CN114639605A CN 114639605 A CN114639605 A CN 114639605A CN 202111437530 A CN202111437530 A CN 202111437530A CN 114639605 A CN114639605 A CN 114639605A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
The invention provides a preparation method of a high-density gene chip array type round hole shape, which is characterized in that an oxide layer is deposited on the surface of a wafer; forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by adopting a primary photoetching process; and after the photoresist mask pattern is subjected to multiple times of soaking and hardening treatment, etching the oxide layer at the bottom of the photoresist mask pattern by adopting a dry etching process to form the array type round hole morphology. The preparation method of the invention adjusts the problem of uneven stress of the photoresist through multiple infiltration and film hardening treatment, realizes the high-density array type round hole structure which can be formed only by one-time photoetching process, not only effectively improves the photoresist mask structure of the round hole shape of the gene chip and the process quality of the round hole shape after dry etching, but also greatly simplifies the whole process flow and reduces the cost.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a preparation method of a high-density gene chip array type circular hole shape.
Background
The gene detection chip belongs to one of semiconductor devices, has wide application in the aspects of various biological breeding, gene detection and the like at present, the higher the requirement for detection is, the higher the design structure gradually develops towards the direction of high-density arrangement, the requirement of the high-density chip structure on the device appearance is very strict, and the array type device structure needs to reach the uniform size, so the process precision requirement in the gene chip preparation process is very strict. Generally, the shape control of small round holes in a chip preparation process is an important process capability, so that the process quality needs to be strictly controlled in related processes of forming round holes such as photoetching and etching, the round holes are symmetrical and highly round in the preparation stage, and the round holes are uniform in size and controllable in precision in the aspect of array arrangement.
Compared with the dry etching process of the round hole on the oxide layer film, the mask shape of the photoresist is the first requirement and the quality is also ensured. Therefore, the shape control of the round holes of the photoresist is the key point of research, the shape of the round holes of the photoresist is influenced by the glue coating uniformity and adhesion, the exposure uniformity, the focal length and the exposure amount, the developing time and method, the film hardening time, the process design and other processes, and in addition, the high-density (dense) round holes are arranged in an array manner, in the photoetching process, process instability factors exist in the aspects of interference of exposure ultraviolet rays, non-uniformity of development, thermal stress deformation caused by baking, dispersion of plasmas in the etching process and the like, and finally, process deviation can be caused, and the structure of a device can not meet the design requirements and the like.
Disclosure of Invention
In order to overcome the defects of irregular patterns and uneven device structures in the preparation link of gene chips in the prior art, the invention provides a preparation method of a high-density gene chip array type circular hole shape, which comprises the following steps:
depositing an oxide layer on the surface of the wafer;
forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by adopting a primary photoetching process;
and after the photoresist mask pattern is subjected to multiple times of soaking and hardening treatment, etching the oxide layer at the bottom of the photoresist mask pattern by adopting a dry etching process to form the array type round hole morphology.
Preferably, the performing the multiple soaking and hardening treatments on the photoresist mask pattern includes:
repeating the soaking and film hardening treatment twice, detecting whether the roundness of the array-type round holes in the photoresist mask pattern after the second treatment and the uniformity of the intervals among the round holes meet preset conditions, and if so, finishing the soaking and film hardening treatment;
otherwise, carrying out next infiltration and film hardening treatment until the roundness of the array-type round holes in the photoresist mask pattern and the uniformity of the intervals among the round holes meet preset conditions after the current treatment.
Preferably, the preset conditions include:
the circularity of the array-type round holes in the photoresist mask pattern is less than 0.2 micron, an
The uniformity of the spacing between the circular holes is less than 0.1 micron.
Preferably, each soaking and hardening process comprises the following steps:
soaking the photoresist mask pattern by using deionized water;
and spin-drying the soaked photoresist mask pattern, and hardening the photoresist in an oven filled with nitrogen to cure the photoresist.
Preferably, the soaking time is 50-70s, the speed of the spin-drying is 600-.
Preferably, the forming of the photoresist mask pattern on the surface of the wafer deposited with the oxide layer by using the one-time photolithography process includes:
spraying a tackifier on the surface of the oxide layer;
coating photoresist on the surface of the oxide layer sprayed with the tackifier;
and forming a photoresist mask pattern after exposing, developing and cleaning the wafer coated with the photoresist.
Preferably, the step of coating photoresist on the surface of the oxide layer after spraying the adhesion promoter comprises the following steps:
rotationally coating photoresist on the surface of the oxide layer sprayed with the tackifier by using a full-automatic gluing and developing machine;
baking the wafer coated with the photoresist according to a preset environment temperature and baking time to enable the viscous photoresist to be changed into a solid state;
the thickness of the coating photoresist is 1.7-1.9 microns, and the uniformity of the photoresist thickness is not more than 1%;
the baking environment temperature is 120 ℃, and the baking time is 120-150 s.
Preferably, the light intensity range of the exposure is 680-750mW/cm2, the dose of the exposure is 315ms +/-5 ms, the focal length range of the exposure is 0.2-0.4, and the uniformity of the light intensity of the exposure is not more than 2%.
Preferably, after the exposing, developing and cleaning the wafer coated with the photoresist, forming a photoresist mask pattern includes:
emitting ultraviolet rays by adopting a scanning stepping exposure machine, and exposing the wafer coated with the photoresist;
developing the exposed surface of the wafer by using a full-automatic glue spreading and developing machine to dissolve the photoresist in the exposure area;
and cleaning the surface of the wafer by using a cleaning solution, removing the photoresist dissolved and denatured in the exposure area, and spin-drying the wafer to form a photoresist mask pattern.
Preferably, before depositing the oxide layer on the surface of the wafer, the method further comprises:
and rinsing the wafer by using deionized water, and then rinsing the surface of the wafer by using DHF cleaning solution.
Preferably, the etching the oxide layer at the bottom of the photoresist mask pattern by using a dry etching process includes:
and etching the oxide layer by adopting plasma, and converting the array type round hole patterns on the photoresist mask to the oxide layer.
Preferably, after the etching the oxide layer at the bottom of the photoresist mask pattern by using the dry etching process, the method further includes:
and removing the photoresist remained on the surface of the silicon oxide after the dry etching by adopting a cleaning process.
Preferably, the depositing an oxide layer on the surface of the wafer includes:
and depositing an oxide layer on the surface of the wafer by adopting PECVD equipment or furnace tube oxidation, wherein the thickness of the oxide layer is 1.6-2.5 microns, and the uniformity requirement of the oxide layer is not more than 1%.
The technical scheme provided by the invention has the following beneficial effects:
in the preparation method of the high-density gene chip array type round hole shape, an oxide layer is deposited on the surface of a wafer; forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by adopting a primary photoetching process; and after the photoresist mask pattern is subjected to multiple times of soaking and hardening treatment, etching the oxide layer at the bottom of the photoresist mask pattern by adopting a dry etching process to form the array type round hole morphology. The invention adjusts the problem of uneven stress of the photoresist through multiple infiltration and film hardening treatments, realizes the high-density array type round hole structure which can be formed only by one-time photoetching process, effectively improves the photoresist mask structure of the round hole appearance of the gene chip and the process quality of the round hole appearance after dry etching, greatly simplifies the whole process flow and reduces the cost.
In addition, the invention ensures the appearance of the photoresist circular hole and the etching appearance of the silicon oxide by optimizing partial parameters in the preparation method, solidifies the technical scheme suitable for preparing the circular hole structure of the gene chip, and effectively realizes the control of the process precision of photoetching, etching and the like, wherein the most important characteristic parameter is that the process deviation can be controlled within 0.05 micron, and the appearance of the photoresist of the circular hole meets the requirements of etching size and section angle in the dry etching process.
Drawings
FIG. 1 is a schematic diagram of a gene chip array round hole structure (CDSEM) formed by the method for controlling the shape of a high-density gene chip array round hole according to the embodiment of the present invention;
FIG. 2 is a diagram of reticle circle hole design dimensions;
FIG. 3 is a photoresist surface map (CDSEM) of a circular hole shape;
FIG. 4 is a cross-sectional view (SEM) of a photoresist in the shape of a circular hole;
FIG. 5 Dry etched silicon oxide surface map (CDSEM) of circular hole shape;
FIG. 6 is a cross-sectional view (SEM) of silicon oxide after dry etching in the shape of a circular hole;
FIG. 7 is a high density array type round hole Shape (SEM) of the gene chip of a company in the prior art;
FIG. 8 is a schematic flow chart of a method for controlling the shape of the circular hole of the high-density gene chip array in the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
In order to explore the accuracy control of the shape of the array circular hole in the high-density gene detection chip, improve the process quality of the array circular hole structure after dry etching and better solve the problems of irregular patterns and uneven device structures in the preparation link of the gene chip, embodiment 1 of the invention provides a preparation method of the shape of the array circular hole of the high-density gene chip, as shown in fig. 8, the method comprises the following specific processes:
s11, depositing an oxide layer on the surface of the wafer;
s12, forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by adopting a one-time photoetching process;
and S13, after the photoresist mask pattern is subjected to multiple soaking and hardening treatments, etching the oxide layer at the bottom of the photoresist mask pattern by adopting a dry etching process to form the array type round hole morphology.
Alternatively, before the step S11, the method may further include the following steps:
s10, pre-cleaning the wafer;
specifically, the silicon wafer is pre-cleaned by adopting cleaning equipment, and the pre-cleaning comprises the steps of rinsing the surface of the silicon wafer by using DHF cleaning solution after deionized water is used for rinsing, and removing contaminated organic particles and the like contained in the silicon wafer.
An alternative to the embodiment of the present invention, in the above-mentioned S11,
an oxide layer can be deposited on the surface of the wafer by adopting PECVD equipment or furnace tube oxidation, the thickness of the oxide layer is 1.6-2.5 microns, and the uniformity requirement of the oxide layer is not more than 1%.
Illustratively, in the embodiment of the invention, a layer of SiO2 film with the thickness of 2.2 +/-0.1 microns can be deposited on the surface of a silicon wafer by adopting PECVD equipment, and the uniformity requirement is less than 1%.
Alternatively to the embodiment of the present invention, the above-mentioned S12 may include the following steps,
s121, spraying a tackifier on the surface of the oxide layer;
s122, coating photoresist on the surface of the oxide layer on which the tackifier is sprayed;
and S123, forming a photoresist mask pattern after exposing, developing and cleaning the wafer coated with the photoresist.
The S122 may include:
s1221, rotationally coating photoresist on the surface of the oxide layer sprayed with the adhesion promoter;
s1222, baking the wafer coated with the photoresist according to a preset ambient temperature and baking time to change the viscous photoresist into a solid state;
illustratively, a full-automatic gumming developing machine can be adopted to spray an HMDS adhesion promoter on the surface of the SiO2 film and rotationally coat 1.8 +/-0.1 micron AZ MIR-703 photoresist, wherein the uniformity of the thickness of the photoresist is less than or equal to 1%; the environment temperature of the baking is 120 ℃, and the baking time can be 120-150 s.
The step S123 may include:
s1231, emitting ultraviolet rays by adopting a scanning stepping exposure machine, and exposing the wafer coated with the photoresist;
s1232, developing the exposed surface of the wafer by using a full-automatic glue spreading and developing machine to dissolve the photoresist in the exposure area;
and S1233, cleaning the surface of the wafer by using a cleaning solution, removing the photoresist dissolved and denatured in the exposure area, and drying the wafer by spinning to form a photoresist mask pattern.
Illustratively, a scanning stepper is adopted to execute the exposure process, the focal length is set to be 0.3 +/-0.1 by compensation before exposure, the light intensity is adjusted to be 680-750mW/cm2, the uniformity requirement is within 2%, and the overexposure is 10% -35% on the basis of the normal exposure dose obtained by process point inspection.
Illustratively, the exposed wafer is developed (e.g., using FHD-5 developer) and cleaned (e.g., using deionized water) using a fully automatic paste developer, and the photoresist mask pattern is formed by removing the modified photoresist in the exposed region.
Alternatively, in the S13, the step of performing the multiple wetting and hardening treatments on the photoresist mask pattern may include the following steps:
repeating the soaking and film hardening treatment twice, detecting whether the roundness of the array-type round holes in the photoresist mask pattern after the second treatment and the uniformity of the intervals among the round holes meet preset conditions, and if so, finishing the soaking and film hardening treatment;
otherwise, carrying out next infiltration and film hardening treatment until the roundness of the array-type round holes in the photoresist mask pattern and the uniformity of the intervals among the round holes meet preset conditions after the current treatment.
Specifically, the preset conditions to be met include:
the circularity of the array-type circular holes in the photoresist mask pattern is less than 0.2 micron, an
The uniformity of the spacing between the circular holes is less than 0.1 micron.
Specifically, the process of each soaking and hardening treatment comprises the following steps:
soaking the photoresist mask pattern by using deionized water;
and spin-drying the soaked photoresist mask pattern, and hardening the photoresist in an oven filled with nitrogen to cure the photoresist.
Specifically, the soaking and hardening process comprises the step of soaking the photoresist mask with deionized water, so that the surface layer of the photoresist contains certain moisture, and the shrinkage deformation of the surface layer of the photoresist contacting gas in the hardening process under the high-temperature nitrogen environment due to solvent volatilization and thermal stress is prevented. For the AZ703 photoresist with the thickness of 1.8 microns in the embodiment of the invention, the soaking and hardening process can be repeatedly performed for 2 times, the soaking time is 50-70s, the spin-drying speed is 600-.
Illustratively, after soaking the photoresist mask for 1 minute by using deionized water, rotating the photoresist mask at a low speed of 800 rpm to spin the photoresist mask until no obvious water drops exist on the surface layer, putting the photoresist mask into a high-temperature 100 ℃ oven which is fully filled with an N2 environment for hardening for 150 seconds, soaking the photoresist mask for 1 minute again by using deionized water, and hardening for 150 seconds again.
An alternative of the embodiment of the present invention is that, in S13, etching the oxide layer at the bottom of the photoresist mask pattern by using a dry etching process includes:
the dry etching process is to etch the SiO2 film of the wafer by adopting plasma under the protection of the photoresist mask pattern, and convert the high-density array type round hole pattern on the photoresist mask to the silicon oxide film.
And etching the SiO2 film of about 2.2 microns with the photoresist as a mask by using dry etching equipment until the SiO2 film is completely etched, and forming array-type high-density circular micropores on the SiO2 film, as shown in figure 1.
An alternative of the embodiment of the present invention is that, after the etching of the oxide layer at the bottom of the photoresist mask pattern by using the dry etching process in S13, the method may further include:
s14, removing the photoresist remained on the surface of the silicon oxide after dry etching by adopting a cleaning process;
specifically, the cleaning process comprises the step of cleaning and removing the photoresist remained on the surface of the silicon oxide after dry etching by using No. 3 SPM liquid medicine (H2SO 4: H2O2 is 3: 1) and No. 1 SC-1 liquid medicine (NH4 OH: H2O 2: H2O is 1: 2: 7).
In order to test the process capability of the invention, microscopic observation of the surfaces and the sections of the photoresist round hole after photoetching and the SiO2 round hole after dry etching is carried out: FIG. 2 shows the design size of the round holes of the photolithography mask as 1.3 microns in diameter and 0.85 micron in pitch; fig. 3 shows the surface topography of the circular holes of the photoresist mask, a single circle with a large radius test deviation is selected, the test maximum diameter is 1.314 micrometers, the test minimum diameter is 1.304 micrometers up to now, and the roundness is 0.01 micrometer, and the test results of different circular holes show that the sizes of the circular holes arranged in a high-density array manner have high uniformity, and the photoetching deviation is less than 0.03um compared with the design size of the circular holes; FIG. 4 is a side wall profile of a photoresist mask with left and right side wall angles of 89.1 and 88.9 degrees, respectively, with a deviation of 0.2 degrees; FIG. 5 shows the surface morphology of a circular hole after dry etching of a SiO2 film, and a single circular hole with the largest roundness is selected for testing, wherein the largest diameter is 1.331um, the smallest diameter is 1.319um, and the roundness is 0.012um, compared with the size of a photoresist before etching, the etching loss is less than 0.05um, and the roundness test results of different circular holes show that the size of an array circular hole after dry etching has high uniformity; FIG. 6 shows the shape of the sidewall of a circular hole etched by SiO2, wherein the angles of the left and right sidewalls are 91.4 degrees and 90.7 degrees, respectively, and the deviation is 0.7 degree.
Compared with the surface circular hole shape of an array high-density gene chip of a company in the prior art, as shown in fig. 7, the preparation method of the embodiment of the invention is extremely advanced from the edge shape of the circular hole, and the results show that the preparation method of the embodiment of the invention can control the precision of the relevant process for preparing the circular hole within 0.05 μm, simultaneously the angle of the side wall after etching can be larger than 88 degrees (the angle of the side wall of the circular hole is smaller than 92 degrees), the deviation is smaller than 1 degree, and the roundness is smaller than 0.02 μm.
For a gene chip structure requiring a round hole shape, the embodiment of the invention provides a preparation method suitable for a high-density array type round hole shape of a gene chip, meanwhile, the shape of a photoresist round hole and the etching shape of silicon oxide are ensured by adjusting partial parameters in the process, the technical scheme suitable for preparing the round hole structure of the gene chip is solidified, and the control of the process precision of photoetching, etching and the like is effectively realized, wherein the most important characteristic parameter is that the process deviation can be controlled within 0.05 micrometer, and the photoresist shape of the round hole meets the requirements of the etching size and the section angle in the dry etching process. The method effectively improves the photoresist mask structure of the round hole shape of the gene chip and the process quality of the round hole shape after dry etching, and obtains the process flow and the scheme which are applicable to mass production.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (13)
1. A preparation method of a high-density gene chip array type round hole shape is characterized by comprising the following steps:
depositing an oxide layer on the surface of the wafer;
forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by adopting a primary photoetching process;
and after the photoresist mask pattern is subjected to multiple times of soaking and hardening treatment, etching the oxide layer at the bottom of the photoresist mask pattern by adopting a dry etching process to form the array type round hole morphology.
2. The method of claim 1, wherein the performing a plurality of wet and hard treatments on the photoresist mask pattern comprises:
repeating the soaking and film hardening treatment twice, detecting whether the roundness of the array-type round holes in the photoresist mask pattern after the second treatment and the uniformity of the intervals among the round holes meet preset conditions, and if so, finishing the soaking and film hardening treatment;
otherwise, carrying out next infiltration and film hardening treatment until the roundness of the array-type round holes in the photoresist mask pattern and the uniformity of the intervals among the round holes after the current treatment meet the preset conditions.
3. The method according to claim 2, wherein the preset conditions include:
the circularity of the array-type circular holes in the photoresist mask pattern is less than 0.2 micron, an
The uniformity of the spacing between the circular holes is less than 0.1 micron.
4. The method of any one of claims 1-3, wherein each soaking and film hardening process comprises:
soaking the photoresist mask pattern by using deionized water;
and spin-drying the soaked photoresist mask pattern, and hardening the photoresist in an oven filled with nitrogen to cure the photoresist.
5. The method as claimed in claim 4, wherein the soaking time is 50-70s, the spin-drying speed is 600-1000 rpm, the temperature in the oven for the film-hardening treatment is 100-120 ℃, and the time for the film-hardening treatment is 120-180 s.
6. The method as claimed in claim 1, wherein the forming a photoresist mask pattern on the surface of the wafer deposited with the oxide layer by using a photolithography process comprises:
spraying a tackifier on the surface of the oxide layer;
coating photoresist on the surface of the oxide layer sprayed with the tackifier;
after exposing, developing and cleaning the wafer coated with the photoresist, a photoresist mask pattern is formed.
7. The method of claim 6, wherein coating a photoresist on the surface of the oxide layer after spraying the adhesion promoter comprises:
rotationally coating photoresist on the surface of the oxide layer sprayed with the tackifier by using a full-automatic gluing and developing machine;
baking the wafer coated with the photoresist according to a preset environment temperature and baking time to enable the viscous photoresist to be changed into a solid state;
the thickness of the coating photoresist is 1.7-1.9 microns, and the uniformity of the photoresist thickness is not more than 1%;
the baking environment temperature is 120 ℃, and the baking time is 120-150 s.
8. The method as claimed in claim 6, wherein the exposure light intensity is in the range of 680-750mW/cm2, the exposure dose is 315ms ± 5ms, the focal length of the exposure is in the range of 0.2-0.4, and the uniformity of the exposure light intensity is not more than 2%.
9. The method of claim 6, wherein forming a photoresist mask pattern after exposing, developing and cleaning the photoresist-coated wafer comprises:
emitting ultraviolet rays by adopting a scanning stepping exposure machine, and exposing the wafer coated with the photoresist;
developing the exposed surface of the wafer by using a full-automatic glue spreading and developing machine to dissolve the photoresist in the exposure area;
and cleaning the surface of the wafer by using a cleaning solution, removing the photoresist which is dissolved and denatured in the exposure area, and drying the wafer by spinning to form a photoresist mask pattern.
10. The method of claim 1, wherein prior to depositing the oxide layer on the wafer surface, further comprising:
and rinsing the wafer by using deionized water, and then rinsing the surface of the wafer by using DHF cleaning solution.
11. The method of claim 1, wherein etching the oxide layer at the bottom of the photoresist mask pattern using a dry etching process comprises:
and etching the oxide layer by adopting plasma, and converting the array type round hole patterns on the photoresist mask to the oxide layer.
12. The method according to claim 1, wherein after the etching the oxide layer at the bottom of the photoresist mask pattern by the dry etching process, the method further comprises:
and removing the photoresist remained on the surface of the silicon oxide after the dry etching by adopting a cleaning process.
13. The method of claim 1, wherein depositing an oxide layer on the wafer surface comprises:
and depositing an oxide layer on the surface of the wafer by adopting PECVD equipment or furnace tube oxidation, wherein the thickness of the oxide layer is 1.6-2.5 microns, and the uniformity requirement of the oxide layer is not more than 1%.
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