CN114639349A

CN114639349A - Display control module and display device

Info

Publication number: CN114639349A
Application number: CN202210300591.9A
Authority: CN
Inventors: 王中杰
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-03-24
Filing date: 2022-03-24
Publication date: 2022-06-17
Anticipated expiration: 2042-03-24
Also published as: CN114639349B

Abstract

The invention provides a display control module and a display device. The display module comprises a display panel and N data drivers; n is an integer greater than 1; the display control module comprises a failure detection circuit and a display control circuit; the failure detection circuit judges whether the driving unit fails or not according to the driving signal output by the last stage of driving circuit; the display control circuit is used for controlling the failed data driver to output preset data voltage when the state indication signal provided by the data driver indicates that the data driver fails, so that a display area corresponding to the failed data driver displays a black picture, and controlling the failed drive unit to stop outputting the drive signal when the judgment result indicates that the drive unit fails. When a part of data drivers and/or a part of driving units included in the display control module and the display device fail, corresponding pictures can be displayed in display areas corresponding to the non-failed data drivers and the non-failed driving units.

Description

Display control module and display device

Technical Field

The invention relates to the technical field of display, in particular to a display control module and a display device.

Background

In the related art, a middle-sized OLED (organic light emitting diode) display module mostly adopts a data driving manner in which a plurality of data drivers are arranged side by side and a driving manner of Gate On Array (GOA, Array substrate row driving). The related display device may have a problem that it cannot correctly display a picture when a portion of the data driver and/or a portion of the driving unit included therein fail.

Disclosure of Invention

The main object of the present invention is to provide a display control module and a display device, which can not display the picture correctly when a part of the data driver and/or a part of the driving unit included therein fails.

In order to achieve the above object, an embodiment of the present invention provides a display control module applied to a display module, where the display module includes a display panel and N data drivers; the display panel comprises a plurality of rows and a plurality of columns of pixel circuits and M driving units; the driving unit includes a multi-stage driving circuit; n and M are integers greater than 1; the nth data driver is used for providing data voltages for pixel circuits in an nth longitudinal display area of the display panel, and the mth driving unit is used for providing driving signals for pixel circuits in an mth transverse display area of the display panel; n is a positive integer less than or equal to N, and M is a positive integer less than or equal to M; the display control module comprises a failure detection circuit and a display control circuit;

the failure detection circuit is respectively electrically connected with a driving signal output end of a last stage driving circuit included in the driving unit and the display control circuit, and is used for judging whether the driving unit fails according to a driving signal output by the last stage driving circuit and providing a judgment result to the display control circuit;

the display control circuit is respectively electrically connected with the status indication terminals of the N data drivers, and is used for receiving the status indication signals provided by the data drivers through the status indication terminals, controlling the failed data drivers to output preset data voltage when the status indication signals provided by the data drivers indicate that the data drivers fail, so that the display areas corresponding to the failed data drivers display black pictures, and controlling the failed drive units to stop outputting the drive signals when the judgment result indicates that the drive units fail.

Optionally, an overlap region is arranged between the nth longitudinal display region and the mth transverse display region;

the display control circuit is further used for providing data drive control signals to the data drivers which are not failed and providing corresponding drive timing control signals to the driving units which are not failed when part of the N data drivers fail and/or part of the M driving units fail so as to display normal pictures in a specific display area;

the specific display area is included in an unreulted display area, and the unreulted display area is a superposition area between a display area corresponding to the unreulted data driver and a display area corresponding to the unreulted driving unit.

Optionally, the display control circuit is further configured to provide corresponding driving timing control signals to the M driving units and provide corresponding data driving control signals to the N data drivers, respectively, when none of the N data drivers and the M driving units fail, so as to control the display panel to display a normal picture in the effective display area.

Optionally, the mth driving unit includes an mth first driving module; the mth first driving module comprises a plurality of stages of first driving circuits; the mth first driving module is used for providing a gate driving signal for the pixel circuit in the mth transverse display area;

the display control circuit is used for generating a driving time sequence control signal; the driving timing control signal includes a first timing control signal for controlling the mth first driving module, the first timing control signal including a first output clock signal; the display control circuit is further used for providing the corresponding first output clock signal to a first driving circuit included in the mth first driving module;

the failure detection circuit comprises a first detection unit; the first detection unit comprises a first waveform intercepting circuit and a first waveform comparison circuit; the first waveform comparison circuit comprises a first output end;

the first waveform intercepting circuit is used for intercepting the waveform of a first output clock signal accessed by a last stage first driving circuit included in the mth first driving module in a first output time period and providing the waveform to a first input end of the first waveform comparing circuit;

the mth first driving module comprises a last stage first driving circuit for providing an effective gate driving signal in the first output time period;

the second input end of the first waveform comparison circuit receives a grid driving signal provided by the last stage of first driving circuit included in the mth first driving module, the first waveform comparison circuit is used for comparing the waveform of the grid driving signal in the first output time period with the waveform accessed by the first input end of the first waveform comparison circuit, when the comparison result is the same, the signal indicating that the mth first driving module does not fail is output through the first output end, and when the comparison result is different, the signal indicating that the mth first driving module fails is output through the first output end.

Optionally, the mth driving unit includes an mth second driving module; the mth second driving module comprises a plurality of stages of second driving circuits; the mth second driving module is used for providing a reset control signal for the pixel circuit in the mth transverse display area;

the driving timing control signal further comprises a second timing control signal for controlling the mth second driving module, the second timing control signal comprising a second output clock signal; the display control circuit is further used for providing the corresponding second output clock signal to a second driving circuit included in the mth second driving module;

the failure detection circuit further comprises a second detection unit; the second detection unit comprises a second waveform intercepting circuit and a second waveform comparison circuit; the second waveform comparison circuit comprises a second output end;

the second waveform intercepting circuit is used for intercepting the waveform of a second output clock signal accessed by the last stage second driving circuit included in the mth second driving module in a second output time period and providing the waveform to the first input end of the second waveform comparing circuit;

the m second driving module comprises a last stage second driving circuit for providing an effective reset control signal in the second output time period;

the second waveform comparison circuit is used for comparing the waveform of the second output time period with the waveform accessed by the second input end of the second waveform comparison circuit, when the comparison result is the same, the second output end outputs a signal indicating that the mth second driving module does not fail, and when the comparison result is different, the second output end outputs a signal indicating that the mth second driving module fails.

Optionally, the mth driving unit includes an mth third driving module; the mth third driving module comprises a plurality of stages of third driving circuits; the mth third driving module is used for providing a light-emitting control signal for the pixel circuit in the mth transverse display area;

the driving timing control signal further includes a third timing control signal for controlling the mth third driving module, the third timing control signal including a third start signal; the display control circuit is further used for providing the third starting signal to the input end of the first-stage third driving circuit in the mth third driving module;

the failure detection circuit further comprises a third detection unit; the third detection unit comprises a waveform delay circuit, a waveform delay circuit and a third waveform comparison circuit; the third waveform comparison circuit comprises a third output end;

the waveform delay circuit is used for delaying the third initial signal for a preset time to obtain a delayed initial signal;

the third waveform comparison circuit is used for comparing the waveform of the light-emitting control signal provided by the last stage of third driving circuit in the mth third driving module with the waveform of the delay starting signal, outputting a signal indicating that the mth third driving module does not fail through the third output end when the comparison result is the same, and outputting a signal indicating that the mth third driving module fails through the third output end when the comparison result is different.

the failure detection circuit further comprises a third detection unit; the third detection unit comprises a waveform delay circuit and a third waveform comparison circuit; the third waveform comparison circuit comprises a third output end; the display panel comprises an effective display area and a blank area, and the data driver is arranged at a first side edge of the display panel; the blank area is positioned at one side of the effective display area close to the data driver; the display panel further comprises a virtual third driving module arranged in the blank area, and the virtual third driving module comprises at least one level of virtual third driving circuit; the virtual third driving circuit is used for providing a corresponding virtual light-emitting control signal; when M is smaller than M, the waveform delay circuit is used for delaying the third initial signal for a first preset time to obtain a first delayed initial signal; the third waveform comparison circuit is configured to compare a waveform of a light emission control signal provided by a last stage third driving circuit in the mth third driving module with a waveform of the first delay start signal, output a signal indicating that the mth third driving module is not failed through the third output terminal when a comparison result is the same, and output a signal indicating that the mth third driving module is failed through the third output terminal when the comparison result is different;

when M is equal to M, the waveform delay circuit is used for delaying the third initial signal for a second preset time to obtain a second delayed initial signal; the third waveform comparison circuit is used for comparing a virtual light-emitting control signal provided by a last-stage virtual third driving circuit included by the virtual third driving module with the second delay starting signal, and when the comparison result is the same, the third output end outputs a signal indicating that the mth third driving module is not failed, and when the comparison result is different, the third output end outputs a signal indicating that the mth third driving module is failed.

Optionally, the failure detection circuit further includes an indication signal output unit;

the indication signal output unit is electrically connected with the first output end, the second output end and the third output end respectively, and is used for outputting a signal indicating that the mth first driving module fails through the first output end when the first waveform comparison circuit outputs the signal indicating that the mth second driving module fails through the first output end, and/or outputting a signal indicating that the mth second driving module fails through the second output end when the second waveform comparison circuit outputs the signal indicating that the mth second driving module fails; and/or when the third waveform comparison circuit outputs a signal indicating that the mth third driving module fails through the third output end, the indication signal output unit outputs a signal indicating that the mth driving module fails, and is used for outputting a signal indicating that the mth first driving module does not fail through the first output end when the first waveform comparison circuit outputs a signal indicating that the mth first driving module does not fail through the first output end, outputting a signal indicating that the mth second driving module does not fail through the second output end when the third waveform comparison circuit outputs a signal indicating that the mth third driving module does not fail through the third output end, and outputting a signal indicating that the mth driving module does not fail through the indication signal output unit.

Optionally, the display panel includes two mth driving units; the first mth driving unit is arranged at the second side edge of the display panel, the second mth driving unit is arranged at the third side edge of the display panel, and the second side edge and the third side edge are opposite side edges;

the failure detection circuit is used for detecting whether the first mth drive unit fails or not and detecting whether the second mth drive unit fails or not.

Optionally, the display control circuit is further configured to detect and record a failure reason when the determination result indicates that the driving unit fails, and provide the failure reason to an external controller.

The embodiment of the invention also provides a display device which comprises the display control module.

The display control module and the display device according to the embodiments of the present invention can still display a corresponding picture in a display area corresponding to an ineffectiveness data driver and an ineffectiveness driving unit when a part of data drivers and/or a part of driving units included in the display control module and/or the display device fail.

Drawings

FIG. 1 is a block diagram of a display control module according to at least one embodiment of the present disclosure;

FIG. 2 is a block diagram of a display control module according to at least one embodiment of the present disclosure;

FIG. 3 is a block diagram of a display control module according to at least one embodiment of the invention;

FIG. 4 is a block diagram of a display control module according to at least one embodiment of the invention;

FIG. 5 is a circuit diagram of at least one embodiment of a first detection unit included in a failure detection circuit included in the display control module according to the present invention;

FIG. 6 is a timing diagram illustrating operation of at least one embodiment of the first detection unit;

FIG. 7 is a circuit diagram of at least one embodiment of a second detection unit included in a failure detection circuit included in the display control module according to the present invention;

FIG. 8 is a timing diagram illustrating operation of at least one embodiment of the second detection unit;

FIG. 9 is a circuit diagram of at least one embodiment of a third detecting unit included in the failure detecting circuit included in the display control module according to the present invention;

FIG. 10 is a block diagram of a display control module in accordance with at least one embodiment of the present disclosure;

FIG. 11 is a circuit diagram of at least one embodiment of a failure detection circuit included in the display control module according to the present invention;

FIG. 12 is a circuit diagram of at least one embodiment of a failure detection circuit included in the display control module according to the present invention;

fig. 13 is a structural diagram of a display control module according to at least one embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

The display control module is applied to a display module, and the display module comprises a display panel and N data drivers; the display panel comprises a plurality of rows and a plurality of columns of pixel circuits and M driving units; the driving unit includes a multi-stage driving circuit; n and M are integers greater than 1; the nth data driver is used for providing data voltage for pixel circuits in an nth longitudinal display area of the display panel, and the mth driving unit is used for providing driving signals for pixel circuits in an mth transverse display area of the display panel; n is a positive integer less than or equal to N, and M is a positive integer less than or equal to M; the display control module comprises a failure detection circuit and a display control circuit;

The display module applied to the display control module comprises a display panel and N data drivers, wherein the display panel comprises M driving units, and the display control module comprises a failure detection circuit and a display control circuit; the failure detection circuit is used for judging whether the driving unit fails or not, the display control circuit receives a state indicating signal provided by the data driver, controls a display area corresponding to the failed data driver to display a black picture when the state indicating signal indicates that the data driver fails, and controls the failed driving unit to stop outputting the driving signal when the judging result indicates that the driving unit fails; so that the display regions corresponding to the failed driving units and the failed data drivers stop displaying the normal screen, and the display regions corresponding to the non-failed driving units and the non-failed data drivers display the normal screen.

In a specific implementation, the second side may be a left side, and the third side may be a right side, but not limited thereto.

In at least one embodiment of the present invention, M is equal to 2, and N is equal to 4. In practice, M and N may be integers greater than 1.

As shown in fig. 1, the display control module according to the embodiment of the present invention is applied to a display module, where the display module includes a display panel P0, a first data driver SDIC1, a second data driver SDIC2, a third data driver SDIC3, and a fourth data driver SDIC 4; the display panel comprises a plurality of rows and columns of pixel circuits (not shown in fig. 1), a first driving unit GOA11, a second first driving unit GOA12, a first second driving unit GOA21 and a second driving unit GOA 22;

the first data driver SDIC1, the second data driver SDIC2, the third data driver SDIC3 and the fourth data driver SDIC4 are disposed at a lower side of the display panel P0;

the first driving unit GOA11 comprises a multi-level driving circuit, the second first driving unit GOA12 comprises a multi-level driving circuit, the first second driving unit GOA21 comprises a multi-level driving circuit, and the second driving unit GOA22 comprises a multi-level driving circuit;

the first driving unit GOA11 and the first second driving unit GOA21 are disposed at the left side of the display panel P0; the first second driving unit GOA21 and the second driving unit GOA22 are disposed at the right side of the display panel P0;

the first driving unit GOA11 and the second first driving unit GOA12 are used for providing driving signals for pixel circuits in a first transverse display area of the display panel;

the second first driving unit GOA21 and the second driving unit GOA22 are used for providing driving signals for pixel circuits in a second horizontal display area of the display panel;

the first data driver SDIC1 is used for providing data voltages for the pixel circuits in the first vertical display area of the display panel;

the second data driver SDIC2 is used for providing data voltages for the pixel circuits in the second vertical display area of the display panel;

the third data driver SDIC3 is used to provide data voltages to the pixel circuits in the third vertical display area of the display panel;

the fourth data driver SDIC4 is configured to provide data voltages to the pixel circuits in the fourth vertical display area of the display panel;

as shown in fig. 1, the display control module according to at least one embodiment of the present invention includes a failure detection circuit 11 and a display control circuit 12;

the failure detection circuit 11 is electrically connected to the driving signal output terminal of the last driving circuit included in the first driving unit GOA11, the driving signal output terminal of the last driving circuit included in the second first driving unit GOA12, the driving signal output terminal of the last driving circuit included in the first second driving unit GOA21, the driving signal output terminal of the last driving circuit included in the second driving unit GOA22, and the display driving circuit 12, and is configured to determine whether the first driving unit GOA11 fails according to the driving signal output by the last driving circuit included in the first driving unit GOA11, determine whether the second first driving unit GOA12 fails according to the driving signal output by the last driving circuit included in the second first driving unit GOA12, judging whether the second first driving unit GOA21 fails according to a driving signal output by a last-stage driving circuit included in the first second driving unit GOA21, judging whether the second driving unit GOA22 fails according to a driving signal output by a last-stage driving circuit included in the second driving unit GOA22, and providing a judgment result to the display control circuit;

the display control circuit 12 is electrically connected to a status indication terminal of the first data driver SDIC1, a status indication terminal of the second data driver SDIC2, a status indication terminal of the third data driver SDIC3, and a status indication terminal of the fourth data driver SDIC4, respectively, and is configured to receive a status indication signal provided by the status indication terminal of the first data driver SDIC1, control the first data driver SDIC1 to output a preset data voltage when the status indication signal provided by the first data driver SDIC1 indicates that the first data driver SDIC1 fails, so that a black screen is displayed in the first vertical display region, and receive a status indication signal provided by the status indication terminal of the second data driver SDIC2, and when the status indication signal provided by the second data driver SDIC2 indicates that the second data driver SDIC2 fails, controlling the second data driver SDIC2 to output a preset data voltage to display a black screen with the second vertical display area, and to receive a status indication signal provided by the third data driver SDIC3 through a status indication terminal thereof, and when the status indication signal provided by the third data driver SDIC3 indicates that the third data driver SDIC3 fails, controlling the third data driver SDIC3 to output the preset data voltage to display a black screen with the third vertical display area, and to receive a status indication signal provided by the fourth data driver SDIC4 through a status indication terminal thereof, and when the status indication signal provided by the fourth data driver SDIC4 indicates that the fourth data driver SDIC4 fails, controlling the fourth data driver SDIC4 to output the preset data voltage to display a black screen with the fourth vertical display area;

the display control circuit 12 is further electrically connected to the first driving unit GOA11, the second first driving unit GOA12, the first second driving unit GOA21 and the second driving unit GOA22, and is configured to control the first driving unit GOA11 to stop outputting the driving signal when the determination result indicates that the first driving unit GOA11 fails, control the first second driving unit GOA12 to stop outputting the driving signal when the determination result indicates that the second first driving unit GOA12 fails, control the first second driving unit GOA21 to stop outputting the driving signal when the determination result indicates that the first second driving unit GOA21 fails, and control the second driving unit GOA22 to stop outputting the driving signal when the determination result indicates that the second driving unit GOA22 fails.

In at least one embodiment of the present invention, when the display control circuit 12 determines that the first driving unit GOA11 and/or the second first driving unit GOA12 fails, the first driving unit GOA11 and the second first driving unit GOA12 are both controlled to stop outputting driving signals;

when the display control circuit 12 determines that the first second driving unit GOA21 and/or the second driving unit GOA22 fail, controlling both the first second driving unit GOA21 and the second driving unit GOA22 to stop outputting driving signals;

but not limited thereto.

As shown in fig. 2, reference numeral a11 is a first landscape display area, and reference numeral a12 is a second landscape display area.

As shown in fig. 3, a first vertical display region is denoted by reference numeral a21, a second vertical display region is denoted by reference numeral a22, a third vertical display region is denoted by reference numeral a23, and a fourth vertical display region is denoted by reference numeral a 24.

In fig. 2 and 3, reference numeral a0 denotes an effective display area of the display panel.

In at least one embodiment of the present invention, there is an overlap region between the nth longitudinal display region and the mth transverse display region;

In a specific implementation, when a part of the N data drivers fails, and/or a part of the M driving units fails, the display control circuit controls a specific display area included in a non-failed display area to display a normal picture.

For example, when the GOA21 and/or the GOA22 fails, and/or the SDIC3 and/or the SDIC4 fails, the display control circuit may control to display a normal screen in the first display area; wherein,

as shown in fig. 4, the first display area a1 may be a first landscape display area, and an overlapping area between left half screen display areas;

the first horizontal display area may be an upper half screen display area, and the second horizontal display area may be a lower half screen display area;

the left half screen display area may include a first portrait display area and a second portrait display area;

the right half screen display area may include a third portrait display area and a fourth portrait display area.

As shown in fig. 4, reference numeral a2 is a second display region, reference numeral A3 is a third display region, and reference numeral a4 is a fourth display region;

the second display region a2 may be a coinciding region between the first landscape display region and the right half-screen display region; the third display area a3 may be a coinciding area between the second landscape display area and the left half-screen display area; the fourth display region a4 may be a coinciding region between the second landscape display region and the right half-screen display region.

In at least one embodiment of the present invention, the display control circuit is further configured to provide corresponding driving timing control signals to the M driving units and provide corresponding data driving control signals to the N data drivers to control the display of a normal picture in the effective display area of the display panel when none of the N data drivers and the M driving units fails.

In specific implementation, when none of the N data drivers and the M driving units fails, the display control circuit controls to display a normal picture in an effective display area of the display panel.

the failure detection circuit comprises a first detection unit; the first detection unit comprises a first waveform intercepting circuit and a first waveform comparing circuit; the first waveform comparison circuit comprises a first output end;

the second input end of the first waveform comparison circuit receives a grid driving signal provided by the last-stage first driving circuit included by the mth first driving module, the first waveform comparison circuit is used for comparing the waveform of the grid driving signal in the first output time period with the waveform accessed by the first input end of the first waveform comparison circuit, when the comparison result is the same, the mth first driving module is not failed, and when the comparison result is different, the mth first driving module is failed.

In at least one embodiment of the present invention, the first driving circuit includes a gate driving signal output transistor having a first pole connected to the first output clock signal, a gate electrically connected to the first pull-up node, and a second pole electrically connected to the corresponding gate driving signal output terminal.

In a specific implementation, the mth driving unit may include an mth first driving module, and the mth first driving module may be a gate driving module that provides a gate driving signal;

the display control circuit is used for generating a first timing control signal for controlling the mth first driving module, wherein the first timing control signal may comprise a first output clock signal;

the failure detection circuit may include a first detection unit, and the first detection unit may include a first waveform interception circuit and a first waveform comparison circuit; the first waveform intercepting circuit intercepts the waveform of a first output clock signal accessed by a last stage first driving circuit included in the mth first driving module in a first output time period, and a first waveform comparison circuit compares the waveform of the first output clock signal output by the last stage first driving circuit included in the mth first driving module in the first output time period, and the waveform of the first output clock signal in the first output time period is the same as the comparison result, and the first output end outputs a signal indicating that the mth first driving module does not fail, and when the comparison result is different, the first output end outputs a signal indicating that the mth first driving module fails.

In a specific implementation, the first timing control signal may further include a first start signal, and an input end of the first stage first driving circuit in the mth first driving module is connected to the first start signal.

At least one embodiment of the failure detection circuit may include a first detection unit; as shown in fig. 5, the first detecting unit may include a first waveform intercepting circuit 51 and a first waveform comparing circuit 52;

an input end of the first waveform intercepting circuit 51 receives a first output clock signal CLKO1 accessed by a last stage first driving circuit included in the mth first driving module;

the first waveform intercepting circuit 51 is configured to intercept a waveform of a first output clock signal CLKO1 accessed by a last stage of first driving circuit included in the mth first driving module in a first output time period, and provide the waveform to a first input terminal of the first waveform comparing circuit 52;

a second input terminal of the first waveform comparison circuit 52 receives a gate driving signal GOUT provided by a last stage first driving circuit included in the mth first driving module;

the first waveform comparison circuit 52 is configured to compare a waveform of the first output clock signal CLKO1 in a first output time period with a waveform of the GOUT in the first output time period, and output a signal indicating that the mth first driving module is not disabled through the first output terminal O1 when the comparison result is the same, and output a signal indicating that the mth first driving module is disabled through the first output terminal O1 when the comparison result is different;

the signal indicating that the mth first driving module is not failed may be a high voltage signal, and the signal indicating that the mth first driving module is not failed may be a low voltage signal.

In fig. 6, reference numeral CLKO1 is a first output clock signal, reference numeral CLKC1 is a first control clock signal (CLKC1 is a control clock signal supplied to the last stage first driving circuit included in the mth first driving module), reference numeral GOUT is a gate driving signal supplied to the last stage first driving circuit included in the mth first driving module, reference numeral STV1 is a first start signal supplied to the mth first driving module, and reference numeral SO1 is a first output period.

As shown in fig. 6, in the first output period SO1, the waveform of GOUT is the same as that of CLKO1, and the mth first driving module does not fail.

As shown in fig. 6, the phase difference between CLKO1 and CLKC1 is 1H, and 1H may be one line time.

the driving timing control signal includes a second timing control signal for controlling the mth second driving module, the second timing control signal including a second output clock signal; the display control circuit is further used for providing the corresponding second output clock signal to a second driving circuit included in the mth second driving module;

In at least one embodiment of the present invention, the second driving circuit includes a reset control signal output transistor having a first pole connected to the second output clock signal, a gate electrically connected to the second pull-up node, and a second pole electrically connected to the corresponding reset control signal output terminal.

In a specific implementation, the second timing control signal may further include a second start signal, and an input end of a first-stage second driving circuit in the mth second driving module is connected to the second start signal.

In a specific implementation, the mth driving unit may include an mth second driving module, and the mth second driving module may be a reset control module that provides a reset control signal;

the display control circuit is configured to generate a second timing control signal for controlling the mth second driving module, where the second timing control signal may include a second output clock signal;

the failure detection circuit may include a second detection unit, and the second detection unit may include a second waveform interception circuit and a second waveform comparison circuit; the second waveform intercepting circuit intercepts the waveform of a second output clock signal accessed by a last-stage second driving circuit included by the mth second driving module in a second output time period, and the second waveform comparing circuit compares the waveform of the second output clock signal output by the last-stage second driving circuit included by the mth second driving module in the second output time period, and the waveform of the second output clock signal in the second output time period is the same as the comparison result, and the second output end outputs a signal indicating that the mth second driving module does not fail, and when the comparison result is different, the second output end outputs a signal indicating that the mth second driving module fails.

At least one embodiment of the failure detection circuit may include a second detection unit; as shown in fig. 7, the second detecting unit may include a second waveform intercepting circuit 71 and a second waveform comparing circuit 72;

an input end of the second waveform intercepting circuit 71 receives a second output clock signal CLKO2 accessed by a last stage second driving circuit included in the mth second driving module;

the second waveform intercepting circuit 71 is configured to intercept a waveform of the second output clock signal CLKO2 accessed by the last stage of second driving circuit included in the mth second driving module in a second output time period, and provide the waveform to a first input terminal of the second waveform comparing circuit 72;

a second input end of the second waveform comparison circuit 72 receives a reset control signal ROUT provided by a last stage second driving circuit included in the mth second driving module;

the second waveform comparison circuit 72 is configured to compare a waveform of the second output clock signal CLKO2 in a second output time period with a waveform of the ROUT in the second output time period, and output a signal indicating that the mth second driving module is not disabled through the second output terminal O2 when the comparison result is the same, and output a signal indicating that the mth second driving module is disabled through the second output terminal O2 when the comparison result is different;

the signal indicating that the mth second driving module is not failed may be a high voltage signal, and the signal indicating that the mth second driving module is not failed may be a low voltage signal.

In fig. 8, reference numeral CLKO2 is a second output clock signal, reference numeral CLKC2 is a second control clock signal (CLKC2 is a control clock signal supplied to the last stage second driving circuit included in the mth second driving module), reference numeral ROUT is a reset control signal supplied to the last stage second driving circuit included in the mth second driving module, reference numeral STV2 is a second start signal supplied to the mth second driving module, and reference numeral SO2 is a second output period.

As shown in fig. 8, in the second output period SO2, the waveform of ROUT is the same as that of CLKO2, and the mth second driving module does not fail.

As shown in fig. 8, the phase difference between CLKO2 and CLKC2 is 1H, and 1H may be one line time.

the driving timing control signal may further include a third timing control signal for controlling the mth third driving module, the third timing control signal including a third start signal; the display control circuit is further used for providing the third starting signal to the input end of the first-stage third driving circuit in the mth third driving module;

the third waveform comparison circuit is used for comparing the waveform of the light-emitting control signal provided by the last stage third driving circuit in the mth third driving module with the waveform of the delay starting signal, when the comparison result is the same, the mth third driving module is not failed, and when the comparison result is different, the mth third driving module is failed, and the mth third driving module is failed.

In at least one embodiment of the present invention, when the mth third driving module includes an a-stage third driving circuit, the predetermined delay time may be an a-line scanning time.

Wherein a may be an integer greater than 1.

In a specific implementation, the mth third driving module may be a light-emitting control circuit for providing a light-emitting control signal;

the failure detection circuit further comprises a third detection unit; as shown in fig. 9, the third detecting unit may include a waveform delay circuit 91, a waveform delay circuit and a third waveform comparison circuit 92; the third waveform comparison circuit 92 includes a third output terminal O3;

the waveform delay circuit 91 is configured to delay the third start signal STV3 for a predetermined time to obtain a delayed start signal, and provide the delayed start signal to the first input end of the third waveform comparison circuit 92;

the second input end of the third waveform comparison circuit 92 is connected to the light-emitting control signal EMOUT provided by the last stage of third driving circuit in the mth third driving module, the third waveform comparison circuit 92 is configured to compare the waveform of the light-emitting control signal provided by the last stage of third driving circuit in the mth third driving module with the waveform of the delay start signal, and when the comparison result is the same, the signal indicating that the mth third driving module is not failed is output through the third output end O3, and when the comparison result is different, the signal indicating that the mth third driving module is failed is output through the third output end O3.

In at least one embodiment of the present invention, the signal indicating that the mth third driving module is not failed may be a high voltage signal, and the signal indicating that the mth third driving module is not failed may be a low voltage signal.

the failure detection circuit further comprises a third detection unit; the third detection unit comprises a waveform delay circuit and a third waveform comparison circuit; the third waveform comparison circuit comprises a third output end; the display panel comprises an effective display area and a blank area, and the data driver is arranged on a first side edge of the display panel; the blank area is positioned at one side of the effective display area close to the data driver; the display panel also comprises a virtual third driving module arranged in the blank area, and the virtual third driving module comprises at least one level of virtual third driving circuit; the virtual third driving circuit is used for providing a corresponding virtual light-emitting control signal;

when M is smaller than M, the waveform delay circuit is used for delaying the third initial signal for a first preset time to obtain a first delayed initial signal; the third waveform comparison circuit is configured to compare a waveform of a light emission control signal provided by a last stage third driving circuit in the mth third driving module with a waveform of the first delay start signal, output a signal indicating that the mth third driving module is not failed through the third output terminal when a comparison result is the same, and output a signal indicating that the mth third driving module is failed through the third output terminal when the comparison result is different;

when M is equal to M, the waveform delay circuit is configured to delay the third start signal by a second predetermined time to obtain a second delayed start signal; the third waveform comparison circuit is used for comparing a virtual light-emitting control signal provided by a last-stage virtual third driving circuit included by the virtual third driving module with the second delay starting signal, and when the comparison result is the same, the third output end outputs a signal indicating that the mth third driving module is not failed, and when the comparison result is different, the third output end outputs a signal indicating that the mth third driving module is failed.

In at least one embodiment of the present invention, the first side edge may be a lower side edge, but is not limited thereto.

In at least one embodiment of the present invention, a dummy pixel circuit may be disposed in the blank area, but not limited thereto.

In at least one embodiment of the invention, the number of stages of the virtual third driving circuit included in the virtual third driving module may be less, for example, the number of stages may be three stages or four stages, but is not limited thereto.

In at least one embodiment of the present invention, the light emitting control signal provided by the last stage third driving circuit in the mth third driving module may be used as a start signal of the first stage virtual third driving circuit included in the virtual third driving module.

As shown in fig. 10, reference numeral a0 is an effective display area of the display panel, and reference numeral AB1 is a blank area of the display panel; the blank area AB1 is disposed between the effective display area A0 and each data driver disposed at the lower side of the display panel;

in fig. 10, reference numeral SDIC1 is a first data driver, reference numeral SDIC2 is a second data driver, reference numeral SDIC3 is a third data driver, and reference numeral SDIC4 is a fourth data driver.

In at least one embodiment of the present invention, the display panel may further include a virtual third driving module disposed in the blank area, and the virtual third driving module may include at least one level of virtual third driving circuit;

when the virtual third driving module comprises a plurality of stages of virtual third driving circuits, the plurality of stages of virtual third driving circuits are cascaded with each other;

the structure of the dummy third driving module may be the same as that of the third driving module, and the dummy third driving module outputs a corresponding dummy emission control signal but does not supply the dummy emission control signal to a corresponding pixel circuit.

In a specific implementation, when the mth third driving module includes an a-stage third driving circuit, the first predetermined delay time may be an a-line scanning time;

when the mth third driving module includes an a-stage third driving circuit, and the virtual third driving module includes a B-stage virtual third driving circuit, the second predetermined delay time may be (a + B) line scanning time;

a may be an integer greater than 1 and B may be a positive integer.

In at least one embodiment of the present invention, the failure detection circuit further includes an indication signal output unit;

the indication signal output unit is electrically connected with the first output end, the second output end and the third output end respectively, and is used for outputting a signal indicating that the mth first driving module fails through the first output end when the first waveform comparison circuit outputs the signal indicating that the mth second driving module fails through the second output end, and/or outputting a signal indicating that the mth second driving module fails through the second output end when the second waveform comparison circuit outputs the signal indicating that the mth second driving module fails; and/or when the third waveform comparison circuit outputs a signal indicating that the mth third driving module fails through the third output terminal, the indication signal output unit outputs a signal indicating that the mth driving module fails, and is configured to output a signal indicating that the mth first driving module does not fail through the first output terminal when the first waveform comparison circuit outputs a signal indicating that the mth second driving module does not fail through the second output terminal, and output a signal indicating that the mth third driving module does not fail through the third output terminal when the third waveform comparison circuit outputs a signal indicating that the mth third driving module does not fail through the third output terminal, the indication signal output unit outputs a signal indicating that the mth driving module does not fail.

In a specific implementation, the failure detection circuit may further include an indication signal output unit, where the indication signal output unit is configured to output a signal indicating that the mth driving unit is not failed when none of the mth first driving module, the mth second driving module, and the mth third driving module is failed, and is configured to output a signal indicating that at least the mth driving unit is failed when at least one of the mth first driving module, the mth second driving module, and the mth third driving module is failed.

As shown in fig. 11, the failure detection circuit includes a first detection unit, a second detection unit, a third detection unit and an indication signal output unit 110;

as shown in fig. 11, the first detecting unit includes a first waveform intercepting circuit 51 and a first waveform comparing circuit 52;

the first waveform intercepting circuit 51 is configured to intercept a waveform of the first output clock signal CLKO1 accessed by the last stage of first driving circuit included in the mth first driving module in a first output time period, and provide the waveform to a first input terminal of the first waveform comparing circuit 52;

as shown in fig. 11, the second detecting unit includes a second waveform intercepting circuit 71 and a second waveform comparing circuit 72;

as shown in fig. 11, the third detecting unit may include a waveform delay circuit 91, a waveform delay circuit and a third waveform comparison circuit 92; the third waveform comparison circuit 92 includes a third output terminal O3;

the waveform delay circuit 91 is configured to delay the third start signal by a predetermined time to obtain a delayed start signal, and provide the delayed start signal to the first input end of the third waveform comparison circuit 92;

a second input end of the third waveform comparison circuit 92 is connected to the light-emitting control signal EMOUT provided by the last stage of third driving circuit in the mth third driving module, the third waveform comparison circuit 92 is configured to compare a waveform of the light-emitting control signal provided by the last stage of third driving circuit in the mth third driving module with a waveform of the delay start signal, when a comparison result is the same, output a signal indicating that the mth third driving module is not failed through the third output end O3, and when the comparison result is different, output a signal indicating that the mth third driving module is failed through the third output end O3;

the indication signal output unit 110 is electrically connected to the first output terminal O1, the second output terminal O2 and the third output terminal O3, respectively, and is configured to output a signal indicating that the mth first driving module fails through the first output terminal O1 when the first waveform comparison circuit 52 outputs the signal indicating that the mth second driving module fails through the second output terminal O2; and/or when the third waveform comparison circuit 92 outputs a signal indicating that the mth third driving module fails through the third output terminal O3, the indication signal output unit 110 outputs a signal indicating that the mth driving module fails, and is configured to output a signal indicating that the mth first driving module does not fail through the first output terminal O1 when the first waveform comparison circuit 52 outputs a signal indicating that the mth first driving module does not fail through the first output terminal O1, output a signal indicating that the mth second driving module does not fail through the second output terminal O2 when the third waveform comparison circuit 92 outputs a signal indicating that the mth third driving module does not fail through the third output terminal O3, and output a signal indicating that the mth driving module does not fail through the indication signal output unit 110.

Alternatively, as shown in fig. 12, the indication signal output unit may include a first and gate AG1 and a second and gate AG 2;

a first input end of the first and gate AG1 is electrically connected to the first output end O1, and a second input end of the first and gate AG1 is electrically connected to the second output end O2; the output end of the first and gate AG1 is electrically connected with the first input end of the second and gate AG 2;

a second input end of the second and gate AG2 is electrically connected to the third output end O3, and an output end of the second and gate AG2 is configured to output a signal indicating whether the mth driving unit is disabled.

In operation of at least one embodiment as shown in fig. 12, when O1 outputs a high voltage signal, it indicates that the mth first driver module has not failed; when the O1 outputs a low voltage signal, indicating that the mth first drive module is failed;

when the O2 outputs a high voltage signal, it indicates that the mth second drive module is not disabled; when the O2 outputs a low voltage signal, indicating that the mth second drive module is failed;

when O3 outputs a high voltage signal, indicating that the mth third drive module is not disabled; when the O3 outputs a low voltage signal, indicating that the mth third drive module is disabled;

when AG2 outputs a high voltage signal, it indicates that the mth drive unit is not disabled; when AG2 outputs a low voltage signal, it indicates that the mth drive unit is disabled.

In specific implementation, the display control circuit is further configured to detect and record a failure cause and provide the failure cause to an external controller when the determination result indicates that the driving unit fails.

In at least one embodiment of the present invention, the external controller may be an electronic control unit, but is not limited thereto.

In at least one embodiment of the present invention, the display control circuit may include a display controller, a level shifter and a monitor, and the display module may further include a timing controller;

the display controller and the monitor may be integrated in the timing controller, and the level shifter may be disposed outside the timing controller;

the timing controller, the level shifter and the failure detection circuit may be disposed on a circuit board.

Alternatively, the Circuit Board may be a PCBA (Printed Circuit Board Assembly), but is not limited thereto.

In actual operation, the display controller is configured to send a low swing voltage signal to the level shifter, the level shifter is configured to perform level shifting on the low swing voltage signal to obtain a high swing voltage signal, the high swing voltage signal may be the driving timing control signal, and the driving timing control signal may include an output clock signal and a start signal, but is not limited thereto.

As shown in fig. 13, the display control module according to the embodiment of the present invention may include a display control circuit and a failure detection circuit 11;

the display control circuit may include a display controller, a level shifter LVSH, and a monitor M1, and the display module may include a display panel P0, a first data driver SDIC1, a second data driver SDIC2, a third data driver SDIC3, a fourth data driver SDIC4, and a timing controller T1;

the display controller included in the display control circuit may be integrated with the timing controller T1;

the display panel comprises a plurality of rows and columns of pixel circuits, a first driving unit GOA11, a second first driving unit GOA12, a first second driving unit GOA21 and a second driving unit GOA 22;

GOA11 and GOA21 are arranged at the left side of the display panel P0, and GOA12 and GOA22 are arranged at the right side of the display panel P0;

the effective display area of the display panel P0 includes a first display area a1, a second display area a2, a third display area A3, and a fourth display area a 4;

the first display area a1 is an overlapping area of the upper half screen display area and the left half screen display area, the second display area a2 is an overlapping area of the upper half screen display area and the right half screen display area, the third display area A3 is an overlapping area of the lower half screen display area and the left half screen display area, and the fourth display area a4 is an overlapping area of the lower half screen display area and the right half screen display area;

the GOAs 11 and 12 are used to provide driving signals for the pixel circuits disposed in the first display region a1 and the second display region a 2;

the GOAs 21 and 22 are used to provide driving signals for the pixel circuits disposed in the third display area A3 and the fourth display area a 4;

a state indicating terminal of the first data driver SDIC1 and a state indicating terminal of the second data driver SDIC2 are electrically connected to a first latch terminal L1 of the timing controller TCON;

a state indicating terminal of the third data driver SDIC3 and a state indicating terminal of the fourth data driver SDIC4 are electrically connected to the second latch terminal L2 of the timing controller TCON;

a status indication terminal of the first data driver SDIC1 outputs a low voltage signal when the first data driver SDIC1 fails (e.g., a Clock embedded in an ISP (Internet service Provider) protocol cannot be recovered, etc.), and a status indication terminal of the second data driver SDIC2 outputs a low voltage signal when the second data driver SDIC2 fails; the L1 receives a low voltage signal when the first data driver SDIC1 and/or the second data driver SDIC2 fails;

a state indicating terminal of the third data driver SDIC3 outputs a low voltage signal when the third data driver SDIC3 fails, and a state indicating terminal of the fourth data driver SDIC2 outputs a low voltage signal when the fourth data driver SDIC4 fails; the L2 receives a low voltage signal when the third data driver SDIC3 and/or the fourth data driver SDIC4 fails;

when L1 receives a low voltage signal, the timing controller TCON may send a command to SDIC1 and SDIC2 by the command sender isp _ TX, so that SDIC1 and SDIC2 output a default level (e.g., a black picture data voltage);

when L2 receives a low voltage signal, the timing controller TCON may send a command to SDIC3 and SDIC4 by the command sender isp _ TX, so that SDIC3 and SDIC4 output a default level (e.g., a black picture data voltage);

the timing controller TCON is further configured to output a low swing voltage signal to the level shifter LVSH, where the level shifter LVSH converts the low swing voltage signal into a high swing voltage signal, the high swing voltage signal is the driving timing control signal, and the driving timing control signal may include a clock signal and a start signal; the level shifter LVSH provides the corresponding driving timing control signals to the GOA11, the GOA12, the GOA21, and the GOA22, respectively;

the failure detection circuit 11 receives the driving signal output by the last stage driving circuit included in GOA11, the driving signal output by the last stage driving circuit included in GOA12, the driving signal output by the last stage driving circuit included in GOA21, and the driving signal output by the last stage driving circuit included in GOA22, and determines whether GOA11, GOA12, GOA21, and GOA22 fail according to the driving signals, and transmits a signal indicating whether GOA11 fails, a signal indicating whether GOA12 fails, a signal indicating whether GOA21 fails, and a signal indicating whether GOA22 fails to the timing controller TCON;

when the timing controller TCON receives a signal indicating a failure of GOA11 and/or a signal indicating a failure of GOA12, the timing controller TCON stops providing the corresponding driving timing control signals to GOAs 11 and 12 through the level shifter LVSH;

when the timing controller TCON receives a signal indicating a failure of GOA21 and/or a signal indicating a failure of GOA22, the timing controller TCON stops providing the corresponding driving timing control signals to GOAs 21 and 22 through the level shifter LVSH;

when the timing controller TCON receives a signal indicating that GOA11 does not fail and a signal indicating that GOA12 does not fail, and the timing controller TCON receives a signal indicating that GOA21 fails and/or a signal indicating that GOA22 does not fail, L1 receives a high-voltage signal, and L2 receives a low-voltage signal, the timing controller TCON controls a picture to be displayed in a first display area A1, and reduces the size of 100% to the size of 25% for vehicle-mounted emergency danger-avoiding display;

the timing controller TCON is further configured to generate display data and control commands;

the monitor M1 is configured to receive a signal indicating whether the GOA11 is disabled, a signal indicating whether the GOA12 is disabled, and a signal indicating whether the GOA21 is disabled, perform processing such as sorting, recording, and encoding, detect a failure cause of the display module, such as PMIC (power management integrated circuit), a high-speed signal, CRC (cyclic redundancy check), and transmit the failure cause to the electronic control unit ECU on the vehicle side through an I2C interface (bidirectional two-wire system synchronous serial bus interface), where the electronic control unit ECU may feed the failure cause back to the manufacturer.

In at least one embodiment of the display control module shown in fig. 13, the TCON, LVSH and failure detection circuit 11 may be disposed on the printed circuit board P1.

In at least one embodiment of the present invention, the display module may be a vehicle-mounted display module, but not limited thereto.

In the related art, the vehicle-mounted display module has a risk of failure of a certain data driver or a certain driving unit due to a harsh use environment (such as severe vibration, wide amplitude, high temperature and low temperature, and the like). Under the situation, full-screen display is abnormal, and important information such as button positions, navigation routes and the like is incomplete, so that driving safety and driving experience are seriously influenced. According to the embodiment of the invention, when a certain data driver and/or a certain driving unit of the vehicle-mounted display module fails, corresponding pictures can be displayed in the display areas corresponding to the non-failed data driver and the non-failed driving unit, so that the emergency risk avoiding effect is achieved.

The display device comprises a display module and the display control module;

the display module is electrically connected with the display control module.

The display device provided by the embodiment of the invention can be any product or part with a display function, such as a vehicle-mounted display device, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display control module is applied to a display module, and the display module comprises a display panel and N data drivers; the display panel comprises a plurality of rows and a plurality of columns of pixel circuits and M driving units; the driving unit includes a multi-stage driving circuit; n and M are integers greater than 1; the nth data driver is used for providing data voltages for pixel circuits in an nth longitudinal display area of the display panel, and the mth driving unit is used for providing driving signals for pixel circuits in an mth transverse display area of the display panel; n is a positive integer less than or equal to N, and M is a positive integer less than or equal to M; the display control module is characterized by comprising a failure detection circuit and a display control circuit;

2. The display control module according to claim 1, wherein there is an overlapping area between the nth vertical display area and the mth horizontal display area;

3. The display control module of claim 2, wherein the display control circuit is further configured to provide corresponding driving timing control signals to the M driving units and provide corresponding data driving control signals to the N data drivers, respectively, when none of the N data drivers and the M driving units are disabled, so as to control the display of a normal picture in the effective display area of the display panel.

4. The display control module of claim 1, wherein the mth driving unit includes an mth first driving module; the mth first driving module comprises a plurality of stages of first driving circuits; the mth first driving module is used for providing a gate driving signal for the pixel circuit in the mth transverse display area;

5. The display control module of claim 4, characterized in that the mth driving unit includes an mth second driving module; the mth second driving module comprises a plurality of stages of second driving circuits; the mth second driving module is used for providing a reset control signal for the pixel circuit in the mth transverse display area;

the second waveform comparison circuit is used for comparing the waveform of the reset control signal in the second output time period with the waveform accessed by the second input end of the second waveform comparison circuit, when the comparison result is the same, the second output end outputs a signal indicating that the mth second driving module does not fail, and when the comparison result is different, the second output end outputs a signal indicating that the mth second driving module fails.

6. The display control module of claim 5, wherein the mth driving unit includes an mth third driving module; the mth third driving module comprises a plurality of stages of third driving circuits; the mth third driving module is used for providing a light-emitting control signal for the pixel circuit in the mth transverse display area;

7. The display control module of claim 5, wherein the mth driving unit includes an mth third driving module; the mth third driving module comprises a plurality of stages of third driving circuits; the mth third driving module is used for providing a light-emitting control signal for the pixel circuit in the mth transverse display area;

8. The display control module according to claim 6 or 7, wherein the failure detection circuit further comprises an indication signal output unit;

9. The display control module of claim 8, wherein the display panel comprises two mth driving units; the first mth driving unit is arranged at the second side edge of the display panel, the second mth driving unit is arranged at the third side edge of the display panel, and the second side edge and the third side edge are opposite side edges;

10. The display control module according to any one of claims 1 to 3, wherein the display control circuit is further configured to detect and record a cause of failure when the determination result indicates that the driving unit fails, and to supply the cause of failure to an external controller.

11. A display apparatus comprising the display control module according to any one of claims 1 to 10.