CN114638349A - Photosensitive neuron, sensor-memory-computing integrated intelligent perception device, method and medium - Google Patents

Abstract

The present application relates to the field of semiconductor technology, and in particular to a photosensitive neuron, a sensor-memory-computing integrated intelligent sensing device, method, and medium, wherein the photosensitive neuron includes: an avalanche detector, which is used for photon-induced avalanche detection when photons are incident. effect, output voltage pulse; the adaptive resistive memory connected in series with the avalanche detector is used to drive the conductive ions to the conductive channel to form deposition under the driving of the voltage pulse, so as to sense the light field of any signal light signal, and/or after training, to produce current pulses of maximum magnitude. Therefore, the problem of low pixel density of the sensor-memory-computing integrated architecture in the related art is solved, the pixel density of the photosensitive neuron network is greatly improved, and the size is small, the power consumption is low, and the speed is fast.

Description

Photosensitive neuron, sensor-memory-computing integrated intelligent perception device, method and medium

technical field

The present application relates to the field of semiconductor technology, and in particular, to a photosensitive neuron, a sensor-memory-computing integrated intelligent sensing device, a method, and a medium.

Background technique

At present, existing sensor-memory-computing integrated architectures include two categories: CMOS (Complementary Metal Oxide Semiconductor) architecture and resistive-variable control network architecture.

Among them, the characteristics of the CMOS architecture can be shown in Figure 1, the sensor (Sensor) and the analog signal processor (PE) are connected in series and then in parallel. The Sensor converts the optical signal into an electrical signal and transmits it to the PE. The PE performs the analog calculation on the photoelectric signal according to a certain timing sequence and instructions. The PE generally exchanges data with the adjacent PE to form a highly correlated calculation of the signals in the adjacent area, which can be completed General image processing tasks such as convolution, filtering, etc. Due to the capability of sequential operation, the calculation processing is flexible. The characteristics of the resistive control network architecture can be shown in Figure 2. The detector is combined with neural synaptic devices (such as memristors, multi-level switches, etc.), the detector is responsible for sensing, and the neural synaptic device is responsible for storage and computing. So as to realize the integrated function fusion of sensing, storage and computing. In this architecture, sometimes synaptic devices have photosensitive properties that can act as sensors at the same time. The neural synaptic device is pre-trained (electrical training) to determine the responsivity R of the photoreceptor unit, and the output current of each photoreceptor unit is equal to the product of the incident light intensity S and the responsivity R. Through the combination of connections between pixels, the output current results of non-adjacent pixels with a certain distance are superimposed according to Kirchhoff's law, and the weighted summation function of neurons is completed (for example, S ₁ -S _m is mapped by weighted summation). process to I ₁ ). On the other hand, adjacent pixels sample the same position in the light field, and it can be approximately considered that the light intensity is the same. They map light intensity to the output currents of different pathways through the above-mentioned neuron weighted summation (such as the process of S1 mapping to _{I1 - Im} through weighted summation). In this method, the size of the synaptic device is often smaller than the size of the detector, which does not affect the spatial detection efficiency.

However, for the CMOS architecture, the main problem is that the state flag area FLAG and the register REGISTERS need to register the state and data required for the calculation, and the analog arithmetic processor ALU is required to calculate the photocurrent data of adjacent pixels according to a certain algorithm weight. The hardware of ALU, FLAG and REGISTERS is relatively complex, with a large area (far exceeding the Sensor size), and the part exceeding the Sensor area cannot be photosensitive, which affects the imaging pixel density; for the resistive control network architecture, it needs to set a certain period extension Mechanism (as shown by the dashed box in Figure 2 is the minimum unit of periodic extension) to increase the number of pixels, thereby increasing the width of the neural network. Adjacent neurons can only be regarded as one pixel at the algorithm level, which greatly reduces the pixel density. On the other hand, current photosensitive neurons are usually made of memristor materials with photosensitive functions, which require stronger light or light in a special wavelength band to trigger the memristive effect.

SUMMARY OF THE INVENTION

The present application provides a light-sensitive neuron, a sensor-memory-computing integrated intelligent sensing device, method and medium, to solve the problem of low pixel density of the sensor-memory-computing integrated structure in the related art, greatly improve the photosensitive neuron network pixel density, and the size Small, low power and fast.

The embodiment of the first aspect of the present application provides a photosensitive neuron, including:

Avalanche detector (Single Photon Avalanche Diode, SPAD), which is used to output voltage pulses based on the photo-induced avalanche effect when photons are incident;

an adaptive resistive memory (ARS) connected in series with the avalanche detector, for driving the voltage pulse, the conductive ions drift to the conductive channel to form a deposition, so as to sense the optical field signal of any signal light, and / or after training, to generate current pulses of maximum amplitude.

Optionally, when no photon is incident, the conductive channel of the adaptive resistive memory is dissolved and dissipated, wherein when the deposition speed of the conductive channel is greater than the diffusion and ablation speed of the conductive channel, the adaptive resistance The variable memory enters the resistance reduction mode, the avalanche detector enters the fast charging mode, and returns to the initial state before the avalanche.

Optionally, after the photosensitive neuron releases the current pulse, the peak value of the pulse is I _peak =V _E /R _min , where V _E is the excess voltage, and R _min is the dynamic change in the resistance of the adaptive resistive memory. the lowest value in the process.

Optionally, the minimum value is determined by the incident photon frequency.

Optionally, also include:

an introduction unit for introducing electrical excitation to adjust the actual resistance value of the adaptive resistive memory and the actual current of the avalanche detector to a target resistance value and a target current based on the incident photon frequency and the electrical excitation , to achieve neuronal activity conditions.

The embodiment of the second aspect of the present application provides an intelligent sensing device integrating sensing, storage and computing, including:

A photosensitive neuron array, the photosensitive neuron array includes a plurality of the photosensitive neurons described in the embodiments of the first aspect to output current.

Optionally, also include:

The training unit is used for training the photosensitive neurons in i row and j column in the photosensitive neuron array, so as to convert the incident light intensity of the signal light into a current sensitivity coefficient, and perform the multiplication and addition operation of the neural network.

Optionally, the calculation formula of the output current is:

Among them, S _ij is the light intensity, R _ij is the sensitivity coefficient of the current, i is the number of rows, j is the number of columns, m is the maximum number of rows, and n is the maximum number of columns.

The embodiment of the third aspect of the present application provides an integrated intelligent perception method for sensing, storage and computing, using the integrated intelligent sensing device for sensing storage and computing described in the embodiment of the second aspect, and the method includes the following steps:

When a photon is incident, a voltage pulse is output based on the photo-induced avalanche effect;

Driven by the voltage pulse, the conductive ions drift to the conductive channel to form deposition, so as to sense the light field signal of any signal light, and/or after training, the current pulse with the maximum amplitude is generated.

Embodiments of the fourth aspect of the present application provide a computer-readable storage medium on which a computer program is stored, and the program is executed by a processor, so as to realize the integrated intellisense of the sensing-memory-computing described in the embodiments of the third aspect method.

Therefore, the embodiments of the present application have the following advantages:

(1) Different from the resistive control network architecture in the related art, the neural network of the embodiment of the present application does not need to set multiple photosensitive neurons in adjacent areas to increase the width of the neural network, and the width of the neural network is realized by means of timing control The photosensitive neurons are stimulated and trained according to a certain time sequence, so that their weights meet the needs of different nodes in the width direction of the neural network. By exchanging time for space, the pixel density of the photosensitive neuron network is greatly improved, with small size, low power consumption and speed. quick.

(2) Different from the CMOS architecture in the related art, the size of the computing core ARS in the neural network of the embodiment of the present application is much smaller than the size of the detector SPAD, and there is no ALU (arithmetic and logic unit, arithmetic logic unit), FLAG (EFLAGS Register) , Status Flag Register) and REGISTERS hardware structure, does not affect the imaging pixel density.

Additional aspects and advantages of the present application will be set forth, in part, in the following description, and in part will be apparent from the following description, or learned by practice of the present application.

Description of drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of an array structure in which a sensor and a processing unit are connected in series and then connected in parallel;

FIG. 2 is an example diagram of a resistive control network architecture;

3 is a block diagram of a photosensitive neuron provided according to an embodiment of the present application;

4 is a schematic structural diagram of a photosensitive neuron according to an embodiment of the present application;

5 is a schematic diagram of a three-port implementation of a photosensitive neuron according to an embodiment of the present application;

FIG. 6 is an example diagram of a sensor-memory-computing integrated intelligent perception device according to an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a sensor-memory-computing integrated intelligent perception device according to an embodiment of the present application;

FIG. 8 is a flowchart of a method for intelligent sensing with integrated storage and computing according to an embodiment of the present application.

Detailed ways

The following describes in detail the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to be used to explain the present application, but should not be construed as a limitation to the present application.

The photosensitive neuron, the sensor-memory-computing integrated intelligent perception device, the method, and the medium of the embodiments of the present application will be described below with reference to the accompanying drawings. In view of the low pixel density of the sensor-memory-computing integrated architecture mentioned by the above-mentioned background technology center, the present application provides a photosensitive neuron, which can perceive light field signals (such as imaging) in situ and calculate and process the light field signals without It is necessary to set up multiple photosensitive neurons in adjacent areas to increase the width of the neural network. The width of the neural network is realized by timing regulation. The photosensitive neurons are stimulated and trained according to a certain timing sequence, so that their weights meet the different width directions of the neural network. It can greatly improve the pixel density of the photosensitive neuron network, and has small size, low power consumption and fast speed, which solves the problem of low pixel density of the sensor-memory-computing integrated architecture in related technologies.

Specifically, FIG. 3 is a schematic diagram of a photosensitive neuron provided by an embodiment of the present application.

As shown in FIG. 3 , the photosensitive neuron 10 includes: an avalanche detector 100 and an adaptive resistive memory 200 .

Among them, the avalanche detector 100 is used to output voltage pulses based on the photo-induced avalanche effect when photons are incident; the adaptive resistive memory 200 is connected in series with the avalanche detector 100, and is used for driving the conductive ions to drift to conductive ions under the driving of the voltage pulse. The channels are deposited to sense the light field signal of either signal light, and/or after training, to generate current pulses of maximum magnitude.

Specifically, as shown in FIG. 4 , when photons are incident, a photo-induced avalanche effect occurs in the avalanche detector 100, and a voltage pulse is output to drive the conductive ions in the adaptive resistive memory 200 to drift to the conductive channel to form deposition, thereby forming deposition. The light field signal of any signal light can be sensed, or after training, the current pulse with the maximum amplitude can be generated. It should be noted that the avalanche detector 100 may be a single photon detector, which has the advantages of easy integration and high sensitivity.

Optionally, in some embodiments, when no photons are incident, the conductive channel of the adaptive resistive memory 200 dissolves and dissipates, wherein when the deposition speed of the conductive channel is greater than the diffusion and ablation speed of the conductive channel, the adaptive resistance change The memory goes into resistance reduction mode and the avalanche detector goes into fast charge mode, returning to its initial state before the avalanche.

Specifically, when no photons are incident, the voltage mainly falls on both ends of the avalanche detector 100, the conductive channel in the adaptive resistive memory 200 is continuously dissolved and dissipated, the channel deposition speed is greater than the diffusion and ablation speed, and the adaptive resistive memory 200 is continuously dissolved and dissipated. The resistance of 200 drops rapidly, and the avalanche detector 100 charges quickly, restoring the state before the avalanche.

Optionally, in some embodiments, after the photosensitive neuron releases the current pulse, the peak value of the pulse is I _peak = _VE /R _min , where _VE is the excess voltage, and R _min is the dynamic change of the resistance of the adaptive resistive memory. the lowest value in the process.

Optionally, in some embodiments, the minimum value is determined by the incident photon frequency.

Specifically, the photosensitive neuron 10 can release a current pulse, the pulse peak value I _peak =V _E /R _min , V _E is the excess voltage (constant value), and R _min is the dynamic change process of the resistance of the adaptive resistive memory 200 the lowest value. It should be noted that the value of R _min is the dynamic minimum value of the resistance of the adaptive resistive memory 200 in each avalanche process, and essentially depends on the dynamic balance result of the deposition and ablation of the conductive channel.

Optionally, in some embodiments, it further includes: an introducing unit for introducing electrical excitation, so as to adjust the actual resistance value of the adaptive resistive memory and the actual current of the avalanche detector as a target based on the incident photon frequency and the electrical excitation resistance and target current to achieve neuronal activity conditions.

It should be understood that the embodiment of the present application can be adjusted by the incident photon frequency. When the photon frequency is high, the avalanche occurrence interval is shorter, and the ratio of the deposition time to the ablation time of the conductive channel increases, and the adaptive resistive memory 200 The conduction channel is wider and the R _min is lower. On the contrary, when the incident photon frequency is small, the avalanche interval is longer, the ratio of the deposition time to the ablation time of the conductive channel decreases, the conductive channel of the adaptive resistive memory 200 is narrower, and the R _min is larger. Therefore, when the photosensitive neurons are excited by high-brightness light, the conductive activity of the adaptive resistive memory 200 is high and the resistance is small; when the photosensitive neurons are excited by low-brightness light, the conductive activity of the adaptive resistive memory 200 is low. , the resistance is large. The embodiments of the present application can use this method to train the activity of neurons.

Therefore, the photosensitive neuron 10 can store the light field information irradiated on it. When the signal light is irradiated on the trained photosensitive neuron 10, the photosensitive neuron 10 will generate a maximum amplitude value of V _E /R _min current pulse. Therefore, light-sensitive neurons are sensory-memory-integrated.

In addition, the photosensitive neuron connected in series with the avalanche detector 100 and the adaptive resistive memory 200 shown in FIG. 4 is a two-port device, and the resistance of the adaptive resistive memory 200 and the magnitude of the avalanche pulse current are dynamically adjusted by the frequency of incident photons . However, the resistance value of the adaptive resistive memory 200 can also be controlled by an electrical method. As shown in FIG. 5 , a third port C is drawn from the middle of the avalanche detector 100 and the adaptive resistive memory 200 to introduce electrical excitation (such as pulses). drive or DC drive) to change the resistance value of the adaptive resistive memory 200 .

According to the photosensitive neurons proposed in the embodiments of the present application, the light field signal (such as imaging) can be sensed in situ and the light field signal can be calculated and processed, and there is no need to set multiple photosensitive neurons in adjacent areas to increase the width of the neural network. The width of the network is realized by timing regulation. The photosensitive neurons are stimulated and trained according to a certain time sequence, so that their weights meet the needs of different nodes in the width direction of the neural network, and time is exchanged for space, which greatly improves the pixel density of the photosensitive neuron network. And the small size, low power consumption and high speed solve the problem of low pixel density of the sensor-memory-computing integrated architecture in related technologies.

Next, referring to the accompanying drawings, the intelligent sensing device device provided according to the embodiments of the present application will be described.

FIG. 6 is a schematic block diagram of an intelligent sensing device integrating sensing, storage and computing according to an embodiment of the present application.

As shown in FIG. 6 , the sensor-memory-computing integrated intelligent perception device 20 includes: a photosensitive neuron array 21 .

Wherein, the photosensitive neuron array 21 includes a plurality of photosensitive neurons as shown in the embodiment of FIG. 3 to output current.

Optionally, in some embodiments, the sensor-memory-computing-integrated intelligent perception device 20 of the embodiments of the present application further includes: a training unit. The training unit is used to train the photosensitive neurons in the i row and j columns in the photosensitive neuron array to convert the incident light intensity of the signal light into the sensitivity coefficient of the current, and perform the multiplication and addition operation of the neural network.

Specifically, as shown in FIG. 7 , in this embodiment of the present application, photosensitive neurons can be formed into an array, and each pixel point (i row and j column) in the array is composed of the photosensitive neurons shown in FIG. 4 . Through training, the photosensitive neuron in row i row j column sets the sensitivity coefficient of the incident light intensity into electric current as R _ij . In this way, when the light intensity incident on the neuron in row i row j column is S _ij , the network outputs The current is:

Among them, S _ij is the light intensity, R _ij is the sensitivity coefficient of the current, i is the number of rows, j is the number of columns, m is the maximum number of rows, and n is the maximum number of columns.

Thus, the multiplication and addition operation of the neural network is completed.

It should be noted that, the foregoing explanations of the embodiment of the photosensitive neuron are also applicable to the intelligent sensing device integrated with sensing, storage and computing in this embodiment, which will not be repeated here.

According to the intelligent sensing device integrating sensing, storage and computing proposed in the embodiment of the present application, it is not necessary to set up multiple photosensitive neurons in adjacent areas to increase the width of the neural network. The photosensitive neurons are stimulated and trained to make their weights meet the needs of different nodes in the width direction of the neural network, and the time is exchanged for space, which greatly improves the pixel density of the photosensitive neuron network, and has small size, low power consumption and fast speed. The problem of low pixel density in the integrated architecture of sensing, storage and computing in technology.

FIG. 8 is a flowchart of a method for intelligent perception integrating sensing, storage and computing according to an embodiment of the present application.

As shown in FIG. 8 , the integrated sensing-memory-computing intelligent sensing method adopts the sensing-memory-computing integrated intelligent sensing device in the embodiment of FIG. 5 , and the method includes the following steps:

S801, when photons are incident, a voltage pulse is output based on the photo-induced avalanche effect.

S802 , under the driving of the voltage pulse, the conductive ions drift to the conductive channel to form deposition, so as to sense the light field signal of any signal light, and/or after training, the current pulse with the maximum amplitude is generated.

It should be noted that the foregoing explanations on the embodiment of the integrated sensing-memory-computing intelligent sensing device are also applicable to the sensing-memory-computing integrated intelligent sensing method of this embodiment, and details are not repeated here.

According to the integrated intelligent sensing method of sensing, storage and computing proposed in the embodiment of the present application, it is not necessary to set up multiple photosensitive neurons in adjacent areas to increase the width of the neural network. The photosensitive neurons are stimulated and trained to make their weights meet the needs of different nodes in the width direction of the neural network, and the time is exchanged for space, which greatly improves the pixel density of the photosensitive neuron network, and has small size, low power consumption and fast speed. The problem of low pixel density in the integrated architecture of sensing, storage and computing in technology.

Embodiments of the present application further provide a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, implements the above-mentioned integrated sensing-memory-computing intelligent sensing method.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or N of the embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present application, "N" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

Any process or method description in the flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or N more executable instructions for implementing custom logical functions or steps of the process , and the scope of the preferred embodiments of the present application includes alternative implementations in which the functions may be performed out of the order shown or discussed, including performing the functions substantially concurrently or in the reverse order depending upon the functions involved, which should It is understood by those skilled in the art to which the embodiments of the present application belong.

The logic and/or steps represented in flowcharts or otherwise described herein, for example, may be considered an ordered listing of executable instructions for implementing the logical functions, may be embodied in any computer-readable medium, For use with, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from and execute instructions from an instruction execution system, apparatus, or apparatus) or equipment. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or apparatus. More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections (electronic devices) with one or N wires, portable computer disk cartridges (magnetic devices), random access memory (RAM), Read Only Memory (ROM), Erasable Editable Read Only Memory (EPROM or Flash Memory), Fiber Optic Devices, and Portable Compact Disc Read Only Memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, followed by editing, interpretation, or other suitable medium as necessary process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of this application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the N steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented by any one of the following techniques known in the art, or a combination thereof: discrete with logic gates for implementing logic functions on data signals Logic circuits, application specific integrated circuits with suitable combinational logic gates, Programmable Gate Arrays (PGA), Field Programmable Gate Arrays (FPGA), etc.

Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, and the program is stored in a computer-readable storage medium. When executed, one or a combination of the steps of the method embodiment is included.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like. Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limitations to the present application. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (10)

1. a photosensitive neuron, is characterized in that, comprises: Avalanche detector, used to output voltage pulse based on photon avalanche effect when photon is incident; The adaptive resistive memory connected in series with the avalanche detector is used to drive the conductive ions to drift to the conductive channel to form deposition under the driving of the voltage pulse, so as to sense the optical field signal of any signal light, and/or pass After training, current pulses of maximum amplitude are generated. 2 . The photosensitive neuron according to claim 1 , wherein when no photons are incident, the conductive channel of the adaptive resistive memory is dissolved and dissipated, wherein the deposition speed of the conductive channel is greater than the deposition speed of the conductive channel. 3 . When the diffusion ablation rate of the conductive channel is reached, the adaptive resistive memory enters a resistance reduction mode, and the avalanche detector enters a fast charging mode, returning to the initial state before the avalanche. 3. The photosensitive neuron according to claim 1 or 2, wherein after the photosensitive neuron releases the current pulse, the peak value of the pulse is I _peak =V _E /R _min , wherein V _E is the excess voltage , R _min is the lowest value of the adaptive resistive memory in the process of dynamic resistance change. 4. The photosensitive neuron of claim 3, wherein the minimum value is determined by the incident photon frequency. 5. photosensitive neuron according to claim 3 or 4, is characterized in that, also comprises: an introduction unit for introducing electrical excitation to adjust the actual resistance value of the adaptive resistive memory and the actual current of the avalanche detector to a target resistance value and a target current based on the incident photon frequency and the electrical excitation , to achieve neuronal activity conditions. 6. A sensing-memory-computing integrated intelligent sensing device, characterized in that, comprising: A photosensitive neuron array, the photosensitive neuron array comprising a plurality of photosensitive neurons according to any one of claims 1-5, to output current. 7. The apparatus of claim 6, further comprising: The training unit is used for training the photosensitive neurons in i row and j column in the photosensitive neuron array, so as to convert the incident light intensity of the signal light into a current sensitivity coefficient, and perform the multiplication and addition operation of the neural network. 8. The device according to claim 7, wherein the calculation formula of the output current is:

Among them, S _ij is the light intensity, R _ij is the sensitivity coefficient of the current, i is the number of rows, j is the number of columns, m is the maximum number of rows, and n is the maximum number of columns. 9. A sensing-memory-computing-integrated intelligent perception method, characterized in that, adopting the sensing-memory-computing integrated intelligent sensing device according to any one of claims 6-8, the method comprises the following steps: When a photon is incident, a voltage pulse is output based on the photo-induced avalanche effect; Driven by the voltage pulse, the conductive ions drift to the conductive channel to form deposition, so as to sense the light field signal of any signal light, and/or after training, the current pulse with the maximum amplitude is generated. 10. A computer storage medium on which a computer program is stored, characterized in that the program is executed by a processor to implement the sensor-memory-computing integrated intellisense method as claimed in claim 9.

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