CN114638349A - Photosensitive neuron and sensing and storage integrated intelligent sensing device, method and medium - Google Patents
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Abstract
The application relates to the technical field of semiconductors, in particular to a photosensitive neuron, a sensing and storage integrated intelligent sensing device, a method and a medium, wherein the photosensitive neuron comprises: the avalanche detector is used for outputting voltage pulses based on a photoinduced avalanche effect when photons are incident; and the self-adaptive resistive random access memory is connected with the avalanche detector in series and is used for drifting conductive ions to a conductive channel to form deposition under the driving of the voltage pulse so as to sense an optical field signal of any signal light and/or generate a current pulse with the maximum amplitude after training. Therefore, the problem of low pixel density of the storage and calculation integrated framework in the related technology is solved, the pixel density of the photosensitive neuron network is greatly improved, and the photosensitive neuron network is small in size, low in power consumption and high in speed.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a photosensitive neuron and sensing and storage computing integrated intelligent sensing device, method and medium.
Background
At present, the existing sensing and computing integrated architectures include two major types, namely CMOS (Complementary Metal Oxide Semiconductor) architectures and resistive switching control network architectures.
The CMOS architecture can be characterized as shown in fig. 1, in which a Sensor (Sensor) and an analog signal Processor (PE) are connected in series and then in parallel. The Sensor converts the optical signal into an electric signal and transmits the electric signal to the PE, the PE performs analog calculation on the optical signal according to a certain time sequence and an instruction, the PE generally interacts data with the adjacent PE to form adjacent area signal high relevance calculation, and conventional image processing tasks such as convolution, filtering and the like can be completed. Due to the sequential operation capability, the calculation processing is flexible. The resistive switching control network architecture has the characteristics that as shown in fig. 2, a detector is combined with a neurosynaptic device (such as a memristor, a multilevel switch and the like), the detector is responsible for sensing, and the neurosynaptic device is responsible for storage and calculation, so that the integration of the sensing, the storage and the calculation is realized. In this architecture, sometimes the neurosynaptic device has photosensitive characteristics and can simultaneously act as a sensor. The neurosynaptic device is trained in advance (electrically) to determine the responsivity R of the light-sensing units, and the output current of each light-sensing unit is equal to the product of the incident light intensity S and the responsivity R. Through the connection combination among the pixels, the output current results of non-adjacent pixels at a certain distance are superposed according to kirchhoff law to complete the weighted summation function of the neurons (such as S)1-SmMapping to I by weighted summation1The process of (d). On the other hand, the adjacent pixels sample the same position of the light field, and the light intensity can be approximately considered to be consistent. They map the light intensity onto the output currents of the different channels (e.g. S) through the effect of weighted summation of the neurons as described above1Mapping to I by weighted summation1-ImThe process of (d). In this approach, the size of the neurosynaptic device is often smaller than the detector size, and does not affect the spatial detection efficiency.
However, for the CMOS architecture, the main problem is that the status FLAG area FLAG and the register REGISTERS are required to register the status and data required for calculation, and the analog arithmetic processor ALU is required to calculate the photo-current data of the adjacent pixels according to a certain algorithm weight. Hardware of ALU, FLAG and REGISTERS is relatively complex, the area is large (far exceeds the size of a Sensor), and the part with the area exceeding the Sensor cannot sense light, so that the imaging pixel density is influenced; for the resistive switching control network architecture, a certain period extension mechanism (as shown by a dashed line box in fig. 2, a period extension minimum unit) needs to be set to increase the number of pixels, so that the width of the neural network is increased. The adjacent neurons can only be regarded as one pixel at the algorithm level, so that the pixel density is greatly reduced. On the other hand, the photosensitive neuron is usually made of memristor materials with photosensitive functions at present, and strong light or light of a special wave band is needed to trigger the memristive effect.
Disclosure of Invention
The application provides a photosensitive neuron and sensing and storage integrated intelligent sensing device, method and medium, which are used for solving the problem of low pixel density of a sensing and storage integrated framework in the related technology, greatly improving the pixel density of a photosensitive neuron network, and having small size, low power consumption and high speed.
An embodiment of a first aspect of the present application provides a photosensitive neuron, including:
an Avalanche detector (SPAD) for outputting voltage pulses based on a photoinduced Avalanche effect when photons are incident;
and the adaptive resistive random access memory (ARS) is connected with the avalanche detector in series and is used for drifting conductive ions to a conductive channel to form deposition under the driving of the voltage pulse so as to sense the optical field signal of any signal light and/or generate a current pulse with the maximum amplitude after training.
Optionally, when no photon is incident, a conductive channel of the adaptive resistive random access memory is dissolved and dissipated, wherein when a deposition rate of the conductive channel is greater than a diffusion ablation rate of the conductive channel, the adaptive resistive random access memory enters a resistance reduction mode, and the avalanche detector enters a fast charging mode and returns to an initial state before avalanche.
Optionally, the photosensitive neuron releases the current pulse, and the pulse peak value is Ipeak=VE/RminWherein V isEIs an excess voltage, RminThe resistance value of the self-adaptive resistive random access memory is the lowest value in the resistance dynamic change process.
Optionally, the lowest value is determined by the incident photon frequency.
Optionally, the method further comprises:
and the introducing unit is used for introducing electrical excitation so as to adjust the actual resistance value of the self-adaptive resistive random access memory and the actual current of the avalanche detector into a target resistance value and a target current based on the incident photon frequency and the electrical excitation, thereby achieving the active condition of the neuron.
The embodiment of the second aspect of the present application provides a sensing and computing integrated intelligent sensing device, including:
a light sensitive neuron array comprising a plurality of light sensitive neurons according to embodiments of the first aspect for outputting an electrical current.
Optionally, the method further comprises:
and the training unit is used for training the photosensitive neurons in i rows and j columns in the photosensitive neuron array so as to convert the incident light intensity of the signal light into a sensitive coefficient of current and execute the multiplication and addition operation of a neural network.
Optionally, the calculation formula of the output current is:
wherein S isijIs the light intensity, RijFor the current sensitivity coefficient, i is the number of rows, j is the number of columns, m is the maximum number of rows, and n is the maximum number of columns.
An embodiment of a third aspect of the present application provides a sensing and computing integrated intelligent sensing method, which uses the sensing and computing integrated intelligent sensing device according to the embodiment of the second aspect, and the method includes the following steps:
outputting a voltage pulse based on a photoinduced avalanche effect when photons are incident;
under the drive of the voltage pulse, the conductive ions drift to the conductive channel to form deposition so as to sense the optical field signal of any signal light, and/or generate the current pulse with the maximum amplitude after training.
A fourth aspect of the present application provides a computer-readable storage medium, on which a computer program is stored, where the program is executed by a processor, so as to implement the sensory-computational integrated intelligent sensing method according to the third aspect of the present invention.
Therefore, the embodiment of the application has the following advantages:
(1) different from a resistance change control network architecture in the related technology, the neural network provided by the embodiment of the application does not need to be provided with a plurality of photosensitive neurons in adjacent regions to increase the width of the neural network, the width of the neural network is realized in a time sequence control mode, the photosensitive neurons are stimulated and trained according to a certain time sequence, the weight of the neural network meets the requirements of different nodes in the width direction of the neural network, space is exchanged through time, the pixel density of the photosensitive neuron network is greatly improved, and the neural network is small in size, low in power consumption and high in speed.
(2) Unlike the CMOS architecture in the related art, the size of the computational core ARS in the neural network of the embodiment of the present application is much smaller than the detector SPAD size, and the hardware structures of ALU (arithmetic and logic unit), FLAG (EFLAGS Register, status FLAG Register), and REGISTERS do not affect the imaging pixel density.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
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The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of an array architecture in which sensors and processing units are connected in series and then connected in parallel;
fig. 2 is an exemplary diagram of a resistive switching control network architecture;
FIG. 3 is a block diagram of a photosensitive neuron according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a photosensitive neuron according to one embodiment of the present application;
FIG. 5 is a schematic diagram of a three-port implementation of a photosensitive neuron according to one embodiment of the present application;
FIG. 6 is an exemplary diagram of a sensory-computational integrated intelligent sensing device according to an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a sensory-computational integrated intelligent sensing device according to an embodiment of the present application;
fig. 8 is a flowchart of a perception-computation-integrated intelligent perception method according to an embodiment of the application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
The photosensitive neuron, the integrated sensory-computational intelligent sensing apparatus, the method, and the medium according to the embodiments of the present application will be described below with reference to the accompanying drawings. Aiming at the problem of low pixel density of the storage and calculation integrated framework mentioned in the background technology center, the application provides a photosensitive neuron which can sense light field signals (such as imaging) in situ and calculate and process the light field signals without arranging a plurality of photosensitive neurons in adjacent areas to increase the width of a neural network, the width of the neural network is realized in a time sequence regulation mode, the photosensitive neurons are stimulated and trained according to a certain time sequence, so that the weights of the photosensitive neurons meet the requirements of different nodes in the width direction of the neural network, the space is exchanged through time, the pixel density of the photosensitive neuron network is greatly improved, and the photosensitive neuron is small in size, low in power consumption and high in speed, and the problem of low pixel density of the storage and calculation integrated framework in the related technology is solved.
Specifically, fig. 3 is a schematic diagram of a photosensitive neuron according to an embodiment of the present disclosure.
As shown in fig. 3, the photosensitive neuron 10 includes: an avalanche detector 100 and an adaptive resistive random access memory 200.
Wherein, the avalanche detector 100 is used for outputting a voltage pulse based on a photoinduced avalanche effect when a photon is incident; the adaptive resistive random access memory 200 is connected in series with the avalanche detector 100, and is used for drifting conductive ions to a conductive channel to form deposition under the driving of a voltage pulse so as to sense an optical field signal of any signal light and/or generate a current pulse with the maximum amplitude after training.
Specifically, as shown in fig. 4, when photons are incident, a light-induced avalanche effect occurs in the avalanche detector 100, a voltage pulse is output, and conductive ions in the adaptive resistive random access memory 200 are driven to drift to a conductive channel to form deposition, so that an optical field signal of any signal light can be sensed, or a current pulse with a maximum amplitude is generated after training. It should be noted that the avalanche detector 100 may be a single photon detector, which has the advantages of easy integration and high sensitivity.
Optionally, in some embodiments, the conductive channel of the adaptive resistive random access memory 200 dissolves and dissipates when no photons are incident, wherein when the deposition rate of the conductive channel is greater than the diffusion ablation rate of the conductive channel, the adaptive resistive random access memory enters a resistance reduction mode, and the avalanche detector enters a fast charge mode and returns to the initial state before avalanche.
Specifically, when no photon is incident, the voltage mainly falls on two ends of the avalanche detector 100, the conductive channel in the adaptive resistive random access memory 200 is continuously dissolved and dissipated, the channel deposition speed is greater than the diffusion ablation speed, the resistance of the adaptive resistive random access memory 200 is rapidly reduced, the avalanche detector 100 is rapidly charged, and the state before avalanche is recovered.
Optionally, in some embodiments, the photosensitive neuron releases a current pulse followed by a pulse peak of Ipeak=VE/RminWherein V isEIs an excess voltage, RminThe resistance value is the lowest value of the self-adaptive resistive random access memory in the resistance dynamic change process.
Optionally, in some embodiments, the lowest value is determined by the incident photon frequency.
In particular, the photosensitive neuron 10 may release a current pulse, the peak of which is Ipeak=VE/Rmin,VETo passResidual voltage (constant value), RminIs the lowest value in the resistance dynamic change process of the adaptive resistive random access memory 200. In addition, R isminThe value is the lowest value of the resistance dynamics of the adaptive resistive random access memory 200 during each avalanche process, and essentially depends on the dynamic balancing results of the conductive channel deposition and ablation.
Optionally, in some embodiments, the method further comprises: and the introducing unit is used for introducing electrical excitation so as to adjust the actual resistance value of the self-adaptive resistive random access memory and the actual current of the avalanche detector into a target resistance value and a target current based on the incident photon frequency and the electrical excitation, thereby achieving the active condition of the neuron.
It should be understood that the embodiments of the present application can be adjusted by the incident photon frequency, when the photon frequency is large, the avalanche occurrence interval is shorter, the ratio of the deposition time to the ablation time of the conductive channel is increased, the conductive channel of the adaptive resistive random access memory 200 is wider, and R is greaterminAnd lower. On the contrary, when the incident photon frequency is small, the avalanche occurrence interval is longer, the ratio of the deposition time to the ablation time of the conductive channel is reduced, the conductive channel of the adaptive resistive random access memory 200 is narrower, and R isminAnd is larger. Therefore, when the photosensitive neuron is excited by high-brightness light, the adaptive resistive random access memory 200 has high conductivity and low resistance; when the photosensitive neuron is excited by light with low brightness, the adaptive resistive random access memory 200 has low conductive activity and large resistance. The embodiments of the present application can train the activity of neurons by this method.
Thus, the photosensitive neuron 10 can store the information of the light field irradiated thereon, and when the signal light is irradiated on the photosensitive neuron 10 which has been trained, the photosensitive neuron 10 will generate a maximum amplitude VE/RminThe current pulse of (2). Thus, the photosensitive neurons are sensory integrated.
In addition, the photosensitive neuron of the avalanche detector 100 and the adaptive resistive random access memory 200 shown in fig. 4 is a two-port device, and the resistance value of the adaptive resistive random access memory 200 and the magnitude of the avalanche pulse current are dynamically adjusted by the incident photon frequency. However, the resistance of the adaptive resistive random access memory 200 can also be adjusted electrically, as shown in fig. 5, a third port C is led out from the middle of the avalanche detector 100 and the adaptive resistive random access memory 200, and an electrical excitation (such as pulse drive or dc drive) is led in to change the resistance of the adaptive resistive random access memory 200.
According to the photosensitive neuron provided by the embodiment of the application, the light field signal can be sensed (such as imaging) in situ and calculated, the width of a neural network is increased without arranging a plurality of photosensitive neurons in adjacent regions, the width of the neural network is realized in a time sequence regulation mode, the photosensitive neuron is stimulated and trained according to a certain time sequence, the weight of the photosensitive neuron meets the requirements of different nodes in the width direction of the neural network, the space is exchanged through time, the pixel density of the photosensitive neuron network is greatly improved, the size is small, the power consumption is low, the speed is high, and the problem of low pixel density of a storage and calculation integrated framework in the related technology is solved.
The sensing and computing integrated intelligent sensing device provided by the embodiment of the application is described next with reference to the attached drawings.
Fig. 6 is a block diagram of a sensory-computational integrated intelligent sensing device according to an embodiment of the present application.
As shown in fig. 6, the sensory-computational integrated smart sensor device 20 includes: a photosensitive neuron array 21.
The photosensitive neuron array 21 includes a plurality of photosensitive neurons according to the embodiment of fig. 3 to output current.
Optionally, in some embodiments, the sensing and computing integrated intelligent sensing device 20 according to the embodiment of the present application further includes: and a training unit. The training unit is used for training the photosensitive neurons in i rows and j columns in the photosensitive neuron array so as to convert the incident light intensity of signal light into a sensitive coefficient of current and execute the multiplication and addition operation of a neural network.
Specifically, as shown in fig. 7, in the embodiment of the present application, photosensitive neurons may be grouped into an array, and each pixel point (i rows and j columns) in the array is composed of the photosensitive neurons shown in fig. 4. Through training, the sensitivity coefficient of the photosensitive neurons in i rows and j columns for converting incident light intensity into current is set as RijThus, when the light intensity incident on the neuron element in i row and j column is SijThe network output current is, in time:
wherein S isijIs the light intensity, RijFor the current sensitivity coefficient, i is the number of rows, j is the number of columns, m is the maximum number of rows, and n is the maximum number of columns.
Thereby, the multiplication and addition operation of the neural network is completed.
It should be noted that the foregoing explanation of the embodiment of the photosensitive neuron is also applicable to the sensing and computing integrated intelligent sensing apparatus of the embodiment, and details are not repeated here.
According to the sensing, storage and calculation integrated intelligent sensing device provided by the embodiment of the application, the width of a neural network is increased without arranging a plurality of photosensitive neurons in adjacent regions, the width of the neural network is realized in a time sequence regulation and control mode, the photosensitive neurons are stimulated and trained according to a certain time sequence, the weights of the photosensitive neurons meet the requirements of different nodes in the width direction of the neural network, a space is exchanged through time, the pixel density of the photosensitive neuron network is greatly improved, the size is small, the power consumption is low, the speed is high, and the problem of low pixel density of a storage and calculation integrated framework in the related technology is solved.
Fig. 8 is a flowchart of a perception-computation-integrated intelligent perception method according to an embodiment of the application.
As shown in fig. 8, the sensing and computing integrated intelligent sensing method adopts the sensing and computing integrated intelligent sensing device of the embodiment of fig. 5, and the method includes the following steps:
and S801, outputting a voltage pulse based on the photoinduced avalanche effect when photons enter.
S802, under the driving of the voltage pulse, the conducting ions drift to the conducting channel to form deposition so as to sense the optical field signal of any signal light, and/or generate the current pulse with the maximum amplitude after training.
It should be noted that the foregoing explanation of the embodiment of the sensing and computing integrated intelligent sensing device is also applicable to the sensing and computing integrated intelligent sensing method of the embodiment, and details are not repeated here.
According to the sensing, storage and calculation integrated intelligent sensing method provided by the embodiment of the application, a plurality of photosensitive neurons do not need to be arranged in adjacent regions to increase the width of a neural network, the width of the neural network is realized in a time sequence regulation mode, the photosensitive neurons are stimulated and trained according to a certain time sequence, the weights of the photosensitive neurons meet the requirements of different nodes in the width direction of the neural network, the space is exchanged through time, the pixel density of the photosensitive neuron network is greatly improved, the size is small, the power consumption is low, the speed is high, and the problem of low pixel density of a storage and calculation integrated framework in the related technology is solved.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the method for sensing, storing and calculating integrated intelligent sensing is realized.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or N embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "N" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more N executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of implementing the embodiments of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or N wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer-readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A photosensitive neuron, comprising:
the avalanche detector is used for outputting voltage pulses based on a photoinduced avalanche effect when photons are incident;
and the adaptive resistive random access memory is connected with the avalanche detector in series and is used for drifting conducting ions to a conducting channel to form deposition under the driving of the voltage pulse so as to sense a light field signal of any signal light and/or generate a current pulse with the maximum amplitude after training.
2. The photosensitive neuron of claim 1, wherein a conductive channel of the adaptive resistive random access memory dissolves and dissipates when no photons are incident, wherein the adaptive resistive random access memory enters a resistance reduction mode when a deposition rate of the conductive channel is greater than a diffusive ablation rate of the conductive channel, and the avalanche detector enters a fast charge mode and returns to an initial state before avalanche.
3. The photosensitive neuron of claim 1 or 2, wherein the photosensitive neuron releases the current pulse with a pulse peak value of Ipeak=VE/RminWherein V isEIs an excess voltage, RminThe resistance value of the self-adaptive resistive random access memory is the lowest value in the resistance dynamic change process.
4. The photosensitive neuron of claim 3, wherein the lowest value is determined by an incident photon frequency.
5. The photosensitive neuron of claim 3 or 4, further comprising:
and the introducing unit is used for introducing electrical excitation so as to adjust the actual resistance value of the self-adaptive resistive random access memory and the actual current of the avalanche detector into a target resistance value and a target current based on the incident photon frequency and the electrical excitation, thereby achieving the active condition of the neuron.
6. The utility model provides a sense integration intelligent perception device that deposits, its characterized in that includes:
a photosensitive neuron array comprising a plurality of photosensitive neurons according to any one of claims 1-5 to output a current.
7. The apparatus of claim 6, further comprising:
and the training unit is used for training the photosensitive neurons in i rows and j columns in the photosensitive neuron array so as to convert the incident light intensity of the signal light into a sensitive coefficient of current and execute the multiplication and addition operation of a neural network.
9. A sensory-computational integrated intelligent perception method, which is characterized in that the sensory-computational integrated intelligent perception device according to any one of claims 6-8 is adopted, and the method comprises the following steps:
when photons are incident, voltage pulses are output based on a photoinduced avalanche effect;
under the drive of the voltage pulse, the conductive ions drift to the conductive channel to form deposition so as to sense the optical field signal of any signal light, and/or generate the current pulse with the maximum amplitude after training.
10. A computer storage medium having a computer program stored thereon, the program being executable by a processor for implementing the sensory-computational integrated smart perception method according to claim 9.
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