CN114637183A - Method and system for time-to-digital conversion - Google Patents
Method and system for time-to-digital conversion Download PDFInfo
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Abstract
A method for time-to-digital conversion is provided. The method comprises the following steps: sending a calibration signal to a time-to-digital converter under at least three temperature conditions; obtaining a reference moment of the calibration signal; obtaining a time length of a delay unit output by the time-to-digital converter under each of the temperature conditions; obtaining the calibration temperature of the time-to-digital converter corresponding to each temperature condition through a temperature sensor; and determining the temperature coefficient of the time-to-digital converter based on the time length of the delay unit, the calibration temperature and the reference time under the at least three temperature conditions. Obtaining the temperature of the time-to-digital converter when receiving a signal to be measured; time data corresponding to the signal to be detected is obtained through a time-to-digital converter; determining a temperature coefficient corresponding to the time-to-digital converter; and determining a corrected time corresponding to the signal to be measured based on the time data, the temperature, and the temperature coefficient.
Description
Technical Field
The present application relates to the field of circuit technology, and more particularly, to a method of determining a temperature coefficient of a time-to-digital converter, a method of correcting a time-to-digital conversion system, a method for time-to-digital conversion, a system for time-to-digital conversion, and a lidar.
Background
A Time To Digital Converter (TDC) is used to convert the Time interval information into a Digital signal, thereby implementing the measurement of the Time interval by the circuit. Time interval measurement, particularly precise time interval measurement, is required in the fields of navigation, laser radar ranging, ultrasonic ranging, space technology, remote sensing imaging, communication and the like.
A Field Programmable Gate Array (FPGA) device, which belongs to a semi-custom circuit in an application-specific integrated circuit. The FPGA device is integrated with a large number of resources which can realize specified connection and have specified functions under the control of a program. For example, a fast Carry Chain (Carry Chain) resource exists in an FPGA device, and can be used for accelerating addition, multiplication, shift operation and the like. These fast carry chains can be used as delay units and implement TDC functions in an interpolation manner, and the time resolution of the TDC can reach an accuracy of tens of ps.
However, the implementation of the TDC function by using the FPGA has some disadvantages, such as the following two aspects:
on the one hand, since the function of the FPGA is implemented by hardware, and particularly, the internal resources thereof are implemented by a semiconductor process, the result of measurement using the FPGA is easily affected by temperature and becomes inaccurate.
In order to reduce measurement errors caused by temperature, a currently common approach is to include a loop oscillator module in the designed module. The loop oscillation module is used for generating a pulse signal with a certain time interval to calibrate the time length converted by the TDC after the temperature change. This method has some problems, such as: the required data volume is larger, so that a larger storage space is occupied; more complex mathematical processing needs to be carried out on the data, so that more design resources are occupied; in addition, each time calibration is performed, the TDC needs to stop timing work and enter a calibration mode, and a certain time is consumed in the calibration process, so that the calibration is unacceptable for occasions requiring the TDC to continuously work.
On the other hand, the carry chains in the FPGA have different lengths and are further represented by time delays, and the time delays range from about ten picoseconds to hundreds of picoseconds, so that the time scales obtained after the FPGA is coded are not uniform, and Differential Nonlinearity (DNL) exists. There is a need in the art for a TDC that corrects for differential non-linearity.
Disclosure of Invention
The application provides a method for determining a temperature coefficient of a time-to-digital converter, which comprises the following steps: sending a calibration signal to a time-to-digital converter under at least three temperature conditions; obtaining a reference moment of a calibration signal; obtaining time data output by the time-to-digital converter under each temperature condition, wherein the time data comprise the time length of each delay unit to be calibrated; obtaining the calibration temperature of the time-to-digital converter corresponding to each temperature condition through a temperature sensor; the temperature coefficient of the time-to-digital converter is determined based on the time data, the calibration temperature and the reference time under at least three temperature conditions.
In one embodiment, determining the temperature coefficient of the time-to-digital converter comprises: fitting the formula Deltatb-a2Kb 2+a1Kb+a0A in (a)0、a1And a2(ii) a Wherein, a0Is the zero order temperature coefficient, a1Is the first order temperature coefficient, a2Is the second order temperature coefficient, Δ tbIs each delay to be calibratedTime length t of unit corresponding to time databAnd a calibration correction value, K, between the time length t at the corresponding reference timebIs the calibration temperature; the zeroth order temperature coefficient, the first order temperature coefficient and the second order temperature coefficient form a temperature coefficient of the time-to-digital converter.
In one embodiment, determining the temperature coefficient of the time-to-digital converter further comprises: based on time data t under another temperature conditionb1And a calibration temperature Kb1Obtaining a calibration correction time t corresponding to the calibration signal under another temperature conditionxbWherein, txb＝tb1+(a2Kb1 2+a1Kb1+a0) (ii) a Verifying a reference time t under another temperature condition1And a calibration correction time t corresponding to the calibration signal under another temperature conditionxbWhether the deviation between the two is qualified or not; if not, the formula delta t is fitted againb＝a2Kb 2+a1Kb+a0。
In one embodiment, the method further comprises: and writing the temperature coefficient into the static random access memory.
Another aspect of the present application also provides a method for time-to-digital conversion, the method including: obtaining the temperature of the time-to-digital converter when receiving a signal to be measured; time data corresponding to the signal to be measured is obtained through a time-to-digital converter; determining a temperature coefficient corresponding to the time-to-digital converter; and determining a corrected time corresponding to the signal to be measured based on the time data, the temperature, and the temperature coefficient.
In one embodiment, the method further comprises: writing the temperature coefficient into the SRAM; wherein determining the temperature coefficient of the time-to-digital converter comprises: the temperature coefficient of the time-to-digital converter is recalled from the sram.
In one embodiment, the time data includes: the time length of each delay cell.
In one embodiment, determining the temperature coefficient corresponding to the time-to-digital converter comprises: the method of determining the temperature coefficient of a time-to-digital converter as described above.
The present application also provides a system for time-to-digital conversion, comprising: a time-to-digital converter for generating time data corresponding to the signal to be measured; a temperature sensor configured to detect a temperature of the time-to-digital converter; a memory storing executable instructions and temperature coefficients of the time-to-digital converter; and one or more processors in communication with the memory to execute the executable instructions to implement the foregoing methods.
In one embodiment, the one or more processors include: a logic unit and an SOC processor in the FPGA; the logic unit is configured to communicate with the memory to execute the executable instructions to: obtaining the temperature of the time-to-digital converter when receiving a signal to be measured; time data corresponding to the signal to be detected is obtained through a time-to-digital converter; determining a temperature coefficient corresponding to the time-to-digital converter; and determining a corrected time corresponding to the signal to be measured based on the time data, the temperature and the temperature coefficient; the SOC processor is configured to process the correction time instant for transmission to the external device.
The method for determining the temperature coefficient of the time-to-digital converter is beneficial to obtaining the time-to-digital converter with temperature compensation performance. The time-to-digital conversion method provided by the embodiment of the application is based on the time of the measured signal compensated by the temperature, so that the measured time is more accurate. The compensation process has simple operation and high speed, and does not influence the normal work of the time-to-digital converter. And the time-to-digital conversion system has low energy consumption and low use cost. The manufacturing cost is also low.
A method of deskewing a time-to-digital conversion system, comprising the steps of: calibrating a first delay chain of a first time digital converter, wherein the first time digital converter is realized based on a carry chain of which one part in the FPGA is restricted; calibrating a second delay chain of a second time-to-digital converter, wherein the second time-to-digital converter is realized based on a carry chain of which the other part in the FPGA is restricted; adjusting a starting point of one of the first delay chain and the second delay chain so that both ends of at least one delay unit of the first delay chain are located in different delay units of the second delay chain on a time axis; writing the adjusted first delay chain into a first delay unit lookup table to form a first comparison chain; and writing the adjusted second delay chain into a second delay unit lookup table to form a second comparison chain.
In one embodiment, the step of scaling the first delay chain comprises: sending a calibration signal to a first time-to-digital converter; and obtaining the reference time of the calibration signal.
In one embodiment, the step of scaling the first delay chain comprises: first time data output by the first time-to-digital converter is obtained, wherein the first time data comprises the time length of each delay unit in the first delay chain.
In one embodiment, the data stored in the first delay cell lookup table includes: the time at which each delay element in the first comparison chain represents relative to the start of the first comparison chain; and the time length of each delay cell in the first comparison chain.
In one embodiment, the first delay chain includes a plurality of long delay cells, the length of the long delay cells being greater than the average length of the delay cells in the first delay chain; wherein, the two ends of at least one delay unit of the first delay chain are positioned in two delay units of the second delay chain, and the two delay units comprise: two ends of more than half of the long delay units in the plurality of long delay units are positioned in two nonadjacent delay units of the second delay chain.
In one embodiment, a first wire constrained between the signal input end and the starting point of the first time-to-digital converter is included; a constrained second wire is arranged between the signal input end and the starting point of the second time digital converter. The time delay of the first trace and the second trace can be the same.
The present application provides in another aspect a method for time-to-digital conversion, comprising: obtaining a first time to be selected, wherein the first time to be selected is equal to a first time output by a first time digital converter when the first time digital converter receives a signal to be detected, and the first time is a time represented by a first delay unit corresponding to the signal to be detected in a first delay chain of the first time digital converter; obtaining a second candidate time, wherein the second candidate time is equal to a second time output by a second time digital converter when the second time digital converter receives a signal to be detected, and the second time is a time represented by a second delay unit corresponding to the signal to be detected in a second delay chain of the second time digital converter, and two ends of at least one delay unit of the first delay chain are located in different delay units of the second delay chain on a time axis; and selecting the smaller one of the first to-be-selected time and the second to-be-selected time.
In one embodiment, both ends of at least one delay cell of the first delay chain are located in two non-adjacent delay cells of the second delay chain; when the second delay unit corresponding to the signal to be measured is located between two non-adjacent delay units, the selecting step includes: determining a time length of the first delay unit; determining a time length of the second delay unit; determining the minimum value of the time length of the first delay unit and the time length of the second delay unit; and selecting one of the first to-be-selected time and the second to-be-selected time, wherein the corresponding time length is equal to the minimum value.
In one embodiment, determining the length of time of the first delay cell comprises: determining a time length of the first delay unit through a first delay unit lookup table; and determining the length of time of the second delay cell comprises: determining a time length of the second delay unit through a second delay unit lookup table; wherein, the data stored in the first delay unit lookup table comprises: the time instant represented by each delay element in the first comparison chain relative to the start of the first comparison chain, and the time length of each delay element in the first comparison chain; all delay units in the first comparison chain correspond to all first delay units in the first delay chain one to one; the data stored by the second delay cell lookup table includes: the time represented by each delay unit in the second comparison chain relative to the start of the second comparison chain, and the time length of each delay unit in the second comparison chain; all delay cells in the second ratio chain correspond one-to-one to all second delay cells in the second delay chain.
In one embodiment, obtaining the first moment to be selected includes: obtaining a first time to be selected based on the first time through a first delay unit lookup table; the obtaining of the second candidate moment comprises: and obtaining a second candidate moment based on the second moment through a second delay unit lookup table.
In one embodiment, further comprising: the method for correcting the time-to-digital conversion system is described.
In one embodiment, the first time-to-digital converter comprises a plurality of carry chains in an FPGA that are constrained to be cascaded; the second time-to-digital converter includes a further plurality of carry chains in the FPGA constrained to be cascaded.
The present application also provides a system for time-to-digital conversion, comprising: a first time-to-digital converter configured to output a first time instant when receiving a signal under test, the first time instant being a time instant characterized by a first delay cell corresponding to the signal under test in a first delay chain that the first time-to-digital converter has; a second time-to-digital converter configured to output a second time instant when receiving the signal to be measured, the second time instant being a time instant characterized by a second delay unit corresponding to the signal to be measured in a second delay chain of the second time-to-digital converter, wherein, on a time axis, at least one delay unit of one of the first delay chain and the second delay chain spans over at least two delay units of the other; a memory storing executable instructions; and one or more processors in communication with the memory to execute the executable instructions to implement the foregoing methods.
In one embodiment, the first time-to-digital converter comprises a plurality of carry chains in an FPGA that are constrained to be cascaded; the second time-to-digital converter includes a further plurality of carry chains in the FPAG that are cascaded in a constrained manner.
In one embodiment, further comprising: a first delay cell lookup table configured to output a first time to be selected based on a first time, the first delay cell lookup table storing data including: a time instant represented by each delay element in the first comparison chain relative to a start point of the first comparison chain, and a time length of each delay element in the first comparison chain; all delay units in the first comparison chain correspond to all first delay units in the first delay chain one to one; and a second delay unit lookup table configured to output a second candidate time based on the second time, the second delay unit lookup table storing data including: the time represented by each delay unit in the second comparison chain relative to the start of the second comparison chain, and the time length of each delay unit in the second comparison chain; all delay units in the second comparison chain correspond to all second delay units in the second delay chain one to one; wherein the one or more processors are in communication with the memory to execute the executable instructions to perform: obtaining a first time to be selected based on the first time through a first delay unit lookup table; and obtaining a second candidate moment based on the second moment through a second delay unit lookup table.
In one embodiment, further comprising: at least one temperature sensor configured to detect a temperature of the first time-to-digital converter and to detect a temperature of the second time-to-digital converter; wherein the memory further stores a temperature coefficient of the first time-to-digital converter and a temperature coefficient of the second time-to-digital converter; and one or more processors in communication with the memory to execute the executable instructions to perform: obtaining the temperature of the time-to-digital converter corresponding to the selected moment when the time-to-digital converter receives the signal to be measured; obtaining the time length of each delay unit generated by the time-to-digital converter corresponding to the selected moment before receiving the signal to be tested; determining the temperature coefficient of the time-to-digital converter corresponding to the selected moment; and correcting the selected time based on the time length, the temperature and the temperature coefficient of each delay unit.
In one embodiment, further comprising: a first trace configured to electrically connect the first time-to-digital converter and the signal input, the first trace being constrained; and the second wire is configured to be electrically connected with the second time-to-digital converter and the signal input end, the second wire is constrained, and the second wire and the first wire can have the same time delay.
In one embodiment, the one or more processors comprise: the data judging and selecting unit is composed of logic units in the FPGA and realizes the method; and the SOC processor in the FPGA is in communication connection with the data judging unit and is configured to process the data output by the data judging unit so as to transmit the data to an external system.
The application also provides a laser radar comprising the time-to-digital conversion system.
The method for correcting the time-to-digital conversion system can correct the differential nonlinear function of two coupled digital converters, and is favorable for obtaining the time-to-digital conversion system with better differential nonlinear performance. The time-to-digital conversion method provided by the embodiment of the application is based on a differential nonlinear compensation mode, and one delay unit is arranged across at least two delay units of another delay chain, namely, the length of the delay unit in one delay chain is subdivided by the delay unit of the other delay chain through parallel comparison. And then the measured time intervals are more detailed and uniform. The time-to-digital conversion system provided by the application has higher measurement precision.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 shows a schematic flow diagram of a method of determining a temperature coefficient of a time-to-digital converter according to the present application;
FIG. 2 shows a schematic block diagram of a system for time-to-digital conversion according to the present application;
FIG. 3 shows a schematic flow diagram of a method for time-to-digital conversion according to the present application;
FIG. 4 shows a schematic block diagram of a system for time-to-digital conversion according to the present application;
FIG. 5 shows a schematic flow diagram of a method of rectifying a time-to-digital conversion system according to the present application;
fig. 6 is a schematic diagram showing an arrangement of delay cells in a time-to-digital conversion system according to an embodiment of the present application;
FIG. 7 shows a schematic flow diagram of a method for time-to-digital conversion according to the present application;
FIG. 8 shows a schematic flow chart of the select candidate moment step according to the present application; and
fig. 9 shows a schematic block diagram of another system for time-to-digital conversion according to the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that in this specification, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not represent any limitation on the features. Thus, the first time-to-digital converter discussed below may also be referred to as the second time-to-digital converter without departing from the teachings of the present application. And vice versa.
As used herein, the terms "approximately," "about," and the like are used as table approximation terms, not as table degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, an embodiment of the present application provides a method 1000 for determining a temperature coefficient of a time-to-digital converter, including the steps of:
and S1010, sending a calibration signal to the time-to-digital converter under a temperature condition. The calibration signal includes a plurality of pulses having calibrated time instants.
And S1040, obtaining the reference time of the calibration signal. The calibration signal may have a reference time that is determined based on an external device, such as a low temperature drift crystal clock.
And S1020, acquiring the time data output by the time-to-digital converter under the temperature condition. In particular, the time-to-digital converter operates with a delay chain comprising a series of delay cells connected end to end. The time data includes the time length of each delay unit to be calibrated.
The time-to-digital converter outputs a corresponding arrival position code value when the arrival pulse works, the code value is converted into the difference value of the time represented by two adjacent code values of specific time data, the time length between the two code values is also regarded as a delay unit of the code value. Therefore, based on the frequency of occurrence of the encoded values, the number of the nominal delay units included in the time data, and the time length of each delay unit, i.e., the delay time, can also be determined.
And S1030, obtaining the calibration temperature of the time-to-digital converter corresponding to each temperature condition through the temperature sensor.
Generally, the temperature conditions for carrying out the method are controlled by external means, for example by controlling the temperature in the insulated space by means of a heat exchanger, so that the time-to-digital converter in the insulated space is at different temperature levels. However, the operating temperature of the time-to-digital converter may differ from the set temperature condition, so measuring the temperature of the time-to-digital converter directly is better than recalling the set temperature condition.
S1050, performing S1010, S1020, S1030, and S1040 under at least three temperature conditions. The number of calibrations may be determined based on the temperature and effect of the time-to-digital converter. For example, 9 times are calibrated within 0 ℃ to 80 ℃, specifically one temperature condition every 10 ℃.
S1060, determining the temperature coefficient of the time-to-digital converter based on the time data, the calibration temperature and the reference time under at least three temperature conditions.
Further, the step of determining the temperature coefficient of the time-to-digital converter comprises:
using the formula:
Δtb＝a2Kb 2+a1Kb+a0 (1)
fitting the data obtained in steps S1020, S1030 and S1040 to obtain a in formula (1)0、a1And a2。
Wherein, a0Is the zero order temperature coefficient, a1Is the first order temperature coefficient, a2Is the second order temperature coefficient, Δ tbIs the time length t of the nominal delay unit at each time databAnd a calibration correction value, K, between the time length t at the corresponding reference timebIs the calibration temperature. Wherein, the zeroth order temperature coefficient, the first order temperature coefficient and the second order temperatureThe coefficients constitute the temperature coefficient of the time-to-digital converter.
When there are only three temperature conditions, equation (1) can be directly calculated. Usually, the time-to-digital converter is calibrated under three or more temperature conditions, and the calibrated data can be curve-fitted by, for example, the least square method.
For example, two hundred flip-flops are included in the time-to-digital converter, and two hundred delay cells can be calibrated. The calibration time at the first temperature is 39ns, the calibration time at the second temperature is 40ns, and the calibration time at the third temperature is 41 ns. The time-to-digital converter may be referenced to a second temperature condition. I.e. a time length of 40ns, is converted into two hundred delay elements, i.e. two hundred code values. The delay element length for each code value is scaled by the frequency at which each code value occurs at the calibration time, based on the total length of 40 ns. And obtaining the calibration correction value which the time represented by one code value should have under other temperature conditions.
Illustratively, these two hundred delay cells may be scaled for any temperature condition as a reference. Under the temperature condition, the time data correction value output by the marked time-to-digital converter is zero.
For example, the end of the one hundred delay cells of the time-to-digital converter is labeled as 20.1 ns. When the reference time t1Is 20ns, the time-to-digital converter includes ninety delay cells in the corresponding time data at the first temperature condition, the time data characterizing the time of day is 18.2 ns. Then at the first temperature the ninety delay cells should be modified to one hundred or the modified value at the time represented by the end of the ninety delay cells is +1.9ns so that although the time data output by the time to digital converter includes ninety delay cells, a time length of 20.1ns can still be accurately derived.
Further, determining the temperature coefficient of the time-to-digital converter further comprises:
based on time at another temperatureData tb1And a calibration temperature Kb1Obtaining a calibration correction time t corresponding to the calibration signal under the other conditionxbWherein, in the step (A),
txb＝tb1+(a2Kb1 2+a1Kb1+a0)；
verifying a reference time t under another temperature condition1And a calibration correction time t corresponding to the calibration signal under the other conditionxbWhether the deviation between the two is qualified or not; if not, the formula delta t is fitted againb＝a2Kb 2+a1Kb+a0. The calibrated formula has high confidence. The accuracy of the re-fitted formula is high.
For example, nine sets of data are obtained under nine temperature conditions, and a is determined by curve fitting eight sets of data0、a1And a2. Then the formula (1) is used for calculating the ninth group of data to obtain the calibration correction time t of the ninth group of dataxbAnd calculating txbWith reference time t of the group of data1The deviation therebetween.
For example, reference time t1Is 20ns, and further, it is predicted that 100 delay units are included in the corresponding time data under a temperature condition, and 99-101 delay units are included in the actually output time data, which can be regarded as txbAnd t1The deviation therebetween was acceptable.
The temperature coefficient of the time-to-digital converter determined by the embodiment of the application has stronger adaptability, and the time after temperature compensation is more accurate.
Further, the difference between two deviations corresponding to two adjacent reference times is the deviation of the delay unit of the previous reference time.
Illustratively, the method 3000 may be a part of a method of manufacturing a system for time-to-digital conversion.
Referring to fig. 2, the system 100 for time-to-digital conversion provided by the present application may be implemented based on a programmable logic device such as an FPGA. The system 100 stores the aforementioned temperature coefficient before shipment. The system 100 for time-to-digital conversion may be advantageously used with various electronic devices, such as lidar, to time periods, machine periods, and the like.
The system 100 includes: a time-to-digital converter 111, a temperature sensor 113, a memory, and one or more processors.
The time-to-digital converter 111 may include a cascaded carry chain, the start of which may be communicatively coupled to the signal input via a trace. The signal output by the time-to-digital converter 111 during operation may be characterized as a delay chain, which may represent a time interval. The time-to-digital converter 111 may generate time data corresponding to the signal to be measured after receiving the signal to be measured.
The temperature sensor 113 is configured to detect the temperature of the time-to-digital converter 111. And for outputting the detected temperature to one or more processors.
The memory may include Random Access Memory (RAM) internal to the FPGA and non-volatile memory external to the FPGA. The memory external to the FPGA may be a Flash memory (Flash memory) or a charged Erasable Programmable read only memory (EEPROM). Memory external to the FPGA may be used to store executable instructions and temperature coefficients for the time-to-digital converter 111. And after the FPGA is powered on, the RAM is also used to store executable instructions and the temperature coefficient of the time-to-digital converter 111. Illustratively, the RAM may include (SRAM) 102 and a temperature coefficient lookup table 115, where the SRAM 102 is used for storing executable instructions, and the temperature coefficient lookup table 115 is used for storing the temperature coefficient of the time-to-digital converter 111.
One or more processors are in communication with the memory to execute the executable instructions. The one or more processors may specifically include: logic units in the FPGA and an soc (system on chip) processor 101.
The logic unit is configured to communicate with the memory to execute the executable instructions to implement the operations shown in fig. 3:
s2010, the temperature of the time-to-digital converter 111 when receiving the signal to be measured is obtained.
And S2020, acquiring time data corresponding to the signal to be measured through a time-to-digital converter.
S2030, the temperature coefficient corresponding to the time-to-digital converter is determined.
S2040, determining a corrected time corresponding to the signal to be measured based on the time data, the temperature, and the temperature coefficient.
And SOC processor 101 may be configured to process the correction time of day for transmission to an external device.
In particular, the logic unit may include a corrective processing unit 112 and a temperature acquisition unit 114. The temperature acquisition unit 114 is used for acquiring the temperature of the time-to-digital converter 111 when receiving the signal to be measured, and can transmit the temperature to the correction processing unit 112 through the bus 103. The correction processing unit 112 is configured to receive the time data, the temperature, and the temperature coefficient, and output the corrected time to the SOC processor 101. For example, the leveling processing unit 112 may be designed with an interface to be hung on the SOC processor 101.
The time-to-digital conversion method adopted by the system 100 is simple in operation and high in speed, and the obtained result is high in precision. The normal working state of the TDC is not influenced during conversion, the TDC is suitable for different working environments, and the operation cost is low.
When the system 100 is built on an FPGA, the FPGA may have integrated therein a bus 103 and one or more processors, RAM, a time-to-digital converter 111, an input/output (I/O) interface 104, an input 105, and a driver 108 connected to the bus.
While fig. 2 illustrates the system 100 for time-to-digital conversion with various components, it is to be understood that not all illustrated components are required to be implemented or provided. More or fewer components may alternatively be implemented or provided. For example, a portion of the carry chain in the FPGA is used to form time-to-digital converter 111, while the remaining carry chains 110 may also be used to form other time-to-digital converters.
The present application provides a method 2000 for time-to-digital conversion that may be implemented using the system 100 for time-to-digital conversion described above. Referring to fig. 3, the method 2000 includes the aforementioned steps S2010 to S2040, wherein the writing order of the three steps S2010 to S2030 is not equal to the implementation order of the three steps.
The method 2000 for time-to-digital conversion provided by the present application requires a small amount of data, thereby occupying a small storage space. The data is processed by simpler mathematics, thereby occupying less design resources.
For example, S2030, the step of determining the temperature coefficient of the time-to-digital converter may include: the temperature coefficient of the time-to-digital converter is recalled from the sram. Exemplary, before the invoking, the method may further include: the temperature coefficient is written into the SRAM. Therefore, the TDC can continuously work at each time of calibration. Time consumption caused by entering a calibration mode in the working process is avoided. When the method is repeatedly executed for multiple times, the mode of calling the temperature coefficient has smaller calculation amount.
The embodiment of the present application further provides a system 500 for time-to-digital conversion, and referring to fig. 4, the system 500 may include: a first time to digital converter 510, a second time to digital converter 513, a memory, and at least one processor.
In an exemplary embodiment, the system 500 may be implemented based on an FPGA. The FPGA has a large number of logic resources and wiring resources inside, and the FPGA can be used for developing software to select a path through which a signal flows. However, synthesis of the same design source code, whether VHDL or Verilog HDL, using different synthesis tools produces different results.
Illustratively, a method of manufacturing the system 500 based on an FPGA may include: the first time-to-digital converter 510 is implemented based on a part of the carry chain constrained inside the FPGA. The second time-to-digital converter 513 is implemented based on a carry chain that is constrained by another portion of the FPGA interior. The constrained carry chain is locked by program logic, and a certain module can be appointed at a certain position of the FPGA through the logic locking, so that the starting position of the delay chain is controlled. The logic lock can ensure that the locked module is not changed in the next synthesis.
Illustratively, the method of manufacturing the system 500 further comprises: constraining a first trace between a signal input end to a starting point of the first time-to-digital converter 510; the second trace between the signal input end and the start of the second time-to-digital converter 513 is constrained. After the route of the wiring in the FPGA is fixed, the time delay of the wiring can be ensured to be fixed. By constraining the first trace and the second trace, the time delay of the signal to be measured to reach the first time-to-digital converter 510 and the second time-to-digital converter 513 is fixed.
And the internal signal of the FPGA can be used as a calibration signal to calibrate the two TDCs simultaneously, so that the delay chains of the two TDCs are obtained. In particular, a large number of random pulses may be included in the calibration signal. The time-to-digital converter outputs a code value for each pulse, and a delay chain is obtained according to the density of the code values. The number of delay units in the delay chain from the start and the length of each delay unit may be obtained, for example.
Referring to fig. 5 and 6, the method of manufacturing the system 500 further includes: the method S3000, S3000 of calibrating the time-to-digital conversion system includes the steps of:
s3010, calibrate the first delay chain of the first time-to-digital converter 510.
S3020, calibrating the second delay chain of the second time-to-digital converter 513.
S3030, adjusting a starting point of one of the first delay chain and the second delay chain such that, on the time axis, two ends of at least one delay unit of the first delay chain are located in two delay units of the second delay chain. The time length of each delay cell can be regarded as a half-open and half-closed interval, for example, when the time length of one delay cell is 9ps, and the end point time is 19ps, the covered interval is (10ps, 19 ps), that is, when the arrival signals are both output to 19 ps., the two ends of the delay cell of the first delay chain fall into two different intervals of the second delay chain.
S3040, writing the adjusted first delay chain into the first delay unit lookup table 511 to form a first comparison chain 3100.
S3050, writing the adjusted second delay chain into the second delay unit look-up table 514 to form a second comparison chain 3200.
In the step S3030, the structures of the delay chain along the time axis are different due to the difference of the actual carry chains in the FPGA. It is therefore desirable that as many delay units as possible in the delay chain span at least two delay units of the other delay chain, i.e. that the length of the delay units is subdivided by the other delay chain into at least two sections in the time axis.
Illustratively, the first delay chain includes long delay cells therein, the long delay cells having a length greater than an average length of the delay cells in the first delay chain. On a time axis, at least half of the long delay units in the first delay chain are arranged across at least two delay units of the second delay chain.
Referring to fig. 6, the right side in fig. 6 is the forward direction of the time axis. It can be considered that the starting point of the first delay chain is reset, and the first comparison chain 6100 formed is the same as the corresponding segment of the first delay chain. It can also be considered that the starting point of the second delay chain is reset, and a second alignment chain 6200 is formed. The first comparison chain 6100 and the second comparison chain 6200 are aligned in time to form a delay cell arrangement. It should be noted that the first comparison chain 6100 and the second comparison chain 6200 are used to represent time data on a time axis, and the lookup table stores data having a mapping relationship with the comparison chains rather than the illustrated graph.
Specifically, the data stored in the first delay cell lookup table includes: the time instant represented by each delay element in the first comparison chain relative to the start of the first comparison chain, and the time length of each delay element in the first comparison chain; all delay cells in the first comparison chain correspond one-to-one with all first delay cells in the first delay chain. The second delay cell lookup table works the same.
The fourth delay unit 6220 from the starting point 6201 of the second comparison chain 6200 is a long delay unit, which spans the third delay unit 6110, the fourth delay unit 6120 and the eighth delay unit of the first comparison chain 6100, i.e., which is subdivided into six segments by the first comparison chain 6100. Similarly, the first comparison chain 6100 also has long delay units subdivided by the second comparison chain 6200.
Illustratively, the starting point 6201 of the second alignment chain 6200 corresponds to a starting time, e.g., 100 ns. The delay lengths of the first delay element 6210 and the second delay element from the beginning of the second alignment chain 6200 are both 0.1 ns. The range of the first delay unit 6210 of the second alignment chain 6200 is (100ns, 100.1 ns), the reading is 100.1ns, it can be seen that the time corresponding to the third delay unit of the second alignment chain 6200 is 100.3ns, meanwhile, the time of the start point of the first alignment chain 6100 is 100ns, and the time of the third delay unit 6110 is the time of the end point 6102, that is, 100.4 ns.
The starting point change of the delay chain of the two TDCs is realized by locking logic resources and wiring of the FPGA. After the start of operation, the trigger pulse signal in the signal can reach two TDCs at the same time, and the time difference between the two TDCs can be obtained at the calibration time, so as to eliminate the trigger pulse signal. The delay cells triggered by the pulse signal may have different bit numbers in the delay chain. E.g., 100.435ns, the pulse signals are received by both TDCs simultaneously. The carry chain corresponding to the fourth delay unit 6220 in the second time-to-digital converter 513 is triggered, and the carry chain corresponding to the fourth delay unit 6120 in the first time-to-digital converter 510 is triggered.
It is to be understood that, in S6030, without adjusting the starting points of the first delay chain and the second delay chain, it is also possible to make at least one delay unit of the first delay chain cross at least two delay units of the second delay chain on the time axis.
In steps S3040 and S3050, the adjusted delay chain is written into a Look-Up Table (LUT) to form a delay unit Look-Up Table. The data in the delay cell lookup table is the time data corresponding to the delay cells of the delay chain. The data calling by using the delay unit lookup table is faster, and the computing resources are saved. But it is still possible to obtain an adjustment value by the processor after running S3030 and use the adjustment value to adjust the calculation for each delay unit.
In the system 500 for time-to-digital conversion made by the method of implementing a system based on an FPGA:
the first time-to-digital converter 510 is configured to output a first time when receiving a signal to be tested, where the first time is a time represented by a first delay unit corresponding to the signal to be tested in a first delay chain of the first time-to-digital converter 510;
the second time-to-digital converter 513 is configured to output a second time when receiving the signal to be tested, where the second time is a time represented by a second delay unit corresponding to the signal to be tested in a second delay chain of the second time-to-digital converter 513, and two ends of at least one delay unit of the first delay chain are located in two different delay units of the second delay chain on the time axis. Illustratively, the delay cells may be located in two non-adjacent delay cells of the second delay chain such that a long delay cell spans multiple delay cells.
One or more processors are in communication with the memory for executing the executable instructions stored in the memory. The executable instructions, when executed by one or more processors, may cause the one or more processors to implement a method for time-to-digital conversion.
Referring to fig. 7, an embodiment of the present application provides a method 4000 for time-to-digital conversion. The method 4000 may be implemented by the system 500 for time-to-digital conversion provided herein.
The method 4000 comprises the following steps:
and S4010, obtaining a first time to be selected. The first time to be selected is obtained based on a first time outputted by the first time-to-digital converter when receiving the signal to be measured, for example, the first time to be selected is equal to the first time. The first time is the time characterized by the first delay unit corresponding to the signal to be measured in the first delay chain of the first time-to-digital converter.
S4020, acquiring a second candidate moment. The second candidate time is obtained based on a second time output by the second time-to-digital converter when the signal to be detected is received, for example, the first candidate time is equal to the second candidate time. The second time is a time characterized by a second delay cell corresponding to the signal to be measured in a second delay chain of the second time-to-digital converter. Wherein, on the time axis, two ends of at least one delay unit of the first delay chain are positioned in two different delay units of the second delay chain.
And S4030, selecting the smaller one of the first candidate time and the second candidate time.
According to the method 4000, the time obtained by comparing the two TDCs is selected, and the measurement precision is improved compared with that of one TDC.
Further, the selected time may be a time represented by a longer delay unit, or a time represented by a shorter delay unit. When the time length of one delay unit is long, it can be subdivided by a plurality of delay units of another delay chain, i.e. both ends of it are located in two non-adjacent delay units of another delay chain. The signal under test may fall between the two non-adjacent delay cells.
Referring to fig. 8, the step S4030 of selecting a candidate time includes:
s4031, the time length of the first delay unit is determined.
S4032, the time length of the second delay unit is determined.
S4033, the minimum value of the time length of the first delay unit and the time length of the second delay unit is determined. If the time length of the first delay unit is equal to the time length of the second delay unit, either one of the time lengths, for example, the time length of the first delay unit, may be the minimum value.
S4034, select one of the first candidate time and the second candidate time whose corresponding time length is equal to the minimum value. For example, when the time length values corresponding to the two are equal, the first time to be selected is selected.
The method 4000 uses a differential non-linear compensation method to make the time interval measured by the system for time-to-digital conversion more detailed and uniform. The time obtained after the two TDCs are compared improves the measurement precision compared with one TDC. When the method 4000 measures a large number of times for a large number of pulses, the overall accuracy of these times is also high.
In the method 4000, the steps S4010 and S4020 are not in sequence. Steps S4031 and S4032 do not succeed.
In some embodiments, S4031 determining the length of time value for the first delay cell comprises: determining a time length of the first delay cell through a first delay cell look-up table, the first delay cell look-up table storing data including: the time instant represented by each delay element in the first comparison chain relative to the start of the first comparison chain, and the time length of each delay element in the first comparison chain. This length can be called up quickly because all delay cells in the first comparison chain have a one-to-one correspondence with all first delay cells in the first delay chain.
S4040 determining the time length of the second delay unit includes: and determining the time length of the second delay unit through a second delay unit lookup table, wherein the second comparison chain is stored in the second delay unit lookup table, and the action of the second delay unit lookup table refers to the first delay unit lookup table.
In a further embodiment, in step S4010, obtaining the first time to be selected includes: and obtaining a first time to be selected based on the first time through the first delay unit lookup table. The first time instant is characterized by a first delay chain. In practice, the time is obtained by adding the time lengths (i.e., a number of time periods) of all the delay units elapsed based on the time of the start of the first delay chain. Illustratively, the starting time of the first delay chain is not adjusted, and the first time to be selected is equal to the first time. Illustratively, the starting point of the first delay chain is adjusted, and the first time to be selected is the time characterized by the first comparison chain. Of course, the time instant characterized by the first comparison chain is obtained based on the first time instant.
The obtaining of the second candidate moment comprises: and obtaining a second candidate moment based on the second moment through a second delay unit lookup table.
For example, in figure 6, at 100.435ns, two TDCs have received pulse signals simultaneously. The carry chain of the fourth delay unit 6120 corresponding to the first comparison chain 6100 in the first time-to-digital converter 510 is triggered. The first delay unit lookup table 511 outputs 100.5ns as the first time instant to be selected based on the first time instant output by the first time-to-digital converter.
The carry chain of the fourth delay unit 6220 of the second time-to-digital converter 513 corresponding to the second comparison chain 6200 is triggered, and the second delay unit lookup table outputs the second candidate time 101.1ns based on the second time output by the second time-to-digital converter 513.
On the one hand, the first smaller moment to be selected is selected to be 100.5 ns.
On the other hand, the time length of the third delay unit 6120 of the first comparison chain 6100 is 0.1ns, and the time length of the fourth delay unit 6220 of the second comparison chain 6200 is 0.8 ns. It can be seen that the corresponding delay cells in the first comparison chain 6100 are shorter in time length.
The first moment to be selected is selected to be 100.5 ns. Can be used for subsequent operations or output.
In an exemplary embodiment, the method 4000 may include the method 3000 of calibrating a time-to-digital conversion system described previously. Specifically, the method 3000 may be executed first, and then the data obtained by the method 3000 may be called in the S4031 step and the S4032 step.
In an exemplary embodiment, the deviation caused by the operation of the TDC at different temperatures may be further corrected. The method 4000 further comprises: obtaining the temperature of the time-to-digital converter corresponding to the selected moment when the time-to-digital converter receives the signal to be measured; obtaining the number of delay units generated by a time-to-digital converter corresponding to the selected moment before receiving a signal to be detected; determining the temperature coefficient of the time-to-digital converter corresponding to the selected moment; and correcting the selected time based on the quantity, the temperature and the temperature coefficient.
For example, if the first time to be selected is selected, the first time to be selected is corrected based on the time data outputted from the first time-to-digital converter, the measured temperature thereof, and the temperature coefficient thereof. For example, under a certain temperature condition, the pulse at the time 102ns is output by the first time-to-digital converter to be 100ns, the first selected time is also 100ns, and the correction value at the temperature is calculated to be 1.8 ns. The first time instant to be selected after rectification is 101.8ns, which is used for subsequent processing.
Referring to fig. 8 on the basis of fig. 4, a hardware configuration diagram of a system 500 having a calibration-time digital conversion system function and/or a time digital conversion function is shown.
The system 500 includes: a first time to digital converter 510, a second time to digital converter 513, storage, and one or more processors. Illustratively, a first temperature sensor 518, a second temperature sensor 520 are also included.
The first time-to-digital converter 510 and the second time-to-digital converter 513 may be designed to be closer when actually disposed, and the first temperature sensor 518 may be configured to simultaneously detect the temperature of the first time-to-digital converter 510 and the temperature of the second time-to-digital converter 513. Illustratively, the first temperature sensor 518 is configured to detect a temperature of the first time-to-digital converter 510. The second temperature sensor 520 is configured to detect the temperature of the second time-to-digital converter 513. Wherein the memory further stores the temperature coefficient of the first time-to-digital converter 510 and the temperature coefficient of the second time-to-digital converter 513.
The memory may include Random Access Memory (RAM) internal to the FPGA and non-volatile memory external to the FPGA. The memory external to the FPGA may be a Flash memory (Flash memory) or a charged Erasable Programmable read only memory (EEPROM). Memory external to the FPGA may be used to store executable instructions and temperature coefficients for the first time-to-digital converter 510 and the second time-to-digital converter 513. And after the FPGA is electrified, the RAM is also used for storing executable instructions and temperature coefficients.
Illustratively, the RAM may include (Static Random-Access Memory, SRAM)502, a temperature coefficient lookup table 516, a first delay cell lookup table 511, and a second delay cell lookup table 514. The SRAM 102 is used for storing executable instructions, and the temperature coefficient lookup table 115 is used for storing temperature coefficients.
Illustratively, the one or more processors may comprise: logic units in the FPGA and the SOC processor 501. The logic unit is configured to communicate with the memory to execute the executable instructions to implement the operations shown in fig. 7 or fig. 8. And SOC processor 101 may be configured to process the correction time of day for transmission to an external device.
Specifically, the logic unit may include a data judging unit 512, a correcting processing unit 517, a first temperature collecting unit 519, and a second temperature collecting unit 521. The first temperature acquisition unit 519 is used for acquiring the temperature of the first time-to-digital converter 510 when receiving the signal to be measured, and may transmit the temperature to the correction processing unit 517 through the bus 503. The second temperature collecting unit 521 has the same function. The correction processing unit 112 is configured to receive the time data corresponding to the time selected by the data selection unit 512, the temperature coefficient output by the temperature and temperature coefficient lookup table 516, and output the corrected time to the SOC processor 501.
The system 500 for time-to-digital conversion provided by the present application may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle-mounted terminal (e.g., a car navigation terminal), etc., a fixed terminal such as a digital TV, a desktop computer, etc., and a dedicated detection device such as a machine vision system, etc. The time-to-digital conversion method adopted by the system 500 has high operation precision and high speed, and the obtained result can better eliminate DNL.
When the system 500 is built on an FPGA, the FPGA may have integrated therein a bus 103 and one or more processors, RAMs, TDCs, sensors, and input/output (I/O) interfaces 504 connected to the bus. Further, the system 500 may also include an output 506, a storage 507, a communication device 515, a drive 508 communicatively coupled to a removable medium 509, and the like.
While fig. 9 illustrates a system 500 for time-to-digital conversion having various components, it is to be understood that not all illustrated components are required to be implemented or provided. More or fewer components may alternatively be implemented or provided.
Illustratively, the first time-to-digital converter 510 includes a plurality of carry chains in a field programmable gate array that are constrained to be cascaded; the second time-to-digital converter 513 includes a further plurality of carry chains in the field programmable gate array that are cascaded in a constrained manner.
Illustratively, the first delay cell lookup table 511 is configured to output the first time to be selected based on the first time, and the first delay cell lookup table 511 stores a first comparison chain having the same structure as the first delay chain. The second delay unit lookup table 514 is configured to output a second candidate time based on the second time, and the second delay unit lookup table stores a second comparison chain, and the structure of the second comparison chain is the same as that of the second delay chain; wherein one or more processors are in communication with the memory to execute the executable instructions to implement the steps as shown in method 4000.
Illustratively, the system 500 further comprises: a first trace and a second trace that are constrained. The first trace is configured to electrically connect the first time-to-digital converter 510 and the input portion 505. The second trace is configured to electrically connect the second time-to-digital converter 513 and the input portion 505. The second trace and the first trace can have the same time delay. Specifically, SOC processor 501 may also transmit signals to the first trace and the second trace through bus 503.
The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea described above. For example, the above features and (but not limited to) features having similar functions in this application are mutually replaced to form the technical solution.
Claims (10)
1. A method of determining a temperature coefficient of a time-to-digital converter, comprising:
sending a calibration signal to a time-to-digital converter under at least three temperature conditions;
obtaining a reference moment of the calibration signal;
obtaining time data output by the time-to-digital converter under each temperature condition, wherein the time data comprise the time length of each delay unit to be calibrated;
obtaining the calibration temperature of the time-to-digital converter corresponding to each temperature condition through a temperature sensor;
determining a temperature coefficient of the time-to-digital converter based on the time data, the calibration temperature, and the reference time under the at least three temperature conditions.
2. The method of claim 1, wherein determining the temperature coefficient of the time-to-digital converter comprises:
fitting the formula Deltatb＝a2Kb 2+a1Kb+a0A in (a)0、a1And a2(ii) a Wherein, a0Is the zero order temperature coefficient, a1Is the first order temperature coefficient, a2Is the second order temperature coefficient, Δ tbIs the time length t of each delay unit to be calibrated when corresponding to the time databAnd a calibration correction value, K, between the time length t corresponding to the reference timebIs the calibration temperature;
wherein the zeroth order temperature coefficient, the first order temperature coefficient, and the second order temperature coefficient constitute the temperature coefficient of the time-to-digital converter.
3. A method for time-to-digital conversion, comprising:
obtaining the temperature of the time-to-digital converter when receiving a signal to be measured;
obtaining time data corresponding to the signal to be detected through the time-to-digital converter;
determining a temperature coefficient corresponding to the time-to-digital converter; and
determining a corrected time corresponding to the signal to be measured based on the time data, the temperature, and the temperature coefficient.
4. A system for time-to-digital conversion, comprising:
a time-to-digital converter for generating time data corresponding to a signal to be measured;
a temperature sensor configured to detect a temperature of the time-to-digital converter;
a memory storing executable instructions and a temperature coefficient of the time-to-digital converter; and
one or more processors in communication with the memory to execute the executable instructions to implement the method of any of claims 5-9.
5. A method of deskewing a time-to-digital conversion system, comprising the steps of:
calibrating a first delay chain of a first time-to-digital converter, wherein the first time-to-digital converter is realized based on a carry chain of which a part inside an FPGA is restricted;
calibrating a second delay chain of a second time-to-digital converter, the second time-to-digital converter implemented based on a carry chain to which another portion inside the FPGA is constrained;
adjusting a starting point of one of the first delay chain and the second delay chain such that, on a time axis, both ends of at least one delay cell of the first delay chain are located in different delay cells of the second delay chain;
writing the adjusted first delay chain into a first delay unit lookup table to form a first comparison chain;
and writing the adjusted second delay chain into a second delay unit lookup table to form a second comparison chain.
6. A method for time-to-digital conversion, comprising:
obtaining a first time to be selected, wherein the first time to be selected is equal to a first time output by a first time digital converter when receiving a signal to be detected, and the first time is a time represented by a first delay unit corresponding to the signal to be detected in a first delay chain of the first time digital converter;
obtaining a second candidate time, where the second candidate time is equal to a second time output by a second time-to-digital converter when receiving a signal to be detected, and the second time is a time represented by a second delay unit corresponding to the signal to be detected in a second delay chain of the second time-to-digital converter, where, on a time axis, two ends of at least one delay unit of the first delay chain are located in different delay units of the second delay chain;
and selecting the smaller one of the first time to be selected and the second time to be selected.
7. The method of claim 6, wherein both ends of at least one delay cell of the first delay chain are located in two non-adjacent delay cells of the second delay chain;
when the second delay unit corresponding to the signal to be measured is located between the two non-adjacent delay units, the selecting step includes:
determining a time length of the first delay cell;
determining a time length of the second delay cell;
determining a minimum value of the time length of the first delay unit and the time length of the second delay unit;
and selecting one of the first time to be selected and the second time to be selected, wherein the corresponding time length is equal to the minimum value.
8. A system for time-to-digital conversion, comprising:
a first time-to-digital converter configured to output a first time instant when receiving a signal under test, the first time instant being a time instant characterized by a first delay cell corresponding to the signal under test in a first delay chain that the first time-to-digital converter has;
a second time-to-digital converter configured to output, when receiving a signal to be measured, a second time instant characterized by a second delay unit corresponding to the signal to be measured in a second delay chain of the second time-to-digital converter, wherein, on a time axis, at least one delay unit of one of the first delay chain and the second delay chain spans over at least two delay units of the other;
a memory storing executable instructions; and
one or more processors in communication with the memory to execute the executable instructions to implement the method of any of claims 15-20.
9. The system of claim 8, further comprising:
a first delay cell lookup table configured to output a first time to be selected based on the first time, the first delay cell lookup table storing data including: a time instant represented by each delay element in a first comparison chain relative to a start point of the first comparison chain, and a time length of each delay element in the first comparison chain; all delay units in the first comparison chain correspond to all first delay units in the first delay chain one to one; and
a second delay cell lookup table configured to output a second candidate time based on the second time, the second delay cell lookup table storing data including: a time instant represented by each delay unit in the second comparison chain relative to a start point of the second comparison chain, and a time length of each delay unit in the second comparison chain; all delay units in the second comparison chain correspond to all second delay units in the second delay chain one to one;
wherein the one or more processors are in communication with the memory to execute the executable instructions to perform:
obtaining the first time to be selected based on the first time through the first delay unit lookup table; and
and obtaining the second candidate time based on the second time through the second delay unit lookup table.
10. A lidar, comprising: a time to digital conversion system as claimed in any one of claims 4, 8 or 9.
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