CN114620672A

CN114620672A - Micro-electro-mechanical system device, micro-electro-mechanical system accelerometer and forming method thereof

Info

Publication number: CN114620672A
Application number: CN202110423645.6A
Authority: CN
Inventors: 陈亭蓉; 林诗玮
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2021-02-22
Filing date: 2021-04-20
Publication date: 2022-06-14
Also published as: TWI809380B; US20230249963A1; US20220267145A1; US11634320B2; TW202233511A

Abstract

A semiconductor oxide plate is formed on a recessed surface in the semiconductor host material layer. A plurality of comb structures are formed in the layer of semiconductor matrix material. The plurality of comb structures includes a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion laterally surrounding the first semiconductor portion is selectively removed relative to the plurality of comb structures using an isotropic etch process. The semiconductor oxide plate, the pair of comb structures, and the patterned etch mask layer covering the comb structures protect the first semiconductor portion from an etchant of an isotropic etch process. Forming a movable structure for the MEMS device, the movable structure comprising a first portion of the layer of semiconductor matrix material in combination with the pair of inner comb structures.

Description

Micro-electro-mechanical system device, micro-electro-mechanical system accelerometer and forming method thereof

Technical Field

Embodiments of the present disclosure relate to microelectromechanical systems devices and methods of forming the same.

Background

Micro-electro mechanical system (MEMS) devices include devices fabricated using semiconductor technology to form mechanical and electrical features. MEMS devices can include moving parts having micron or submicron dimensions and mechanisms for electrically coupling the moving parts to electrical signals. The electrical signal may be an input signal that induces movement of the moving part or an output signal that results from movement of the moving part. MEMS devices are useful devices that can be integrated with other devices (e.g., semiconductor devices) to act as sensors or actuators.

Disclosure of Invention

The embodiment of the present disclosure provides a micro electro mechanical system device, which includes: a movable structure located in a laterally confined space, wherein the movable structure comprises a central mass portion and a first movable comb structure comprising an inner comb shaft portion fitted to a first sidewall of the central mass portion and a plurality of first movable comb fingers projecting laterally from the inner comb shaft portion, wherein: the central mass portion comprises a portion of a first semiconductor material; a semiconductor oxide plate comprising an oxide of the first semiconductor material covering the entire bottom surface of the central mass portion; and the first movable comb structure comprises a dielectric liner physically exposed to a cavity within a matrix and a conductive fill material portion located within the inner comb shaft portion and extending continuously into each of the plurality of first movable comb fingers and laterally surrounded by the dielectric liner.

The disclosed embodiment provides a micro-electromechanical system accelerometer, which is characterized by comprising: a movable structure located in a laterally confined space, wherein the movable structure comprises a central mass portion comprising a portion of a first semiconductor material, a first movable comb structure fixed on a first side of the central mass portion, and a second movable comb structure fixed on a second side of the central mass portion, wherein each of the first and second movable comb structures comprises a respective comb shaft portion and respective sets of a plurality of movable comb fingers projecting laterally from the respective comb shaft portion; a first fixed comb structure fixed on a first sidewall of the laterally confined space and comprising a plurality of first fixed comb fingers interleaved with the plurality of movable comb fingers of the respective sets of the first movable comb structure; a second fixed comb structure fixed to a second sidewall of the laterally confined space and comprising a plurality of second fixed comb fingers interleaved with the plurality of second movable comb fingers; and a semiconductor oxide plate comprising an oxide of the first semiconductor material and covering an entire bottom surface of the central mass portion.

An embodiment of the present disclosure provides a method for forming a mems device, including: forming a recessed surface by recessing a region of the first horizontal surface of the semiconductor base material layer; forming a semiconductor oxide plate on the recessed surface; forming a plurality of comb structures extending from a second horizontal surface of the layer of semiconductor matrix material toward the first horizontal surface, wherein the plurality of comb structures comprises a pair of inner comb structures laterally spaced apart by a first portion of the layer of semiconductor matrix material and a pair of outer comb structures interleaved with the pair of inner comb structures; and selectively removing a second portion of the semiconductor matrix material layer laterally surrounding the first portion of the semiconductor matrix material layer relative to the plurality of comb structures using an isotropic etch process, wherein the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer protect the first portion of the semiconductor matrix material layer from an etchant of the isotropic etch process, the patterned etch mask layer being located on the second horizontal surface and covering the plurality of comb structures.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a vertical cross-sectional view of an exemplary structure including a semiconductor matrix material layer after forming a recessed cavity according to an embodiment of the present disclosure.

FIG. 1B is a horizontal cross-sectional view of an exemplary structure taken along the horizontal plane B-B' shown in FIG. 1A.

Fig. 2 is a vertical cross-sectional view of an exemplary structure after forming diffusion barrier spacers (diffusion barrier spacers) at the periphery of a recessed cavity, in accordance with an embodiment of the present disclosure.

Fig. 3 is a vertical cross-sectional view of an exemplary structure after forming a semiconductor oxide panel in accordance with an embodiment of the present disclosure.

Fig. 4 is a vertical cross-sectional view of an exemplary structure after removal of a diffusion barrier spacer in accordance with an embodiment of the present disclosure.

Fig. 5A is a vertical cross-sectional view of an exemplary structure after bonding a layer of semiconductor host material to a handle substrate according to an embodiment of the disclosure.

FIG. 5B is a horizontal cross-sectional view of an exemplary structure taken along the plane B-B' shown in FIG. 5A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 5A.

Fig. 6A is a vertical cross-sectional view of an exemplary structure after forming a comb and moat trench (moat trench), in accordance with an embodiment of the present disclosure.

FIG. 6B is a horizontal cross-sectional view of an exemplary structure taken along the plane B-B' shown in FIG. 6A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 6A.

Fig. 7A is a vertical cross-sectional view of an exemplary structure after forming a comb structure and a wall structure according to an embodiment of the disclosure.

FIG. 7B is a horizontal cross-sectional view of an exemplary structure taken along the plane B-B' shown in FIG. 7A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 7A.

Fig. 8A is a vertical cross-sectional view of an example structure after forming a metal material portion, according to an embodiment of the present disclosure.

FIG. 8B is a top view of an exemplary structure along the plane B-B' shown in FIG. 11A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 11A.

Figure 9A is a vertical cross-sectional view of an exemplary structure after forming a patterned etch mask layer, in accordance with an embodiment of the present disclosure.

Fig. 9B is a partial perspective top view of the exemplary structure shown in fig. 9A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 9A.

Fig. 10A is a vertical cross-sectional view of an exemplary structure after isotropic etching of unmasked portions of the semiconductor matrix material layer selective to the patterned etch mask layer, the comb structure, the moat fill structure, and the semiconductor oxide plate, in accordance with an embodiment of the present disclosure.

FIG. 10B is a horizontal cross-sectional view of an exemplary structure taken along the plane B-B' shown in FIG. 9A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 9A.

Fig. 11A is a vertical cross-sectional view of an exemplary structure after removal of a patterned etch mask layer in accordance with an embodiment of the present disclosure.

FIG. 11B is a top view of an exemplary structure along the plane B-B' shown in FIG. 11A. The hinge-type vertical plane a-a' is a plane of the vertical sectional view shown in fig. 11A.

Figure 12 is a vertical cross-sectional view of an accelerometer formed by peeling apart a handle substrate and singulating an exemplary structure into a plurality of accelerometers according to an embodiment of the disclosure.

Fig. 13 is a flow diagram illustrating a set of processing steps that may be performed to form a MEMS device in accordance with an embodiment of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below …", "below …", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

Many MEMS devices utilize accurate proof masses to accurately measure physical parameters. For example, accelerometers convert the displacement of a movable element into acceleration by, for example, measuring a change in capacitance induced by the displacement of the movable element. The displacement of the movable element is proportional to the force applied to the movable element, which is proportional to the mass of the proof mass element within the movable element. Process variations of the isotropic etch process may result in variations in the quality of the proof mass elements. Variations in the proof mass of the mass element may result in variations (i.e., inaccuracies) in the acceleration measurements. Thus, a precision proof mass element with reduced mass variations that may be caused by the fabrication process may enhance precision measurements in some MEMS devices.

Embodiments of the present disclosure generally relate to microstructures including micro-electromechanical system (MEMS) devices. The MEMS device includes a proof mass for measuring movement of an object to which the MEMS device is attached. For example, the MEMS device may include an accelerometer. Embodiments of the present disclosure may be used to form high precision proof masses for MEMS devices.

In particular, a semiconductor host material layer may be provided, the semiconductor host material layer comprising a semiconductor material to be subsequently patterned into movable structures including proof masses and a semiconductor host layer comprising cavities within which the movable structures may be confined. A surface portion of the semiconductor matrix layer may be recessed from the first horizontal surface in a vertical direction to form a recessed cavity. Diffusion barrier spacers (e.g., silicon nitride spacers) may be formed on the sidewalls of the recessed cavity. An oxidation process may be performed to form a first semiconductor oxide plate on the recessed horizontal surface of the recessed cavity and a second semiconductor oxide plate on the non-recessed portion of the first horizontal surface of the semiconductor matrix material layer. The diffusion barrier spacer may be removed selectively with respect to the semiconductor oxide plate using an isotropic selective etch process. The second semiconductor oxide plate may be bonded to a handle substrate.

The comb trenches can be formed from the second horizontal surface of the semiconductor matrix material layer toward the first horizontal surface of the semiconductor matrix material layer. The comb grooves may include two pairs of staggered respective inner and outer comb grooves. A first portion of the semiconductor matrix material layer that is subsequently patterned into a proof mass (i.e., a central mass portion) may be located between the two inner comb grooves. The outer comb grooves may be connected by comb shaft extension grooves. The outer comb grooves and the comb shaft extension grooves jointly surround all the inner comb grooves and define lateral boundaries for a cavity to be subsequently formed. The common comb shaft cavity portion may define a boundary of a cavity in which the formed movable element is subsequently laterally confined. A dielectric liner layer and a conductive fill material may be deposited in the comb trenches, and excess portions of the dielectric liner layer and the conductive fill material above a level including a top surface of the semiconductor matrix material layer may be removed by a planarization process. The remaining portion of the dielectric liner layer and the remaining portion of the conductive fill material in each comb trench comprise comb structures. The comb structure includes an inner comb structure formed in the inner comb groove and an outer comb structure formed in the outer comb groove.

An etch mask layer (e.g., a photoresist layer) can be formed over the second horizontal surface of the semiconductor matrix material layer and can be patterned to provide openings in regions surrounded by the common comb shaft portions of the outer comb structure. The openings can be formed in regions not overlying the comb structures such that each comb structure is covered by a patterned etch mask layer. An isotropic etching process may be used to etch a second portion of the semiconductor matrix material layer outside of the comb structures and within the area surrounded by the common comb shaft portion of the outer comb structure. The first semiconductor oxide plate, the inner comb structure, and the patterned etch mask layer protect a first portion of the semiconductor matrix material layer during the isotropic etch process. Specifically, the first semiconductor oxide plate protects the first portion of the layer of semiconductor matrix material from below, which becomes the proof mass structure, and thus the first portion has a uniform thickness through a major portion thereof.

The movable structure including the central mass portion, the inner comb structure, and the outer comb structure can be peeled off from the second semiconductor oxide plate. The volume of material of the layer of semiconductor material that can be etched forms a cavity that is laterally bounded by the portion of the common comb shaft of the outer comb structure. The semiconductor die, including suitable electrical contact structures for the comb structure, may be attached to a semiconductor substrate layer, which is the remainder of the semiconductor substrate material layer that is outside of the cavity. The semiconductor die may include suitable contact structures that may electrically bias portions of the comb structure in a configuration that provides a capacitor structure. The capacitor structure may be configured in any configuration that produces a change in capacitance when the movable structure moves relative to the fixed structure including the outer comb structure. The microstructures may include an accelerometer that can measure the acceleration of a system to which the microstructures are attached. Various aspects of embodiments of the disclosure are set forth in further detail below.

Referring to fig. 1A and 1B, showing the semiconductor matrix material layer 10, the semiconductor matrix material layer 10 may be provided as a planar structure comprising a first horizontal surface 101 on a first side and a backside surface (i.e., a second horizontal surface) on a second side, having a uniform thickness throughout the planar structure, but is not necessarily limited thereto. The layer of semiconductor host material 10 comprises a first semiconductor material, which may be a single crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the layer of semiconductor host material 10 may comprise a single crystal semiconductor layer, such as a single crystal silicon layer. The uniform thickness of the layer of semiconductor matrix material 10 may range from 30 microns to 1 millimeter (mm), such as from 100 microns to 600 microns. Although the regions used to form a single accelerometer are shown in fig. 1A and 1B, it should be understood that a two-dimensional array of accelerometers may be formed on a single wafer. Thus, the patterns shown in fig. 1A and 1B may be repeated in a two-dimensional array of patterns over the layer of semiconductor substrate material 10.

A photoresist layer (not shown) may be applied over the first horizontal surface 101 of the layer of semiconductor host material 10 and may be photolithographically patterned to form an opening having the general shape of a proof mass (also referred to as a central mass portion) to be subsequently formed. In one embodiment, the periphery of the opening in the photoresist layer may be laterally offset outward from the periphery of a subsequently to-be-formed proof mass by a lateral offset distance, which may range, for example, from 0.5 microns to 30 microns. Accordingly, the region of the opening in the photoresist layer may have a larger area than the region (a _ PM) of the detection quality to be formed later. In a non-limiting illustrative example, the openings in the photoresist layer may have an elongated rounded rectangular shape with a longitudinal dimension in a range from 300 microns to 6mm and a lateral dimension in a range from 30 microns to 600 microns, although smaller and larger dimensions may also be used.

The pattern of openings in the photoresist layer may be transferred into the upper portion of the layer of semiconductor matrix material 10 by an etching process, which may include an anisotropic etching process or an isotropic etching process. A recessed cavity 13 may be formed which is recessed in a vertical direction from the first horizontal surface 101 of the semiconductor substrate material layer 10. A recessed horizontal surface may be provided at the bottom of the recessed cavity 13. The recess depth of the recess cavity 13 may range from 0.3 microns to 10 microns, such as from 0.6 microns to 5 microns, although smaller recess depths and larger recess depths may also be used. The recess cavity 13 has sidewalls 13S, the sidewalls 13S connecting the recess bottom surface 13R of the recess cavity 13 to the un-recessed portion of the first horizontal surface 101 of the semiconductor matrix material layer 10. The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 2, a diffusion barrier spacer 11 (also referred to as a blocking spacer) comprising a diffusion barrier material may be formed at the periphery of the recessed cavity 13. The diffusion barrier spacer 11 comprises a material that blocks the diffusion of oxygen through the diffusion barrier spacer 11. For example, the diffusion barrier spacer 11 may comprise and/or may consist essentially of silicon nitride. Other suitable materials are also within the intended scope of the present disclosure. In some embodiments, the blocking spacer 11 may be any material and is configured to protect the sidewalls 13S of the recessed cavity 13 from subsequently formed semiconductor oxide slabs (

slabs

12A and 12B in fig. 3). The diffusion barrier spacer 11 may be formed, for example, by conformally depositing a layer of diffusion barrier material, such as a silicon nitride layer or a metal nitride layer comprising a metal nitride material (TaN, TiN or WN), on the recess bottom surface 13R and sidewalls 13S of the recess cavity 13 and on the non-recessed portions of the first horizontal surface 101 of the semiconductor matrix material layer 10. In other embodiments, diffusion barrier spacers 11 may be formed by denaturing portions of the layer of semiconductor matrix material 10. The thickness of the diffusion barrier material layer may range from 30nm to 200nm, although lesser and greater thicknesses may also be used. An anisotropic etch process may be performed to remove horizontal portions of the diffusion barrier material layer deposited on the recessed bottom surface of the recessed cavity and on the un-recessed portions of the first horizontal surface 101 of the semiconductor substrate material layer 10. The remaining vertical portions of the diffusion barrier material layer constitute diffusion barrier spacers 11. In one embodiment, each sidewall 13S of the recessed cavity 13 may contact a respective outer sidewall of the diffusion barrier spacer 11. The diffusion barrier spacer 11 may have a substantially tubular shape and may therefore be topologically homeomorphic to a torus, i.e., may be continuously deformed into a torus without creating new holes or destroying pre-existing holes.

Referring to fig. 3, an oxidation process may be performed to deposit the semiconductor substrate material layer 10 at the bottom and half of the concave cavity 13The physically exposed surface portions on the unrecessed portions of the conductive matrix material layer 10 are converted into semiconductor oxide plates (12A, 12B). For example, a thermal oxidation process may be performed to convert the physically exposed surface portions of the semiconductor base material layer 10 into semiconductor oxide material portions. The diffusion barrier spacer 11 prevents oxygen atoms from diffusing through the diffusion barrier spacer 11 to the semiconductor base material layer 10, thereby forming sidewalls of the recessed cavity 13 during the oxidation process. The thermal oxidation process may employ a dry oxidation process, a wet oxidation process, or a rapid thermal oxidation process. For example, dry oxidation is carried out using O₂Thermal oxidation process as an oxidizing agent. The wet oxidation is carried out by using H₂Thermal oxidation with O as the oxidant. Rapid thermal oxidation is a thermal oxidation process that employs a single wafer processing chamber and provides thermal oxidation at high temperatures.

The first semiconductor oxide plate 12A may be formed at the bottom of the recessed cavity 13 by converting the underlying surface portion of the semiconductor matrix material layer 10 into a dielectric semiconductor oxide material portion. A second semiconductor oxide plate 12B may be formed on the first horizontal surface 101 of the un-recessed portion of the layer of semiconductor matrix material 10 by converting the underlying surface portion of the layer of semiconductor matrix material 10 into an additional dielectric semiconductor oxide material portion. The thickness of the first and second semiconductor oxide plates (12A, 12B) may range from 50nm to 500nm, although lesser and greater thicknesses may also be used. In one embodiment, if the semiconductor matrix material layer 10 comprises any material other than silicon (e.g., a silicon-germanium alloy or a III-V compound semiconductor material), the first and second semiconductor oxide plates (12A, 12B) may comprise and/or may consist essentially of silicon oxide or an oxide of the semiconductor material of the semiconductor matrix material layer 10.

Referring to fig. 4, the diffusion barrier spacers 11 may be removed selectively with respect to the material of the first and second semiconductor oxide plates (12A, 12B) and the material of the semiconductor matrix material layer 10. For example, if diffusion barrier spacer 11 comprises silicon nitride, a wet etch process using hot phosphoric acid may be performed to remove diffusion barrier spacer 11 selectively to the material of the first and second semiconductor oxide plates (12A, 12B) and the material of semiconductor base material layer 10. The semiconductor surface of the semiconductor substrate material layer 10 may be physically exposed at the sidewalls of the recessed cavity 13.

Referring to fig. 5A and 5B, the semiconductor host material layer 10 may be bonded to the handle substrate 20 through the second semiconductor oxide plate 12B. The handle substrate 20 may include a semiconductor substrate, a conductive substrate, a dielectric substrate, or a combination thereof. Handle substrate 20 may have a thickness sufficient to provide structural support during subsequent thinning of semiconductor base material layer 10. For example, the thickness of the handle substrate 20 may range from 60 microns to 1 mm.

The horizontal top surface of the handle substrate 20 comprises a material that can be bonded to the semiconductor oxide material of the second semiconductor oxide plate 12B. The second plate of semiconductor oxide 12B may be bonded to the handle substrate 20 by bonding the second plate of semiconductor oxide 12B to the handle substrate 20. The second semiconductor oxide plate 12B may be bonded to the horizontal top surface of the handle substrate 20 using a suitable bonding method. For example, if the handle substrate 20 includes a semiconductor top surface, the handle substrate 20 may be bonded to the second semiconductor oxide plate 12B using a semiconductor-to-oxide bond (e.g., a silicon-to-silicon oxide bond). Alternatively, if the handle substrate 20 includes a top semiconductor oxide surface (e.g., a top silicon oxide surface), the handle substrate 20 may be bonded to the second semiconductor oxide plate 12B using an oxide-to-oxide bond (e.g., a silicon oxide-to-silicon oxide bond). The semiconductor-to-oxide bonding or oxide-to-oxide bonding may be performed by an annealing process at an elevated temperature, which may range from 200 degrees celsius to 600 degrees celsius.

The layer of semiconductor matrix material 10 may then be thinned by grinding, polishing and/or etching the back side surface of the layer of semiconductor matrix material 10 on the opposite side of the second semiconductor oxide plate 12B. The final step of the thinning process may include a polishing step that provides a horizontal planar surface on the back side (i.e., polished side) of the layer of semiconductor matrix material 10. The polished back side surface of the layer of semiconductor matrix material 10 is referred to herein as the second horizontal surface 102. The thickness t of the layer of semiconductor matrix material 10, measured between the second horizontal surface 102 and the first horizontal surface 101 contacting the second semiconductor oxide plate 12B, may range from 2 to 60 microns, such as from 4 to 30 microns, although lesser and greater thicknesses may also be used. The lower limit of the thickness t of the semiconductor matrix material layer 10 may be imposed by the minimum capacitance requirements of the capacitor structure to be subsequently formed, and the upper limit of the thickness t of the semiconductor matrix material layer 10 may be imposed by the process capability and economic feasibility of the subsequent etching process for forming the comb trenches through the semiconductor matrix material layer 10.

Referring to fig. 6A and 6B, a photoresist layer 37 may be applied over the second horizontal surface 102 of the layer of semiconductor matrix material 10 and the photoresist layer 37 may be photolithographically patterned to form an opening through the photoresist layer 37. The pattern of openings in photoresist layer 37 may include two staggered comb patterns. Each interleaved comb pattern may include an inner comb pattern (CPI1 or CPI2) and an outer comb pattern (CPO1 or CPO 2). The first interleaved comb patterns (CPI1, CPO1) include a first inner comb pattern CPI1 and a first outer comb pattern CPO 1. The second interleaved comb patterns (CPI2, CPO2) include a second inner comb pattern CPI2 and a second outer comb pattern CPO 2.

Each inner comb pattern (CPI1 or CPI2) includes a respective comb axis pattern and a respective comb tooth pattern that may be adjacent to the respective comb axis pattern. Each comb-axis pattern of the inner comb patterns (CPI1, CPI2) may extend laterally along the first horizontal direction hd1, with or without lateral undulations. Each outer comb pattern (CPO1 or CPO2) includes a respective comb axis pattern and a respective comb tooth pattern that can be contiguous with the respective comb axis pattern. Each comb axis pattern of the outer comb patterns (CPO1, CPO2) may extend laterally along the first horizontal direction hd1, with or without lateral undulations. The comb axis pattern within the outer comb pattern (CPO1, CPO2) may be contiguous with a comb axis extension pattern CSEP extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. Specifically, the end segments (end segments) of each of the comb axis patterns within the outer comb patterns (CPO1, CPO2) may be contiguous with the end segments of the comb axis extension pattern CSEP such that the set of comb axis patterns within the outer comb patterns (CPO1, CPO2) and the comb axis extension pattern CSEP collectively form a generally rectangular shape that defines the outer boundaries of the cavities that will subsequently be formed in the semiconductor matrix material layer 10.

The two interleaved comb patterns may be arranged such that the two inner comb patterns (CPI1, CPI2) are close to each other and the two outer comb patterns (CPO1, CPO2) are far from each other. In other words, the lateral separation distance along the second horizontal direction hd2 between the comb-axis patterns of the two outer comb patterns (CPO1, CPO2) is greater than the lateral separation distance between the comb-axis patterns of the two inner comb patterns (CPI1, CPI 2).

An elongated region masked by the photoresist layer 37 may be disposed between the comb axis patterns of the two inner comb patterns (CPI1, CPI2), including the region in which the proof mass (i.e., central mass portion) will be subsequently patterned from the layer of semiconductor substrate material 10. The opening in photoresist layer 37 may include a proof-mass barrier pattern PMBP located at the boundary of the region in which the proof mass will subsequently be formed. The comb axis pattern of the two inner comb patterns (CPI1, CPI2) may have an extended portion wrapped around the detection mass barrier pattern PMBP to provide an etchant confinement structure (etchal confinement structure) that prevents lateral etching of the portion of the semiconductor substrate material layer 10 around the detection mass barrier pattern PMBP.

Each of the comb tooth patterns in the inner comb patterns (CPI1, CIP2) and the outer comb patterns (CPO1, CPO2) includes a plurality of comb tooth patterns parallel to each other. Each comb tooth pattern extends laterally away from the respective comb axis pattern along a common longitudinal direction of the comb tooth pattern. Each tooth pattern may be elongated along a longitudinal direction and may have a dry region (stem region) having a substantially uniform width and conforming to a respective comb axis pattern. Each tooth pattern may also have tip sections with a gradually decreasing width with distance from the respective comb axis pattern. The common longitudinal direction of the comb tooth patterns within the comb tooth pattern may be angled in a range from 1 degree to 10 degrees (e.g. from 2 degrees to 8 degrees) with respect to the second horizontal direction hd2 to optimize the capacitance variation of the capacitor structure to be subsequently formed as a function of the displacement of the movable structure to be subsequently formed. The tip segment of each comb tooth pattern can advantageously be used to increase the change in capacitance during displacement of the movable structure (i.e., the central mass portion) to be subsequently formed.

The comb-tooth patterns of the first inner comb pattern CPI1 and the comb-tooth patterns of the first outer comb pattern CPO1 may be staggered in parallel longitudinal directions for all of the comb-tooth patterns of the first inner comb pattern CPI1 and the first outer comb pattern CPO 1. The interleaved area may include tip segments of the first inner comb pattern CPI1 and comb tooth patterns of the first outer comb pattern CPO 1. Also, the comb-tooth patterns of the second inner comb pattern CPI2 and the comb-tooth patterns of the second outer comb pattern CPO2 may be staggered in the parallel longitudinal direction for all of the comb-tooth patterns of the second inner comb pattern CPI2 and the second outer comb pattern CPO 2. The interleaved region may include tip segments of the second inner comb pattern CPI2 and comb tooth patterns of the second outer comb pattern CPO 2. The longitudinal direction of the comb-tooth patterns of the second inner comb pattern CPI2 and the comb-tooth patterns of the second outer comb pattern CPO2 may be inclined in a direction opposite to the second horizontal direction hd2 with respect to the longitudinal direction of the comb-tooth patterns of the first inner comb pattern CPI1 and the comb-tooth patterns of the first outer comb pattern CPO 1. The overall pattern of openings in photoresist layer 37 may have a Mirror Symmetry Plane (MSP) extending along first horizontal direction hd 1.

In one embodiment, in a top view, the area where the quality of detection will subsequently be formed and the areas of some portions of the two inner comb patterns (CPI1, CPI2) extending along the first horizontal direction hd1 may be located between a pair of longitudinal sidewalls of the first semiconductor oxide board 12A. Although the present disclosure is illustrated using an embodiment in which an accelerometer is illustrated, and the pattern of openings in photoresist layer 37 is optimized for forming an accelerometer, the methods of the present disclosure may be used to form any microstructure that includes a movable structure that includes a proof mass (i.e., a movable center mass). As such, the design of the openings in photoresist layer 37 may or may not be symmetrical. Further, although the present disclosure is illustrated using two sets of staggered patterns, a single staggered comb structure or three or more staggered comb structures of microstructures, which can be MEMS devices, can be formed using a single staggered pattern or three or more staggered patterns. In general, the proof mass may be formed within a region defined by the periphery of the first semiconductor oxide plate 12A.

Further, the pattern in the photoresist layer 37 may include a pattern of regions of the moat groove laterally surrounding the comb tooth pattern of the first inner comb pattern CPI1 and the comb tooth pattern of the first outer comb pattern CPO 1. For example, the pattern of moats may include: a pattern of proximal moat grooves, a region laterally surrounding the moat grooves, the region laterally surrounding the comb-tooth pattern of the first inner comb pattern CPI1 and the comb-tooth pattern of the first outer comb pattern CPO 1; a pattern of intermediate moats laterally encircling the pattern of proximal moats; a pattern of distal moat trenches laterally surrounding the pattern of middle moat trenches; and a pattern of suspension spring moat grooves (suspension spring moat grooves) connecting a respective pair of segments of the pattern of proximal moat grooves with the pattern of the comb shaft portion.

An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer 37 through the upper portion of the semiconductor base material layer 10. The anisotropic etch process may be a reactive ion etch process that etches unmasked portions of the layer of host semiconductor material 10 and thus replicates the pattern of openings in the photoresist layer in upper portions of the layer of semiconductor host material 10. Comb grooves (31, 41, 51) are formed through an upper portion of the semiconductor base material layer 10. Each of the comb trenches extends from the second horizontal surface 102 of the semiconductor substrate material layer 10 towards the first horizontal surface 101 of the semiconductor substrate material layer 10. In one embodiment, the comb grooves (31, 41, 51) extend in a vertical direction to a horizontal plane including the top surface of the first semiconductor oxide plate 12A, i.e., a horizontal plane including a horizontal interface between the first semiconductor oxide plate 12A and the semiconductor host material layer 10. The anisotropic etch process may have a material selectivity for the first semiconductor oxide plate 12A relative to the materialAn etch chemistry that etches the semiconductor material of the semiconductor matrix material layer 10. For example, the anisotropic etch process may have the use of HBr/NF₃/O₂/SF₆The etch chemistry of (a).

Two interleaved comb grooves can be formed that replicate the pattern of the two interleaved comb patterns. Each of the interleaved comb slots may include an inner comb slot 31 and an outer comb slot 41. The first interleaved comb grooves include a first inner comb groove 311 and a first outer comb groove 411 on one side of a Mirror Symmetry Plane (MSP). The second interleaved comb grooves include a second inner comb groove 312 and a second outer comb groove 412 on opposite sides of a Mirror Symmetry Plane (MSP).

Each inner comb groove 31 includes a respective comb groove shaft portion which reproduces a comb shaft pattern and a respective comb groove tooth portion which reproduces a comb tooth pattern and is contiguous to the respective comb groove shaft portion. Each comb groove shaft portion of the inner comb groove 31 may extend laterally along the first horizontal direction hd1 with or without lateral undulations. Each outer comb groove 41 includes a respective comb groove shaft portion which reproduces a comb shaft pattern and a respective comb groove tooth portion which reproduces a comb tooth pattern and is contiguous with the respective comb groove shaft portion. Each comb groove shaft portion of the outer comb grooves 41 may extend laterally along the first horizontal direction hd1 with or without lateral undulations. The comb groove shaft portion in the outer comb groove 41 may be contiguous with the comb groove extension portion 43 extending in the lateral direction along the second horizontal direction hd 2. Specifically, the end segments of each of the comb groove shaft portions within the outer comb grooves 41 may be contiguous with the end segments of the comb groove extension 43 such that the set of comb groove shaft portions within the outer comb grooves 41 and the comb groove extension 43 together form a generally rectangular shape that defines the outer boundary of a cavity that will subsequently be formed in the semiconductor matrix material layer 10.

The two interleaved comb grooves (31, 41) may be arranged such that the two inner comb grooves (311, 312) are close to each other and the two outer comb grooves (411, 412) are distant from each other. In other words, a lateral separation distance between the comb groove shaft portions of the two outer comb grooves (411, 412) along the second horizontal direction hd2 is greater than a lateral separation distance between the comb groove shaft portions of the two inner comb grooves (311, 312).

A first portion of the semiconductor substrate material layer 10 having a generally elongated rectangular shape corresponding to a region from which a proof mass (i.e., a central mass portion) is to be subsequently patterned may be disposed between the comb groove shaft portions of the two inner comb grooves (311, 312). A proof-mass barrier trench 51 may be formed under an opening in the photoresist layer 37 that includes a proof-mass barrier pattern (PMBP) at the boundary of the area where the proof mass will be subsequently formed. A pair of proof mass barrier trenches 51 may be laterally spaced along the first horizontal direction hd 1. The comb groove shaft portions of the two inner comb grooves (311, 312) may have extensions that wrap around the detection mass barrier groove 51 and may then be used to form a structure that limits lateral etching of the semiconductor matrix material layer 10 during a subsequent isotropic etching process.

Each comb groove tooth portion within the inner comb groove 31 and the outer comb groove 41 may include a plurality of comb groove tooth portions parallel to each other. Each comb groove tooth portion extends laterally away from the respective comb groove shaft portion along a common longitudinal direction of the comb groove tooth portions. Each comb groove tooth portion may be elongated along the longitudinal direction and may have a dry region having a substantially uniform width and fitting to the respective comb groove shaft portion, and each comb groove tooth portion may have a tip section having a width gradually decreasing with a distance from the respective comb groove shaft portion. The common longitudinal direction of the comb groove tooth portions within the comb groove tooth portions may be at an angle in a range from 1 degree to 10 degrees, such as from 2 degrees to 8 degrees. The tip section of each comb groove tooth portion can be advantageously used to increase the variation in capacitance during displacement of the movable structure to be subsequently formed.

The comb-groove tooth portions of the first inner comb groove 311 and the comb-groove tooth portions of the first outer comb groove 411 may be staggered in parallel longitudinal directions for all of the comb-groove tooth portions in the first inner comb groove 311 and the first outer comb groove 411. The interleaved region may include a tip section of the first inner comb groove 311 and a comb groove tooth portion of the first outer comb groove 411. Also, for all the comb groove tooth portions in the second inner comb groove 312 and the second outer comb groove 412, the comb groove tooth portions of the second inner comb groove 312 and the comb groove tooth portions of the second outer comb groove 412 may be staggered in parallel longitudinal directions. The interleaved region may include a tip section of the second inner comb groove 312 and a comb groove tooth portion of the second outer comb groove 412. The longitudinal directions of the comb groove tooth portions of the second inner comb grooves 312 and the comb groove tooth portions of the second outer comb grooves 412 may be inclined in a direction opposite to the second horizontal direction hd2 with respect to the longitudinal directions of the comb groove tooth portions of the first inner comb grooves 311 and the comb groove tooth portions of the first outer comb grooves 411. The overall pattern of comb grooves (31, 41, 51) may have a Mirror Symmetry Plane (MSP) extending along the first horizontal direction hd 1.

In one embodiment, in top view, the area where the mass of detection will subsequently be formed and the area of some part of the comb groove shaft portions of the two inner comb grooves (311, 312) extending laterally along the first horizontal direction hd1 may be located between a pair of longitudinal sidewalls of the first semiconductor oxide plate 12A. The photoresist layer 37 may then be removed, for example by ashing.

The moat grooves (81, 91, 96, 86) may laterally surround the regions of the inner and

outer comb grooves

31, 41. For example, the moat trench (81, 91, 96, 86) may comprise: a proximal moat groove 81 laterally surrounding the inner comb groove 31 and the outer comb groove 41; an intermediate moat groove 91 laterally surrounding the proximal moat groove 81; a distal moat groove 96 laterally surrounding the intermediate moat groove 91; and a suspension spring moat 86 connecting a respective pair of segments of the proximal moat 81 with the moat shaft portions of the two outer moats (411, 412).

Referring to fig. 7A and 7B, a dielectric liner layer may be conformally formed on the physically exposed surfaces of the semiconductor host material layer 10 in the comb trenches (31, 41, 51), in the moat trenches (81, 91, 96, 86), and over the second horizontal surface 102 of the semiconductor host material layer 10. In one embodiment, the dielectric liner layer may be formed by an oxidation process that converts the physically exposed surface portions of the semiconductor host material layer 10 into a semiconductor oxide liner, such as a silicon oxide liner. Alternatively, the dielectric liner layer may be formed by conformally depositing a dielectric material, such as silicon oxide, silicon nitride, a dielectric metal oxide (e.g., aluminum oxide and/or hafnium oxide). The thickness of the dielectric liner layer may be in the range from 4nm to 100nm, for example from 6nm to 20 nm. In general, the thickness of the dielectric liner layer may be optimized to maximize capacitive coupling between comb structures to be subsequently formed and to minimize leakage current through the dielectric liner layer.

Subsequently, a conductive material may be deposited in the remaining volume of the comb trenches (31, 41, 51) and moat trenches (81, 91, 96, 86) and over a horizontally extending portion of the dielectric liner layer overlying the second horizontal surface 102 of the semiconductor base material layer 10. The conductive material may include a doped semiconductor material or a metallic material. For example, the conductive material may comprise heavily doped polysilicon, which may be p-doped or n-doped. The conductive material may fill the remaining volume of the comb trenches (31, 41, 51) and moat trenches (81, 91, 96, 86).

A planarization process may be used to remove excess portions of the conductive material and horizontally extending portions of the dielectric liner layer that are above a horizontal plane including the second horizontal surface 102 of the semiconductor matrix material layer 10. The planarization process may use Chemical Mechanical Planarization (CMP) and/or a recess etch process. In embodiments in which a recess etch process is used, the horizontally extending portion of the dielectric liner layer may be used as an endpoint measurement layer for a recess etch step that removes conductive material overlying the horizontally extending portion of the dielectric liner. Subsequently, the horizontally extending portions of the dielectric liner may be removed by an isotropic etching step (e.g., a wet etching step using dilute hydrofluoric acid). In embodiments in which a Chemical Mechanical Planarization (CMP) process is used, the horizontally extending portions of the dielectric liner may serve as a planarization stop layer during polishing of the conductive material overlying the horizontally extending portions of the dielectric liner. Subsequently, the horizontally extending portions of the dielectric liner may be removed by an isotropic etching step, e.g. a wet etching step using dilute hydrofluoric acid.

The remaining portion of the dielectric liner layer includes a dielectric liner (32, 42, 52, 82, 92, 87, 97). The dielectric liners (32, 42, 52, 82, 92, 87, 97) include an inner dielectric liner 32 formed within a respective one of the inner comb trenches 31, an outer dielectric liner 42 formed within a respective one of the outer comb trenches 41, a barrier dielectric liner 52 formed within a respective one of the proof-mass barrier trenches 51, and a moat trench dielectric liner (82, 92, 87, 97). The remaining portion of the conductive fill material comprises a conductive fill material portion (34, 44, 54, 84, 94, 89, 99). The conductive fill material portions (34, 44, 54, 84, 94, 89, 99) include an inner conductive fill material portion 34 that can be formed within a respective one of the inner comb trenches 31, an outer conductive fill material portion 44 that is formed within a respective one of the outer comb trenches 41, a barrier conductive fill material portion 54 that is formed within a respective one of the proof-mass barrier trenches 51, and a moat fill material portion (84, 94, 89, 99) that is formed within a respective one of the moat trenches (81, 91, 86, 96).

The combination of the remaining portion of the dielectric liner layer and the remaining portion of the conductive material includes a comb structure (30, 40). Specifically, each combination of an inner dielectric liner 32 and an inner conductive fill material portion 34 includes an inner comb structure 30, and each combination of an outer dielectric liner 42 and an outer conductive fill material portion 44 includes an outer comb structure 40. A first interleaved comb structure (301, 401) comprising a first inner comb structure 301 and a first outer comb structure 401 may be formed on one side of a Mirror Symmetry Plane (MSP), and a second interleaved comb structure (302, 402) comprising a second inner comb structure 302 and a second outer comb structure 402 may be formed on an opposite side of the Mirror Symmetry Plane (MSP). A barrier structure 50 including a barrier dielectric liner 52 and a barrier conductive fill material portion 54 may be formed in each proof-mass barrier trench 51.

The moat trench dielectric liners (82, 92, 87, 97) can include an inner dielectric liner 82 that can be formed in the proximal moat trench 81, an intermediate dielectric liner 92 that can be formed in the intermediate moat trench 91, an outer dielectric liner 97 that can be formed in the distal moat trench 96, and a suspension spring dielectric liner 87 that can be formed in the suspension spring moat trench 86. The moat trench fill material portions (84, 94, 89, 99) can include a proximal fill material portion 84 that can be formed in the proximal moat trench 81, an intermediate fill material portion 94 that can be formed in the intermediate moat trench 91, a distal fill material portion 99 that can be formed in the distal moat trench 96, and a suspension spring fill material portion 89 that can be formed in the suspension spring moat trench 86.

The combination of the inner dielectric liner 82 and the proximal filler material portion 84 constitutes the proximal end wall structure 80. The combination of the intermediate dielectric liner 92 and the intermediate fill material portion 94 constitutes the intermediate wall structure 90. The combination of the outer dielectric liner 97 and the distal filler material portion 99 constitute the distal wall structure 95. Each combination of a suspension spring dielectric liner 87 and a suspension spring filler material portion 89 constitutes a suspension wall structure 85.

In general, each of the comb structures (30, 40) may include a respective dielectric liner (32 or 42) and a respective conductive fill material portion (34 or 44). Each of the comb structures (30, 40) extends from the second horizontal surface 102 of the layer of semiconductor matrix material 10 towards the first horizontal surface 101 of the layer of semiconductor matrix material 10 located at the interface with the second semiconductor oxide plate 12B. Each dielectric liner (32, 42) may be a patterned portion of a dielectric liner layer and each conductive fill material portion (34, 44) may be a remaining portion of a conductive fill material. In one embodiment, the comb structures (30, 40) include a pair of inner comb structures (301, 302) and a pair of outer comb structures (401, 402), the pair of inner comb structures (301, 302) being laterally spaced apart by a first portion of the layer of semiconductor matrix material 10, the pair of outer comb structures (401, 402) being interleaved with the pair of inner comb structures (301, 302). The comb shaft portions of the outer comb structures (401, 402) extend along the first horizontal direction hd1 and then along the second horizontal direction hd2 to abut each other, defining a substantially rectangular area which is laterally fully enclosed by the combined comb shaft portions of the outer comb structures (401, 402). In other words, the comb shaft portion of the outer comb structure (401, 402) may constitute a frame laterally enclosing all tooth portions of the outer comb structure (401, 402) and the entire inner comb structure (301, 302).

Two interleaved comb structures (30, 40) can be formed, the two interleaved comb structures (30, 40) having a horizontal cross-sectional shape that replicates the pattern of the two interleaved comb patterns. Each interleaved comb structure (30, 40) can include an inner comb structure 30 and an outer comb structure 40. The first interleaved comb structure includes a first inner comb structure 301 and a first outer comb structure 401 on one side of a Mirror Symmetry Plane (MSP). The second interleaved comb structure includes a second inner comb structure 302 and a second outer comb structure 402 located on opposite sides of a Mirror Symmetry Plane (MSP).

Each inner comb structure 30 comprises a respective comb structure shaft portion, which replicates a comb shaft pattern, and a respective comb structure tooth portion, which replicates and is contiguous with the respective comb structure shaft portion. Each comb structure shaft portion of the inner comb structure 30 may extend laterally along the first horizontal direction hd1 with or without lateral undulations. Each outer comb structure 40 comprises a respective comb structure shaft portion, which replicates the comb shaft pattern, and a respective comb structure tooth portion, which replicates the comb tooth pattern and is contiguous with the respective comb structure shaft portion. Each comb structure shaft portion of the outer comb structure 40 may extend laterally along the first horizontal direction hd1 with or without lateral undulations. The comb structure shaft portions within the outer comb structure 40 may abut comb structure extension portions 46 extending laterally along the second horizontal direction hd 2. Specifically, the end segments of each of the comb structure shaft portions within the outer comb structure 40 can be adjoined with the end segments of the comb structure extensions 46 such that the set of comb structure shaft portions within the outer comb structure 40 and the comb structure extensions 46 collectively form a generally rectangular shape that defines the outer boundary of a cavity that will subsequently be formed in the layer of semiconductor matrix material 10.

The two interleaved comb structures (30, 40) may be arranged such that the two inner comb structures (301, 302) are close to each other and the two outer comb structures (401, 402) are far from each other. In other words, the lateral separation distance between the comb structure shaft portions of the two outer comb structures (401, 402) along the second horizontal direction hd2 is larger than the lateral separation distance between the comb structure shaft portions of the two inner comb structures (301, 302).

A first portion of the layer of semiconductor matrix material 10 having a generally elongated rectangular shape corresponding to a region from which a proof mass (i.e., a central mass portion) can be subsequently patterned can be disposed between the comb structure shaft portions of the two inner comb structures (301, 302). Barrier structure 50 may be formed in the proof-mass barrier trench 51. A pair of barrier structures 50 may be laterally spaced apart along the first horizontal direction hd 1. The comb structure shaft portions of the two inner comb structures (301, 302) may have an extension portion that wraps around the barrier structure 50 and is subsequently used to form a structure that limits lateral etching of the semiconductor matrix material layer 10 during a subsequent isotropic etching process.

Each comb structure tooth portion within the inner and

outer comb structures

30 and 40 includes a plurality of comb structure tooth portions that may be parallel to each other. Each comb structure tooth portion extends laterally away from the respective comb structure shaft portion along a common longitudinal direction of the comb structure tooth portions. Each comb structure tooth portion may be elongated along a longitudinal direction and may have a dry region having a substantially uniform width and fitted to the respective comb structure shaft portion, and each comb structure tooth portion may have a tip section having a width gradually decreasing with a distance from the respective comb structure shaft portion. The common longitudinal direction of the comb structure tooth portions within the comb structure tooth portions may be at an angle in a range from 1 degree to 10 degrees, such as from 2 degrees to 8 degrees. The tip section of the tooth portion of each comb structure can be advantageously used to increase the variation of capacitance during the displacement of the movable structure to be subsequently formed.

The comb-structure tooth portions of the first inner comb structure 301 and the comb-structure tooth portions of the first outer comb structure 401 may be staggered in parallel longitudinal directions for all comb-structure tooth portions in the first inner comb structure 301 and the first outer comb structure 401. The interleaved region may include a tip segment of the first inner comb structure 301 and a comb structure tooth portion of the first outer comb structure 401. Likewise, the comb structure teeth portions of the second inner comb structure 302 may be interleaved with the comb structure teeth portions of the second outer comb structure 402 in parallel longitudinal directions for all comb structure teeth portions in the second inner comb structure 302 and the second outer comb structure 402. The interleaved region may include the tip segment of the second inner comb structure 302 and the comb structure teeth portion of the second outer comb structure 402. The longitudinal directions of the comb-structure tooth portions of the second inner comb structure 302 and the comb-structure tooth portions of the second outer comb structure 402 may be inclined in a direction opposite to the second horizontal direction hd2 with respect to the longitudinal directions of the comb-structure tooth portions of the first inner comb structure 301 and the comb-structure tooth portions of the first outer comb structure 401. The overall pattern of comb structures (30, 40) and barrier structures 50 may have a Mirror Symmetry Plane (MSP) extending along the first horizontal direction hd 1.

Referring to fig. 8A and 8B, a metal material portion (110, 120, 130) may be formed on the second horizontal surface 102 of the semiconductor matrix material layer 10 and over the comb structure (30, 40). For example, a patterned deposition mask (not shown), such as a patterned photoresist layer, may be formed over the exemplary structure, and at least one metallic material may be deposited by physical vapor deposition. The at least one metallic material may include, for example, a metallic liner material (e.g., TiN, TaN, or WN) and an under bump metallic material (e.g., Ni, Cr, Cu), and stacks thereof. The thickness of the at least one metal material may range from 100nm to 2,000nm, although lesser and greater thicknesses may also be used. The patterned deposition mask and portions of the at least one metallic material overlying the patterned deposition mask may be removed, such as by a lift-off process.

The remaining portion of the at least one metallic material deposited on the inner comb structure 30 comprises a movable metal plate 110. The remaining portion of the at least one metallic material deposited on the outer comb structure 40 comprises a fixed metallic plate 120. The remaining portion of the at least one metal material deposited on the semiconductor matrix material layer 10 includes the spring structure 130, and the spring structure 130 may include an opening between an inner frame of the spring structure 130 and an outer frame of the spring structure 130. The spring structures 130 can have a suitable pattern to provide application of an electrical bias voltage to opposing portions of the fixed comb structure 40.

Referring to fig. 9A and 9B, an etch mask material layer 67 may be applied over the various metal material portions (110, 120, 130), and the etch mask material layer 67 may be lithographically patterned to form openings through the etch mask material layer 67. Etch mask material layer 67 may comprise a photoresist material or may comprise a hard mask material (e.g., silicon nitride, silicon oxide, or a dielectric metal oxide). Etch mask material layer 67 may be directly patterned (if etch mask material layer 67 comprises a photoresist material), or etch mask material layer 67 may be patterned by: a photoresist layer is applied over the etch mask material layer 67 and patterned and the pattern in the photoresist layer is transferred into the etch mask material layer using an anisotropic etch process.

The pattern of the openings in patterned etch mask layer 67 may be selected such that a subset of the openings in patterned etch mask layer 67 are formed within the boundaries defined by the comb shaft portions of outer comb structures 40 and comb structure extension portions 46. Furthermore, the pattern of the openings in patterned etch mask layer 67 does not overlap the comb structures (30, 40), comb structure extensions 46, barrier structures 50, or regions of a portion of semiconductor host material layer 10 located between intermediate wall structures 90 and distal wall structures 95. The openings in the patterned etch mask layer 67 are located in areas where no metal material portions (110, 120, 130) are present. A subset of the openings in patterned etch mask layer 67 may overlie the areas of gaps between adjacent pairs of comb structure tooth portions. A subset of the openings in patterned etch mask layer 67 may be formed between barrier structure 50 and comb structure extension 46. The openings in the patterned etch mask layer 67 are not present within the first portion of the semiconductor substrate material layer 10 between the pair of comb structure axle portions of the inner comb structure 30 and the lateral extensions of the inner comb structure 30, and between the pair of barrier structures 50. A subset of the openings in patterned etch mask layer 67 may be formed between proximal end wall structures 80 and comb structure extensions 46.

Referring to fig. 10A and 10B, portions of the semiconductor matrix material layer 10 not masked by the patterned etch mask layer 67 may be etched using a combination of an anisotropic etch process and an isotropic etch process or using an isotropic etch process. In one embodiment, an anisotropic etch process may be formed to etch through unmasked portions of the semiconductor matrix material layer 10. Deep trenches may be formed to the depth of the first semiconductor oxide plate 12A under the openings in the patterned etch mask layer 67.

Subsequently, an isotropic etching process using an isotropic etchant may be performed, which etches the semiconductor material of the semiconductor matrix material layer 10 selectively with respect to the dielectric material of the first and second semiconductor oxide plates (12A, 12B) and the dielectric material of the dielectric liner (32, 42, 52). A portion of the semiconductor matrix material layer 10 may be removed by an isotropic etching process. The removed portions of the semiconductor substrate material layer 10 include portions that are located within the lateral boundaries defined by the comb structure shaft portions within the outer comb structure 40, the comb structure extensions 46, and the inner wall structure 80, and that are located outside of the comb structure shaft portions of the inner comb structure 30. The removed portion of the layer of semiconductor host material 10 is referred to herein as a second portion of the layer of semiconductor host material 10. Further, the portion of the semiconductor substrate material layer 10 between the intermediate wall structure 90 and the distal end wall structure 95 is removed. The unetched portions of the semiconductor matrix material layer 10 that remain after the isotropic etching process and are located outside of the distal end wall structures 95 are referred to herein as semiconductor matrix layers 10M. The unetched portions of the semiconductor matrix material layer 10 remaining after the isotropic etching process and located between the proximal wall structures 80 and the intermediate wall structures 90 are referred to herein as a semiconductor frame 10F.

The isotropic etching process may use a wet etching process that selectively etches the semiconductor material of the semiconductor matrix material layer 10 relative to the material of the first and second semiconductor oxide plates (12A, 12B) and the material of the dielectric liner (32, 42, 52). In one embodiment, the wet etch process may use thermal trimethyl-2hydroxyethyl ammonium hydroxide ("thermal TMY") or tetramethylammonium hydroxide ("TMAH"). The duration of the isotropic etching process may be selected such that the etch front (etch front) of the isotropic etching process reaches the entire area of the portion of the top surface of the second semiconductive oxide sheet 12B that is within the area defined by the combination of the comb structure shaft portions, the comb structure extensions 46 and the proximal end wall structure 80 within the outer comb structure 40. The comb-structure extension 46 is attached to the semiconductor frame 10F through the spring wall structure 85 and the inner wall structure 80.

The movable structure includes inner comb structures 30, a first portion of the semiconductor matrix material layer 10 between the inner comb structures 30 and remains unetched after the isotropic etching process, and a pair of barrier structures 50 attached to the first portion of the semiconductor matrix material layer 10 may be peeled off from remaining unetched portions (which are referred to herein as third portions) of the semiconductor matrix material layer 10, which remain outside of the combination of the comb structure shaft portions, the comb structure extensions 46, and the proximal end wall structures 80 within the outer comb structure 40. In one embodiment, the peripheral region of the first portion of the semiconductor matrix material layer 10 may be concurrently etched by the isotropic etchant as the isotropic etchant flows through the meandering channel (weaving channel) defined by the extension of the comb structure shaft portion of the inner comb structure 30 and the extension of the barrier structure 50.

The first portion of the layer of semiconductor matrix material 10 includes the proof mass of the movable structure, which is referred to herein as the central mass portion 10A. The third portion of the semiconductor host material layer 10 is referred to herein as the semiconductor host layer 10M. The first and second semiconductor oxide plates (12A, 12B) and the dielectric liner (32, 42, 52) act as an etch barrier defining the extent of the cavity 61 formed when the second portion of the layer of semiconductor matrix material 10 is removed. The inner side walls of the comb structure shaft portions, the comb structure extension 46 and the proximal end wall structure 80 within the outer comb structure 40 may serve as the outer lateral boundaries of the cavity 61. The side walls of the comb structure shaft portion of the inner comb structure 30 may serve as inner lateral boundaries of the cavity 61, the cavity 61 surrounding a first portion of the semiconductor matrix material layer 10 that is not etched by the isotropic etching process.

The volume of the recessed cavity 13 may merge into the cavity 61. In embodiments in which the handle substrate 20 comprises a semiconductor material such as silicon, the surface of the handle substrate 20 not covered by the second semiconductor oxide plate 12B may be isotropically recessed to form voids that are added to the cavities 61. The void may have an undercut below the periphery of the second plate of semiconductor oxide 12B. The isotropic etchant may etch portions of the semiconductor matrix material layer 10 located below the boundary formed by the comb structure shaft portions within the outer comb structures 40, the comb structure extension portions 46 and the proximal end wall structures 80, and undercut portions of the semiconductor matrix material layer 10 located outside the boundary in a lateral direction.

In an alternative embodiment, the anisotropic etching process may be omitted, and the isotropic etching process may be elongated to etch through the second portion of the semiconductor matrix material layer 10 to form the cavity. In such an embodiment, the duration of the isotropic etch process may be extended to ensure that the etch front of the isotropic etch process reaches the entire area of the portion of the top surface of the second semiconductor oxide plate 12B that is within the area defined by the combination of the comb structure shaft portions, the comb structure extensions 46 and the proximal end wall structure 80 within the outer comb structure 40.

In general, the isotropic etchant of the isotropic etching process may be applied by patterning openings in the etch mask layer 67. The isotropic etchant etches the semiconductor material of the semiconductor matrix material layer 10 with respect to the material of the semiconductor oxide plates (12A, 12B) and with respect to the material of the comb structures (30, 40) that are in contact with the semiconductor matrix material layer 10, the material of the comb structures (30, 40) may be the material of the dielectric liners (32, 42). A second portion of the layer of semiconductor matrix material 10 that laterally surrounds the first portion of the layer of semiconductor matrix material 10 may be selectively removed relative to the comb structures (30, 40) using an isotropic etching process. The first semiconductor oxide plate 12A, the pair of inner comb structures 30, and the patterned etch mask layer 67 may protect the first portion of the semiconductor matrix material layer 10 from an etchant of the isotropic etch process, the patterned etch mask layer 67 being located on the second horizontal surface 102 of the semiconductor matrix material layer 10 and covering the comb structures 30.

The portion of the patterned etch mask layer 67 covering the first portion of the semiconductor matrix material layer 10 protects the front-side surface of the first portion of the semiconductor matrix material layer 10 during the isotropic etching process. The first semiconductor oxide plate 12A protects the backside of the first portion of the semiconductor matrix material layer 10 during the isotropic etching process. Therefore, after the isotropic etching process, the central mass portion 10A, which is the first portion of the semiconductor matrix material layer 10, may have a uniform thickness between the first semiconductor oxide plate 12A and the interface with the patterned etching mask layer 67. In one embodiment, the central mass portion 10A may have a uniform thickness over the entire area laterally surrounded by the comb structure shaft portion of the inner comb structure 30 and the barrier structure 50.

The cavity 61 may be formed by removing a second portion of the semiconductor matrix material layer 10. The semiconductor matrix layer 10M including the unetched third portion of the semiconductor matrix material layer 10 laterally surrounds the cavity 61. The movable structure (10A, 30, 50) comprising the combination of the first portion of the semiconductor substrate material layer 10 and the pair of inner comb structures 30 can be peeled off from the semiconductor substrate layer 10M by an isotropic etching process.

The inner comb structure 30 is a component of the movable structure (10A, 30, 50) and is hereinafter referred to as the movable comb structure 30. The movable comb structure 30 includes a first movable comb structure 301 and a second movable comb structure 302. The comb structure teeth portion of the inner comb structure 30 comprises movable comb fingers of the movable structure (10A, 30, 50).

The outer comb structure 40 is a fixed component, and thus is hereinafter referred to as a fixed comb structure 40. The fixed comb structure 40 includes a first fixed comb structure 401 and a second fixed comb structure 402. The comb structure tooth portion of the fixed comb structure 40 includes fixed comb fingers.

Referring to fig. 11A and 11B, the patterned etching mask layer 67 may be removed, for example, by ashing. The metallic material portions (110, 120, 130) are located on the top surface of the movable structure (10A, 30, 50), on the top surface of the fixed comb structure 40, on the top surface of the semiconductor frame 10F, and on the top surface of the semiconductor matrix layer 10M. The metallic material portion (110, 120, 130) includes a movable metallic plate 110 formed on the movable structure (10A, 30, 50), a fixed metallic plate 120 formed on the fixed comb structure 40, and a spring structure 130 formed on the semiconductor frame 10F and the semiconductor substrate layer 10M and over the gap between the semiconductor frame 10F and the semiconductor substrate layer 10M. The spring structure 130 includes an opening over the area of the gap to provide resiliency.

Referring to fig. 12, each accelerometer 100 above the handle substrate 20 may be singulated, for example, by vacuum dicing (vacuum dicing). Subsequently, the handle substrate 20 may be stripped, for example, by removing the semiconductor oxide plates (12A, 12B). For example, a wet etch using hydrofluoric acid may be performed to remove the semiconductor oxide plates (12A, 12B). Each accelerometer 100 may be electrically connected to a controller circuit or to a control unit employing wiring that may be attached to the spring structure 130 or to the fixed metal plate 120. The control circuit or control unit may be configured to measure acceleration based on changes in capacitance of capacitor structures within the accelerometer 100.

Referring collectively to fig. 1A-12 and in accordance with various embodiments of the present disclosure, there is provided a micro-electro-mechanical system (MEMS) device comprising: a movable structure (10A, 30, 50) located in the laterally confined space and comprising a central mass portion 10A and a first movable comb structure 301, said first movable comb structure 301 comprising an inner comb shaft portion (i.e. the comb structure shaft portion of the first inner comb structure 301) fitted to a first side wall of said central mass portion 10A and first movable comb fingers (i.e. the comb structure teeth portions of the first inner comb structure 301) protruding in lateral direction from the comb shaft portion. The central mass portion 10A includes a portion of the first semiconductor material. A semiconductor oxide plate comprising an oxide of the first semiconductor material (e.g., first semiconductor oxide plate 12A) covers the entire bottom surface of the central mass portion 10A. The first movable comb structure 301 includes a dielectric liner (e.g., inner dielectric liner 32) physically exposed to the cavity within the laterally confined space, and a conductive fill material portion (e.g., inner conductive fill material portion 34) located within the inner comb shaft portion and extending continuously into each of the first movable comb fingers and laterally surrounded by the dielectric liner 32.

In one embodiment, the movable structure (10A, 30, 50) comprises a second movable comb structure 302, said second movable comb structure 302 comprising another inner comb shaft portion (i.e., the comb structure shaft portion of the second inner comb structure 302) fitted to the second sidewall of said central mass portion 10A and second movable comb fingers (i.e., the comb structure tooth portions of the second inner comb structure 302) protruding from the inner comb shaft portion in a lateral direction. In one embodiment, the semiconductor oxide plate 12A has a width greater than the lateral spacing between the inner and outer comb shaft portions. In one embodiment, the semiconductive oxide plate 12A contacts a bottom surface of the inner comb shaft portion and a bottom surface of the outer comb shaft portion.

In one embodiment, the laterally confined space may be located within an opening in a semiconductor substrate layer 10M, the semiconductor substrate layer 10M comprising another portion of the first semiconductor material. In one embodiment, the first fixed comb structure 401 may be fixed to a first sidewall of the laterally confined space and may include first fixed comb fingers (i.e., comb structure tooth portions of the first outer comb structure 401) interleaved with first movable comb fingers.

In one embodiment, the MEMS device of the present disclosure may comprise a MEMS accelerometer configured to measure displacement of the movable structure (10A, 30, 50) relative to the first fixed comb structure 401 by sensing a change in capacitance of a capacitor structure comprising the first movable comb structure 301 and the first fixed comb structure 401.

According to one aspect of the present disclosure, a micro-electromechanical systems (MEMS) accelerometer is provided, comprising a movable structure (10A, 30, 50) located in a laterally confined space. The movable structure (10A, 30, 50) can include a central mass portion 10A, a first movable comb structure 301, and a second movable comb structure 302, the central mass portion 10A including a portion of a first semiconductor material, the first movable comb structure 301 secured to a first side of the central mass portion 10A, the second movable comb structure 302 secured to a second side of the central mass portion 10A. Each of the first and second

movable comb structures

301 and 302 includes a respective comb shaft portion and a respective set of movable comb fingers (i.e., comb structure tooth portions) protruding laterally from the respective comb shaft portion. The first fixed comb structure 401 is fixed to a first sidewall of the lateral confinement space and includes first fixed comb fingers (i.e., comb structure tooth portions of the first outer comb structure 401) interleaved with first movable comb fingers. The second fixed comb structure 402 is fixed to a second sidewall of the laterally confined space and includes second fixed comb fingers (i.e., comb structure tooth portions of the second outer comb structure 402) interleaved with second movable comb fingers. A semiconductor oxide plate comprising an oxide of the first semiconductor material (e.g., first semiconductor oxide plate 12A) covers the entire bottom surface of the central mass portion 10A.

In one embodiment, the first stationary comb structure 401 includes an additional dielectric liner (e.g., outer dielectric liner 42) physically exposed to the cavity within the laterally confined space and an additional conductive fill material portion (e.g., outer conductive fill material portion 44) located within a respective one of the first stationary comb fingers and laterally surrounded by the additional dielectric liner 42. In one embodiment, each of the first movable comb structure 301, the second movable comb structure 302, the first fixed comb structure 401, and the second fixed comb structure 402 includes a respective dielectric liner (32, 34) and includes a respective conductive fill material portion (34, 44), the dielectric liner (32, 34) being physically exposed to a cavity within the laterally confined space. In one embodiment, the conductive fill material portions (34, 44) may have a different material composition than the first semiconductor material of the central mass portion 10A and the semiconductor matrix layer 10M.

In one embodiment, the first semiconductor oxide plate 12A may have a width greater than a lateral spacing between an interface between the central mass portion 10A and the first movable comb structure 301 and an interface between the central mass portion 10A and the second movable comb structure 302. In one embodiment, the first semiconductor oxide plate 12A may have a lateral extent along the second horizontal direction hd2 that is greater than the combination of the central mass portion 10A and the two comb structure shaft portions of the inner comb structure 30 (which do not include the comb structure tooth portions of the inner comb structure 30). In this embodiment, the planar top surface of the peripheral portion of the first semiconductor oxide plate 12A may be physically exposed to the cavities 61 located between adjacent pairs of movable comb fingers within the first movable comb structure 301 and between adjacent pairs of movable comb fingers within the second movable comb structure 302.

In one embodiment, the top surface of the central mass portion 10A and the top surface of each conductive fill material portion (34, 44, 54) may be physically exposed to the cavity 61 within the laterally confined space. The entire top surface of the central mass portion 10A (which faces the semiconductor die 70) may lie in a horizontal plane. The entire bottom surface of the central mass portion 10A (which contacts the first semiconductor oxide plate 12A) may be located in another horizontal plane. In one embodiment, the thickness of the central mass portion 10A may be uniform.

In one embodiment, a MEMS device of the present disclosure may comprise a MEMS accelerometer. The combination of movable structures (10A, 30, 50) and semiconductor matrix layer 10M may be attached to a semiconductor structure (e.g., semiconductor die 70) that includes a semiconductor substrate 72, field effect transistors (including a subset of semiconductor devices 74) on semiconductor substrate 72, and a metal interconnect structure formed within dielectric material layer 76. The field effect transistor may comprise the following circuitry: the circuitry is configured to measure displacement of the movable structure (10A, 30, 50) relative to the pair of fixed comb structures 40 and the semiconductor substrate layer 10M by sensing a change in capacitance of a capacitor structure comprising the pair of movable comb structures 30 and the pair of fixed comb structures 40.

In one embodiment, the MEMS device of the present disclosure may include a capacitor structure that includes two subsets of conductive fill material portions (e.g., outer conductive fill material portions 44) of the first fixed comb structure 401 and/or the second fixed comb structure 402 as first and second conductive nodes. In one embodiment, a first conductive node of the capacitor structure may be formed by electrically connecting a first subset of the outer conductive fill material portions 44 located within the pair of outer comb structures (i.e., the fixed comb structures 40), and a second conductive node of the capacitor structure may be formed by electrically connecting a second subset of the outer conductive fill material portions 44 located within the pair of outer comb structures 40. In one embodiment, the outer conductive fill material portions 44 within the first subset may alternate with the outer conductive fill material portions 44 within the second subset within each outer comb structure 40. In an illustrative example, the outer conductive fill material portions 44 within each of the outer comb structures (i.e., the fixed comb structures 40) can be numbered sequentially using positive integers starting from 1, and an odd-numbered set of the outer conductive fill material portions 44 can be connected to a first conductive node of the capacitor structure, and an even-numbered set of the outer conductive fill material portions 44 can be connected to a second conductive node of the capacitor structure.

According to another aspect of the present disclosure, a micro-electromechanical systems (MEMS) accelerometer is provided, the MEMS device may include a movable structure (10A, 30, 50) located in a laterally confined space. The movable structure may comprise a central mass portion 10A, a first movable comb structure 301 and a second movable comb structure 302, the central mass portion 10A comprising a portion of a first semiconductor material, the first movable comb structure 301 being fixed to a first side of the central mass portion, the second movable comb structure 302 being fixed to a second side of the central mass portion 10A, wherein each of the first and second

movable comb structures

301, 302 comprises a respective comb shaft portion and a respective set of movable comb fingers protruding laterally from the respective comb shaft portion. The MEMS device may further comprise a first fixed comb structure 401, the first fixed comb structure 401 being fixed to a first sidewall of the laterally confined space and comprising first fixed comb fingers interleaved with the respective set of movable comb fingers of the first movable comb structure 301. The MEMS device may further include a second fixed comb structure 402, the second fixed comb structure 402 being fixed to a second sidewall of the laterally confined space and including second fixed comb fingers interleaved with second movable comb fingers. The MEMS device may also include a semiconductive oxide plate 12A, the semiconductive oxide plate 12A comprising an oxide of the first semiconductor material 10 and covering the entire bottom surface of the central mass portion 10A.

In general, the MEMS accelerometer of the present disclosure may be configured to measure the displacement of a movable structure (10A, 30, 50) relative to a first fixed comb structure 401 and/or a second fixed comb structure 402 by sensing a change in capacitance of a capacitor structure comprising at least the first movable comb structure 401 and the first fixed comb structure 402. The capacitor structure may include a first movable comb structure 301, a second movable comb structure 302, a first fixed comb structure 401, and a second fixed comb structure 402.

Referring to fig. 13, a flow diagram 1300 illustrates a set of processing steps that may be performed to form a MEMS device in accordance with an embodiment of the present disclosure. At step 1310, a recessed surface may be formed by recessing a region of the first horizontal surface 101 of the semiconductor matrix material layer 10. At step 1320, a semiconductor oxide plate (e.g., first semiconductor oxide plate 12A) may be formed on the recessed surface. At step 1330, a comb structure (30, 40) extending from the second horizontal surface 102 of the semiconductor matrix material layer 10 towards the first horizontal surface 101 of the semiconductor matrix material layer 10 may be formed in the semiconductor matrix material layer 10. The comb structures (30, 40) include a pair of inner comb structures 30 laterally spaced apart by a first portion of the layer of semiconductor substrate material 10 and a pair of outer comb structures 40 interleaved with the pair of inner comb structures. At step 1340, a second portion of the semiconductor matrix material layer 10 that laterally surrounds the first portion of the semiconductor matrix material layer 10 can be selectively removed relative to the comb structures (30, 40) using an isotropic etching process. The semiconductor oxide plate 12A, the pair of comb structures 30 and the patterned etch mask layer 67 protect a first portion of the semiconductor matrix material layer 10 from an etchant of the isotropic etch process, the patterned etch mask layer 67 being located on the second horizontal surface 102 and covering the comb structures (30, 40). At step 1350, the semiconductor die 70 may be bonded to the semiconductor host material layer 10M, and the handle substrate 20 may be thinned to provide an enclosing material layer (encapsulant layer) 120. The bonded assembly can be diced to provide discrete MEMS devices including respective accelerometers 100.

Thus, according to another aspect of the present disclosure, there is provided a method of forming a micro-electromechanical system (MEMS) accelerometer, the method of forming a MEMS device may comprise the operation of forming the recessed surface 13 by recessing a region of the first horizontal surface 101 of the layer of semiconductor matrix material 10. The method may further include the operation of forming a semiconductor oxide plate 12A on the recessed surface 13. The method may include an operation of forming comb structures (301, 302) extending from the second horizontal surface 102 towards the first horizontal surface 101 of the layer of semiconductor matrix material 10, wherein the comb structures comprise a pair of inner comb structures (301, 302) and a pair of

outer comb structures

401, 402, the pair of inner comb structures (301, 302) being laterally spaced apart by a first portion of the layer of semiconductor matrix material, the pair of

outer comb structures

401, 402 being interleaved with the pair of inner comb structures (301, 302). The method further comprises an operation of selectively removing a second portion of the layer of semiconductor matrix material 10 laterally surrounding the first portion of the layer of semiconductor matrix material with respect to the comb structures (301, 302, 401, 402) using an isotropic etching process, wherein the semiconductor oxide plate 12A, the pair of

inner comb structures

301, 302 and a patterned etching mask layer, which is located on the second horizontal surface 102 and covers the comb structures, protect the first portion 10A of the layer of semiconductor matrix material 10 from the etchant of the isotropic etching process.

In various embodiments, a proof mass comprising a central mass portion 10A may be provided from the first portion of the layer of semiconductor matrix material 10, which may have a uniform thickness due to the presence of the semiconductor oxide plate 12A at the bottom surface of the first portion of the layer of semiconductor matrix material 10 and due to the presence of the patterned etch mask layer 67 at the top surface of the first portion of the layer of semiconductor matrix material 10. Thus, the random etching of the bottom surface of the proof mass, which is present in prior art methods, can be completely avoided and the central mass portion 10A can have a well defined mass, which can be determined with high precision by the pattern of the movable comb structure 30. The displacement of the movable comb structure 30 is proportional to an inertial force applied to the movable structure (10A, 30, 50) which is proportional to a product of a mass of the movable structure (10A, 30, 50) and an acceleration of the movable structure (10A, 30, 50). Since the mass of the central mass portion 10A can be determined with high precision, the mass of the movable structure (10A, 30, 50) can be determined with high precision. Thus, measurement of a change in capacitance of a capacitor comprising at least one of the movable structure (10A, 30, 50) and the fixed comb structure 40 may provide an accurate measurement of the acceleration of the movable structure (10A, 30, 50), and thus of the object to which the MEMS device is attached. A highly accurate measurement of acceleration enhances the accuracy of the velocity calculation and distance traveled calculation as well as the accuracy of the estimation of the force applied to the object to which the accelerometer is attached.

The accelerometer 100 of the present disclosure may be used in a variety of applications to measure acceleration and/or rotation of any object, such as a mobile device, an optical device, or a vehicle. In the example shown, the accelerometer 100 may be used as an actuator in an optical image stabilization system.

In some embodiments, the movable structure comprises a second movable comb structure comprising another inner comb shaft portion fitted to a second sidewall of the central mass portion and a plurality of second movable comb fingers protruding laterally from the inner comb shaft portion.

In some embodiments, the width of the semiconductor oxide plate is greater than the lateral spacing between the inner and outer comb shaft portions.

In some embodiments, the semiconductor oxide plate contacts a bottom surface of the inner comb shaft portion and a bottom surface of the outer comb shaft portion.

In some embodiments, the laterally confined space is located within an opening in a semiconductor substrate layer that includes another portion of the first semiconductor material.

In some embodiments, the mems device further comprises a first fixed comb structure fixed to the first sidewall of the laterally confined space and comprising a plurality of first fixed comb fingers interleaved with the plurality of first movable comb fingers.

In some embodiments, the first stationary comb structure includes an additional dielectric liner physically exposed to the cavity within the laterally confined space and an additional conductive fill material portion located within a respective one of the first stationary comb fingers and laterally surrounded by the additional dielectric liner.

In some embodiments, the mems device includes a mems accelerometer configured to measure displacement of the movable structure relative to the first fixed comb structure by sensing a change in capacitance, the capacitor structure including the first movable comb structure and the first fixed comb structure.

In some embodiments, a top surface of the central mass portion and a top surface of the conductive fill material portion are physically exposed to the cavity; and the entire top surface of the central mass section lies in a horizontal plane.

The disclosed embodiment provides a micro-electromechanical system accelerometer, which is characterized by comprising: a movable structure located in a laterally confined space, wherein the movable structure comprises a central mass portion comprising a portion of a first semiconductor material, a first movable comb structure secured on a first side of the central mass portion, and a second movable comb structure secured on a second side of the central mass portion, wherein each of the first and second movable comb structures comprises a respective comb shaft portion and respective sets of a plurality of movable comb fingers projecting laterally from the respective comb shaft portion; a first fixed comb structure fixed on a first sidewall of the laterally confined space and comprising a plurality of first fixed comb fingers interleaved with the plurality of movable comb fingers of the respective sets of the first movable comb structure; a second fixed comb structure fixed on a second sidewall of the lateral confinement space and including a second plurality of fixed comb fingers interleaved with the second plurality of movable comb fingers; and a semiconductor oxide plate comprising an oxide of the first semiconductor material and covering an entire bottom surface of the central mass portion.

In some embodiments, each of the first movable comb structure, the second movable comb structure, the first fixed comb structure, and the second fixed comb structure comprises a respective dielectric liner physically exposed to a cavity within the laterally confined space and comprises a respective conductive fill material portion.

In some embodiments, the mems accelerometer is configured to measure displacement of the movable structure relative to the first and second fixed comb structures by sensing a change in capacitance of a capacitor structure that includes the first movable comb structure, the second movable comb structure, the first fixed comb structure, and the second fixed comb structure.

In some embodiments, a width of the semiconductor oxide plate is greater than a lateral spacing between an interface between the central mass portion and the first movable comb structure and an interface between the central mass portion and the second movable comb structure.

In some embodiments, a peripheral portion of the semiconductor oxide plate is physically exposed to the cavity between adjacent pairs of movable comb fingers within the first movable comb structure and between adjacent pairs of movable comb fingers within the second movable comb structure; said laterally confined space being located within an opening in a semiconductor substrate layer, said semiconductor substrate comprising another portion of said first semiconductor material; and each of the first movable comb structure, the second movable comb structure, the first fixed comb structure, and the second fixed comb structure comprises a respective conductive fill material portion having a different material composition than the first semiconductor material.

In some embodiments, a cavity is formed by removing the second portion of the layer of semiconductor matrix material; a semiconductor host layer including a third portion of the semiconductor host material layer laterally surrounding the cavity; and a movable structure comprising a combination of said first portion of said layer of semiconductor substrate material and said pair of inner comb structures, peeled from said semiconductor substrate layer.

In some embodiments, forming the plurality of comb structures comprises: forming a plurality of comb trenches in the semiconductor matrix material layer, wherein each of the plurality of comb trenches extends from the second horizontal surface of the semiconductor matrix material layer towards the first horizontal surface of the semiconductor matrix material layer; and forming the plurality of comb structures within the plurality of comb trenches, wherein each of the plurality of comb structures comprises a respective dielectric liner and a respective conductive fill material portion.

In some embodiments, the method of forming a microelectromechanical systems device further comprises: forming a dielectric liner layer on the physically exposed surfaces of the plurality of comb trenches; depositing a conductive fill material in remaining volumes of the plurality of comb trenches after forming the dielectric liner layer; and removing portions of the conductive fill material from outside the plurality of comb trenches, wherein each of the plurality of dielectric liners comprises a remaining portion of the dielectric liner layer and each of the conductive fill material portions comprises a remaining portion of the plurality of conductive fill materials.

In some embodiments, the mems device comprises a mems accelerometer; and attaching the combination of the movable structure and the semiconductor matrix layer to a semiconductor structure, the semiconductor structure comprising a semiconductor substrate, a plurality of field effect transistors located on the semiconductor substrate, and a plurality of metal interconnect structures formed within a plurality of dielectric material layers, wherein the plurality of field effect transistors comprise the following circuitry: the circuit is configured to measure displacement of the movable structure relative to the pair of outer comb structures and the semiconductor substrate layer by sensing a change in capacitance of a capacitor structure that includes the pair of inner comb structures and the pair of outer comb structures.

In some embodiments, the method of forming a microelectromechanical systems device further comprises: forming an additional semiconductor oxide plate on the first horizontal surface of the layer of semiconductor matrix material; attaching the additional semiconductor oxide plate to an operating substrate prior to forming the plurality of comb trenches, wherein a laterally confined space is formed between the semiconductor oxide plate and the operating substrate; forming the patterned etch mask layer on the second horizontal surface of the semiconductor matrix material layer by applying an etch mask material layer and forming a plurality of openings through the etch mask material layer, wherein the plurality of openings are formed in a plurality of regions that do not overlap with regions of the plurality of comb structures; and applying an isotropic etchant of the isotropic etching process through the opening in the patterned etch mask layer, wherein the isotropic etchant selectively etches the material of the semiconductor matrix material layer with respect to the material of the semiconductor oxide plate and the material of the additional semiconductor oxide plate and with respect to the material of the plurality of comb structures in contact with the semiconductor matrix material layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[ description of symbols ]

10: semiconductor host material layer/first semiconductor material

10A: central mass part/movable structure/first part

10F: semiconductor frame

10M: semiconductor substrate layer

11: diffusion barrier spacer/barrier spacer

12A: plate/semiconductor oxide plate/first semiconductor oxide plate

12B: plate/semiconductor oxide plate/second semiconductor oxide plate

13: concave cavity

13R: bottom surface of the recess

13S: side wall

20: handle substrate

30: comb structure/inner comb structure/movable comb structure

31: comb groove/inner comb groove

32: dielectric liner/inner dielectric liner

34: conductive fill material portion/inner conductive fill material portion

37: photoresist layer

40: comb structure/outer comb structure/fixed comb structure

41: comb groove/outer comb groove

42: dielectric liner/outer dielectric liner

43: comb groove extension

44: conductive fill material portion/outer conductive fill material portion

46: comb structure extension

50: barrier/movable structure

51: comb trench/proof mass barrier trench

52: dielectric liner/barrier dielectric liner

54: conductive fill material portion/barrier conductive fill material portion

61: hollow cavity

67: etching the mask material layer

70: semiconductor die

72: semiconductor substrate

74: semiconductor device with a plurality of transistors

76: layer of dielectric material

80: proximal end wall structure/inner wall structure

81: trench/near-end trench

82: dielectric liner/trench dielectric liner/inter-dielectric liner

84: conductive fill material portion/trench fill material portion/near end fill material portion

85: hanging wall structure/spring wall structure

86: trench/suspension spring trench

87: dielectric liner/trench dielectric liner/suspension spring dielectric liner

89: conductive fill material portion/trench fill material portion/suspension spring fill material portion

90: intermediate wall structure

91: trench/intermediate trench

92: dielectric liner/trench dielectric liner/inter-dielectric liner

94: conductive fill material portion/trench fill material portion/intermediate fill material portion

95: distal end wall structure

96: moat/distal moat

97: dielectric liner/trench dielectric liner/outer dielectric liner

99: conductive fill material portion/trench fill material portion/distal fill material portion

100: accelerometer

101: a first horizontal surface

102: a second horizontal surface

110: metallic material part/movable metal plate

120: metallic material part/fixed metal plate/surrounding material layer

130: metallic material part/spring structure

301: first inner comb structure/inner comb structure/first movable comb structure

302: second inner comb structure/inner comb structure/second movable comb structure

401: first outer comb structure/outer comb structure/first stationary comb structure

402: second outer comb structure/outer comb structure/second stationary comb structure

311: first inner comb groove/inner comb groove

312: second inner comb groove/inner comb groove

411: first outer comb groove/outer comb groove

412: second outer comb groove/outer comb groove

1300: flow chart

1310. 1320, 1330, 1340, 1350: step (ii) of

A-A': hinge type vertical plane

A _ PM: region(s)

B-B': horizontal plane/surface

CPI 1: inner comb pattern/first inner comb pattern

CPI 2: inner comb pattern/second inner comb pattern

CPO 1: outer comb pattern/first outer comb pattern

CPO 2: outer comb pattern/second outer comb pattern

CSEP: comb shaft extension pattern

hd 1: first horizontal direction

hd 2: second horizontal direction

MSP: mirror symmetry plane

PMBP: detecting quality barrier patterns

t: thickness of

Claims

1. A microelectromechanical systems device, comprising:

a movable structure located in a laterally confined space, wherein the movable structure comprises a central mass portion and a first movable comb structure comprising an inner comb shaft portion fitted to a first sidewall of the central mass portion and a plurality of first movable comb fingers projecting laterally from the inner comb shaft portion, wherein:

the central mass portion comprises a portion of a first semiconductor material;

a semiconductor oxide plate comprising an oxide of the first semiconductor material covering the entire bottom surface of the central mass portion; and

the first movable comb structure comprises a dielectric liner physically exposed to a cavity within a matrix and a conductive fill material portion located within the inner comb shaft portion and extending continuously into each of the plurality of first movable comb fingers and laterally surrounded by the dielectric liner.

2. The mems device of claim 1, wherein the movable structure comprises a second movable comb structure comprising another inner comb shaft portion affixed to a second sidewall of the central mass portion and a plurality of second movable comb fingers projecting laterally from the inner comb shaft portion.

3. The mems device of claim 2, wherein the semiconductor oxide plate has a width greater than a lateral spacing between the inner and outer comb shaft portions, wherein the semiconductor oxide plate contacts a bottom surface of the inner comb shaft portion and a bottom surface of the outer comb shaft portion, wherein the laterally confined space is located within an opening in a semiconductor substrate layer comprising another portion of the first semiconductor material.

4. The mems device of claim 1, further comprising a first fixed comb structure fixed to a first sidewall of the lateral confinement space and comprising a plurality of first fixed comb fingers interleaved with the plurality of first movable comb fingers, wherein the first fixed comb structure comprises an additional dielectric liner physically exposed to the cavity within the lateral confinement space and an additional conductive filler material portion located within a respective one of the first fixed comb fingers and laterally surrounded by the additional dielectric liner.

5. A micro-electromechanical system accelerometer, comprising:

a movable structure located in a laterally confined space, wherein the movable structure comprises a central mass portion comprising a portion of a first semiconductor material, a first movable comb structure secured on a first side of the central mass portion, and a second movable comb structure secured on a second side of the central mass portion, wherein each of the first and second movable comb structures comprises a respective comb shaft portion and respective sets of a plurality of movable comb fingers projecting laterally from the respective comb shaft portion;

a first fixed comb structure fixed on a first sidewall of the laterally confined space and comprising a plurality of first fixed comb fingers interleaved with the plurality of movable comb fingers of the respective sets of the first movable comb structure;

a second fixed comb structure fixed to a second sidewall of the laterally confined space and comprising a plurality of second fixed comb fingers interleaved with the plurality of second movable comb fingers; and

a semiconductor oxide plate comprising an oxide of the first semiconductor material and covering an entire bottom surface of the central mass portion.

6. The micro-electromechanical systems accelerometer of claim 5, wherein each of the first movable comb structure, the second movable comb structure, the first fixed comb structure, and the second fixed comb structure comprises a respective dielectric pad physically exposed to a cavity within the lateral confinement space and comprises a respective conductive fill material portion.

7. The mems accelerometer of claim 6, wherein the mems accelerometer is configured to measure displacement of the movable structure relative to the first and second fixed comb structures by sensing a change in capacitance of a capacitor structure comprising the first movable comb structure, the second movable comb structure, the first fixed comb structure, and the second fixed comb structure.

8. A method of forming a microelectromechanical systems device, comprising:

forming a recessed surface by recessing a region of the first horizontal surface of the semiconductor substrate material layer;

forming a semiconductor oxide plate on the recessed surface;

forming a plurality of comb structures extending from a second horizontal surface of the layer of semiconductor matrix material toward the first horizontal surface, wherein the plurality of comb structures comprises a pair of inner comb structures laterally spaced apart by a first portion of the layer of semiconductor matrix material and a pair of outer comb structures interleaved with the pair of inner comb structures; and

removing a second portion of the semiconductor matrix material layer laterally surrounding the first portion of the semiconductor matrix material layer selectively with respect to the plurality of comb structures using an isotropic etch process, wherein the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer protect the first portion of the semiconductor matrix material layer from an etchant of the isotropic etch process, the patterned etch mask layer being located on the second horizontal surface and covering the plurality of comb structures.

9. The method of forming a microelectromechanical systems device of claim 8, wherein:

forming a cavity by removing the second portion of the layer of semiconductor matrix material;

a semiconductor substrate layer including a third portion of said semiconductor substrate material layer laterally surrounding said cavity; and

a movable structure comprising a combination of the first portion of the layer of semiconductor substrate material and the pair of inner comb structures, peeled from the semiconductor substrate layer, wherein forming the plurality of comb structures comprises:

forming a plurality of comb trenches in the semiconductor matrix material layer, wherein each of the plurality of comb trenches extends from the second horizontal surface of the semiconductor matrix material layer toward the first horizontal surface of the semiconductor matrix material layer; and

forming the plurality of comb structures within the plurality of comb trenches, wherein each of the plurality of comb structures comprises a respective dielectric liner and a respective conductive fill material portion.

10. The method of forming a microelectromechanical systems device of claim 9, further comprising:

forming a dielectric liner layer on the physically exposed surfaces of the plurality of comb trenches;

depositing a conductive fill material in remaining volumes of the plurality of comb trenches after forming the dielectric liner layer; and

removing portions of the conductive fill material from outside the plurality of comb trenches,

wherein each of the plurality of dielectric liners comprises a remaining portion of the dielectric liner layer and each of the conductive fill material portions comprises a remaining portion of the plurality of conductive fill materials.