CN114616655A - 光学装置的晶圆级制造 - Google Patents

光学装置的晶圆级制造 Download PDF

Info

Publication number
CN114616655A
CN114616655A CN202080074592.5A CN202080074592A CN114616655A CN 114616655 A CN114616655 A CN 114616655A CN 202080074592 A CN202080074592 A CN 202080074592A CN 114616655 A CN114616655 A CN 114616655A
Authority
CN
China
Prior art keywords
wafer
photonic
optical
electronic
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080074592.5A
Other languages
English (en)
Inventor
桑德普·拉兹丹
维普尔库马尔·K·帕特尔
马克·A·韦伯斯特
马修·J·特拉弗索
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cisco Technology Inc
Original Assignee
Cisco Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Technology Inc filed Critical Cisco Technology Inc
Publication of CN114616655A publication Critical patent/CN114616655A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12002—Three-dimensional structures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1228—Tapered waveguides, e.g. integrated spot-size transformers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G02B6/305—Optical coupling means for use between fibre and thin-film device and having an integrated mode-size expanding section, e.g. tapered waveguide
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G02B6/4212—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms the intermediate optical element being a coupling medium interposed therebetween, e.g. epoxy resin, refractive index matching material, index grease, matching liquid or gel
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4266—Thermal aspects, temperature control or temperature monitoring
    • G02B6/4268—Cooling
    • G02B6/4269—Cooling with heat sinks or radiation fins
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12038—Glass (SiO2 based materials)
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12085—Integrated
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12166—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08235—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29193—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Optical Couplings Of Light Guides (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

本文描述的各方面包括一种方法，该方法包括：将光子晶圆与电子晶圆进行接合以形成晶圆组件；去除晶圆组件的衬底以暴露光子晶圆或电子晶圆的表面；在光子晶圆的金属层与电子晶圆的金属层之间形成电连接；以及通过在所暴露的表面处将中介层晶圆与晶圆组件进行接合来将中介层晶圆添加至晶圆组件。中介层晶圆包括与光子晶圆和电子晶圆中的一者或两者的金属层电耦合的贯穿过孔。该方法还包括切割晶圆组件以形成多个管芯。每个管芯的相应边缘耦合器在通过切割形成的界面处被光学暴露。

Description

光学装置的晶圆级制造
技术领域
本公开中呈现的实施例总体涉及光子器件，并且更具体地，涉及制造具有边缘耦合器的光子器件。
背景技术
光子芯片可以包括光学接口以允许从光源(例如，激光器或光纤)接收光信号和/或将光信号发送到光纤或检测器。一些光子芯片包括设置在光子芯片顶部的光栅耦合器。然而，光栅耦合器对波长和偏振是敏感的并需要非常严格的工艺控制，这往往会增加光子芯片的成本和/或降低制造良率。其他光子芯片包括边缘耦合器，这些边缘耦合器可以设置在光子芯片的侧面并且更容易制造，并且相比于光栅耦合器可以提供不依赖波长的且改进的光学耦合。
附图说明
为了能够详细理解本公开的上述特征的方式，可以通过参考实施例来获得对上文简要概括的本公开的更具体的描述，其中的一些实施例在附图中示出。然而，应当注意，附图示出了典型的实施例并因此不应被视为限制性的；还涵盖其他等效的实施例。
图1示出了根据一个或多个实施例的绝缘体上硅(SOI)器件。
图2A和图2B示出了根据一个或多个实施例的包括与电子晶圆接合的光子晶圆的示例性晶圆组件。
图3A至图3I示出了根据一个或多个实施例的用于制造光学装置的示例性顺序。
图4是根据一个或多个实施例的用于制造光学装置的示例性方法。
图5示出了根据一个或多个实施例的包括边缘耦合器的光子芯片的侧视图。
图6A至图6E示出了根据一个或多个实施例的图5的边缘耦合器的截面图。
图7A和图7B示出了根据一个或多个实施例的锥形波导的视图。
为了便于理解，在可能的情况下，使用相同附图标记来表示附图共有的相同元件。可以设想，在一个实施例中公开的元件可有益地用在其他实施例中而无需具体阐述。
具体实施方式
概述
本公开中呈现的一个实施例是一种方法，所述方法包括：将光子晶圆与电子晶圆进行接合以形成晶圆组件；去除所述晶圆组件的衬底以暴露所述光子晶圆或所述电子晶圆的表面；在所述光子晶圆的金属层与所述电子晶圆的金属层之间形成电连接；以及通过在所暴露的表面处将中介层晶圆与所述晶圆组件进行接合，来将所述中介层晶圆添加至所述晶圆组件。所述中介层晶圆包括与所述光子晶圆和所述电子晶圆中的一者或两者的金属层电耦合的贯穿过孔。所述方法还包括切割所述晶圆组件以形成多个管芯，其中，每个管芯的相应边缘耦合器在通过所述切割形成的界面处被光学暴露。
另一实施例是一种方法，所述方法包括在光子晶圆中形成多个光学元件。所述多个光学元件包括多个边缘耦合器。所述方法还包括：在电子晶圆中形成多个电子元件；将所述光子晶圆与所述电子晶圆进行接合以形成晶圆组件；在所述多个光学元件与所述多个电子元件之间形成电连接；以及通过将中介层晶圆与所述晶圆组件的外表面进行接合，来将所述中介层晶圆添加至所述晶圆组件。所述中介层晶圆包括贯穿过孔，所述贯穿过孔与所述多个光学元件和所述多个电子元件中的一者或两者电耦合。所述方法还包括切割所述晶圆组件以形成多个管芯。每个管芯的相应边缘耦合器在通过所述切割形成的界面处被光学暴露。
另一实施例是一种用于形成多个管芯的晶圆组件。所述晶圆组件包括光子晶圆，所述光子晶圆包括多个光学元件。所述多个光学元件包括多个边缘耦合器，所述多个边缘耦合器被布置成使得所述多个管芯中的每个管芯的相应边缘耦合器将在切割界面处被光学暴露。所述晶圆组件还包括电子晶圆，所述电子晶圆具有与所述光子晶圆的第二表面接合的第一表面。所述电子晶圆包括多个电子元件，并且在所述多个光学元件与所述多个电子元件之间形成电连接。所述晶圆组件还包括与第三表面接合的中介层晶圆，所述第三表面是以下两者中的一者：所述电子晶圆的与所述第一表面相反的表面和所述光子晶圆的与所述第二表面相反的表面。所述晶圆组件还包括延伸穿过所述中介层晶圆的多个贯穿过孔。所述多个贯穿过孔与所述多个光学元件和所述多个电子元件中的一者或两者电耦合。
示例实施例
交换机和其他联网设备中包括的集成电路(IC)的处理能力和速度不断提高；因此，将大量数据移入和移出这些交换机和联网设备是一项重大挑战。非常需要光学输入/输出解决方案来克服这一挑战。硅光子是一种可用来解决这一问题的有发展前景的技术。通过使用硅光子平台来制造光学元件，可利用现有IC组装基础设施，这往往会降低制造成本并支持规模扩大。
在一些情况下，基于硅光子的光学元件的制造和/或封装与互补金属氧化物半导体(CMOS)制造和/或封装技术保持兼容。一些非限制性示例包括表面安装技术，诸如受控塌陷芯片连接(也称为“C4”或“倒装芯片”)、球栅阵列(BGA)等。此外，减少光学元件的整体封装面积可能是有益的，这可以支持高信号和功率完整性(例如，支持高速和高级调制技术，诸如112G PAM4)并具有低功率要求和寄生效应。
本文描述的实施例包括制造光学装置的方法，所述方法允许以成本效益的方式实现用于高数据速率收发器模块和封装内光学应用的高速光学输入/输出。更具体地，制造方法包括光子晶圆与电子晶圆的晶圆级组装，从而降低下游制造工艺的成本、复杂性和周期时间，同时提高制造良率并支持高速/功率完整性操作。通过在晶圆级将光子晶圆与电子晶圆进行接合，消除了在下游制造工艺中单独封装电子IC和光子IC的需要。此外，在晶圆级将光子晶圆与电子晶圆进行接合有助于改善输入/输出耦合，减少寄生效应，并支持用于光学引擎与IC共同封装的小外形尺寸。
图1示出了根据一个或多个实施例的绝缘体上硅(SOI)器件100。SOI器件100包括表面层105、绝缘层110(也被称为掩埋氧化物(BOX)层)和半导体衬底115。尽管本文的实施例将表面层105和半导体衬底115称为硅，但本公开不限于此。例如，可以使用其他半导体或可选的透光材料来形成此处所示的结构。此外，表面层105与半导体衬底115可以由相同材料制成，但在其他实施例中，表面层105与半导体衬底115由不同材料制成。
表面层105的厚度可以在小于100纳米至大于一微米的范围内。更具体地，表面层105的厚度可以在100纳米至300纳米之间。绝缘层110的厚度可取决于期望的应用而变化。在一个实施例中，绝缘层110的厚度可以在小于一微米至数十微米的范围内。半导体衬底115的厚度可以取决于SOI器件100的具体应用而广泛变化。例如，半导体衬底115可以具有典型半导体晶圆的厚度(例如，100微米至700微米)，或者可以被减薄并安装在另一衬底上。
对于光学应用，硅表面层105和绝缘层110(例如，二氧化硅、氮化硅、氮氧化硅等)可以提供将光信号限定在表面层105中的硅波导中的对比折射率。在后续处理步骤中，表面层105可以被蚀刻以形成一个或多个硅波导。由于与诸如二氧化硅之类的绝缘体相比，硅具有更高的折射率，因此光信号在其传播穿过表面层105时倾向于主要保留在硅波导中。此外，也可以在制造过程中沉积(一个或多个)其他层，诸如(一个或多个)氮化硅层，以用于形成附加光导波导层。
图2A和图2B示出了根据一个或多个实施例的包括与电子晶圆215接合的光子晶圆210的示例性晶圆组件200。更具体地，图2A是晶圆组件200的俯视图，并且图2B提供了晶圆组件200的透视图。光子晶圆210和电子晶圆215可以由任何(一种或多种)合适的半导体材料形成，这将在下面更详细地讨论。
如图所示，晶圆组件200包括多个矩形光子芯片205(例如，约10个至约200个光子芯片)。代替一次形成单个光子芯片205，晶圆组件200能够使用相同的制造步骤来并行地形成多个光子芯片205。晶圆组件200可以被切割以分离相邻的光子芯片205。在一些实施例中，用于切割晶圆组件200的切割工艺包括机械锯切、划线和劈开以及激光切割中的一种或多种。
在基于一个或多个SOI器件的一些实施例中，每个光子芯片205包括图1所示的绝缘层110和半导体衬底115。然而，表面层105已被处理以包括各种光学元件(例如，波导、耦合器、调制器、检测器等)和/或电子元件。例如，可以通过对表面层105执行各种制造步骤(诸如蚀刻或掺杂表面层105的硅材料)以及沉积或生长附加材料来形成光学元件。在一些实施例中，光子晶圆210和电子晶圆215中的一者是使用SOI器件来制造的。在其他实施例中，光子晶圆210和电子晶圆215两者都是使用SOI器件来制造的。
在一些实施例中，相邻的光子芯片205各自包括在通过切割工艺形成的侧表面处光学暴露的相应边缘耦合器(未示出)。边缘耦合器可以被设计为高效地耦合至外部光承载介质。在一些实施例中，使用边缘耦合器可以减轻与穿过侧表面来发射光信号相关联的光损耗。
图3A至图3I示出了根据一个或多个实施例的用于制造光学装置的示例性顺序。更具体地，示意图300、326、330、334、344、360、366、374、384描绘了针对光学装置的不同制造阶段。尽管光学装置被描绘为单个光子芯片(例如，单个管芯)，但应当理解，可以在晶圆级制造中并行地制造其他光子芯片。
在示意图300中，光子晶圆302(图2B的光子晶圆210的一个示例)与电子晶圆306(图2B的电子晶圆215的一个示例)彼此分离。在一些实施例中，光子晶圆302和电子晶圆306中的每一者均使用SOI器件(例如，至少包括表面层105、绝缘层110和半导体衬底115)来形成。光子晶圆302包括一个或多个光学元件，而电子晶圆306包括一个或多个电子元件。光学元件和/或电学元件可以部分地形成在表面层105和/或形成在表面层105上方的一个或多个层(例如，附加光波导层)中。
如图所示，光子晶圆302包括多个光学元件：边缘耦合器314-1、314-2、光学检测器316和光学调制器318。多个光学元件可以彼此光学耦合。例如，在操作期间，边缘耦合器314-1可以从外部光承载介质接收光信号，光检测器316检测光信号，光调制器318调制光信号，并且边缘耦合器314-2在外部耦合调制后的光信号(例如，通过光子芯片的边缘耦合到另一外部光承载介质)。在一些配置中，边缘耦合器314-1接收调制后的光信号，并且光检测器316检测调制后的光信号并将其转换成电信号。
光子晶圆302还包括顶表面310、多个金属层312-1、312-2、在金属层312-1、312-2之间延伸的过孔、以及在金属层312-2与表面层105或其他(一个或多个)半导体层之间延伸的过孔。光子晶圆302设置在衬底304(例如，半导体衬底115的一部分)上。
如图所示，电子晶圆306包括电子元件324。在一些实施例中，电子元件324包括晶体管或包括晶体管的其他电子电路。电子晶圆306还包括顶表面320、多个金属层322-1、322-2、322-3、322-4、在金属层322-1、322-2、322-3、322-4之间延伸的过孔、以及在金属层322-4与表面层105或其他(一个或多个)半导体层之间延伸的过孔。电子晶圆306设置在衬底308(例如，半导体衬底115的一部分)上。
在示意图326中，光子晶圆302被倒置(或翻转)，并且光子晶圆302的顶表面310与电子晶圆306的顶表面320接触。可以执行接合工艺以在接合线328处将光子晶圆302与电子晶圆306进行接合，从而形成晶圆组件。在一些实施例中，将光子晶圆与电子晶圆接合通过晶圆级氧化物-氧化物接合来进行。可以设想其他合适类型的直接接合。在一些实施例中，接合工艺包括晶圆级混合接合，其中，氧化物-氧化物接合和金属互连在单个接合步骤中实现。例如，在顶表面310、320包括导电接合点阵列的情况下，可以使用直接接合互连(DBI)或面对面接合。
在图330中，从晶圆组件去除衬底以暴露光子晶圆302或电子晶圆306的表面。如图所示，去除衬底304以暴露光子晶圆302的表面332。在其他实施例中，可以去除衬底308以暴露电子晶圆306的表面。衬底304或308可以使用任何合适的技术(例如，使用光刻和化学蚀刻工艺)来去除。
在图334中，在表面332上方、向光子晶圆302添加附加氧化物或其他合适的电介质材料，并且在光子晶圆302中添加过孔，使得晶圆厚度增加了厚度336以延伸至表示晶圆组件的外表面的表面338。多个过孔340-1、340-2、…、340-6从表面338形成并部分或完全延伸穿过光子晶圆302和/或部分或完全穿过电子晶圆306。在一些实施例中，多个过孔340-1、340-2、…、340-6形成为贯穿氧化物过孔。多个导电接触件342-1、342-2、…、342-7形成在表面338处，并与过孔340-1、340-2、…、340-6中的相应一个或多个耦合。
过孔340-1、340-2、340-3、340-5从表面338延伸穿过光子晶圆302，并部分地延伸穿过电子晶圆306到达金属层322-1。过孔340-4、340-6部分地延伸穿过光子晶圆302到达金属层312-1。以这种方式，导电接触件342-1、342-2、342-3、342-6与电子晶圆306的电子元件电耦合，并且导电接触件342-3、342-7与光子晶圆302的光学元件电耦合。
在图344中，晶圆组件被倒置，并且光子晶圆302的表面338与中介层晶圆346的表面348接触。中介层晶圆346可以由任何合适的材料(诸如硅或玻璃)形成。可以执行接合工艺以在接合线358处将晶圆组件与中介层晶圆346接合。在一些实施例中，通过晶圆级氧化物-氧化物接合来将晶圆组件与中介层晶圆346进行接合。还可以设想其他合适类型的直接接合(例如，晶圆级混合接合)。
中介层晶圆346包括多个贯穿过孔350-1、350-2、…、350-7，它们在表面348处形成的多个表面接触件352-1、352-2、…、352-7与在表面356处形成的多个表面接触件354-1、354-2、…、354-7之间延伸，其中表面356与表面348相反。
在图360中，焊球362-1、362-2、…、362-7附接至表面接触件354-1、354-2、…、354-7以形成与贯穿过孔350-1、350-2、…、350-7电耦合的表面安装连接器。表面安装连接器可以具有任何合适的形式，无论是标准化的还是专有的。例如，焊球362-1、362-2、…、362-7可以布置为球栅阵列(例如，具有0.4mm至0.65mm的间距)或倒装芯片凸块(例如，具有50微米至150微米的间距)。
在形成表面安装连接器之后，然后可以沿着线364-1、364-2切割晶圆组件以形成多个管芯。在一些实施例中，线364-1、364-2被选择为使得边缘耦合器314-1、314-2在通过切割形成的界面处被光学暴露。如本文所用，“光学暴露”是指边缘耦合器314-1、314-2在侧表面处被物理暴露或从侧表面略微凹陷(例如，1微米至5微米)，但仍可以与外部光承载介质光学耦合。如图366所示，通过切割形成的界面是侧表面368-1、368-2。可以对界面执行进一步处理，例如蚀刻或抛光侧表面368-1、368-2，以实现边缘耦合器314-1、314-2与外部光承载介质的高光学耦合效率。
在图366中，多个电接触件380-1、380-2、…、380-7形成在集成电路(IC)衬底378或中介层的表面382上。第一管芯的表面安装连接器(例如，焊球362-1、362-2、…、362-7)与电接触件380-1、380-2、…、380-7电耦合。
在图374中，外部光承载介质372附接至第一管芯。在一些实施例中，外部光承载介质372包括以下各项中的一项：外部光子芯片的光波导、外部光子芯片的边缘耦合器、激光器、发光二极管、单根光纤以及对多根光纤进行布置的光纤阵列单元。在一些实施例中，如图所示，在将外部光承载介质372附接至第一管芯之前，将第一管芯与IC衬底378进行电耦合。这种排序可能适合于用于附接焊球362-1、362-2、…、362-7的回流温度高于用于附接外部光承载介质372的环氧树脂固化温度的情况。然而，在其他实施例中，外部光承载介质372附接至第一管芯在第一管芯与IC衬底378电耦合之前，这在对焊球362-1、362-2、…、362-7使用低温焊料或使用可承受更高温度的环氧树脂时可能是合适的。
外部光承载介质372与边缘耦合器314-1光学耦合。可以通过无源和/或有源对准技术来实现外部光承载介质372与边缘耦合器314-1的光学耦合。在一些实施例中，外部光承载介质372和/或第一管芯包括有助于对准的一个或多个对准特征。例如，一个或多个对准特征的尺寸可以被设计为使得当与第一管芯的参考表面或另一对准特征耦合时，外部光承载介质372与边缘耦合器314-1光学耦合。尽管示出两个边缘耦合器314-1、314-2，但其他实现方式可以包括不同数量的边缘耦合器。例如，光子晶圆302可以包括三个插脚耦合器(prong coupler)：用于接收未调制的光的第一插脚耦合器、用于发送调制后的光(例如，在收发器的发送侧)的第二插脚耦合器以及用于接收调制后的光(用于检测)的第三插脚耦合器。此外，在一些实施例中，可以在光子晶圆302中形成输入和输出阵列(例如，使得边缘耦合器可以是光纤阵列单元(FAU))。
在一些实施例中，在外部光承载介质372与边缘耦合器314-1光学耦合之后，在第一管芯的界面(此处为侧表面368-1)与外部光承载介质372之间施加折射率匹配材料370(例如，环氧树脂)。以这种方式，光信号可以穿过折射率匹配材料370传播。折射率匹配材料370可以被固化(例如，使用UV光或热)以将外部光承载介质372附接至第一管芯。在其他实施例中，外部光承载介质372可以在不使用用于光学耦合的折射率匹配材料370的情况下而附接至第一管芯(例如，使用插头或连接器可去除地附接)。
在图384中，将热界面材料386施加至衬底308的表面376(例如，第二衬底的包括在第一管芯中的部分)。热界面材料386的一些非限制性示例包括导热油脂、间隙填充剂(例如，弹性体片材)、绝缘硬件(例如，诸如氧化铝、氮化铝、氧化铍之类的陶瓷)、导热垫或薄膜(例如，硅胶或石墨)、导热胶带、相变材料、导热环氧树脂等。热盖388通过热界面材料386附接至第一管芯。如图所示，热盖388的表面390与热界面材料386接触。热盖388可以用作散热片或散热器。热盖388可以由任何(一种或多种)合适的材料(例如，铝、铜、碳基或石墨基复合材料等)形成。
图4是根据一个或多个实施例的用于制造光学装置的示例性方法400。方法400可以与其他实施例结合使用，例如，以执行图3A至图3I中描绘的序列。
方法400开始于框405，其中，在光子晶圆中形成多个光学元件。在一些实施例中，光子晶圆用于制造多个管芯，并且每个管芯包括相应的一个或多个光学元件。在一些实施例中，多个光学元件部分地形成在SOI衬底的表面层中。
在框410处，在电子晶圆中形成多个电子元件。在一些实施例中，电子晶圆用于制造多个管芯，并且每个管芯包括相应的一个或多个电子元件。在一些实施例中，多个电子元件部分地形成在SOI衬底的表面层中。
在框415处，将光子晶圆与电子晶圆进行接合。将光子晶圆与电子晶圆接合形成晶圆组件。在一些实施例中，将光子晶圆与电子晶圆接合包括晶圆级氧化物-氧化物接合。在框420处，去除晶圆组件的衬底以暴露光子晶圆或电子晶圆的表面。在一些实施例中，晶圆组件的衬底包括SOI衬底的半导体衬底。在一些实施例中，去除衬底包括执行光刻和化学蚀刻工艺。
在框425处，从晶圆组件的外表面形成过孔。在一些实施例中，过孔延伸至光子晶圆的金属层和电子晶圆的金属层。在一些实施例中，光子晶圆或电子晶圆从所暴露的表面生长，并增加一定厚度以限定外表面。
在框430处，中介层晶圆在表面处与晶圆组件接合。以这种方式，将中介层晶圆添加至晶圆组件中。在一些实施例中，将中介层晶圆与晶圆组件接合包括晶圆级氧化物-氧化物接合。在一些实施例中，中介层晶圆包括与过孔电耦合的贯穿过孔。在框435处，在晶圆组件上形成表面安装连接器。在一些实施例中，焊球可以附接至中介层晶圆的表面接触件。
在框440处，切割晶圆组件以形成多个管芯。在一些实施例中，切割晶圆组件包括机械锯切、划线和劈开以及激光切割中的一种或多种。还可以设想其他合适的切割技术。在一些实施例中，每个管芯的相应边缘耦合器在通过切割晶圆组件形成的界面处被光学暴露。
在框445处，将第一管芯的表面安装连接器与集成电路衬底的电接触件进行电耦合。在框450处，将外部光承载介质附接至第一管芯。在一些实施例中，以相反次序来执行框445、450。在一些实施例中，外部光承载介质包括以下各项中的一项：外部光子芯片的光波导、外部光子芯片的边缘耦合器、激光器、发光二极管、单根光纤以及对多根光纤进行布置的光纤阵列单元。
在一些实施例中，附接外部光承载介质包括将外部光承载介质与第一管芯的边缘耦合器进行光学耦合。可以通过无源和/或有源对准技术来实现将外部光承载介质与边缘耦合器光学耦合。在一些实施例中，附接外部光承载介质包括在第一管芯的界面与外部光承载介质之间施加折射率匹配材料(例如，环氧树脂)。折射率匹配材料可以被固化(例如，使用UV光或热)以将外部光承载介质附接至第一管芯。
在框455处，将热界面材料施加至衬底的表面。在框460处，将热盖(例如，散热片或散热器)附接至第一管芯，使得热盖的表面与热界面材料接触。方法400在完成框460之后结束。
图5示出了光子芯片的侧视图500，所述光子芯片包括使用多插脚嵌入式结构形成的边缘耦合器520。侧视图500所示的特征可以与其他实施例结合使用。例如，边缘耦合器520表示图3A至图3I的边缘耦合器314-1、314-2的一种可能实现方式。
在侧视图500中，光波导505(例如，硅波导)形成在边缘耦合器520上方(例如，边缘耦合器520可以嵌入在光子芯片的绝缘层中，诸如氧化物层中)。光波导505在光子芯片的一个或多个光学元件(未示出)与边缘耦合器520之间耦合光信号。在另一实施例中，多插脚结构可以相对于光波导505被翻转，使得边缘耦合器520的插脚被形成在光波导505上方的层中(即，光波导505位于边缘耦合器520的插脚与绝缘层之间)。
如侧视图500所示，边缘耦合器520的一个界面耦合至光波导505，而另一界面在光子芯片的侧表面525处被光学暴露。在一些实施例中，通过对图3F中描绘的晶圆组件执行切割工艺来形成侧表面525。在一些情况下，侧表面525可以进行进一步处理(例如，抛光)以提高与外部光承载介质的光学耦合效率。
边缘耦合器520包括波导适配器515，该波导适配器515可以与外部光承载介质(例如，FAU的光纤)光学耦合。边缘耦合器520由可以包括嵌入在绝缘材料(例如，二氧化硅或氮氧化硅)中的相同材料(例如，氮化硅或氮氧化硅)的单独插脚510A、510B、510C制成。以这种方式，单独插脚510A、510B、510C设置在不同层上，并且不同层中的每一层被电介质材料(例如，氧化物层)分离。在一个实施例中，插脚510A、510B、510C和边缘耦合器520的材料可能不同于光子芯片的绝缘层的材料。通常，边缘耦合器520可以由具有比围绕插脚510A、510B、510C的绝缘材料的材料更高的折射率的任何(一种或多种)材料来制成。
图6A至图6E示出了根据一个或多个实施例的图5的边缘耦合器520的截面图。具体地，图6A示出了波导适配器515的最靠近侧表面525(或耦合界面)的部分的截面A-A。本文中，波导适配器515包括四个单独插脚510A、510B、510C、510D，它们可以具有相同或相似的宽度(W)和高度(H)(或厚度)尺寸。这些尺寸以及插脚510A、510B、510C、510D之间的间距可以取决于具体应用而变化。在所示示例中，波导适配器515可以被配置为与具有10微米模场直径的单模光纤接口连接。如本领域普通技术人员将理解的，这些尺寸可取决于具体应用而变化。具体地，尺寸可以选择为使得耦合界面处的插脚的模与光要耦合至或从其耦合的外部器件的模基本上匹配。如本文所述，“基本上匹配”包括模大小相等的情况，以及模大小在彼此的约25％以内的情况。本文中，插脚510A、510B、510C、510D的宽度可以在约200纳米至300纳米的范围内，高度在约100纳米至250纳米之间。更具体地，宽度可以是约200纳米，而高度是约200纳米。插脚510A与插脚510C之间的距离以及插脚510D与插脚510B之间的距离可以是约两微米。如上所述，插脚510A、510B、510C、510D的尺寸以及间距可以根据耦合至光子芯片的外部光源的模或设计而变化。
图6B示出了波导适配器515的截面B-B。此图示出，随着多插脚适配器远离侧表面525凹陷时，插脚510B、510C、510D的宽度减小，而插脚510A的宽度增加。如图所示，以绝热方式使插脚510A、510B、510C、510D的宽度逐渐变细。逐渐变细导致光能从由位于波导适配器515右侧的插脚510A、510B、510C、510D限定的光学模逐渐转变，其中，插脚510A、510B、510C、510D的宽度和高度与在波导适配器515中更靠左的位置处逐渐越来越多地限定在上插脚510A中的模相同或相似。这种逐渐变细将由插脚510A、510B、510C、510D限定的光能单独传递至插脚510A。然而，反之亦然。也就是说，随着光信号从左向右传播，使宽度逐渐变细还使得在上插脚510A中引入的信号能够传递至由插脚510A、510B、510C、510D限定的模。插脚510A、510B、510C、510D的宽度可连续变化(例如，以线性或非线性方式，诸如指数地或以更高阶多项式型线)，或在替代实施例中，如波导适配器515从右向左延伸那样以离散增量变化。如图5所示，最终，插脚510B、510C、510D终止(其终止波导适配器515)，而插脚510A继续传输光信号。在一个实施例中，波导适配器515可以具有约100微米至500微米的长度。此外，波导适配器515可针对所有此长度或仅针对其一部分逐渐变细。例如，在插脚510A、510B、510C、510D的宽度开始改变之前，插脚510A、510B、510C、510D的宽度对于前5微米至50微米可以保持基本上相等。
图6C示出了边缘耦合器520的截面C-C。在此，波导适配器515已终止，留下插脚510A来承载光信号。尽管示出为线性的，但插脚510A可弯曲、变弯、扭曲等以将光信号承载至光子芯片或测试结构的不同区域。因此，插脚510A的长度可以远大于插脚510B、510C、510D的长度以使插脚510A能够将光信号承载至不同区域。
图6D示出了边缘耦合器520和光波导505的截面D-D。如图所示，插脚510A的宽度大于光波导505的宽度。此外，取决于用于制造晶圆的技术，插脚510A与光波导505之间的距离可以在数百纳米到仅几纳米之间的范围内。取决于用于制造半导体晶圆的技术，插脚510A的一部分可直接接触光波导505。
图6E示出了边缘耦合器520和光波导505的截面E-E。本文中，插脚510A的宽度已缩小，而光波导505的宽度已增大。再次以绝热方式示出的这种逐渐变细导致插脚510A中的光信号以最小的损耗传递至光波导505，并且反之亦然。最终，插脚510A终止并且光波导505可以将光信号承载至不同光学元件，例如光子芯片中。
尽管上述实施例讨论了通过改变宽度而使得插脚510A、510B、510C、510D逐渐变细，但如果高度变细或两者的某种组合，则可能发生光功率的类似传递。然而，使插脚510A、510B、510C、510D的高度逐渐变细可能需要与如图6A至图6E所示的使宽度逐渐变细不同的光刻和制造技术或材料。也不必使所有插脚的宽度都逐渐变细。例如，在一些设计中，期望的光能传递可以通过仅使插脚510A的宽度逐渐变细而不必使插脚510B、510C、510D的宽度逐渐变细来获得。
图7A和图7B示出了根据一个或多个实施例的锥形波导的视图。更具体地，图7A和图7B示出了用于在波导之间传递光信号的部分重叠的倒锥形波导结构。如图所示，图7示出了与第二锥形波导710部分重叠的第一锥形波导705的平面图。具体地，图7A可以是图5中光子芯片的一部分的布置，其中，光波导505与插脚510A重叠。波导的逐渐变细是以绝热方式完成的，以最小化光损耗。尽管图7A和图7B示出了锥形的宽度线性变化，但只要满足绝热标准，波导也可以以非线性方式逐渐变细，例如以指数或某一高阶多项式型线。在一个实施例中，第一锥形波导705与第二锥形波导710之间的距离小于一微米。例如，第一锥形波导705与第二锥形波导710可以分离100纳米或更小。分离距离会影响光信号在第一锥形波导705与第二锥形波导710之间传递的效率，因此，结构可以设计为使得第一锥形波导705与第二锥形波导710在制造技术允许的情况下尽可能接近。
图7B示出了第一锥形波导705和第二锥形波导710的俯视图。通过使第一锥形波导705与第二锥形波导710至少部分地重叠，可以在半导体晶圆的不同层中的波导之间传送光信号。在一个实施例中，第一锥形波导705和第二锥形波导710在它们的相应端开始逐渐变细的地方部分重叠。锥形的斜率或变化可取决于用于形成第一锥形波导705和第二锥形波导710的材料。在一个实施例中，在最宽点处，第一锥形波导705和第二锥形波导710可以具有范围介于200纳米至2微米之间的宽度。在最窄点处，第一锥形波导705和第二锥形波导710可以具有从100纳米至200纳米的宽度。锥形部分的长度可以在10微米至50微米之间的范围内，例如，为约20微米。
在上文中，参考了本公开中呈现的实施例。然而，本公开的范围不限于具体描述的实施例。相反，无论是否涉及不同的实施例，都涵盖所描述的特征与元件的任何组合以实现和实践所涵盖的实施例。此外，尽管本文公开的实施例可以实现优于其他可能的解决方案或现有技术的优势，但给定实施例是否实现特定优势并不会限制本公开的范围。因此，除非在(一个或多个)权利要求中明确记载，否则前述各个方面、特征、实施例和优点仅仅是说明性的并且不被认为是所附权利要求的要素或限制。
参考根据本公开中呈现的实施例的方法、装置(系统)和计算机程序产品的流程图和/或框图来描述本公开的各方面。应当理解，可以由计算机程序指令来实施流程图图示和/或框图的每个框以及流程图图示和/或框图中的各个框的组合。这些计算机程序指令可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器以产生机器，使得经由计算机或其他可编程数据处理装置的处理器执行的指令创建用于实现流程图和/或框图的一个或多个框中指定的功能/动作的方式。
这些计算机程序指令也可以存储在计算机可读介质中，所述计算机可读介质可以指示计算机、其他可编程数据处理装置或其他设备以特定方式起作用，使得存储在计算机可读介质中的指令产生制品，所述制品包括实现流程图和/或框图的一个或多个框中指定的功能/动作的指令。
计算机程序指令还可以被加载到计算机、其他可编程数据处理装置或其他设备上，以使得在计算机、其他可编程装置或其他设备上执行一系列操作步骤，以产生计算机实现的过程，使得在计算机或其他可编程装置上执行的指令提供用于实现在流程图和/或框图的一个或多个框中指定的功能/动作的过程。
图中的流程图和框图示出了根据各种实施例的系统、方法和计算机程序产品的可能实现方式的架构、功能性和操作。在这方面，流程图或框图中的每个框可以表示代码的模块、段或部分，包括用于实现指定的(一个或多个)逻辑功能的一个或多个可执行指令。还应注意，在一些替代实现方式中，框中提及的功能可以不按图中指出的次序出现。例如，连续示出的两个框实际上可以基本上同时执行，或者这些框有时可以以相反次序执行，这取决于所涉及的功能性。还将注意，框图和/或流程图图示中的每个框以及框图和/或流程图图示中的框的组合可以由执行指定功能或动作的基于专用硬件的系统或通过专用硬件和计算机指令的组合来实现。
鉴于前述内容，本公开的范围由所附权利要求决定。

Claims (23)

1.一种方法，包括：
将光子晶圆与电子晶圆进行接合以形成晶圆组件；
去除所述晶圆组件的衬底以暴露所述光子晶圆或所述电子晶圆的表面；
在所述光子晶圆的金属层与所述电子晶圆的金属层之间形成电连接；
通过在所暴露的表面处将中介层晶圆与所述晶圆组件进行接合来将所述中介层晶圆添加至所述晶圆组件，其中，所述中介层晶圆包括与所述光子晶圆和所述电子晶圆中的一者或两者的金属层电耦合的贯穿过孔；以及
切割所述晶圆组件以形成多个管芯，其中，每个管芯的相应边缘耦合器在通过所述切割形成的界面处被光学暴露。
2.根据权利要求1所述的方法，其中，(i)将所述光子晶圆与所述电子晶圆进行接合和(ii)将所述中介层晶圆与所述晶圆组件进行接合中的一者或两者包括晶圆级氧化物-氧化物接合。
3.根据权利要求1或2所述的方法，
其中，将所述光子晶圆与所述电子晶圆进行接合包括晶圆级混合接合，并且
其中，所述晶圆级混合接合在所述光子晶圆的金属层与所述电子晶圆的金属层之间形成所述电连接。
4.根据前述权利要求中任一项所述的方法，
其中，对于所述多个管芯中的每个管芯，所述相应边缘耦合器包括波导适配器，所述波导适配器与所述光子晶圆的包括在所述管芯中的部分的光波导光学耦合，并且
其中，所述波导适配器被配置为使得光信号的光学模在所述光波导处的第一较小模大小与第二较大模大小之间转换，所述第二较大模大小基本上与外部光承载介质的模大小匹配。
5.根据权利要求4所述的方法，其中，所述波导适配器包括至少一个锥形波导，所述至少一个锥形波导被配置为调整所述光学模的直径。
6.根据权利要求4或5所述的方法，
其中，所述波导适配器包括设置在不同层上的多插脚结构，并且
其中，所述不同层中的每个层由电介质材料分离。
7.根据前述权利要求中任一项所述的方法，还包括：
将外部光承载介质附接至所述多个管芯中的第一管芯，其中，所述外部光承载介质与所述第一管芯的所述边缘耦合器光学耦合。
8.根据权利要求7所述的方法，其中，将所述外部光承载介质附接至所述第一管芯，包括：
在所述第一管芯的界面与所述外部光承载介质之间施加折射率匹配材料；以及
固化所述折射率匹配材料。
9.根据权利要求7或8所述的方法，其中，所述外部光承载介质是以下各项中的一项：外部光子芯片的光波导、所述外部光子芯片的边缘耦合器、激光器、发光二极管、单根光纤以及对多根光纤进行布置的光纤阵列单元。
10.根据前述权利要求中任一项所述的方法，还包括：
在切割所述晶圆组件之前，形成与所述贯穿过孔电耦合的表面安装连接器。
11.根据权利要求10所述的方法，还包括：
将所述多个管芯中的第一管芯的所述表面安装连接器与集成电路衬底的电接触件进行电耦合。
12.根据权利要求11所述的方法，其中，去除所述晶圆组件的衬底包括去除所述晶圆组件的第一衬底并留下所述晶圆组件的第二衬底，所述方法还包括：
在将包括在所述第一管芯中的所述表面安装连接器电耦合之后，将热界面材料施加至所述第二衬底的包括在所述第一管芯中的部分；以及
通过所述热界面材料将热盖附接至所述第一管芯。
13.一种方法，包括：
在光子晶圆中形成多个光学元件，其中，所述多个光学元件包括多个边缘耦合器；
在电子晶圆中形成多个电子元件；
将所述光子晶圆与所述电子晶圆进行接合以形成晶圆组件；
在所述多个光学元件与所述多个电子元件之间形成电连接；
通过将中介层晶圆与所述晶圆组件的外表面进行接合来将所述中介层晶圆添加至所述晶圆组件，其中，所述中介层晶圆包括与所述多个光学元件和所述多个电子元件中的一者或两者电耦合的贯穿过孔；以及
切割所述晶圆组件以形成多个管芯，其中，每个管芯的相应边缘耦合器在通过所述切割形成的界面处被光学暴露。
14.根据权利要求13所述的方法，还包括：
通过去除所述晶圆组件的衬底以暴露所述光子晶圆或所述电子晶圆的表面来形成所述晶圆组件的外表面。
15.根据权利要求13或14所述的方法，其中，(i)将所述光子晶圆与所述电子晶圆进行接合和(ii)将所述中介层晶圆与所述晶圆组件进行接合中的一者或两者包括晶圆级氧化物-氧化物接合。
16.根据权利要求13、14或15所述的方法，
其中，将所述光子晶圆与所述电子晶圆进行接合包括晶圆级混合接合，并且
其中，所述晶圆级混合接合在所述光子晶圆的金属层与所述电子晶圆的金属层之间形成所述电连接。
17.根据权利要求13至16中任一项所述的方法，
其中，对于所述多个管芯中的每个管芯，所述相应边缘耦合器包括波导适配器，所述波导适配器与所述光子晶圆的包括在所述管芯中的部分的光波导光学耦合，并且
其中，所述波导适配器被配置为使得光信号的光学模在所述光波导处的第一较小模大小与第二较大模大小之间转换，所述第二较大模大小基本上与外部光承载介质的模大小匹配。
18.根据权利要求17所述的方法，其中，所述波导适配器包括至少一个锥形波导，所述至少一个锥形波导被配置为调整所述光学模的直径。
19.根据权利要求17或18所述的方法，
其中，所述波导适配器包括设置在不同层上的多插脚结构，并且
其中，所述不同层中的每个层由电介质材料分离。
20.根据权利要求13至19中任一项所述的方法，还包括：
将外部光承载介质附接至所述多个管芯中的第一管芯，其中，所述外部光承载介质与所述第一管芯的所述边缘耦合器光学耦合。
21.根据权利要求20所述的方法，其中，将所述外部光承载介质附接至所述第一管芯，包括：
在所述第一管芯的界面与所述外部光承载介质之间施加折射率匹配材料；以及
固化所述折射率匹配材料。
22.根据权利要求20或21所述的方法，其中，所述外部光承载介质是以下各项中的一项：外部光子芯片的光波导、所述外部光子芯片的边缘耦合器、激光器、发光二极管和光纤。
23.一种用于形成多个管芯的晶圆组件，所述晶圆组件包括：
光子晶圆，包括多个光学元件，其中，所述多个光学元件包括多个边缘耦合器，所述多个边缘耦合器被布置为使得所述多个管芯中的每个管芯的相应边缘耦合器将在切割界面处被光学暴露；
电子晶圆，具有与所述光子晶圆的第二表面接合的第一表面，其中，所述电子晶圆包括多个电子元件，并且其中，在所述多个光学元件与所述多个电子元件之间形成电连接；
中介层晶圆，与第三表面接合，所述第三表面是以下两者中的一者：所述电子晶圆的与所述第一表面相反的表面和所述光子晶圆的与所述第二表面相反的表面；以及
多个贯穿过孔，延伸穿过所述中介层晶圆，所述多个贯穿过孔与所述多个光学元件和所述多个电子元件中的一者或两者电耦合。
CN202080074592.5A 2019-11-07 2020-11-05 光学装置的晶圆级制造 Pending CN114616655A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/677,404 2019-11-07
US16/677,404 US11391888B2 (en) 2019-11-07 2019-11-07 Wafer-scale fabrication of optical apparatus
PCT/US2020/059104 WO2021092169A1 (en) 2019-11-07 2020-11-05 Wafer-scale fabrication of optical apparatus

Publications (1)

Publication Number Publication Date
CN114616655A true CN114616655A (zh) 2022-06-10

Family

ID=73646505

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080074592.5A Pending CN114616655A (zh) 2019-11-07 2020-11-05 光学装置的晶圆级制造

Country Status (4)

Country Link
US (1) US11391888B2 (zh)
EP (1) EP4055424A1 (zh)
CN (1) CN114616655A (zh)
WO (1) WO2021092169A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116500721A (zh) * 2023-06-27 2023-07-28 北方集成电路技术创新中心(北京)有限公司 半导体结构及其形成方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11391888B2 (en) * 2019-11-07 2022-07-19 Cisco Technology, Inc. Wafer-scale fabrication of optical apparatus
US20210249574A1 (en) 2020-02-06 2021-08-12 Lumileds Llc Light-emitting device with metal inlay and bottom contacts
US11575074B2 (en) 2020-07-21 2023-02-07 Lumileds Llc Light-emitting device with metal inlay and top contacts
US11502038B2 (en) * 2020-08-03 2022-11-15 Nanya Technology Corporation Semiconductor structure having via through bonded wafers and manufacturing method thereof
US20220189821A1 (en) * 2020-12-16 2022-06-16 Globalfoundries U.S. Inc. Heat spreading isolation structure for semiconductor devices
US20230044331A1 (en) * 2021-08-09 2023-02-09 Intel Corporation Multi-layered hybrid integrated circuit assembly

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8842945B2 (en) * 2011-08-09 2014-09-23 Soitec Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates
KR20160095731A (ko) * 2015-02-04 2016-08-12 에스케이하이닉스 주식회사 패키지 온 패키지 타입 적층 패키지 및 그의 제조방법
US9786641B2 (en) 2015-08-13 2017-10-10 International Business Machines Corporation Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
US9933566B2 (en) * 2015-11-13 2018-04-03 Cisco Technology, Inc. Photonic chip with an evanescent coupling interface
US10192857B2 (en) * 2016-10-31 2019-01-29 Hewlett Packard Enterprise Development Lp Direct bandgap semiconductor bonded to silicon photonics
US10371893B2 (en) * 2017-11-30 2019-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect device and method
SG11202009807UA (en) * 2018-04-04 2020-11-27 Univ New York State Res Found Heterogeneous structure on an integrated photonics platform
US10777430B2 (en) * 2018-06-27 2020-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Photonic integrated package and method forming same
US10393959B1 (en) 2018-10-26 2019-08-27 Cisco Technology, Inc. Photonic integrated circuit bonded with interposer
US11391888B2 (en) * 2019-11-07 2022-07-19 Cisco Technology, Inc. Wafer-scale fabrication of optical apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116500721A (zh) * 2023-06-27 2023-07-28 北方集成电路技术创新中心(北京)有限公司 半导体结构及其形成方法
CN116500721B (zh) * 2023-06-27 2023-10-24 北方集成电路技术创新中心(北京)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
WO2021092169A1 (en) 2021-05-14
US20210141154A1 (en) 2021-05-13
EP4055424A1 (en) 2022-09-14
US11391888B2 (en) 2022-07-19

Similar Documents

Publication Publication Date Title
CN114616655A (zh) 光学装置的晶圆级制造
US11156783B2 (en) Photonic integration platform
US11860415B2 (en) Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US10481326B2 (en) Photonic chip with an evanescent coupling interface
US11899251B2 (en) Vertical integrated photonics chiplet for in-package optical interconnect
US9049806B2 (en) Integrated device and manufacturing method
US9620489B2 (en) Integrated multi-chip module optical interconnect platform
US6935792B2 (en) Optoelectronic package and fabrication method
US20120207426A1 (en) Flip-chip packaging for dense hybrid integration of electrical and photonic integrated circuits
US10564352B1 (en) Photonic integrated circuit bonded with interposer
US11886023B2 (en) Photonic optoelectronic module packaging
US20230185033A1 (en) Photonic integrated circuit packaging architectures
TW202235934A (zh) 封裝及半導體元件及其形成方法
US11480745B2 (en) Companion and host chip photonic integration
US20240192439A1 (en) Heterogeneous package structures with photonic devices
WO2024118244A1 (en) Photonic integrated circuit packages including substrates with glass cores

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination