CN114614824A - Analog-to-digital converter based on time staggered noise and application method thereof - Google Patents
Analog-to-digital converter based on time staggered noise and application method thereof Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The embodiment of the invention discloses an analog-to-digital converter based on time staggered noise and an application method thereof, wherein the analog-to-digital converter comprises: the first channel switching circuit, the second channel switching circuit, the multiplexer, the shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit; according to the invention, the dual-channel conversion circuit is used for processing the level signal to be converted, wherein the first channel conversion circuit is accessed to the common mode level based on the first preset period, and the second channel conversion circuit is accessed to the common mode level based on the second preset period, so that the two channel conversion circuits can perform analog-to-digital conversion at staggered time. The full-circuit use dynamic power consumption of the analog-to-digital converter is realized by sharing the dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit, so that the application requirements of different bandwidths and different accuracies can be met along with different sampling frequencies and over-sampling rates.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an analog-to-digital converter based on time staggered noise and an application method thereof.
Background
The noise shaping successive approximation type digital-to-analog converter NS-SAR combines the advantages of a delta-sigma ADC and an SAR ADC, and is a novel ADC structure which can realize high resolution and high power consumption efficiency.
However, as the size of the capacitor in the capacitive digital-to-analog converter CDAC increases, the settling time of the digital-to-analog conversion in the successive approximation analog-to-digital converter SAR becomes significantly longer to meet the requirement of high resolution. In addition, to realize a sharp noise transfer function NTF, a margin amplification method needs to be adopted to compensate for signal attenuation, and the margin amplification process occupies the time of digital-to-analog conversion calculation, so that the time left for SAR conversion is reduced.
Although the bandwidth of the existing noise-shaped successive approximation digital-to-analog converter NS-SAR can be improved, the noise-shaped performance and the conversion efficiency of digital-to-analog conversion are negatively affected.
Disclosure of Invention
In order to solve the above technical problem, an embodiment of the present application provides a successive approximation type analog-to-digital converter based on time staggered noise, and the specific scheme is as follows:
in a first aspect, an embodiment of the present application provides an analog-to-digital converter based on time-interleaved noise, where the analog-to-digital converter includes: the first channel switching circuit, the second channel switching circuit, the multiplexer, the shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit;
the first channel switching circuit and the second channel switching circuit respectively comprise two comparison input ends, wherein a first comparison input end of the first channel switching circuit and a second comparison input end of the second channel switching circuit are used for accessing a level to be switched, the first comparison input end and a third comparison input end of the first channel switching circuit are used for accessing a common mode level in a first preset time period, and the second comparison input end and a fourth comparison input end of the second channel switching circuit are used for accessing the common mode level in a second preset time period;
the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit are also connected with the positive phase input end of the shared dynamic amplifier;
the inverting output end of the shared dynamic amplifier is connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the first feedback error circuit, and the non-inverting output end of the shared dynamic amplifier is connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the second feedback error circuit;
the positive phase output end of the shared dynamic amplifier is also connected with a third comparison input end of the first channel conversion circuit and a fourth comparison input end of the second channel conversion circuit through the feedforward error circuit;
the output ends of the first channel switching circuit and the second channel switching circuit are respectively connected with the input end of a multiplexer, and the multiplexer is used for outputting a digital signal according to a first switching signal of the first channel switching circuit and a second switching signal of the second channel switching circuit.
According to a specific implementation manner of the embodiment of the present application, the first channel conversion circuit and the second channel conversion circuit are the same, and the conversion circuit includes a DAC array having a preset number of capacitors, a data weight averaging circuit, a comparator, and a successive approximation logic circuit;
the first positive phase input end of the comparator is used for accessing the level to be converted through the DAC array, the first positive phase input end of the comparator is also used for accessing the common mode level, the first positive phase input end of the comparator is respectively connected with the output ends of the first feedback error circuit and the second feedback error circuit, and the first positive phase input end of the comparator is connected with the positive phase input end of the shared dynamic amplifier;
the second input end of the comparator is used for accessing the common mode level, and the second input end of the comparator is also connected with the output end of the feedforward error circuit;
each capacitor of the DAC array is connected with a preset electric signal branch through a capacitor switch, the successive approximation logic circuit is connected with a first part of capacitor switches of the DAC array, and the successive approximation logic circuit is also connected with a second part of capacitor switches of the DAC array through the data weight averaging circuit;
the output end of the comparator is connected with the input end of the successive approximation logic circuit, and the output end of the successive approximation logic circuit is connected with the output end of the conversion circuit.
According to a specific implementation manner of an embodiment of the present application, the DAC array includes i +1 capacitors, an upper plate branch, a lower plate branch, and an input level branch, where the capacitors are respectively connected to the upper plate branch, the lower plate branch, and the input level branch according to a preset proportional relationship;
wherein, i number of capacitors are respectively set 2 for each bit position capacitor according to a preset sequenceiRedundant ranges of LSBs;
and a capacitor covering the redundancy range of the preset value is arranged between the fifth bit and the sixth bit.
According to a specific implementation manner of the embodiment of the present application, a gain ratio of the first comparison input terminal and the third comparison input terminal of the first channel conversion circuit is 2: 1;
the gain ratio of the second comparison input terminal and the fourth comparison input terminal of the second channel switching circuit is 2: 1.
According to a specific implementation manner of the embodiment of the present application, the first feedback error circuit includes a first channel first-order feedback error branch and a second channel first-order feedback error branch, and the second feedback error circuit includes a first channel second-order feedback error branch and a second channel second-order feedback error branch;
the output end of the first channel second-order feedback error branch circuit and the output end of the second channel first-order feedback branch circuit are both connected with the first comparison input end of the first channel conversion circuit;
and the output end of the second channel second-order feedback error branch and the output end of the first channel first-order feedback branch are both connected with a second comparison input end of the second channel conversion circuit.
According to a specific implementation manner of the embodiment of the present application, the working states of the first channel switching circuit and the second channel switching circuit each include a sampling stage, a switching stage, and a margin amplifying stage;
wherein the time of the sampling phase and the margin amplifying phase accounts for 1/2 of the time period, and the time of the conversion phase accounts for 1/2 of the time period;
when the working state of the first channel switching circuit is in a sampling stage or a margin amplifying stage, the working state of the second channel switching circuit is in a switching stage;
and when the working state of the first channel conversion circuit is in a conversion stage, the working state of the second channel conversion circuit is in a sampling stage or a margin amplification stage.
According to a specific implementation manner of the embodiment of the present application, after the first channel conversion circuit completes residue amplification, the first feedback error circuit outputs a first-order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the first channel conversion circuit;
when the second channel conversion circuit completes margin amplification, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.
According to a specific implementation manner of the embodiment of the present application, the shared dynamic amplifier includes a floating reverse amplification circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch;
the floating reverse amplification circuit comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the first channel input branch, the second input end is connected with the second channel input branch, the first output end is connected with the first channel output branch, and the second output end is connected with the second channel output branch;
in a second aspect, an embodiment of the present application provides an application method of an analog-to-digital converter based on time-interleaved noise, which is applied to the analog-to-digital converter based on time-interleaved noise described in any of the foregoing first aspect and the first aspect, where the application method includes:
processing the level to be converted and the common mode level in a first preset period through a first channel conversion circuit to obtain a first conversion signal;
processing the level to be converted and the common mode level in a second preset period through a second channel conversion circuit to obtain a second conversion signal;
and performing preset calculation according to the first conversion signal and the second conversion signal through a multiplexer to output a digital circuit signal.
According to a specific implementation manner of the embodiment of the present application, the synthesized noise of the first converted signal and the second converted signalThe transfer function is calculated as:
wherein NTF represents the noise transfer function, KFBIndicating a feedback error, KFFIndicating a feedforward error, z-1KFBRepresenting a first order feedback error, z-2KFBRepresenting the second order feedback error, z-2KFFRepresenting a second order feedforward error.
The embodiment of the application provides an analog-to-digital converter based on time staggered noise and an application method thereof, wherein the analog-to-digital converter comprises: the first channel switching circuit, the second channel switching circuit, the multiplexer, the shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit; according to the embodiment of the application, the dual-channel conversion circuit processes the level signal to be converted, wherein the first channel conversion circuit is accessed to the common mode level based on the first preset period, and the second channel conversion circuit is accessed to the common mode level based on the second preset period, so that the two channel conversion circuits perform analog-to-digital conversion at staggered time. The full-circuit use dynamic power consumption of the analog-to-digital converter is realized by sharing the dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit, so that the application requirements of different bandwidths and different accuracies can be met along with different sampling frequencies and over-sampling rates.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 is a schematic circuit diagram illustrating an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application;
FIG. 2 is a block diagram of a dual-channel TI-NS-SAR with a second-order feedback error and a feedforward error of an analog-to-digital converter based on time-interleaved noise provided by an embodiment of the present application;
fig. 3 is a schematic diagram illustrating operation timing sequences of a first channel conversion circuit and a second channel conversion circuit of an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application;
FIG. 4a is a schematic diagram illustrating an interconnection of a shared dynamic amplifier of an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application;
fig. 4b is a schematic circuit diagram illustrating a shared dynamic amplifier of an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application;
FIG. 4c is a schematic diagram illustrating operation timings of different signals in a shared dynamic amplifier of an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application;
fig. 5 is a schematic method flow diagram illustrating an application method of an analog-to-digital converter based on time-interleaved noise according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Referring to fig. 1, a schematic circuit structure diagram of a successive approximation type analog-to-digital converter based on time staggered noise provided in the embodiment of the present application is shown, as shown in fig. 1, the successive approximation type analog-to-digital converter based on time staggered noise includes:
the first channel switching circuit, the second channel switching circuit, the multiplexer, the shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit;
the first channel conversion circuit and the second channel conversion circuit respectively comprise two comparison input ends, wherein a first comparison input end of the first channel conversion circuit and a second comparison input end of the second channel conversion circuit are used for accessing a level to be converted, the first comparison input end and a third comparison input end of the first channel conversion circuit are used for accessing a common mode level in a first preset time period, and the second comparison input end and a fourth comparison input end of the second channel conversion circuit are used for accessing the common mode level in a second preset time period;
the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit are also connected with the positive phase input end of the shared dynamic amplifier;
the inverting output end of the shared dynamic amplifier is respectively connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the first feedback error circuit, and the non-inverting output end of the shared dynamic amplifier is respectively connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the second feedback error circuit;
the positive phase output end of the shared dynamic amplifier is also connected with a third comparison input end of the first channel conversion circuit and a fourth comparison input end of the second channel conversion circuit through the feedforward error circuit;
the output ends of the first channel switching circuit and the second channel switching circuit are respectively connected with a multiplexer, and the multiplexer is used for outputting a digital circuit signal according to a first switching signal of the first channel switching circuit and a second switching signal of the second channel switching circuit.
In a specific embodiment, the first channel conversion circuit # CH1 and the second channel conversion circuit # CH2 have the same structure, and both the first channel conversion circuit and the second channel conversion circuit are analog-to-digital amplifiers (TI-NS-SAR) based on time-interleaved noise-shaped successive approximation type.
As shown in fig. 1, the analog-to-digital converter based on time-interleaved noise proposed in the present embodiment has a dual-channel TI-NS-SAR, i.e., the first channel conversion circuit and the second channel conversion circuit.
The first comparison input end and the third comparison input end of the first channel switching circuit pass through a first magnetic flux switch
Accessing a common mode level VCM. A second comparison input terminal and a fourth comparison input terminal of the second channel switching circuitThe comparison input end passes through a second magnetic flux switch
Accessing a common mode level VCM。
Wherein the third comparison input terminal and the fourth comparison input terminal are connected to a common mode level VCMTo perform comparator reset processing.
In a specific embodiment, the start-up time of the first channel switching circuit and the start-up time of the second channel switching circuit are different. The first channel switching circuit performs sampling, conversion and amplification cycles according to a first preset time period. And the second channel switching circuit performs sampling, conversion and amplification circulation according to a second preset time period.
The first preset time period and the second preset time period occupy the same time length, and the first preset time period is circulated in advance of the 1/2 cycle lengths of the second preset time period.
Meanwhile, the embodiment further comprises a feedforward error circuit, wherein the feedforward error circuit is used for providing a second-order feedforward error for the first channel conversion circuit and the second channel conversion circuit so as to enhance the noise shaping performance of the TI-NS-SAR at high frequency and avoid the dynamic range loss caused by the rising peak of the noise transfer function NTF.
The embodiment also comprises a shared dynamic amplifier and one-time intermediate error feedback, so that the redundant bit number of the first channel conversion circuit and the second channel conversion circuit is reduced, the redundant bit number of the first channel conversion circuit and the second channel conversion circuit is reduced to 1 bit, and higher bandwidth and more time for SAR conversion are obtained.
The normal phase input end of the shared dynamic amplifier passes through a first channel magnetic flux switch
The non-inverting input end of the shared dynamic amplifier is also connected with the first channel switching circuit and passes through the second channel magnetic fluxSwitch with a switch body
Is connected with the second channel switching circuit.
Specifically, each magnetic flux switch in this embodiment is switched on and off according to the specific operating states of the first channel switching circuit and the second channel switching circuit, so as to achieve control functions such as signal acquisition, signal output, and redundancy adjustment.
According to a specific implementation manner of the embodiment of the present application, the working states of the first channel switching circuit and the second channel switching circuit each include a sampling stage, a switching stage, and a margin amplifying stage;
wherein the time of the sampling phase and the margin amplifying phase accounts for 1/2 of the time period, and the time of the conversion phase accounts for 1/2 of the time period;
when the working state of the first channel switching circuit is in a sampling stage or a margin amplifying stage, the working state of the second channel switching circuit is in a switching stage;
and when the working state of the first channel conversion circuit is in a conversion stage, the working state of the second channel conversion circuit is in a sampling stage or a margin amplification stage.
In a specific embodiment, the sampling phase is a period during which the first channel conversion circuit and the second channel conversion circuit pre-sample the input level. The conversion stage is a period of time for the TI-NS-SAR analog-to-digital converter to carry out SAR conversion. And the margin amplification stage is a time period when the TI-NS-SAR samples the margin value through the FIR filter and amplifies the margin value through the amplifier.
Specifically, assuming that Ts is a sampling period of a single channel, the sampling phase, the conversion phase, and the margin amplification phase occupy 1/4, 1/2, and 1/4 of Ts, respectively.
The time allocation method can balance the time required by the amplification of the residual value and the redundancy range of the intermediate error feedback.
In practical applications, the times of the sampling phase and the margin amplifying phase may not be equal, but it is required to ensure that the sum of the times of the sampling phase and the margin amplifying phase is equal to the time of the conversion phase.
Specifically, as shown in fig. 3, for the conversion circuits of different channels, the sampling stage, the conversion stage, and the margin amplification stage are all non-overlapping. The sampling period of a single channel can be adaptively adjusted according to the actual application scenario, which is not limited herein.
Because the working states of the conversion circuits of different channels are not overlapped, when the first channel conversion circuit operates according to a first preset period and the second channel conversion circuit operates according to a second preset period, the clocks of the first channel conversion circuit and the second channel conversion circuit are subjected to different analog-to-digital conversion processing truncation.
It should be noted that, when the first channel switching circuit is started according to a first preset period, the second channel switching circuit is started according to a second preset period later than the start time of the first channel switching circuit, at this time, the processing state of the first channel is a sampling phase, and the processing state of the second channel is empty.
In addition, the second channel switching circuit may also be started according to a first preset period, at this time, the first channel switching circuit is started according to a second preset period, and the starting sequence is not specifically limited in this embodiment.
According to a specific implementation manner of the embodiment of the present application, after the first channel conversion circuit completes the margin amplification, the first feedback error circuit outputs a first-order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the first channel conversion circuit;
when the second channel conversion circuit finishes the margin amplification stage, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.
In a specific embodiment, when the operating state of the first channel conversion circuit or the second channel conversion circuit is in a margin amplification stage, it indicates that the first channel conversion circuit or the second channel conversion circuit has completed a sampling stage and a conversion stage in one cycle, and the first channel conversion circuit or the second channel conversion circuit performs amplification processing on the margin in the conversion stage.
The first feedback error circuit, the second feedback error circuit and the feedforward error circuit can carry out error feedback and error feedforward according to the amplification condition of the residual value. Specifically, the error feedforward and the error feedback process occur in an intermediate error feedback stage after the margin amplification stage is completed.
After the error feedforward and the error feedback are completed in the intermediate error feedback stage after the current sampling period, the feedforward error and the feedback error are used for corresponding calculation in the conversion stage of the next sampling period.
Specifically, when the first channel conversion circuit and the second channel conversion circuit complete the SAR conversion, the shared dynamic amplifier samples and amplifies the residual value, and samples the residual value on a preset FIR filter capacitor.
In the intermediate error feedback stage, C, as shown in FIG. 1FBAnd 2CFBThe sampled residue values on will be cross-coupled to another channel z through charge sharing of the DAC array-1Or self-coupling to z-2。
As shown in fig. 1, the intermediate sharing of SAR conversion may be initiated after the headroom amplification phase and continues until the conversion of the last bit of SAR is completed. In FIR z-1And z-2Has a capacitance ratio of 2:1, which together form (2 z)-1–z-2)/3. The gain G and signal attenuation factor of a shared dynamic amplifier will define K due to charge sharingFBThe value of (c). G can be used to achieve zero point optimization of NTF.
In the error feedforward stage, the sampling margin is generated through self coupling and is transmitted to a capacitor, so that the input nodes of the multi-input comparators in the same channel can share charges conveniently. The gain G of the shared dynamic amplifier, K is determined by the signal attenuation factor of the charge sharing and the ratio of the multiple input pairsFFThe value of (c). The upper plate of the CDAC is connected to one input of the comparator with a gain of 1, while the feed forward path is connected to the other input of the comparator with a gain of 0.5. This results in lower power consumption and less noise for the feed forward path.
According to a specific implementation manner of the embodiment of the present application, the first channel conversion circuit and the second channel conversion circuit are the same conversion circuit, and the conversion circuit includes a DAC array having a preset number of capacitors, a data weight averaging circuit, a comparator, and a successive approximation logic circuit;
the first positive phase input end of the comparator is used for accessing the level to be converted through the DAC array, the first positive phase input end of the comparator is also used for accessing the common mode level, the first positive phase input end of the comparator is respectively connected with the output ends of the first feedback error circuit and the second feedback error circuit, and the first positive phase input end of the comparator is connected with the positive phase input end of the shared dynamic amplifier;
the second input end of the comparator is used for accessing the common mode level, and the second input end of the comparator is also connected with the output end of the feedforward error circuit;
each capacitor of the DAC array is connected with a preset electric signal branch through a capacitor switch, the successive approximation logic circuit is connected with a first part of capacitor switches of the DAC array, and the successive approximation logic circuit is also connected with a second part of capacitor switches of the DAC array through the data weight averaging circuit;
the output end of the comparator is connected with the input end of the successive approximation logic circuit, and the output end of the successive approximation logic circuit is connected with the output end of the conversion circuit.
In a specific embodiment, as shown in fig. 1, the conversion circuit includes a digital-to-analog conversion array having a predetermined number of capacitors, where the digital-to-analog conversion array is a DAC array.
The DAC array may also be referred to as a capacitive digital-to-analog converter CDAC.
The capacitive digital-to-analog converter CDAC comprises an upper plate branch VREFPLower polar plate branch VREFNAnd input level branch VINAnd each branch is provided with a capacitance switch corresponding to each capacitor in the CDAC.
By controlling the closing of the capacitive switch, the control of the CDAC redundancy range can be achieved.
In this embodiment, the control of the capacitor switch is realized by a successive approximation logic circuit, which directly connects the capacitor from the 0 th bit to the 5 th bit of the CDAC and a capacitor switch for preventing the capacitor, via a digital signal D1<5:0>And realizing signal control.
The successive approximation logic link also connects the capacitive switches of the 7 th bit to the 22 th bit of the CDAC through the data weight averaging circuit, DWA circuit, and passes through the digital signal D1<9:6>And realizing signal control.
Specifically, in this embodiment, the 9-bit asynchronous split monotonic switch SAR is implemented by using a bottom plate sampling manner, so that additional signal attenuation caused by CDAC top plate parasitic can be avoided.
The upper plate of the CDAC is connected with the first positive input end of the comparator to output a level signal to be converted to the comparator.
The input end of the comparator is also used for accessing the common mode level and the output end of the multi-path error circuit, and the comparator is a multi-path input comparator.
The comparator can calculate the noise transfer function NTF according to a preset rule through the input of the multipath level and the error correction.
The data weight averaging circuit DWA circuit recombines the 4 most significant bits MSBs of the SAR to mitigate damage caused by capacitor mismatch in the CDAC.
According to a specific implementation manner of an embodiment of the present application, the DAC array includes i +1 capacitors, an upper plate branch, a lower plate branch, and an input level branch, where the capacitors are respectively connected to the upper plate branch, the lower plate branch, and the input level branch according to a preset proportional relationship;
wherein, i number of capacitors are respectively set 2 for each bit position capacitor according to a preset sequenceiRedundant ranges of LSBs;
and a prevention capacitor covering a preset numerical redundancy range is arranged between the fifth bit and the sixth bit.
In a specific embodiment, 1-bit redundancy is introduced between the 5 th bit 8C and the 6 th bit 16C to cover the range of the 14 least significant LSBs, so that overload risk caused by intermediate error feedback and detuning condition of the shared amplifier can be effectively prevented.
Wherein, as shown in FIG. 1, the capacitors from right to left are respectively set to 2iAnd the redundancy range of the LSBs, wherein the capacitance at the rightmost side is the 0 th bit capacitance, and the bit positions are sequentially increased towards the left.
Specifically, the value of i may be adaptively replaced according to an actual application scenario, and the value of i is not specifically limited in this embodiment.
According to a specific implementation manner of the embodiment of the present application, a gain ratio of the first comparison input terminal and the third comparison input terminal of the first channel conversion circuit is 2: 1;
the gain ratio of the second comparison input terminal and the fourth comparison input terminal of the second channel switching circuit is 2: 1.
In a specific embodiment, the gains of the first comparison input terminal and the second comparison input terminal are 1, and the gains of the third comparison input terminal and the fourth comparison input terminal are 0.5.
Of course, specific values of the first comparison input terminal, the second comparison input terminal, the third comparison input terminal and the fourth comparison input terminal may be adaptively replaced according to an actual application scenario, and the specific values of the comparison input terminals are not limited herein.
In this embodiment, the top plate of the CDAC is connected to one input of the comparator with a gain of 1, while the feed forward path is connected to the other input of the comparator with a gain of 0.5. This results in lower power consumption and less noise for the feed forward path.
The capacitance switch circuit is used to reduce the stabilization time required for charge sharing if z is injected immediately after the sampling phase-2Second order feedback error, then during SAR conversion of the most significant MSB bits, the capacitive switches may break down due to large signal swings on the CDAC array. z is a radical of-2Second order feedback errors are injected during SAR conversion to circumvent the risk of breakdown.
There is no risk of breakdown for the capacitive switch with feed forward error because it is injected into the capacitor C isolated from the main CDACAAbove. With the noise shaping enhancement of the second order error feedback, the signal-to-noise-distortion ratio SNDR can be kept above 78dB (the rated gain G of the shared dynamic amplifier is 12) under the condition of plus or minus 20% gain change. This allows the circuit to achieve high bandwidth while still maintaining sufficient noise shaping effect, despite the small OSR, without requiring any calibration to reduce gain variation of the shared dynamic amplifier.
The analog-to-digital converter of the present embodiment obtains a bandwidth of 30MHz with a sampling frequency of 330MHz and an OSR of 5.5.
According to a specific implementation manner of the embodiment of the present application, the first feedback error circuit includes a first channel first-order feedback error branch and a second channel first-order feedback error branch, and the second feedback error circuit includes a first channel second-order feedback error branch and a second channel second-order feedback error branch;
the output end of the first channel second-order feedback error branch circuit and the output end of the second channel first-order feedback branch circuit are both connected with the first comparison input end of the first channel conversion circuit;
and the output end of the second channel second-order feedback error branch and the output end of the first channel first-order feedback branch are both connected with a second comparison input end of the second channel conversion circuit.
In particular embodiments, FIG. 2 shows a block diagram of a two-channel TI-NS-SAR with second-order feedback error and feedforward error. Because of the inherent delay z between the two channels-1The remainder of one channel will be generated when the next stage is coupled to this channel. In this case, the intermediate error is fed back to generate a second-order high-pass transfer function, and the high-pass transfer function can be used as a molecular term of the target noise transfer function.
For z-1The intermediate error feedback is unavoidable because the amplification margin is not available at the beginning of the SAR conversion. For and z-2May also be used with intermediate error feedback.
As shown in FIG. 2, to further improve (1-z) in the second order NTF-1)2One of KFF×z-2Constitutes a low-pass transfer function TF at the denominator of the noise transfer function NTF, which results in KFFIn the case of 0.5, there is quantization noise suppression in the low frequency band of 3.5 dB.
In a specific embodiment, the denominator term TF (1+0.5 z) with first order feedforward error realization-1) In contrast, 1+0.5z is proposed-2The term has fewer out-of-band peaks (-5.5dB) and therefore causes less loss of dynamic range DR. The second-order feedforward error proposed by the design is realized in the two-channel TI-NS-SAR through a self-coupled feedforward channel, and the whole process does not introduce additional cross-coupling injection in the middle, as shown in the timing diagram in FIG. 3. This feed-forward injection can be introduced before the first bit SAR conversion, thus avoiding additional redundancy and alleviating overload problems due to intermediate errors in the SAR conversion process.
According to a specific implementation manner of the embodiment of the present application, the shared dynamic amplifier includes a floating reverse amplification circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch;
the floating reverse amplification circuit comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the first channel input branch, the second input end is connected with the second channel input branch, the first output end is connected with the first channel output branch, and the second output end is connected with the second channel output branch;
the first channel input branch, the second channel input branch, the first channel output branch and the second channel output branch are all connected to the common mode level.
In the specific embodiment, as shown in fig. 4a, 4b and 4c, a Floating Inverting Amplifier (FIA) and a stable output Common Mode (CM) level are used for margin amplification to compensate for signal attenuation and noise that is always coming from the FIR capacitor.
The floating-in inverting amplifier FIA may be any FIA circuit structure in the prior art, which is not limited in this embodiment.
Since the headroom amplification stages of the two channels are non-overlapping, the FIA can be shared by the two channels. The greatest benefit of this sharing is that the redundancy requirements are relaxed so that the entire detuning range can be covered. The detuning of the FIA will be provided to the SAR through an intermediate error feedback loop; it is necessary to introduce an extra redundancy window to avoid the risk of overload. Compared to a split FIA, a shared FIA contributes less detuning per channel, and therefore leads to less redundancy requirements.
The time-interleaved-noise-based full analog-to-digital conversion circuit provided by the embodiment of the application uses dynamic power consumption, so that the application requirements of different bandwidths and different accuracies can be met along with different sampling frequencies and over-sampling rates OSR.
When the DWA circuit is turned on for use, the signal-to-noise-and-distortion ratio SNDR, the signal-to-noise ratio SNR and the spurious-free dynamic range SFDR can be measured to be 73.5dB, 74.4dB and 86.6dB, respectively. With the input of two level signals of-7.5 dBFs, IMD3 was measured to be-81.6 dB and-80 dB at 25.7MHz and 26.2 MHz. The DR test was 74.7dB, and the total power consumption loss at 1V was 3.07 mW. The Schreier FoM was therefore calculated to be 173.4dB and only 0.8dB change in SNDR was measured for 5 different chip samples. The analog-to-digital converter proposed by the present embodiment significantly improves the quality factor FoMs.
Referring to fig. 5, a schematic method flow chart of an application method of an analog-to-digital converter based on time interleaving noise according to an embodiment of the present application is shown, and as shown in fig. 5, the application method of the analog-to-digital converter based on time interleaving noise according to the embodiment of the present application includes:
step S501, a level to be converted and a common mode level are processed through a first channel conversion circuit in a first preset period to obtain a first conversion signal;
step S502, processing the level to be converted and the common mode level in a second preset period through a second channel conversion circuit to obtain a second conversion signal;
in step S503, a multiplexer performs a preset calculation according to the first conversion signal and the second conversion signal to output a digital circuit signal.
According to a specific implementation manner of the embodiment of the present application, the calculation formula of the noise transfer function of the first converted signal or the second converted signal is:
wherein NTF represents the noise transfer function, KFBIndicating a feedback error, KFFIndicating a feedforward error, z-1KFBRepresenting a first order feedback error, z-2KFBRepresenting the second order feedback error, z-2KFFRepresenting a second order feed forward error.
In one embodiment, the feedback error K is determined by the connection relationship of the first feedback error circuit in FIG. 1FBThe calculation formula of (2) is as follows:
as can be seen from the connection relationship of the feedforward error circuit in FIG. 1, the feedforward error KFFThe calculation formula of (2) is as follows:
wherein G represents the gain of the shared dynamic amplifier, CFFIs the capacitance value of the capacitor ground terminal in the feedforward error circuit, CFBIs the capacitance value of the capacitor ground terminal in the feedback error circuit, CDACIs the capacitance value of the DAC array.
In an implementation aspect of the present embodiment, the capacitance and the gain may take the following values:
CDAC＝1.4pF(single-end)；CFB＝138fF；CFF＝15fF；CA＝170fF；G＝12。
in summary, the embodiments of the present application provide an analog-to-digital converter based on time-interleaved noise and an application method thereof, and the bandwidth can be effectively expanded and the bandwidth limitation faced by a single-channel NS-SAR can be avoided by setting a dual-channel TI-NS-SAR analog-to-digital conversion circuit. In addition, the analog-to-digital converter in the embodiment enhances the noise shaping through the second-order feedback error, so that the shared dynamic amplifier can meet the required noise shaping effect without any calibration of the circuit. By setting the extra redundant bit, the embodiment also avoids the influence of the time-interleaved structure on the reduction of the analog-to-digital conversion efficiency of the SAR. In addition, for a specific implementation process of the application method of the analog-to-digital converter based on the time-interleaved noise mentioned in the above embodiment, reference may be made to the specific implementation process of the above device embodiment, and details are not repeated here.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (10)
1. An analog-to-digital converter based on time-interleaved noise, the analog-to-digital converter comprising: the first channel switching circuit, the second channel switching circuit, the multiplexer, the shared dynamic amplifier, the first feedback error circuit, the second feedback error circuit and the feedforward error circuit;
the first channel conversion circuit and the second channel conversion circuit respectively comprise two comparison input ends, wherein a first comparison input end of the first channel conversion circuit and a second comparison input end of the second channel conversion circuit are used for accessing a level to be converted, the first comparison input end and a third comparison input end of the first channel conversion circuit are used for accessing a common mode level in a first preset time period, and the second comparison input end and a fourth comparison input end of the second channel conversion circuit are used for accessing the common mode level in a second preset time period;
the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit are also connected with the positive phase input end of the shared dynamic amplifier;
the inverting output end of the shared dynamic amplifier is respectively connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the first feedback error circuit, and the non-inverting output end of the shared dynamic amplifier is respectively connected with the first comparison input end of the first channel switching circuit and the second comparison input end of the second channel switching circuit through the second feedback error circuit;
the positive phase output end of the shared dynamic amplifier is also connected with a third comparison input end of the first channel conversion circuit and a fourth comparison input end of the second channel conversion circuit through the feedforward error circuit;
the output ends of the first channel switching circuit and the second channel switching circuit are respectively connected with a multiplexer, and the multiplexer is used for outputting a digital circuit signal according to a first switching signal of the first channel switching circuit and a second switching signal of the second channel switching circuit.
2. The analog-to-digital converter according to claim 1, wherein the first channel conversion circuit and the second channel conversion circuit are the same conversion circuit, and the conversion circuit comprises a DAC array having a preset number of capacitors, a data weight averaging circuit, a comparator, and a successive approximation logic circuit;
the first positive phase input end of the comparator is used for accessing the level to be converted through the DAC array, the first positive phase input end of the comparator is also used for accessing the common mode level, the first positive phase input end of the comparator is respectively connected with the output ends of the first feedback error circuit and the second feedback error circuit, and the first positive phase input end of the comparator is connected with the positive phase input end of the shared dynamic amplifier;
the second input end of the comparator is used for accessing the common mode level, and the second input end of the comparator is also connected with the output end of the feedforward error circuit;
each capacitor of the DAC array is connected with a preset electric signal branch through a capacitor switch, the successive approximation logic circuit is connected with a first part of capacitor switches of the DAC array, and the successive approximation logic circuit is also connected with a second part of capacitor switches of the DAC array through the data weight averaging circuit;
the output end of the comparator is connected with the input end of the successive approximation logic circuit, and the output end of the successive approximation logic circuit is connected with the output end of the conversion circuit.
3. The analog-to-digital converter according to claim 2, wherein the DAC array comprises i +1 capacitors, an upper plate branch, a lower plate branch and an input level branch, and the capacitors are respectively connected to the upper plate branch, the lower plate branch and the input level branch according to a preset proportional relationship;
wherein, i number of capacitors are respectively set 2 for each bit position capacitor according to a preset sequenceiRedundant ranges of LSBs;
and a prevention capacitor covering a preset numerical redundancy range is arranged between the fifth bit and the sixth bit.
4. The analog-to-digital converter of claim 1, wherein the gain ratio of the first comparison input and the third comparison input of the first channel conversion circuit is 2: 1;
the gain ratio of the second comparison input terminal and the fourth comparison input terminal of the second channel switching circuit is 2: 1.
5. The analog-to-digital converter according to claim 1, wherein the first feedback error circuit comprises a first channel first order feedback error branch and a second channel first order feedback error branch, and the second feedback error circuit comprises a first channel second order feedback error branch and a second channel second order feedback error branch;
the output end of the first channel second-order feedback error branch circuit and the output end of the second channel first-order feedback branch circuit are both connected with the first comparison input end of the first channel conversion circuit;
and the output end of the second channel second-order feedback error branch and the output end of the first channel first-order feedback branch are both connected with a second comparison input end of the second channel conversion circuit.
6. The analog-to-digital converter according to claim 1, wherein the operating states of the first channel conversion circuit and the second channel conversion circuit each include a sampling phase, a conversion phase and a margin amplification phase;
wherein, the time of the sampling phase and the time of the margin amplifying phase occupy 1/2 of the time period, and the time of the conversion phase occupies 1/2 of the time period;
when the working state of the first channel switching circuit is in a sampling stage or a margin amplifying stage, the working state of the second channel switching circuit is in a switching stage;
and when the working state of the first channel conversion circuit is in a conversion stage, the working state of the second channel conversion circuit is in a sampling stage or a margin amplification stage.
7. The analog-to-digital converter according to claim 6, wherein the first feedback error circuit outputs a first order feedback error to the second channel conversion circuit, the second feedback error circuit outputs a second order feedback error to the first channel conversion circuit, and the feedforward error circuit outputs a second order feedforward error to the first channel conversion circuit after the first channel conversion circuit completes residue amplification;
when the second channel conversion circuit completes margin amplification, the first feedback error circuit outputs a first-order feedback error to the first channel conversion circuit, the second feedback error circuit outputs a second-order feedback error to the second channel conversion circuit, and the feedforward error circuit outputs a second-order feedforward error to the second channel conversion circuit.
8. The analog-to-digital converter according to claim 1, wherein the shared dynamic amplifier comprises a floating-in inverting amplifier circuit, a first channel input branch, a second channel input branch, a first channel output branch, and a second channel output branch;
the floating reverse amplification circuit comprises a first input end, a second input end, a first output end and a second output end, wherein the first input end is connected with the first channel input branch, the second input end is connected with the second channel input branch, the first output end is connected with the first channel output branch, and the second output end is connected with the second channel output branch;
the first channel input branch, the second channel input branch, the first channel output branch and the second channel output branch are all connected to the common mode level.
9. An application method of a time-interleaved noise based analog-to-digital converter according to any one of claims 1 to 8, the application method comprising:
processing the level to be converted and the common mode level in a first preset period through a first channel conversion circuit to obtain a first conversion signal;
processing the level to be converted and the common mode level in a second preset period through a second channel conversion circuit to obtain a second conversion signal;
and performing preset calculation according to the first conversion signal and the second conversion signal through a multiplexer to output a digital signal.
10. The method according to claim 9, wherein the noise transfer function of the synthesized first converted signal and the second converted signal is calculated by:
wherein NTF represents the noise transfer function, KFBDenotes the feedback error, KFFIndicating a feedforward error, z-1KFBRepresenting a first order feedback error, z-2KFBRepresenting the second order feedback error, z-2KFFRepresenting a second order feedforward error.
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