CN114614799A - Pulse regulation and control circuit - Google Patents
Pulse regulation and control circuit Download PDFInfo
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- CN114614799A CN114614799A CN202210241206.8A CN202210241206A CN114614799A CN 114614799 A CN114614799 A CN 114614799A CN 202210241206 A CN202210241206 A CN 202210241206A CN 114614799 A CN114614799 A CN 114614799A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
Abstract
The application relates to a pulse regulation and control circuit, which comprises a first-stage circuit, a second-stage circuit, a third-stage circuit and a pulse width monitoring circuit; the first-stage circuit, the second-stage circuit and the third-stage circuit are sequentially connected in series; the first-stage circuit is used for converting a rising edge signal with a preset slope into a first pulse signal and transmitting the first pulse signal to the second-stage circuit; the second-stage circuit is used for narrowing the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal; the pulse width of the second pulse signal is smaller than that of the first pulse signal; the pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal. The pulse regulation and control circuit provided by the embodiment of the application uses a three-stage circuit and simultaneously realizes narrow pulse width output and pulse width monitoring.
Description
Technical Field
The application relates to the technical field of signal processing, in particular to a pulse regulation and control circuit.
Background
With the development of lasers, ultra-narrow laser pulses are widely applied to various fields such as main oscillation power amplifiers, electro-optical modulators, laser radars, raman spectroscopy and the like. Among them, the pulse driving circuit is an important device that affects laser pulse performance. The picosecond pulse generator is used as a core component of the pulse driving circuit and directly determines the key performance of the system. The modern engineering application has higher and higher requirements on the diversification of high-speed pulse signal sources, and the requirements are that the pulse frequency is high, the speed is high, the portability is met, and the pulse width and the amplitude of pulses can be adjusted.
However, in the pulse signal generator of the existing scheme, the pulse signal generated by the picosecond pulse signal generating circuit generally has a width of about 1000 picoseconds, a wide pulse width, or a complicated pulse regulation and control mechanism, and has certain limitations in the application in the fields of laser seed source control, radiation antenna signal source, signal detection and the like. Therefore, the development of a picosecond pulse generator with simple structure, adjustable pulse width and amplitude and capability of monitoring is a technical problem which needs to be solved in the technical field of pulse signal processing at present.
Disclosure of Invention
In order to solve the above technical problem or at least partially solve the above technical problem, the present application provides a pulse regulation and control circuit, which includes a first stage circuit, a second stage circuit, a third stage circuit, and a pulse width monitoring circuit;
the first-stage circuit, the second-stage circuit and the third-stage circuit are sequentially connected in series;
the first-stage circuit is used for converting a rising edge signal with a preset slope into a first pulse signal and transmitting the first pulse signal to the second-stage circuit; the second-stage circuit is used for narrowing the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal;
the pulse width of the second pulse signal is smaller than that of the first pulse signal;
the pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal.
In some embodiments, the first stage circuit further comprises a first capacitor, the second stage circuit further comprises a second capacitor, and the third stage circuit further comprises a third capacitor;
the first capacitor, the second capacitor and the third capacitor are sequentially connected in series;
the input end of the first capacitor is used for receiving the rising edge signal, and the output end of the first capacitor is used for outputting a first pulse signal; the input end of the second capacitor is used for receiving the first pulse signal; the output end of the third capacitor is used for outputting a second pulse signal;
the input end of the pulse width monitoring circuit is electrically connected with the output end of the first capacitor, and the output end of the pulse width monitoring circuit is electrically connected with the second capacitor; the pulse width monitoring circuit is used for providing bias voltage for the second capacitor.
In some embodiments, the first stage circuit further comprises a first resistor, the second stage circuit further comprises a second resistor, and the third stage circuit further comprises a third resistor and a fourth resistor;
the input end of the first resistor is electrically connected with the output end of the first capacitor, and the output end of the first resistor is connected with the ground;
the input end of the second resistor is electrically connected with the output end of the second capacitor, and the output end of the second resistor is connected with the ground;
the input end of the third resistor and the input end of the fourth resistor are electrically connected with the output end of the third capacitor, the output end of the third resistor is connected with the ground, and the output end of the fourth resistor is connected with the equivalent ground.
In some embodiments, the pulse width monitoring circuit comprises a comparator, an adjustable voltage source and a first choke unit connected in series in this order;
the input end of the comparator is electrically connected with the output end of the first capacitor;
the output end of the first choke unit is electrically connected with the input end of the second capacitor;
the comparator is used for monitoring the pulse width of the first pulse signal;
the adjustable voltage source is used for providing the bias voltage for the second capacitor;
the first choke unit is used for blocking an alternating current signal through a direct current signal.
In some embodiments, the pulse width monitoring circuit further comprises a second choke unit;
the input end of the second choke unit is electrically connected with the output end of the adjustable voltage source; the output end of the second choke unit is electrically connected with the input end of the second resistor;
the second resistor is an adjustable resistor.
In some embodiments, the circuit further comprises an amplitude control circuit, wherein an output end of the amplitude control circuit is electrically connected with the third stage circuit; the input end of the amplitude control circuit is used for receiving TTL voltage switch signals;
the amplitude control circuit is used for adjusting the amplitude of the second pulse signal.
In some embodiments, the amplitude control circuit comprises a fifth resistor, a microstrip impedance transformer and a PIN diode switch connected in series in sequence;
the output end of the PIN diode switch is electrically connected with the output end of the third capacitor;
and the TTL voltage switch signal is used for controlling the conduction or the closing of the PIN diode switch.
In some embodiments, an input buffer circuit is also included;
the input buffer circuit is used for adjusting an initial pulse trigger signal into the rising edge signal with a preset slope and transmitting the rising edge signal to the input end of the first-stage circuit.
In some embodiments, the input buffer circuit comprises a sixth resistor, a seventh resistor, and a PNP transistor;
the input end of the sixth resistor is used for receiving the initial pulse trigger signal;
the output end of the sixth resistor is electrically connected with the control end of the PNP triode and is used for controlling the PNP triode to be switched on or switched off;
the output end of the PNP triode is electrically connected with the seventh resistor; the seventh resistor outputs the rising edge signal;
the input buffer circuit is used for determining the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor;
wherein the frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same.
In some embodiments, the input buffer circuit further comprises an eighth resistor and an NPN transistor;
the input end of the eighth resistor is used for receiving the initial pulse trigger signal;
the output end of the eighth resistor is electrically connected with the control end of the NPN triode and is used for controlling the switching on or off of the NPN triode; the output end of the NPN triode is used for outputting the rising edge signal;
the input buffer circuit is used for adjusting the slope of the rising edge signal to be the preset slope by changing the resistance value of the eighth resistor.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
the pulse regulation and control circuit provided by the embodiment of the application uses a three-stage circuit and simultaneously realizes narrow pulse width output and pulse width monitoring. The pulse width of the first pulse signal output by the first-stage circuit can be monitored in real time, and the second-stage circuit is adopted to realize narrowing processing of the second pulse signal through adjustment of the pulse width of the first pulse signal, so that the requirement of the narrow pulse width of the pulse signal is met.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a pulse regulation circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a pulse regulation circuit according to an embodiment of the present disclosure;
fig. 3 is a diagram illustrating a correspondence relationship between a pulse width of a second pulse signal output from point P2 and a pulse width of a first pulse signal output from point P1 according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a pulse regulation circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a pulse regulation circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a pulse regulation circuit according to an embodiment of the present application.
Detailed Description
In order that the above-mentioned objects, features and advantages of the present application may be more clearly understood, the solution of the present application will be further described below. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein; it is to be understood that the embodiments described in this specification are only some embodiments of the present application and not all embodiments.
In the related art, there is a high-speed pulse generator that is formed by using an avalanche transistor and a pulse shaping transmission line technology, and a pulse signal of 500ps minimum is generated by performing frequency-selective output by using a distribution parameter effect of a transmission line on a high-frequency signal. However, since the avalanche transistor is used, although a pulse output of 500ps at minimum is obtained, the amplitude is limited, and the output pulse amplitude is low.
In the prior art, a digital circuit method is also utilized, a pulse scheme with adjustable pulse width is synthesized based on a programmable logic device FPGA and a high-speed ECL device, and the aim of large-range precise continuous adjustment of pulse width is realized through the cooperation of an FPGA internal counter and a programmable delay chip. However, the method based on the digital circuit generates a pulse signal with a wide range of precise and continuously adjustable pulse width, and the pulse width output can be controlled. But the pulse width and the output amplitude can not be controlled at the same time, and the minimum pulse width based on the method can only reach a few nanoseconds, and the requirement of the practical narrow pulse width can not be met.
In the prior art, a scheme of using a digital circuit and an analog circuit in a mixed manner is also used for achieving the purpose of simultaneously adjusting the pulse width and the amplitude, the digital circuit generates an adjustable pulse width within the range of 1.95ns-800ns, and the pulse amplitude is controlled by adjusting the current magnitude of a current source. However, by using a mix of digital and analog circuits, independent adjustability of pulse width and amplitude can be achieved. However, the scheme needs to use more integrated circuit modules, is complex in structure and high in cost, is limited by the working frequency of a digital circuit, has nanosecond pulse width, and cannot meet the requirement of narrow pulse width in practice.
In practical engineering application, many precise photoelectric detection systems all put forward higher requirements on ultra-wideband high-speed pulse signal sources, so how to accurately obtain narrow pulses and monitor the pulse width in real time, and regulate and control the pulses without increasing circuit complexity so as to improve the detection performance of the system, which is a main technical problem to be solved by the application.
In view of at least one of the above problems, an embodiment of the present application provides a pulse regulation circuit, as shown in fig. 1, where fig. 1 is a schematic structural diagram of the pulse regulation circuit provided in the embodiment of the present application, and as can be seen from fig. 1, the pulse regulation circuit includes: the pulse width monitoring circuit comprises a first-stage circuit, a second-stage circuit, a third-stage circuit and a pulse width monitoring circuit, wherein the first-stage circuit, the second-stage circuit and the third-stage circuit are sequentially connected in series. The first-stage circuit is used for converting a rising edge signal with a preset slope into a first pulse signal and transmitting the first pulse signal to the second-stage circuit. The second-stage circuit is used for narrowing the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal. The pulse width of the second pulse signal is smaller than that of the first pulse signal. The pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal.
As shown In fig. 1, the input terminal In1 of the first stage circuit is used for receiving a rising edge signal, and the output terminal Out1 of the first stage circuit is used for outputting a first pulse signal. An input end In2 of the second-stage circuit is electrically connected with an output end Out1 of the first-stage circuit, an output end Out2 of the second-stage circuit is electrically connected with an input end In3 of the third-stage circuit, and an output end Out3 of the third-stage circuit is used for outputting a second pulse signal. The pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal. The second stage circuit is used for narrowing the second pulse signal by adjusting the pulse width of the first pulse signal.
The pulse regulation and control circuit provided by the embodiment of the application uses a three-stage circuit and simultaneously realizes narrow pulse width output and pulse width monitoring. The pulse width of the first pulse signal output by the first-stage circuit can be monitored in real time, and the second-stage circuit is adopted to realize narrowing processing of the second pulse signal through adjustment of the pulse width of the first pulse signal, so that the requirement of the narrow pulse width of the pulse signal is met.
In some embodiments, the pulse width of the second pulse signal is less than the pulse width of the first pulse signal and the pulse width of the pulse signal output by the second stage circuit. Namely, the pulse width of the second pulse signal is smaller than that of the first pulse signal and that of the pulse signal at the input end of the third-stage circuit.
According to the technical scheme provided by the embodiment of the disclosure, the pulse width of the second pulse signal can be effectively reduced, and the pulse width of the second pulse signal is smaller than that of the pulse signal at the input end of the third-stage circuit by adjusting the pulse width of the first pulse signal without setting an additional pulse width regulating and controlling circuit for the third-stage circuit.
As shown in fig. 1, the output terminal Out1 of the first stage circuit, i.e., at point P1, is used for outputting a first pulse signal. The output terminal Out3 of the third stage circuit, i.e. at point P2, is used for outputting the second pulse signal. The pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal at the point P1. The second stage circuit is used for realizing narrowing processing on the second pulse signal at the point P2 by adjusting the pulse width of the first pulse signal at the point P1.
In some embodiments, as shown In FIG. 1, for example, the input terminal In4 of the pulse width monitoring circuit is electrically connected to the output terminal Out1 of the first stage circuit, and the output terminal Out4 of the pulse width monitoring circuit is electrically connected to the output terminal Out2 of the second stage circuit. The pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a pulse regulation circuit provided in an embodiment of the present application, and as can be seen from fig. 2, the first-stage circuit further includes a first capacitor C1, the second-stage circuit further includes a second capacitor C2, and the third-stage circuit further includes a third capacitor C3. The first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in series in this order. The input terminal In1 of the first capacitor C1 is used for receiving a rising edge signal, and the output terminal Out1 of the first capacitor C1 is used for outputting a first pulse signal. An input end In2 of the second capacitor C2 is electrically connected with an output end Out1 of the first capacitor C1, an input end In2 of the second capacitor C2 is used for receiving the first pulse signal, an output end Out2 of the second capacitor C2 is electrically connected with an input end In3 of the third capacitor C3, and an output end Out3 of the third capacitor C3 is used for outputting the second pulse signal.
An input end In4 of the pulse width monitoring circuit is electrically connected with an output end Out1 of the first capacitor C1, an output end Out4 of the pulse width monitoring circuit is electrically connected with the second capacitor C2, and the pulse width monitoring circuit is used for providing a bias voltage for the second capacitor C2.
In some embodiments, as shown in fig. 2, the output terminal Out4 of the pulse width monitoring circuit is electrically connected to the output terminal Out2 of the second capacitor C2.
In some embodiments, as shown in fig. 2, the first stage circuit further comprises a first resistor R1, the second stage circuit further comprises a second resistor R2, and the third stage circuit further comprises a third resistor R3 and a fourth resistor R4. The input end of the first resistor R1 is electrically connected to the output end Out1 of the first capacitor C1, and the output end of the first resistor is connected to ground. The input end of the second resistor R2 is electrically connected to the output end Out2 of the second capacitor C2, and the output end of the second resistor is connected to ground. The input end of the third resistor R3 and the input end of the fourth resistor R4 are both electrically connected with the output end Out3 of the third capacitor C3, the output end of the third resistor R3 is grounded, and the output end of the fourth resistor R4 is equivalently grounded.
Illustratively, as can be seen from fig. 2, the rising edge signal has two positive and negative terminals, which are respectively input to the first stage circuit to form a complete circuit signal loop. The output end of the first resistor R1, the output end of the second resistor R2 and the output end of the third resistor R3 are all electrically connected to the negative signal line, and a negative voltage or a low-level voltage is provided to one end of the resistor in the circuit, that is, one end equivalent to the resistor is connected to ground. The output end of the fourth resistor R4 outputs a pulse signal, and the output end of the fourth resistor R4 may be connected to a positive power supply direct-current voltage, for example, so that the output end of the fourth resistor R4 realizes an equivalent ground connection.
As shown in fig. 2, the pulse width monitoring circuit is used to monitor the pulse width of the first pulse signal output from the output terminal Out1, i.e., point P1, of the first capacitor C1. Since the output end Out3 of the third capacitor C3, that is, the pulse width of the second pulse signal output from the point P2 has a direct corresponding relationship with the pulse width of the first pulse signal output from the point P1, the pulse width of the second pulse signal output from the point P2 in the third stage circuit can be indirectly obtained by monitoring the pulse width of the first pulse signal at the point P1. Fig. 3 is a graph illustrating a correspondence relationship between a pulse width of the first pulse signal at the point P1 and a pulse width of the second pulse signal at the point P2, where fig. 3 is a graph illustrating a correspondence relationship between a pulse width of the second pulse signal output at the point P2 and a pulse width of the first pulse signal output at the point P1 according to the embodiment of the present application, and it can be seen from fig. 3 that the larger the pulse width of the first pulse signal at the point P1, the smaller the pulse width of the second pulse signal at the point P2. Conversely, when the pulse width of the first pulse signal at the point P1 is smaller, the pulse width of the second pulse signal at the point P2 is larger. Therefore, the adjustment of the pulse width of the second pulse signal at the point P2 can be achieved by adjusting the pulse width of the first pulse signal at the point P1. And the pulse width of the first pulse signal at point P1 is greater than the pulse width of the second pulse signal at point P2. The first pulse signal is a nanosecond pulse signal, and the second pulse signal is a picosecond pulse signal. Therefore, compared with the pulse width of the pulse signal of P2 point picosecond level, the pulse signal of P1 point nanosecond level adjusts the pulse width by the nanosecond regulation base number, the realization is easier, and the adjustment precision is high. Therefore, the second stage circuit is used for narrowing the second pulse signal at the output end of the third stage circuit by increasing the pulse width of the first pulse signal.
For example, as shown in fig. 3, when the pulse width of the first pulse signal is adjusted at point P1, the pulse width may be adjusted from 1.4ns to 1.6ns, where the pulse width 1.6ns at point P1 corresponds to the pulse width of the second pulse signal at point P2 being 400ps, and the pulse width 1.4ns at point P1 corresponds to the pulse width of the second pulse signal at point P2 being 700ps, that is, the pulse width of the first pulse signal is adjusted from 1.4ns to 1.6ns, the pulse width of the second pulse signal may be adjusted from 700ps to 400ps, and the pulse width at point P1 is adjusted to be larger, so that the effect of the pulse width at point P2 being smaller can be achieved, and the larger pulse width is easier to be achieved than the smaller pulse width and easier to operate. If the pulse width at the point P2 is adjusted only at the point P2, if the pulse width at the picosecond level is to be realized, the pulse width at the picosecond level can only be adjusted to be small, for example, the pulse width is directly adjusted from 700ps to 400ps, the adjustment of the pulse width must be firstly adjusted at the picosecond level, the adjustment from a small pulse width to a smaller pulse width is not easy to control, and the adjustment is not easy to realize, and the precision of adjusting the narrow pulse width from a larger pulse width at the point P1 provided by the embodiment of the present application is not high. The circuit provided by the embodiment of the application can adjust the nanosecond-level pulse width and indirectly realize the output effect of the picosecond-level pulse width.
And, by comparing the corresponding relationship between the first pulse signal outputted from the point P1 of the second stage circuit input terminal and the second pulse signal outputted from the point P2 of the third stage circuit output terminal, and the corresponding relationship between the pulse signal outputted from the point P2 of the third stage circuit input terminal and the second pulse signal outputted from the point P2 of the third stage circuit output terminal. The corresponding relationship between the first pulse signal outputted from the point P1 of the second stage circuit and the second pulse signal outputted from the point P2 of the third stage circuit is clearer and more obvious, as can be seen from fig. 3. Therefore, due to the special pulse width correspondence relationship between the first pulse signal at the point P1 and the second pulse signal at the point P2, the embodiment of the present application implements pulse width adjustment of the second pulse signal at the point P2 by performing pulse width adjustment on the first pulse signal at the point P1, and has a better effect on pulse width adjustment of the second pulse signal at the point P2. In addition, the amplitude of the first pulse signal at the point P1 is greater than that of the second pulse signal at the point P2, so that the pulse width monitoring circuit can monitor the amplitude more easily.
In some embodiments, the first stage circuit may comprise at least 2 first capacitors C1 connected in series, for example, and/or the second stage circuit may comprise at least 2 second capacitors C2 connected in series, for example, and/or the third stage circuit may comprise at least 2 third capacitors C3 connected in series, for example. According to the technical scheme provided by the embodiment of the disclosure, the capacitors connected in series are arranged in each stage of circuit, so that the RC time constant of the whole circuit is smaller, and the pulse width of the second pulse signal is narrower.
In some embodiments, as shown in fig. 4, fig. 4 is a schematic structural diagram of a pulse regulation circuit provided in an embodiment of the present application, and as can be seen from fig. 4, the pulse width monitoring circuit includes a comparator, an adjustable voltage source, and a first choke unit, which are sequentially connected in series. The input terminal of the comparator is electrically connected with the output terminal Out1 of the first capacitor C1, and the output terminal of the comparator is electrically connected with the input terminal of the adjustable voltage source. The output end of the adjustable voltage source is electrically connected with the input end of the first choke unit, and the output end of the first choke unit is electrically connected with the input end In2 of the second capacitor C2. The comparator is used for monitoring the pulse width of the first pulse signal. The adjustable voltage source is used to provide a bias voltage to the second capacitor C2. The first choke unit is used for blocking the alternating current signal through the direct current signal. Namely, the first choke unit is used for passing the dc bias voltage and preventing the leakage of the ac signal from the adjustable voltage source.
In some embodiments, the comparator is used to monitor the pulse width of the first pulse signal at point P1 of the output terminal Out1 of the first capacitor C1. The comparator may be, for example, a high-speed comparator, and the high-speed comparator may be, for example, a comparator having a response speed of 1GHz or more. The comparator may, for example, shape the first pulse signal into a square wave signal, and the comparator may monitor the pulse width of the first pulse signal in real time. The pulse width of the first pulse signal detected by the comparator is used for adjusting the voltage value of the adjustable voltage source according to the corresponding relation between the pulse width of the first pulse signal and the pulse width of the second pulse signal, then the adjustable voltage source is used for providing proper bias voltage for the second capacitor C2 in the second-stage circuit, the bias voltage can be used for adjusting the capacitance value of the second capacitor C2, the pulse width of the first pulse signal can be adjusted by changing the capacitance value of the second capacitor C2, and therefore the pulse width of the second pulse signal can be adjusted.
In some embodiments, the pulse width monitoring circuit does not affect the operation of the first stage circuit, the second stage circuit, and the third stage circuit. And through cooperation with the pulse width monitoring circuit, the second-stage capacitor C2 is a tuning capacitor, and the second capacitor C2 may include at least one of a varactor diode and an active capacitor, for example, without changing the circuit structure to adjust the pulse width of the first pulse signal. When the second capacitor C2 is a varactor, the capacitance of the varactor can be changed by the bias voltage provided by the adjustable voltage source to the second capacitor C2, and thus the pulse width of the first pulse signal can be continuously and precisely adjusted. When the second capacitor C2 is an active capacitor, the capacitance of the second capacitor C2 can be changed by the bias voltage provided by the adjustable voltage source to the second capacitor C2, and the resistive loss of the active capacitor is very low, so that the active capacitor has a high Q value.
Optionally, the adjustment of the pulse width of the rising edge signal can also be achieved by adjusting any one of the capacitance (C) and the resistance (R) in the first stage circuit, the second stage circuit and the third stage circuit, for example, by changing the RC time constant. The RC time constant may therefore be a consideration in designing the pulse conditioning circuit.
In some embodiments, as shown in fig. 4, the pulse width monitoring circuit further includes a second choke unit. The input end of the second choke unit is electrically connected with the output end of the adjustable voltage source, and the output end of the second choke unit is electrically connected with the input end of the second resistor R2. Since the input terminal of the second resistor R2 is electrically connected to the output terminal Out2 of the second capacitor C2, the output terminal of the second choke unit is electrically connected to the output terminal Out2 of the second capacitor C2. The second resistor R2 is an adjustable resistor.
Alternatively, the second resistor R2 may be, for example, an adjustable potentiometer, a sliding rheostat, or the like, the resistance value of which may be digitally encoded or manually adjusted.
Illustratively, the second capacitor C2 may be, for example, a step recovery diode, a certain forward bias voltage is provided to the second capacitor C2 by an adjustable voltage source, when the pulse signal comes, the step recovery diode is reversely biased and is equivalent to a charge storage capacitor, and at this time, the pulse width of the first pulse signal can be adjusted by changing the resistance value of the second resistor R2, and the pulse width can be adjusted to be narrower.
Optionally, the second choke unit further includes, for example, a resistance adjuster for adjusting a resistance value of the second resistor R2. The resistance adjuster may be, for example, an adjustable potentiometer, a sliding rheostat, or the like.
According to the pulse regulation and control circuit provided by the embodiment of the application, the pulse width monitoring circuit is introduced into the second-stage circuit of the three-stage circuit, so that under the condition that the first-stage circuit and the second-stage circuit are not influenced, the second capacitor can be used as a tuning capacitor by randomly selecting the variable capacitance diode, the step recovery diode or the two-port active capacitor, and therefore the effects that the adjustable range of the pulse width of the second pulse signal is wider, the minimum pulse width of the second pulse signal is further narrowed, the circuit loss is smaller, and the Q value is higher are achieved.
In some embodiments, the adjustable voltage source is a voltage source capable of adjusting voltage, such as a potentiometer, a digital-to-analog conversion voltage source, and the like.
In some embodiments, the first choke unit and the second choke unit may be, for example, the same structure or different structures. The first choke unit and the second choke unit may be, for example, high-frequency choke units, which may be, for example, choke inductors, coils, transmission line structures or microstrip impedance transformers.
In some casesIn an embodiment, referring to the circuit structure shown in fig. 4, the first choke unit and/or the second choke unit may be, for example, a microstrip impedance transformer. The input impedance Z of the microstrip impedance transformer is observed from point P1inThe following relation is satisfied:
wherein Z is0The characteristic impedance of a transmission line refers to the electrical line between the adjustable voltage source and point P1 in fig. 4. ZLThe electrical length θ is the load impedance at the other end of the transmission line, and is related to frequency, characteristic impedance, and physical length. For AC signals, when Z L0, theta pi/2, Zin→ infinity, which plays a role of preventing high frequency leakage. For a DC signal, θ is 0, Zin＝ZLAnd the function of direct current is achieved. j is a constant.
In some embodiments, a wider rejection bandwidth may be achieved, extending the range of high frequency chokes, for example, by employing a non-uniform transmission line structure.
In the pulse regulation and control circuit provided by the embodiment of the application, the first choke unit and/or the second choke unit in the pulse monitoring circuit can adopt a quarter-wavelength (lambda/4) microstrip impedance converter to replace a traditional high-frequency choke inductor, so that the effects of direct current bias and alternating current leakage resistance are achieved, an inductor with a large weight is avoided, the structure is simple and convenient, and the integration level is high. Therefore, the microstrip impedance converter is used as a high-frequency choking unit, the structure of the whole pulse regulation and control circuit can be simplified, the circuit integration level is improved, and the microstrip impedance converter is compatible with a PCB (printed circuit board) process for circuit board wiring.
In some embodiments, as shown in fig. 4, the pulse monitoring circuit further includes, for example, a fourth capacitor C4, an input terminal of the fourth capacitor C4 is electrically connected to the output terminal Out1 of the first capacitor C1, and an input terminal of the fourth capacitor C4 is also electrically connected to the output terminal of the first choke unit. The output terminal of the fourth capacitor C4 is electrically connected to the input terminal of the comparator. At this time, the input terminal of the fourth capacitor C4 and the output terminal of the first choke unit are both connected to the point P1. The fourth capacitor C4 is mainly used to prevent the voltage signal output by the adjustable voltage source from being transmitted to the comparator through the first choke unit, which may cause the pulse monitoring circuit to be short-circuited. As shown in fig. 4, in the pulse width monitoring circuit, the output terminal of the first choke unit is electrically connected to the input terminal of the second capacitor C2, and the output terminal of the second choke unit is electrically connected to the output terminal of the second capacitor C2, so that the adjustable voltage source can provide a bias voltage to the second capacitor C2.
In some embodiments, as shown in fig. 5, fig. 5 is a schematic structural diagram of a pulse regulation circuit provided in an embodiment of the present application, and as can be seen from fig. 5, the pulse regulation circuit further includes an amplitude control circuit, and an output terminal of the amplitude control circuit is electrically connected to the third stage circuit. The input end of the amplitude control circuit is used for receiving TTL voltage switch signals. The amplitude control circuit is used for adjusting the amplitude of the second pulse signal.
Optionally, TTL (Transistor logic), i.e., Transistor-Transistor logic, the TTL voltage signal is generated by a TTL device.
Alternatively, the amplitude of the second pulse signal may be larger than the amplitude of the rising edge signal and/or the amplitude of the first pulse signal, for example. Or the amplitude of the second pulse signal is less than or equal to the amplitude of the rising edge signal and/or the amplitude of the first pulse signal. Specifically, the amplitude of the second pulse signal is set according to the amplitude requirement of the actual second pulse signal, which is not limited by the embodiment of the present disclosure.
The pulse regulation and control circuit that this application embodiment provided can adjust the amplitude of the second pulse signal of output through amplitude control circuit, and this amplitude control circuit's simple structure realizes easily, and can be fine satisfy the accurate requirement to the pulse amplitude scope in the reality.
In some embodiments, as shown in fig. 5, the amplitude control circuit includes a fifth resistor R5, a microstrip impedance converter and a PIN diode switch D1 connected in series in that order. The output terminal of the PIN diode switch D1 is electrically connected to the output terminal Out3 of the third capacitor C3. The TTL voltage switch signal is used to control the conduction or the closing of the PIN diode switch D1. The input end of the fifth resistor R5 is used for receiving a TTL voltage switch signal, the output end of the fifth resistor R5 is electrically connected with the input end of the microstrip impedance converter, and the output end of the microstrip impedance converter is electrically connected with the control end of the PIN diode switch. When the TTL voltage switch signal is high, the PIN diode switch D1 turns off in the reverse direction. When the TTL voltage switch signal is at a low level, the TTL voltage switch signal controls D1 to turn on forward under the action of the bias voltage.
A common diode consists of a PN junction. A thin layer of low-doped Intrinsic (Intrinsic) semiconductor layer is added between P and N semiconductor materials, and the diode with the P-I-N structure is a PIN diode. Optionally, the PIN diode switch is a photodiode switch.
In some embodiments, the pulse regulation circuit further comprises an output driving circuit, wherein an input end of the output driving circuit is electrically connected with an output end of the third stage circuit. As shown in fig. 5, the output driving circuit includes an NPN transistor Q1, a PNP transistor Q2, a ninth resistor R9, a tenth resistor R10, a zener diode D2, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and a dc bias current source IbThe DC bias current source IbFor providing a dc bias current to the output of NPN transistor Q1. Wherein, the input end of the ninth resistor R9 and the input end of the 10 th resistor are used for receiving the supply voltage. A ninth resistor R9, an NPN triode Q1 and a direct current bias current source IbSequentially connected in series, and a sixth capacitor C6 connected in parallel with the DC bias current source IbAt both ends of the same. The tenth resistor R10 and the PNP transistor Q2 are connected in series. A ninth resistor R9, an NPN triode Q1 and a DC bias current source I connected in seriesbConnected in parallel with a tenth resistor R10 and a PNP transistor Q2 connected in series. The fifth capacitor C5 and the zener diode D2 are connected in series, the input end of the fifth capacitor C5 is electrically connected to the output end of the ninth resistor R9, and the output end of the zener diode D2 is electrically connected to the control end of the PNP triode Q2.
The PNP transistor is a transistor formed by 2P-type semiconductors and 1N-type semiconductor sandwiched therebetween, and is called a PNP transistor. The NPN transistor is a transistor formed by sandwiching a P-type semiconductor between two N-type semiconductors, and is also called a transistor.
Specifically, as shown in fig. 5, an output end Out3 of the third capacitor C3 is electrically connected to a control end of the NPN transistor Q1, an input end of the ninth resistor R9 and an input end of the tenth resistor R10 are respectively configured to receive a supply voltage, an output end of the ninth resistor R9 is electrically connected to the input end of the NPN transistor Q1, and an output end of the NPN transistor Q1 is electrically connected to the dc bias current source IbElectrically connected, DC-biased current source IbThe output end of the pulse regulation and control circuit is electrically connected with the negative power line of the pulse regulation and control circuit. A sixth capacitor C6 connected in parallel with the DC bias current source IbAt both ends of the same. The input end of a fifth capacitor C5 is electrically connected with the output end of the ninth resistor, the output end of a fifth capacitor C5 is electrically connected with the input end of a Zener diode D2, the output end of the Zener diode D2 is electrically connected with the control end of a PNP triode Q2, the output end of the PNP triode Q2 is electrically connected with the output end of a tenth resistor R10 and the input end of a seventh capacitor C7 respectively, and the input end of the PNP triode Q2 is electrically connected with the cathode power line of the pulse regulation and control circuit. The output end of the seventh capacitor C7 is used for outputting the pulse signal of the regulation end to the outside.
In some embodiments, the input terminal of the ninth resistor R9 is configured to receive a supply voltage, such as 5V.
In some embodiments, the amplitude control circuit is used to adjust the amplitude Vo of the second pulse signal, wherein the amplitude Vo of the second pulse signal satisfies the following relation:
Vo＝Vcc-Vp2-Ib*R9-VQ1_sat-VD2
wherein, VQ1_satFor the saturation voltage drop of NPN transistor Q1, Vcc is the supply voltage, VD2The clamping voltage of the zener diode D2 acts as a clipping function. I isbAnd providing a DC bias current value for the output end of the NPN triode Q1 by a DC bias voltage source. When the TTL voltage switch signal is at high level, the PIN diode switch D1 is turned off in reverse direction, and the voltage V at the P2 point of the DC static operating point of the output drive circuit isp2At this time Vp2The size of (B) is determined by R3 and R4. When TTL voltage switchWhen the signal is at low level, D1 is conducted in forward direction under the action of bias voltage, Vp2Determined by R3, R4 and R5. When the whole pulse control circuit is designed according to the circuit structure of FIG. 5, Vcc, Ib、R9、VQ1_sat、VD2All the values are fixed values, and at this time, the adjustment of the amplitude Vo of the second pulse signal can be realized according to the above formula only by adjusting the voltage at the point P2.
Therefore, the control of the maximum output signal amplitude of the second pulse signal at the point P2 is realized by setting different static operating points. The setting of the quiescent operating point is achieved by switching the bias resistance value in conjunction with PIN diode switch D1. When the TTL voltage switch signal is at low level, D1 is conducted in forward direction under the action of bias voltage, and Vp2Determined by R3, R4 and R5. When the TTL voltage switch signal is at high level, the PIN diode switch D1 is turned off in reverse direction, and the voltage V at the P2 point of the DC static operating point of the output drive circuit isp2At this time Vp2The size of (B) is determined by R3 and R4.
In the pulse regulation and control circuit provided in the embodiment of the application, as shown in fig. 5, the amplitude control circuit can provide a larger bias voltage for the static operating point of the output driving circuit, and the problem that the second pulse signal output by the third-stage circuit is weaker in amplitude and cannot drive the output driving circuit to transmit the second pulse signal outwards is solved, so that low-voltage driving of the output driving circuit can be realized. For example, a 5V supply voltage is used to supply power to the input terminal of the NPN transistor Q1, so that the output driving circuit can be guaranteed to operate normally no matter how small the amplitude of the second pulse signal output from the point P2 is, and low-voltage driving of the output driving circuit is realized.
In some embodiments, the input impedance Z of the microstrip impedance transformer in the amplitude control circuitinThe following relation is satisfied:
wherein Z is0Is the characteristic impedance of the transmission line, which is referred to as FIG. 4A wire between the adjustable voltage source and point P1. . For AC signals, when ZLWhen 0, theta, pi/2, Zin→ infinity, which plays a role of preventing high frequency leakage. For a DC signal, θ is 0, Zin＝ZL，ZLR9, which functions as a direct current.
Exemplarily, as shown in fig. 5, by setting the TTL signal to a high level, the amplitude of the obtained second pulse signal is 1V under a 50 Ω load. And setting the TTL signal to be low level to obtain the amplitude of the second pulse signal to be 2V.
In some embodiments, as shown in fig. 6, fig. 6 is a schematic diagram of another structure of a pulse regulation circuit provided in the embodiments of the present application, where the pulse regulation circuit further includes an input buffer circuit. The input buffer circuit is used for adjusting the initial pulse trigger signal into a rising edge signal with a preset slope and transmitting the rising edge signal to the input end of the first-stage circuit.
The input buffer circuit is used for receiving an initial pulse trigger signal and outputting a rising edge signal with a preset slope to the input end of the first-stage circuit.
The input buffer circuit can adjust the amplitude of the first pulse signal by adjusting the slope of the rising edge signal to be a preset slope. For example, the amplitude of the first pulse signal can be increased by adjusting the slope of the rising edge signal, and then the amplitude of the pulse signal is adjusted for the second time in the amplitude control circuit in the pulse regulation circuit, so that when the amplitude control circuit performs the increase adjustment on the amplitude of the pulse signal, the adjustment is easier, and the accuracy of the amplitude adjustment can be improved.
Parameters such as frequency, amplitude, pulse width and the like of pulse signals in the pulse regulation and control circuit are independent from each other during regulation, and cannot influence each other. And the pulse width or the frequency of the pulse signal after being adjusted can not be influenced when the amplitude of the pulse signal is adjusted. That is, if the pulse width or amplitude of the pulse signal is adjusted after the frequency adjustment of the pulse signal is finished, the frequency of the pulse signal is not affected. The pulse regulation and control circuit provided by the embodiment of the application has no sequential regulation on the three parameters of the frequency, the pulse width and the amplitude of the pulse signal, namely the three parameters can be regulated in any sequence according to the design of an actual circuit.
In some embodiments, as shown in fig. 6, the input buffer circuit is used for determining the frequency of the initial pulse trigger signal, and the input buffer circuit includes a sixth resistor R6, a seventh resistor R7, and a PNP transistor Q3. The input end of the sixth resistor R6 is used for receiving the initial pulse trigger signal. The initial pulse trigger signal has a steep rising edge. The output end of the sixth resistor R6 is electrically connected to the control end of the PNP transistor Q3, and is used to control the PNP transistor to be turned on or off. The output end of the PNP triode Q3 is electrically connected to the seventh resistor R7, and the seventh resistor R7 outputs a rising edge signal. As shown in fig. 6, the seventh resistor R7 outputs a rising edge signal at point P0. The input buffer circuit is used for determining the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor R7. The frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same. The input terminal of the PNP transistor Q3 is connected to ground.
Exemplarily, a simulation experiment is performed on an output waveform with an amplitude of 2V operating at a frequency of 30MHz, and by changing the resistance value of the seventh resistor R7, the waveform of the falling edge of the pulse is steeper, and thus a higher operating frequency can be obtained.
In some embodiments, as shown in fig. 6, the input buffer circuit is used to adjust the slope of the rising edge signal to a predetermined slope. The input buffer circuit further includes an eighth resistor R8 and an NPN transistor Q4. The input terminal of the eighth resistor R8 is used for receiving the initial pulse trigger signal. The output end of the eighth resistor R8 is electrically connected to the control end of the NPN transistor Q4, and is used to control the NPN transistor Q4 to turn on or turn off. The output of NPN transistor Q4 is used to output a rising edge signal. As shown in fig. 6, the output terminal of the NPN transistor Q4 outputs a rising edge signal at point P0. The input buffer circuit is used for changing the resistance value of the eighth resistor R8 to adjust the slope of the rising edge signal to be a preset slope.
The input buffer circuit is used for changing the resistance value of the eighth resistor R8 to adjust the slope of the rising edge signal to a preset slope. Adjustment of the amplitude of the first pulse signal may be achieved. The input end of the NPN triode Q4 is electrically connected with the power supply voltage end. The supply voltage may be, for example, 5V.
Since the amplitude of the first pulse signal output by the third stage circuit is positively correlated with the rising edge slope of the rising edge signal output at the point P0, adjusting the resistance value of the eighth resistor R8 can change the driving current of the NPN transistor Q4, and adjusting the driving current of the NPN transistor Q4 can change the rising edge slope of the rising edge signal output at the point P0 within a certain range. Therefore, the input buffer circuit provided by the embodiment of the present application can also change the amplitude of the first pulse signal output by the third stage circuit by changing the resistance value of the eighth resistor R8.
The amplitude of the second pulse signal is affected by the amplitude of the first pulse signal, namely, the larger the amplitude of the first pulse signal is, and the easier the amplitude of the second pulse signal is to adjust. Illustratively, when the resistance value of the eighth resistor R8 is decreased, the voltage is kept constant, the current supplied to the NPN transistor Q4 per unit time increases, the response speed of the second pulse signal is increased after the three-stage circuit, the slope of the rising edge of the second pulse signal is higher, the amplitude of the second pulse signal output by the third-stage circuit is larger, and therefore the adjustment of the amplitude of the second pulse signal is easier.
In some embodiments, as shown In fig. 6, the input buffer circuit further includes a waveform shaping circuit module, and the waveform shaping circuit module is further configured to shape the original trigger signal trigger In signal, where the trigger In signal is a normal square wave signal with a falling edge, and output the initial pulse trigger signal with a steep rising edge to the eighth resistor and the sixth resistor. The waveform shaping circuit module comprises an NPN triode Q5, an eleventh resistor R11 and a twelfth resistor R12. The input of the eleventh resistor R11 receives a supply voltage, which may be 5V, for example. An output end of the eleventh resistor R11 is electrically connected with an input end of an NPN triode Q5. An input end of the twelfth resistor R12 is configured to receive a trigger in signal, an output end of the twelfth resistor R12 is electrically connected to a control end of the NPN transistor Q5, and an output end of the NPN transistor Q5 is connected to a negative line of the entire circuit. The NPN transistor Q5, the eleventh resistor R11, and the twelfth resistor R12 are capable of changing the trigger in signal with a slow falling edge into the initial pulse trigger signal with a steep rising edge. The eleventh resistor R11 here outputs an initial pulse trigger signal with a steep rising edge.
The output end of the eleventh resistor R11 is electrically connected with the input end of the eighth resistor R8, and an initial pulse trigger signal with a steep rising edge is provided for the eighth resistor R8. The input end of the NPN triode Q4 is electrically connected with the power supply voltage end. An input end of the sixth resistor R6 is electrically connected with an output end of the eleventh resistor R11.
The pulse driving circuit provided by the embodiment of the application further comprises an input buffer circuit capable of shaping common square wave signals, so that the application range of the driving circuit provided by the embodiment of the application is wider. When the initial pulse trigger signal having a steep rising edge can be directly supplied to the eighth resistor and the sixth resistor, the waveform shaping circuit portion in the input buffer circuit can be omitted.
Exemplarily, after the trigger in signal with the rising edge time of 5ns is shaped by the waveform shaping circuit module in the input buffer circuit, the initial pulse trigger signal with the rising edge time of 1ns may be output, so that the rising edge becomes steep. And the output pulse width of the second pulse signal output by the 1ns initial pulse trigger signal through the three-stage circuit is 500ps, and the amplitude is 1V. The three-stage circuit provided by the embodiment of the application can well realize the effect of narrow pulse width.
The pulse regulation and control circuit provided by the embodiment of the present application is described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A pulse regulation and control circuit is characterized by comprising a first-stage circuit, a second-stage circuit, a third-stage circuit and a pulse width monitoring circuit;
the first-stage circuit, the second-stage circuit and the third-stage circuit are sequentially connected in series;
the first-stage circuit is used for converting a rising edge signal with a preset slope into a first pulse signal and transmitting the first pulse signal to the second-stage circuit; the second-stage circuit is used for narrowing the second pulse signal at the output end of the third-stage circuit by adjusting the pulse width of the first pulse signal;
the pulse width of the second pulse signal is smaller than that of the first pulse signal;
the pulse width monitoring circuit is used for monitoring the pulse width of the first pulse signal.
2. The circuit of claim 1, wherein the first stage circuit further comprises a first capacitor, the second stage circuit further comprises a second capacitor, and the third stage circuit further comprises a third capacitor;
the first capacitor, the second capacitor and the third capacitor are sequentially connected in series;
the input end of the first capacitor is used for receiving the rising edge signal, and the output end of the first capacitor is used for outputting a first pulse signal; the input end of the second capacitor is used for receiving the first pulse signal; the output end of the third capacitor is used for outputting a second pulse signal;
the input end of the pulse width monitoring circuit is electrically connected with the output end of the first capacitor, and the output end of the pulse width monitoring circuit is electrically connected with the second capacitor; the pulse width monitoring circuit is used for providing bias voltage for the second capacitor.
3. The circuit of claim 2, wherein the first stage circuit further comprises a first resistor, the second stage circuit further comprises a second resistor, and the third stage circuit further comprises a third resistor and a fourth resistor;
the input end of the first resistor is electrically connected with the output end of the first capacitor, and the output end of the first resistor is connected with the ground;
the input end of the second resistor is electrically connected with the output end of the second capacitor, and the output end of the second resistor is connected with the ground;
the input end of the third resistor and the input end of the fourth resistor are electrically connected with the output end of the third capacitor, the output end of the third resistor is connected with the ground, and the output end of the fourth resistor is connected with the equivalent ground.
4. The circuit of claim 3, wherein the pulse width monitoring circuit comprises a comparator, an adjustable voltage source and a first choke unit connected in series in this order;
the input end of the comparator is electrically connected with the output end of the first capacitor;
the output end of the first choke unit is electrically connected with the input end of the second capacitor;
the comparator is used for monitoring the pulse width of the first pulse signal;
the adjustable voltage source is used for providing the bias voltage for the second capacitor;
the first choke unit is used for blocking an alternating current signal through a direct current signal.
5. The circuit of claim 4, wherein the pulse width monitoring circuit further comprises a second choke unit;
the input end of the second choke unit is electrically connected with the output end of the adjustable voltage source; the output end of the second choke unit is electrically connected with the input end of the second resistor;
the second resistor is an adjustable resistor.
6. The circuit of claim 2, further comprising an amplitude control circuit, an output of the amplitude control circuit being electrically connected to the third stage circuit; the input end of the amplitude control circuit is used for receiving TTL voltage switch signals;
the amplitude control circuit is used for adjusting the amplitude of the second pulse signal.
7. The circuit of claim 6, wherein the amplitude control circuit comprises a fifth resistor, a microstrip impedance transformer and a PIN diode switch connected in series in sequence;
the output end of the PIN diode switch is electrically connected with the output end of the third capacitor;
and the TTL voltage switch signal is used for controlling the conduction or the closing of the PIN diode switch.
8. The circuit of claim 1, further comprising an input buffer circuit;
the input buffer circuit is used for adjusting an initial pulse trigger signal into the rising edge signal with a preset slope and transmitting the rising edge signal to the input end of the first-stage circuit.
9. The circuit of claim 8, wherein the input buffer circuit comprises a sixth resistor, a seventh resistor, and a PNP transistor;
the input end of the sixth resistor is used for receiving the initial pulse trigger signal;
the output end of the sixth resistor is electrically connected with the control end of the PNP triode and is used for controlling the PNP triode to be switched on or switched off;
the output end of the PNP triode is electrically connected with the seventh resistor; the seventh resistor outputs the rising edge signal;
the input buffer circuit is used for determining the frequency of the initial pulse trigger signal by changing the resistance value of the seventh resistor;
wherein the frequency of the initial pulse trigger signal, the frequency of the rising edge signal, the frequency of the first pulse signal and the frequency of the second pulse signal are all the same.
10. The circuit of claim 8, wherein the input buffer circuit further comprises an eighth resistor and an NPN transistor;
the input end of the eighth resistor is used for receiving the initial pulse trigger signal;
the output end of the eighth resistor is electrically connected with the control end of the NPN triode and is used for controlling the switching on or off of the NPN triode; the output end of the NPN triode is used for outputting the rising edge signal;
the input buffer circuit is used for adjusting the slope of the rising edge signal to be the preset slope by changing the resistance value of the eighth resistor.
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