CN114610136A - Self-adaptive nonlinear voltage regulation method and electronic equipment - Google Patents
Self-adaptive nonlinear voltage regulation method and electronic equipment Download PDFInfo
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- CN114610136A CN114610136A CN202210221418.XA CN202210221418A CN114610136A CN 114610136 A CN114610136 A CN 114610136A CN 202210221418 A CN202210221418 A CN 202210221418A CN 114610136 A CN114610136 A CN 114610136A
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- 230000033228 biological regulation Effects 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims abstract description 10
- 230000003044 adaptive effect Effects 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 1
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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Abstract
The invention discloses a self-adaptive nonlinear voltage regulation method and electronic equipment, which comprise a VRM power supply, a processor and a ROM (read only memory) module connected with the processor, wherein the VRM power supply is connected with the processor through a VID (video identifier) bus, the processor comprises a power control unit and a plurality of cores, and the VRM power supply outputs a self-adaptive nonlinear loadline, can self-adaptively output a loadline curve according to the number of working cores of the processor and simultaneously reduces the working voltage when the processor works at low current. The power consumption of the processor can be effectively reduced, and particularly, the power consumption of the processor can be greatly reduced under the condition that the number of working cores of the processor is small.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a self-adaptive nonlinear voltage adjusting method and electronic equipment.
Background
With the integration of processors becoming higher and higher, the processors are developing towards multi-core, low-voltage and large-current directions, and the power consumption of the processors is also becoming higher and higher. As the working current of the processor is larger and larger, and the instantaneous change of the working current of the processor is larger and larger, the working voltage of the processor can generate larger fluctuation when the current is changed instantaneously, and the working reliability of the processor is influenced, so that the load line (loadline) function is provided for a VRM power supply for supplying power to the processor by intel at the earliest. The load line (loadline) refers to the characteristic of the VRM power supply output voltage that powers the processor dropping linearly as the output current increases. The VRM power supply with the load line (loadline) function can linearly reduce the output voltage along with the increase of the output current, although the output voltage swing of the switching power supply can be effectively controlled and reduced when the working current of the processor is instantaneously changed, and meanwhile, the power consumption of the processor can be reduced and the energy efficiency of the processor can be improved when the working current of the processor is increased. However, no matter how many cores of the processor work and the working current is large in the current load line (load) technology, the VRM power supply outputs a fixed linear load line (load) to meet all working conditions of the processor, the flexibility is poor, and the load line (load) cannot be adjusted in real time according to the working conditions of the processor, so that the power consumption of the processor is reduced to the maximum extent, and the energy efficiency of the processor is improved.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a method for adaptive nonlinear voltage adjustment and an electronic device, which solve the problems in the background art.
In order to achieve the purpose, the invention is realized by the following technical scheme: an adaptive nonlinear voltage regulation method, comprising the steps of:
s1: the VRM power supply configures a load line according to the information of the processor and supplies power to the processor;
s2: the processor determines the intercept voltage of the load line through table lookup according to the current working core number and sends the configuration information of the intercept voltage to the VRM power supply;
s3: the processor judges the threshold range of the current working current and determines the slope value of the load line through table lookup;
s4: the VRM power supply outputs a segmented load line based on the slope value.
Preferably, the data interface is used for exchanging external data and comprises a wired interface and a wireless interface, the wired interface comprises USB type A, USB type C, RS232 and CAN, and the wireless interface comprises 4G/WIFI.
Preferably, the processor and VRM power supply communicate over a VID bus.
Preferably, the correspondence of the number of working cores, the intercept voltage, and the slope value in steps S2 and S3 is stored in a table manner in a storage medium of the device.
The invention also provides an adaptive non-linear voltage regulation electronic device comprising a VRM power supply, a processor, and a ROM memory module coupled to the processor, the VRM power supply coupled to the processor via a VID bus, the processor comprising a power control unit and a plurality of cores.
Preferably, the VRM power supply is used for configuring the load line according to the information of the processor and supplying power to the processor.
Preferably, the processor is configured to communicate with the VRM power supply to set the output voltage of the VRM power supply and the slope of the load line based on the number of operating cores and the change in operating current.
Preferably, the ROM storage module is configured to store a target correspondence table of the number of processor cores and the intercept voltage and the voltage slope.
The invention provides a self-adaptive nonlinear load line adjusting mechanism. Firstly, the nonlinearity means that the load line output by the VRM power supply is not linear, but the processor outputs a sectional type load line according to different load line slope values when working at different current magnitudes, so that the power consumption of the processor when working at low current can be reduced, the voltage fluctuation of the processor when the current changes instantaneously can be reduced, and the self-adaption means that the VRM power supply outputs different load lines according to different processor working core numbers.
Compared with the prior art, the invention can adaptively configure the output load line of the VRM power supply according to the number of the working cores of the processor, and reduce the power consumption of the processor when the number of the working cores is less; the slope of the VRM power supply output load line can be configured according to the working current of the processor, and the power consumption of the processor under light load is reduced.
Drawings
FIG. 1 is a schematic diagram of a VRM power supply supplying power to a processor;
FIGS. 2a and 2b are schematic views of a load line (loadline);
FIG. 3 is a configuration flowchart of embodiment 1 of the present invention;
fig. 4 is a block diagram of an electronic device according to embodiment 1 of the present invention;
FIG. 5 is a graph of a processor power supply load line (loadline) according to embodiment 1 of the present invention;
FIG. 6 is a load line (loadline) graph of example 1 of the present invention;
FIG. 7 is a schematic power consumption diagram according to embodiment 1 of the present invention;
FIG. 8 is a load line (loadline) graph according to example 2 of the present invention;
fig. 9 is a load line (loadline) graph of embodiment 3 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Fig. 1 is a schematic diagram of a VRM power supply supplying power to a processor, wherein 101 is a PWM controller of the VRM power supply, the VRM power supply is divided into multiple phases for supplying power to the processor, wherein 102, 103 and 104 are n-phase switching circuits of the VRM power supply respectively, and the output of the n-phase switching circuits is connected in parallel for supplying power to 105 the processor.
The working power consumption of the processor can be represented by the formula Ploss＝α·C·U2F, where Ploss is the processor power consumption, α is the scaling factor, C is the processor equivalent capacitance, U is the processor operating voltage, and f is the processor operating frequency, it can be seen from the equation that reducing the processor operating voltage effectively reduces the processor power consumption. The processor operating voltage currently has a range where the processor can operate properly when the VRM power supply output voltage is within the range, and beyond which the processor may be damaged or otherwise not operating properly. Therefore, to reduce processor power consumption and reduce fluctuations in the output voltage of the VRM power supply during transient changes in current, the VRM power supply outputsThe output voltage decreases as the output current increases, referred to as the load line function.
FIG. 2a is a functional diagram of a VRM power supply load line (loadline), wherein the horizontal axis represents the output current of the VRM power supply and the vertical axis represents the output voltage of the VRM power supply. The interval between the intercept voltage Vcc (the intercept voltage is the output voltage of the VRM power supply when the output current is 0) 115 and the lower limit voltage VL 116 is the voltage range in which the processor can operate normally. And 111 shows the VRM power supply turn-on load line functional output voltage curve, with the output voltage decreasing as the VRM power supply output current increases. 114 is a graph illustrating that the VRM power supply is fixed to power the processor at the intercept voltage Vcc, and the VRM power supply output voltage is fixed as the VRM power supply output current increases. As can be seen in the left diagram of FIG. 2, the VRM power supply fixes the output voltage to power the processor, the processor power consumption is region 112 plus region 113, and after the VRM power supply turns on the load line function, the processor power consumption is only region 113. It is apparent that the load line functionality of the VRM power supply may save processor power.
As shown in FIG. 2b, when the processor operating current 122 varies instantaneously from small to large and then from large to small (e.g., 500A/us), the VRM power supply output voltage also fluctuates, with time t on the horizontal axis and the VRM power supply output voltage Vout and VRM output current Iout on the vertical axis. The curve 120 is the voltage fluctuation of the fixed output voltage of the VRM power supply, and the curve 121 is the voltage fluctuation of the VRM power supply after the VRM power supply starts the load line function.
In the invention, the number of current threshold values is set according to actual needs, if one current threshold value is set, the current threshold value is taken as a node, the output smaller than the current threshold value is taken as a first slope, and the output larger than the current threshold value is taken as a second slope; if two current thresholds a and b are set, the output smaller than the current threshold a is a first slope, the output larger than the current threshold b is a second slope smaller than the current threshold b, the output larger than the current threshold b is a third slope, and so on.
Fig. 3 is a configuration flowchart of embodiment 1 of the present invention, which is set as a current threshold, in step 401, the VRM power source configures a load line (loadline) according to information of the processor and supplies power to the processor 402, in step 403, the processor determines an intercept voltage 404 of the load line through table lookup according to a current operating core number and sends configuration information of the intercept voltage to the VRM power source, in step 405, the processor determines whether a current operating current exceeds the threshold, and determines a first slope and a second slope of the load line through table lookup, in case that the current of the processor does not exceed the threshold, the load line configured with the VRM power source is the first slope 406, and in case that the current of the processor exceeds the threshold, the load line configured with the VRM power source is the second slope 407.
The load line selection and the operating slope selection for the adaptive nonlinear load line may be stored in a table in a memory medium of the electronic device such as external ROM of 208, and the processor selects the appropriate load line by looking up the table based on the number of cores and operating currents it is operating on, and then communicates with the VRM power supply via the VID bus to set the VRM power supply to cause the VRM power supply to output the desired load line. Table 1 below gives the target correspondence of processor portion operating cores to intercept voltage and voltage slope.
TABLE 1 target correspondence of processor core count to intercept voltage and voltage slope
Fig. 4 is a block diagram of an electronic device according to embodiment 1 of the present invention, which includes a VRM power supply 201, a processor 207, and a ROM memory module 208 connected to the processor, where the VRM power supply 201 and the processor 207 are connected via a VID bus, and the processor 207 includes a power control unit 206 and 4 cores 202, 203, 204, 205.
As shown in fig. 5, which is a graph of a processor power supply load line (loadline) in embodiment 1 of the present invention, 214 an intercept voltage VCC is an upper limit of an operating voltage of a processor, 215 a voltage VL is a lower limit of the operating voltage of the processor, and the processor can normally operate within a range of the voltage VL-VCC. Currently, a VRM power supply can only configure one load line to satisfy all operating conditions of a processor, no matter how many cores of the processor are operating. The output voltage Vout is Vcc-Iout R, Vcc is the intercept voltage 214, Iout is the processor operating current, and R is the load line slope. When all 4 cores of the processor work, the processor works at the maximum current 211, when only 2 cores of the processor work, the maximum working current 212 of the 2 cores is almost 1/2 of the maximum working current 211 of the 4 cores, the voltage drop is almost half of the working voltage drop of the 4 cores, when only 1 core of the processor works, the maximum working current 213 of the 1 core is almost 1/4 of the maximum working current of the 4 cores, and the voltage drop is almost 1/4 of the working voltage drop of the 4 cores.
As shown in fig. 6, which is a load line (loadline) graph of embodiment 1 of the present invention, 225 is a VRM power supply output load line (loadline) when the processor 3 or 4 cores are operating, an intercept voltage 222 at zero current of the VRM power supply is Vcc1, 226 is a VRM power supply output load line when only 1 or 2 cores of the processor are operating, and an intercept voltage 223 at zero current of the VRM power supply is Vcc 2. The VRM power supply self-adaptive output load line can realize that the working voltage of the processor is integrally reduced when the number of the working cores of the processor is small, so that the power consumption of the processor when the number of the working cores of the processor is small can be greatly reduced.
FIG. 7 is a power consumption diagram of embodiment 1 of the present invention, wherein 317 is the output load line of the prior art VRM power supply, the intercept voltage 319 is Vcc, and the processor power consumption is the sum of the areas 314, 312 and 318, and the processor power consumption saved is 310 areas. 311 is the VRM power supply output nonlinear load line and the intercept voltage 315 is Vcc1, where the processor power consumption is the sum of 314 and 312 regions and the processor power saved is the sum of 310 and 318 regions. 313 is the VRM power output nonlinear load line when the number of processor cores is small, the intercept voltage 316 is Vcc3, the processor power consumption is 314 region, and the saved processor power consumption is the sum of 312, 310 and 318 regions. As is apparent from fig. 6, the adaptive non-linear load line can further reduce the power consumption of the processor compared to the prior art, especially when the number of cores of the processor is small.
As shown in fig. 8, which is a load line (loadline) graph of embodiment 2 of the present invention, a three-segment adaptive non-linear load line diagram using a 4-core processor as an example, when only 1 or 2 cores of the processor are in operation, the VRM power output load lines 412, 412 are divided into a first slope segment 416, a second slope segment 417 and a third slope segment 418. When the processor has 3 or 4 cores in operation, the VRM power supply outputs load line 411. 411 is divided into a first slope segment 413, a second slope segment 414 and a third slope segment 415. The division of the load line into different slope segments increases system control complexity but may reduce processor power consumption.
Referring to fig. 9, which is a load line (loadline) graph of embodiment 3 of the present invention, taking a 4-core processor as an example, a VRM power supply is configured with 3 loadlines, where the VRM power supply outputs a load line 427 when the intercept voltage Vcc3 is 424 when only one core of the processor is operating, the VRM power supply outputs a load line 426 when two cores of the processor are operating, the intercept voltage Vcc2 is 423 when 3 or 4 cores of the processor are operating, the VRM power supply outputs a load line 425 when the intercept voltage Vcc1 is 422. The VRM power supply may be adapted to output load lines 425, 426, 427 in comparison to a processor that has only 1 load line for the VRM power supply regardless of whether several cores are operating, which may reduce processor power consumption, particularly when only 1 or 2 cores are operating.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (7)
1. A self-adaptive nonlinear voltage regulation method is characterized in that: the method comprises the following steps:
s1: the VRM power supply configures a load line according to the information of the processor and supplies power to the processor;
s2: the processor determines the intercept voltage of the load line through table lookup according to the current working core number and sends the configuration information of the intercept voltage to the VRM power supply;
s3: the processor judges the threshold range of the current working current and determines the slope value of the load line through table lookup;
s4: the VRM power supply outputs a segmented load line based on the slope value.
2. The adaptive non-linear voltage regulation method of claim 1, wherein: the processor and VRM power supply communicate over a VID bus.
3. The adaptive non-linear voltage regulation method of claim 1, wherein: the correspondence of the number of working cores, the intercept voltage, and the slope value in the steps S2 and S3 is stored in a storage medium of the device in a table manner.
4. An adaptive non-linear voltage regulation electronic device, characterized by: the processor comprises a VRM power supply, a processor and a ROM storage module connected with the processor, wherein the VRM power supply is connected with the processor through a VID bus, and the processor comprises a power control unit and a plurality of cores.
5. An adaptive non-linear voltage regulation electronic device as recited in claim 4, wherein: the VRM power supply is used for configuring the load line according to the information of the processor and supplying power to the processor.
6. An adaptive non-linear voltage regulation electronic device as recited in claim 4, wherein: the processor is used for communicating with the VRM power supply to set the output voltage of the VRM power supply and the slope of a load line according to the number of the working cores and the change of the working current.
7. An adaptive non-linear voltage regulation electronic device as recited in claim 4, wherein: the ROM storage module is used for storing a target corresponding relation table of the number of the working cores of the processor, intercept voltage and voltage slope.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210221418.XA CN114610136A (en) | 2022-03-07 | 2022-03-07 | Self-adaptive nonlinear voltage regulation method and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210221418.XA CN114610136A (en) | 2022-03-07 | 2022-03-07 | Self-adaptive nonlinear voltage regulation method and electronic equipment |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070260899A1 (en) * | 2006-05-03 | 2007-11-08 | Edward Burton | Mechanism for adaptively adjusting a direct current loadline in a multi-core processor |
| US20190050039A1 (en) * | 2017-08-10 | 2019-02-14 | Microsoft Technology Licensing, Llc | Load line regulation via clamping voltage |
| US10948934B1 (en) * | 2019-11-08 | 2021-03-16 | Alpha And Omega Semiconductor (Cayman) Limited | Voltage regulator with piecewise linear loadlines |
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- 2022-03-07 CN CN202210221418.XA patent/CN114610136A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070260899A1 (en) * | 2006-05-03 | 2007-11-08 | Edward Burton | Mechanism for adaptively adjusting a direct current loadline in a multi-core processor |
| US20190050039A1 (en) * | 2017-08-10 | 2019-02-14 | Microsoft Technology Licensing, Llc | Load line regulation via clamping voltage |
| US10948934B1 (en) * | 2019-11-08 | 2021-03-16 | Alpha And Omega Semiconductor (Cayman) Limited | Voltage regulator with piecewise linear loadlines |
| CN112787506A (en) * | 2019-11-08 | 2021-05-11 | 万国半导体国际有限合伙公司 | Voltage modulator with piecewise linear load line |
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Application publication date: 20220610 |