CN114597244A - Display panel and mobile terminal - Google Patents
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- CN114597244A CN114597244A CN202210200015.7A CN202210200015A CN114597244A CN 114597244 A CN114597244 A CN 114597244A CN 202210200015 A CN202210200015 A CN 202210200015A CN 114597244 A CN114597244 A CN 114597244A
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- 206010070834 Sensitisation Diseases 0.000 claims abstract description 23
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- 230000031700 light absorption Effects 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 97
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- 238000002161 passivation Methods 0.000 claims description 54
- -1 phosphorus ions Chemical class 0.000 claims description 15
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
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- Life Sciences & Earth Sciences (AREA)
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Abstract
The embodiment of the application provides a display panel and a mobile terminal; the display panel comprises a plurality of sub-pixel units, at least one sub-pixel unit comprises a switch transistor and at least one photosensitive sensor, the photosensitive sensor comprises a shading layer, a first insulating layer, a light absorption layer and a photosensitive electrode layer, wherein the orthographic projection of the light absorption layer on the shading layer is positioned in the shading layer, the photosensitive electrode layer comprises a first photosensitive electrode and a second photosensitive electrode which are arranged in a separated mode, the first photosensitive electrode is electrically connected with the first end of the light absorption layer, and the second photosensitive electrode is electrically connected with the second end of the light absorption layer; above-mentioned display panel is through setting up at least one photosensor in at least one sub-pixel unit, and photosensor includes light-absorbing layer and with light-absorbing layer electric connection's sensitization electrode layer, only needs increase an amorphous silicon process and just can be integrated in the inside of sub-pixel unit with photosensor to low-cost local ambient light that detects has been realized.
Description
Technical Field
The application relates to the field of display, in particular to a display panel and a mobile terminal.
Background
With the rapid development of the panel industry, people have put forward other requirements on the display panel besides the requirements on the display such as high resolution, wide viewing angle, low power consumption and the like. The display panel has the advantages of enriching panel functions, increasing man-machine interaction and improving the competitiveness of the display panel, and is one of the main development directions of the current display panels. The ambient light detection function can automatically adjust the screen brightness according to the brightness of an external environment, and can automatically turn on a flash lamp or supplement light according to the external environment when photographing.
However, the existing ambient light sensor basically adopts a plug-in mode, which inevitably increases the manufacturing cost. Therefore, how to integrate the ambient light sensor into the array substrate with a smaller number of photomasks to realize low-cost ambient light detection integration has become a technical difficulty for various panel manufacturers and terminal manufacturers.
Therefore, a display panel and a mobile terminal are needed to solve the above technical problems.
Disclosure of Invention
The embodiment of the application provides a display panel and a mobile terminal, which can solve the technical problem that the current display panel is difficult to realize low-cost detection of ambient light.
The embodiment of the application provides a display panel, which comprises a plurality of sub-pixel units, wherein at least one sub-pixel unit comprises a switch transistor and at least one photosensitive sensor; the photosensitive sensor comprises a shading layer, a first insulating layer arranged on the shading layer, a light absorption layer arranged on the first insulating layer and a photosensitive electrode layer arranged on the light absorption layer;
wherein, the light-absorbing layer is in orthographic projection on the light shield layer is located in the light shield layer, the sensitization electrode layer is including the first sensitization electrode and the second sensitization electrode that the separation set up, first sensitization electrode with the first end electricity on light-absorbing layer is connected, the second sensitization electrode with the second end electricity on light-absorbing layer is connected.
Optionally, in some embodiments of the present application, the photosensitive sensor further includes a second metal layer, the second metal layer is on the same layer as the source/drain metal layer in the switch transistor and is arranged in an insulating manner, and the second metal layer includes a first metal block and a second metal block arranged in an insulating manner with the first metal block;
the first photosensitive electrode is electrically connected with a driving chip of the display panel through the first metal block, and the second photosensitive electrode is electrically connected with the driving chip through the second metal block.
Optionally, in some embodiments of the present application, the light shielding layer includes at least two of a first sub-light shielding layer, a second sub-light shielding layer, and a third sub-light shielding layer;
the first sub-shading layer and the shading metal layer in the switch transistor are arranged on the same layer in an insulating mode, the second sub-shading layer and the grid metal layer in the switch transistor are arranged on the same layer in an insulating mode, and the third sub-shading layer and the second metal layer are arranged on the same layer in an insulating mode.
Optionally, in some embodiments of the present application, the photosensitive sensor further includes an ohmic contact layer disposed on the light absorbing layer, the ohmic contact layer including a first sub-ohmic contact layer and a second sub-ohmic contact layer disposed in insulation with the first sub-ohmic contact layer;
the first photosensitive electrode is electrically connected with the light absorption layer through the first sub-ohmic contact layer, and the second photosensitive electrode is electrically connected with the light absorption layer through the second sub-ohmic contact layer.
Optionally, in some embodiments of the present application, the material of the ohmic contact layer is an amorphous silicon layer heavily doped with phosphorus ions, and the material of the light absorbing layer is an amorphous silicon layer.
Optionally, in some embodiments of the present application, each of the first photosensitive electrode layer and the second photosensitive electrode layer includes a first sub-electrode and a second sub-electrode disposed on the first sub-electrode, the first sub-electrode is electrically connected to the light absorbing layer through the ohmic contact layer, and the second sub-electrode is electrically connected to the second metal layer;
the first sub-electrode and the common electrode in the switch transistor are arranged on the same layer and in an insulating mode, and the second sub-electrode and the pixel electrode in the switch transistor are arranged on the same layer and in an insulating mode.
Optionally, in some embodiments of the present application, each of the first photosensitive electrode layer and the second photosensitive electrode layer includes a third sub-electrode, one end of the third sub-electrode is directly electrically connected to the light absorbing layer, and the other end of the third sub-electrode is electrically connected to the second metal layer;
the third sub-electrode and the pixel electrode in the switch transistor are arranged in the same layer and in an insulating mode.
Optionally, in some embodiments of the present application, the switching transistor further includes a planarization layer, a first passivation layer disposed on the planarization layer, the common electrode disposed on the first passivation layer, a second passivation layer disposed on the first passivation layer and covering the common electrode, and the pixel electrode disposed on the second passivation layer;
wherein the first insulating layer includes the first passivation layer or a stack of the planarization layer and the first passivation layer.
Optionally, in some embodiments of the present application, a portion of the planarization layer corresponding to the photosensitive sensor has an opening, and a portion of the first passivation layer is disposed in the opening;
wherein the light absorbing layer is disposed on the first passivation layer and within the opening.
Correspondingly, the embodiment of the application also provides a mobile terminal, which comprises a terminal main body and the display panel, wherein the terminal main body and the spliced display panel are combined into a whole.
The embodiment of the application provides a display panel and a mobile terminal; the display panel comprises a plurality of sub-pixel units, wherein at least one sub-pixel unit comprises a switch transistor and at least one photosensitive sensor, the photosensitive sensor comprises a light shielding layer, a first insulating layer arranged on the light shielding layer, a light absorbing layer arranged on the first insulating layer and a photosensitive electrode layer arranged on the light absorbing layer, wherein the orthographic projection of the light absorbing layer on the light shielding layer is positioned in the light shielding layer, the photosensitive electrode layer comprises a first photosensitive electrode and a second photosensitive electrode which are arranged in a separated mode, the first photosensitive electrode is electrically connected with a first end of the light absorbing layer, and the second photosensitive electrode is electrically connected with a second end of the light absorbing layer; above-mentioned display panel is through at least one set up at least one photosensor in the sub-pixel unit, photosensor include light-absorbing layer and with light-absorbing layer electric connection's sensitization electrode layer, only need increase an amorphous silicon process will photosensor integrate in the inside of sub-pixel unit to realized that low cost is local to detect ambient light.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;
FIG. 4 is a schematic flow chart of a manufacturing method for manufacturing a first display panel provided in the present application;
fig. 5A to 5E are specific processes of a method for manufacturing a display panel provided by the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application aims at the technical problem that the current display panel is difficult to realize low-cost detection of the ambient light, and the embodiment of the application can improve the technical problem.
The technical solution of the present application will now be described with reference to specific embodiments.
Referring to fig. 1 to 5E, an embodiment of the present invention provides a display panel 10, which includes a plurality of sub-pixel units, at least one of the sub-pixel units includes a switch transistor T1 and at least one photosensor S1; wherein the photosensitive sensor S1 includes a light shielding layer 201, a first insulating layer disposed on the light shielding layer 201, a light absorbing layer 203 disposed on the first insulating layer, and a photosensitive electrode layer disposed on the light absorbing layer 203;
wherein, light-absorbing layer 203 is in orthographic projection on light-shielding layer 201 is located in light-shielding layer 201, the sensitization electrode layer includes first sensitization electrode 205 and the second sensitization electrode 206 of separation setting, first sensitization electrode 205 with the first end electricity of light-absorbing layer 203 is connected, second sensitization electrode 206 with the second end electricity of light-absorbing layer 203 is connected.
The above-mentioned display panel 10 that this application embodiment provided is through at least one set up at least one photosensor S1 in the sub-pixel unit, photosensor S1 include light-absorbing layer 203 and with light-absorbing layer 203 electric connection' S photosensitive electrode layer, only need increase an amorphous silicon process will photosensor S1 integrate in the inside of sub-pixel unit to realized that low cost is local to detect ambient light.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Fig. 1 is a schematic diagram of a first cross-sectional structure of a display panel 10 according to an embodiment of the present disclosure; wherein the display panel 10 comprises a plurality of sub-pixel units, at least one of which comprises a switch transistor T1 and at least one photosensor S1; the photosensitive sensor S1 includes a light shielding layer 201, a first insulating layer disposed on the light shielding layer 201, a light absorbing layer 203 disposed on the first insulating layer, and a photosensitive electrode layer disposed on the light absorbing layer 203;
wherein, light-absorbing layer 203 is in orthographic projection on light-shielding layer 201 is located in light-shielding layer 201, the sensitization electrode layer includes first sensitization electrode 205 and the second sensitization electrode 206 of separation setting, first sensitization electrode 205 with the first end electricity of light-absorbing layer 203 is connected, second sensitization electrode 206 with the second end electricity of light-absorbing layer 203 is connected.
In the embodiment of the present application, a portion of the sub-pixel unit corresponding to the switching transistor T1 includes a substrate 101, a light shielding metal layer 102 disposed on the substrate 101, a buffer layer 103 disposed on the substrate 101 and covering the light shielding metal layer 102, an active layer 104 disposed on the buffer layer 103, a gate insulating layer 105 disposed on the buffer layer 103 and covering the active layer 104, a gate metal layer 106 disposed on the gate insulating layer 105, an interlayer insulating layer 107 disposed on the gate insulating layer 105 and completely covering the gate metal layer 106, a source/drain metal layer 108 disposed on the interlayer insulating layer 107, a planarization layer 109 disposed on the interlayer insulating layer 107 and completely covering the source/drain metal layer 108, a first passivation layer 110 disposed on the planarization layer 109, a common electrode 111 disposed on the first passivation layer 110, a second passivation layer 111 disposed on the first passivation layer 110, and a gate insulating layer 105 disposed on the gate insulating layer 103, A second passivation layer 112 disposed on the first passivation layer 110 and covering the common electrode 111, and a pixel electrode 113 disposed on the second passivation layer 112;
in a top view direction of the display panel 10, an orthogonal projection of the active layer 104 on the substrate 101 is located in the light-shielding metal layer 102, and an orthogonal projection of the gate metal layer 106 on the substrate 101 is located in the light-shielding metal layer 102.
Further, a first via hole 1071 and a second via hole 1072 are disposed on the interlayer insulating layer 107, the source electrode 1081 of the source/drain metal layer 108 is electrically connected to one end of the active layer 104 through the first via hole 1071, and the drain electrode 1082 of the source/drain metal layer 108 is electrically connected to the other end of the active layer 104 through the second via hole 1072.
Further, a sixth via hole 1123 is disposed on the second passivation layer 112, and the pixel electrode 113 is electrically connected to the source 1081 of the source-drain metal layer 108 through the sixth via hole 1123.
In the embodiment of the present application, the portion of the sub-pixel unit corresponding to the photosensor S1 includes the substrate 101, a first sub-shading layer 2011 disposed on the substrate 101, the buffer layer 103 disposed on the substrate 101 and covering the first sub-shading layer 2011, a gate insulating layer 105 disposed on the buffer layer 103, a second sub-shading layer 2012 disposed on the gate insulating layer 105, the interlayer insulating layer 107 disposed on the gate insulating layer 105 and completely covering the second sub-shading layer 2012, a third sub-shading layer 2013 and a second metal layer 202 disposed on the interlayer insulating layer 107 in the same layer, and the planarization layer 109 disposed on the interlayer insulating layer 107;
the second metal layer 202 is insulated from the third sub-light shielding layer 2013; the portion of the planarization layer 109 corresponding to the photo sensor S1 has an opening 1091, a portion of the first passivation layer 110 is disposed in the opening 1091, and the light absorbing layer 203 is disposed on the first passivation layer 110 and in the opening 1091.
In the embodiment of the present application, the first insulating layer is the first passivation layer 110; the light-shielding layer 201 includes the first sub-light-shielding layer 2011, the second sub-light-shielding layer 2012 and the third sub-light-shielding layer 2013. The first sub-light-shielding layer 2011 is disposed in a same layer and insulated from the light-shielding metal layer 102 in the switch transistor T1, the second sub-light-shielding layer 2012 is disposed in a same layer and insulated from the gate metal layer 106 in the switch transistor T1, and the third sub-light-shielding layer 2013 is disposed in a same layer and insulated from the second metal layer 202.
In the embodiment of the present application, the photosensitive sensor S1 further includes a photosensitive electrode layer disposed on the light absorption layer 203, the photosensitive electrode layer includes a first photosensitive electrode 205 and a second photosensitive electrode 206 disposed separately, the first photosensitive electrode 205 is electrically connected to the first end of the light absorption layer 203, the second photosensitive electrode 206 is electrically connected to the second end of the light absorption layer 203.
In the embodiment of the present application, the photosensor S1 further includes a second metal layer 202, the second metal layer 202 is disposed in a same layer and insulated from the source/drain metal layer 108 in the switch transistor T1, and the second metal layer 202 includes a first metal block 2021 and a second metal block 2022 disposed in an insulated manner from the first metal block 2021;
the first photosensitive electrode 205 is electrically connected to the driving chip of the display panel 10 through the first metal block 2021, and the second photosensitive electrode 206 is electrically connected to the driving chip through the second metal block 2022.
In the embodiment of the present application, the photo sensor S1 further includes an ohmic contact layer 204 disposed on the light absorbing layer 203, and the ohmic contact layer 204 includes a first sub-ohmic contact layer 2041 and a second sub-ohmic contact layer 2042 disposed in an insulating manner from the first sub-ohmic contact layer 2041;
the first photosensitive electrode 205 is electrically connected to the light absorbing layer 203 through the first sub-ohmic contact layer 2041, and the second photosensitive electrode 206 is electrically connected to the light absorbing layer 203 through the second sub-ohmic contact layer 2042.
Further, the material of the ohmic contact layer 204 is an amorphous silicon layer heavily doped with phosphorus ions, and the material of the light absorbing layer 203 is an amorphous silicon layer.
Specifically, the light absorbing layer 203 is made of amorphous silicon, and the photosensitive electrode layer is made of indium tin oxide; since the work functions of the amorphous silicon material and the indium tin oxide material are different greatly, a contact barrier exists when the light absorbing layer 203 is in contact with the photosensitive electrode layer. Therefore, by adding the ohmic contact layer 204 with lower resistivity between the light absorbing layer 203 and the photosensitive electrode layer, the contact barrier can be reduced, and the light absorbing layer 203 and the photosensitive electrode layer can be more easily conducted.
In the embodiment of the present application, each of the first photosensitive electrode 205 layer and the second photosensitive electrode 206 layer includes a first sub-electrode and a second sub-electrode disposed on the first sub-electrode, and the second sub-electrode is directly electrically connected to the first sub-electrode; the first sub-electrode is electrically connected with the light absorption layer 203 through the ohmic contact layer 204, and the second sub-electrode is electrically connected with the second metal layer 202;
the first sub-electrode is disposed in a layer and insulated from the common electrode 111 in the switch transistor T1, and the second sub-electrode is disposed in a layer and insulated from the pixel electrode 113 in the switch transistor T1.
Further, the first sub-electrode includes a first sub-electrode block 2051 and a second sub-electrode block 2061 insulated from the first sub-electrode block 2051; the second sub-electrode includes a third sub-electrode block 2052 and a fourth sub-electrode block 2062 insulated from the third sub-electrode block 2052.
Further, the photo sensor S1 further includes the second passivation layer 112, the second passivation layer 112 completely covers the light absorbing layer 203, the ohmic contact layer 204 and the first sub-electrode, a third via hole 1121 and a fourth via hole 1122 are disposed on the second passivation layer 112, the first photo electrode 205 is electrically connected to the first metal block 2021 through the third via hole 1121, and the second photo electrode 206 is electrically connected to the second metal block 2022 through the fourth via hole 1122.
In the embodiment of the present application, since the portion of the planarization layer 109 corresponding to the photosensitive sensor S1 is provided with the opening 1091, the distance between the light absorbing layer 203 and the third sub-light shielding layer 2013 is equal to the thickness of the first passivation layer 110 (the thickness of the first passivation layer 110 is generally about 2000 angstroms), so that the distance between the light absorbing layer 203 and the third sub-light shielding layer 2013 is far less than 1 um; at this time, the third light shading sub-layer 2013 is reused as a bottom gate structure of the photosensor S1, so that the third light shading sub-layer 2013 has a regulating and controlling effect on a conductive channel of the light absorbing layer 203. When a positive voltage is applied to the third sub-light shielding layer 2013, the photosensor S1 is turned on, and when a negative voltage is applied to the third sub-light shielding layer 2013, the photosensor S1 is turned off.
Further, a fifth through hole 1073 is disposed on the interlayer insulating layer 107, and the third sub-shielding layer 2013 is electrically connected to the second sub-shielding layer 2012 through the fifth through hole 1073; this makes it possible to switch the second sub-light shielding layer 2012 to the electrical signal of the photo sensor S1, and to more easily saturate the electrical signal of the photo sensor S1.
In the embodiment of the present application, the substrate 101 may be a polyimide film, and the substrate 101 may be formed of one or more polyimide films. The active layer 104 includes a conductive portion and a non-conductive portion, the non-conductive portion of the active layer 104 is made of polysilicon, and the conductive portion of the active layer 104 is made of polysilicon doped with phosphorus ions. The buffer layer 103, the first passivation layer 110, and the second passivation layer 112 may be made of one or more inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or silicon dioxide, which can isolate water and oxygen. The material of the gate insulating layer 105 may be one or more of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon dioxide, or the like, so as to perform an insulating protection function. The light-shielding metal layer 102, the second metal layer 202, the first light-shielding sub-layer 2011, the second light-shielding sub-layer 2012, the third light-shielding sub-layer 2013, and the source/drain metal layer 108 may be made of a metal material having excellent conductivity, such as molybdenum, copper, and aluminum.
In the embodiment of the present invention, the material of the interlayer insulating layer 107 may be one or more of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, which are used to isolate water and oxygen and play a role in insulating and protecting other functional film layers. The material of the planarization layer 109 may be one or more of organic materials such as acrylic resin, polycarbonate, and polystyrene, and is used to slowly release stress generated by the display panel 10, so as to enhance the bending resistance of the display panel 10 and avoid cracks.
In this embodiment, the common electrode 111, the pixel electrode 113, and the photosensitive electrode are made of at least one of indium tin oxide and indium gallium tin oxide.
In the embodiment of the present application, the thickness of the planarization layer 109 is 1000 nm to 1500 nm, and the thickness is very thick, so that a certain distance is kept between the source/drain metal layer 108 and the common electrode 111, and electrostatic interference or signal crosstalk generated between the source/drain metal layer 108 and the common electrode 111 is avoided.
In the embodiment of the present application, the switch transistor T1 on the display panel 10 is of a top-gate structure, so that the problem of parasitic capacitance caused by the overlapping area of the source drain metal layer 108 and the gate metal layer 106 in the vertical direction can be greatly improved.
Specifically, the method steps of the display panel 10 prepared in the first embodiment of the present application are as follows:
firstly, the light-shielding metal layer 102 and a first sub-light-shielding layer 2011 which is the same layer as the light-shielding metal layer 102 and is arranged in an insulating manner are respectively prepared on the substrate 101, the light-shielding metal layer 102 is used for shielding the bottom of the switching transistor T1 device, and the first sub-light-shielding layer 2011 shields the bottom of the photosensitive sensor S1; then, preparing the buffer layer 103 and an amorphous silicon layer on the substrate 101, changing the amorphous silicon layer into a polysilicon layer through Excimer Laser Annealing (ELA), and doping phosphorus ions at two ends of the edge of the polysilicon layer to form a conductor part of the active layer 104; then, forming the gate metal layer 106 and the second sub-light-shielding layer 2012 which is the same layer as the gate metal layer 106 and is disposed in an insulating manner on the gate insulating layer 105, where the second sub-light-shielding layer 2012 is used as a gate trace of the photosensor S1 and is also reused as the light-shielding layer 201 of the photosensor S1; thereafter, depositing an interlayer insulating layer 107 on the gate insulating layer 105, and etching the first via hole 1071, the second via hole 1072, and the fifth via hole 1073 of the interlayer insulating layer 107 through a photo-exposure etching process; then, the source/drain metal layer 108, the second metal layer 202 and the third light shading sub-layer 2013 are prepared on the interlayer insulating layer 107, the source 1081 of the source/drain metal layer 108 is electrically connected with the active layer 104 through the first via 1071, the drain 1082 of the source/drain metal layer 108 is electrically connected with the active layer 104 through the second via 1072, and the third light shading sub-layer 2013 is electrically connected with the second light shading sub-layer 2012 through the fifth via 1073.
Thereafter, the planarization layer 109 is deposited on the interlayer insulating layer 107, and a portion of the planarization layer 109 corresponding to the photosensitive sensor S1 has the opening 1091; the planarization layer 109 may be made of an organic planarization material, or an insulating layer material such as SiNx/SiOx. Thereafter, depositing a layer of the first passivation layer 110 on the planarization layer 109; then, a layer of amorphous silicon is deposited as the light absorbing layer 203 of the photo sensor S1. And depositing a layer of phosphorus ion heavily-doped amorphous layer on the amorphous silicon layer.
Thereafter, a bottom ito layer is deposited on the first passivation layer 110, the bottom ito layer serving as the common electrode 111 in the area of the switching transistor T1 and serving as the first sub-electrode of the photosensor S1 in the area of the photosensor S1; then, the area of the photosensor S1 is masked by the pattern of the bottom ito layer, and the heavily doped amorphous layer with phosphorus ions is etched to form the ohmic contact layer 204.
Then, depositing the second passivation layer 112 on the first passivation layer 110, and etching a pixel electrode 113 hole and a bridging hole of the photosensitive electrode layer in the area of the photosensitive sensor S1 by exposure etching; finally, a top ito layer is deposited on the second passivation layer 112, the pixel electrode 113 is formed in the transistor area of the opening 1091 by exposure and etching, the second sub-electrode of the photosensor S1 is formed in the photosensor area S1, the second sub-electrode is electrically connected to the light absorbing layer 203 through the bridging hole of the first passivation layer 110, and the other end of the second sub-electrode is electrically connected to the second metal layer 202 (source drain 1082 trace) through the third via hole 1121 or the fourth via hole 1122 of the second passivation layer 112.
The display panel 10 prepared in the embodiment of the present application has the following advantages:
first, the absorption layer of the photosensitive sensor S1 is disposed above the planarization layer 109 so that the absorption layer is closer to ambient light with less interference;
secondly, the light shielding layer 201 below the absorption layer of the photosensor S1 can be shielded by selecting three metals, namely, a light shielding metal material, a gate metal material and a source drain 1082 metal material, and at least 2 or more metal materials can be adopted to repeatedly shield light, so that interference light incident to the light absorption layer 203 from backlight is reduced, and the ambient light detection precision is improved;
finally, the light absorbing layer 203 is prepared by only adding an amorphous silicon process, so that the ambient light function can be integrated on the array substrate, wherein the pattern of the ohmic contact layer 204 can be defined by the photomask of the bottom indium tin oxide layer, wet etching is firstly performed to manufacture the pattern of the bottom indium tin oxide layer after the bottom indium tin oxide layer is exposed, and then dry etching is performed to manufacture the pattern of the ohmic contact layer 204.
Therefore, in the embodiment of the present application, the amorphous silicon type photosensor S1 with excellent performance is integrated inside the panel, so as to realize the function of ambient light, simplify the process as much as possible, and dispose the light absorbing layer 203 above the planarization layer 109, closer to the ambient light, and have less interference; in addition, the light shielding layer 201 below the light absorbing layer 203 can be shielded by selecting three metals, namely a light shielding metal material, a gate metal material and a source/drain electrode 1082 metal material, and at least 2 or more than 2 metal materials can be adopted for repeatedly shielding light, so that interference light incident to the light absorbing layer 203 from a backlight is reduced, and the ambient light detection precision is improved.
Aiming at the technical problem that the current display panel 10 is difficult to realize low-cost detection of ambient light, the embodiment of the present application provides a display panel 10; the display panel 10 includes a plurality of sub-pixel units, at least one of which includes a switching transistor T1 and at least one photosensor S1, the photosensitive sensor S1 includes a light shielding layer 201, a first insulating layer disposed on the light shielding layer 201, a light absorbing layer 203 disposed on the first insulating layer, and a photosensitive electrode layer disposed on the light absorbing layer 203, an orthographic projection of the light absorbing layer 203 on the light shielding layer 201 is located within the light shielding layer 201, the photosensitive electrode layer includes a first photosensitive electrode 205 and a second photosensitive electrode 206 separately disposed, the first photosensitive electrode 205 is electrically connected to a first end of the light absorbing layer 203, the second photosensitive electrode 206 is electrically connected to a second end of the light absorbing layer 203, wherein the display panel 10 further comprises the planarization layer 109, the planarization layer 109 has the opening 1091, and the light absorbing layer 203 is disposed in the opening 1091; according to the display panel 10, at least one photosensitive sensor S1 is arranged in at least one sub-pixel unit, the photosensitive sensor S1 comprises the light absorbing layer 203 and the photosensitive electrode layer electrically connected with the light absorbing layer 203, and only one amorphous silicon process is needed to integrate the photosensitive sensor S1 into the sub-pixel unit, so that the low-cost detection of ambient light is realized. In addition, since the light absorbing layer 203 is disposed in the opening 1091, the third light sub-shielding layer 2013 below the light absorbing layer 203 can be reused as a bottom gate of the photosensor S1, so as to regulate and control the conductive channel of the light absorbing layer 203.
Example two
Fig. 2 is a schematic diagram of a second cross-sectional structure of the display panel 10 according to the embodiment of the present application; the structure of the display panel 10 in the second embodiment of the present application is the same as or similar to the structure of the display panel 10 in the first embodiment of the present application, except that the opening 1091 is not disposed in the area of the planarization layer 109 corresponding to the photosensitive sensor S1, and the first insulating layer includes the planarization layer 109 and the first passivation layer 110. Since the thickness of the planarization layer 109 is thicker and generally exceeds 1um, the distance between the light absorbing layer 203 and the third sub-light shielding layer 2013 is too large, so that the third sub-light shielding layer 2013 cannot be reused as the bottom gate structure of the photosensor S1, and the third sub-light shielding layer 2013 cannot regulate and control the conductive channel of the light absorbing layer 203. At this time, the light absorbing layer 203 corresponds to a photo resistor.
Compared with the first embodiment of the present application, in the second embodiment of the present application, since the opening 1091 is not formed in the planarization layer 109, the third light shielding sub-layer 2013 cannot regulate and control the light absorbing layer 203, so that it is difficult for the display panel 10 to close the light sensor S1 without sensing the external ambient light, and thus the power consumption of the display panel 10 is increased.
Aiming at the technical problem that the current display panel 10 is difficult to realize low-cost detection of ambient light, the embodiment of the application provides a display panel 10; the display panel 10 comprises a plurality of sub-pixel units, at least one sub-pixel unit comprises a switch transistor T1 and at least one photosensitive sensor S1, the photosensitive sensor S1 comprises a light shielding layer 201, a first insulating layer arranged on the light shielding layer 201, a light absorbing layer 203 arranged on the first insulating layer, and a photosensitive electrode layer arranged on the light absorbing layer 203, wherein the orthographic projection of the light absorbing layer 203 on the light shielding layer 201 is positioned in the light shielding layer 201, the photosensitive electrode layer comprises a first photosensitive electrode 205 and a second photosensitive electrode 206 which are separately arranged, the first photosensitive electrode 205 is electrically connected with a first end of the light absorbing layer 203, and the second photosensitive electrode 206 is electrically connected with a second end of the light absorbing layer 203; according to the display panel 10, at least one photosensitive sensor S1 is arranged in at least one sub-pixel unit, the photosensitive sensor S1 comprises the light absorbing layer 203 and the photosensitive electrode layer electrically connected with the light absorbing layer 203, and only one amorphous silicon process is needed to integrate the photosensitive sensor S1 into the sub-pixel unit, so that the low-cost detection of ambient light is realized.
EXAMPLE III
Fig. 3 is a schematic view of a third cross-sectional structure of the display panel 10 according to the embodiment of the present application; the structure of the display panel 10 in the third embodiment of the present application is the same as or similar to the structure of the display panel 10 in the second embodiment of the present application, except that the first photosensitive electrode 205 layer and the second photosensitive electrode 206 layer both include a third sub-electrode, one end of the third sub-electrode is directly electrically connected to the light absorbing layer 203, and the other end of the third sub-electrode is electrically connected to the second metal layer 202;
specifically, the third sub-electrode includes a fifth electrode block 2053 and a sixth electrode block 2063 which are disposed in the same layer and insulated from each other, one end of the fifth electrode block 2053 is directly electrically connected to the light absorbing layer 203, and the other end of the fifth electrode block 2053 is electrically connected to the first metal block 2021; one end of the sixth electrode block 2063 is directly electrically connected to the light absorbing layer 203, and the other end of the sixth electrode block 2063 is electrically connected to the second metal block 2022;
the fifth electrode block 2053 and the sixth electrode block 2063 are disposed in the same layer and in an insulated manner as the pixel electrode 113 in the switching transistor T1.
Compared with the second embodiment of the present application, in the third embodiment of the present application, because the indium tin oxide material is in direct contact with the amorphous silicon material, a contact barrier exists; but the contact potential barrier is not completely non-conductive, and a certain current can also pass through, and in the third scheme, in order to omit the coating process of heavily doping the amorphous silicon with phosphorus ions, the indium tin oxide material and the amorphous silicon material are required to be in direct contact. Therefore, in the third embodiment of the present application, a plating process of heavily doping amorphous silicon with phosphorus ions may be omitted with respect to the second embodiment of the present application, but a contact barrier existing between the photosensitive electrode layer and the absorption layer may be increased, thereby decreasing the sensitivity of the photosensitive sensor S1.
Aiming at the technical problem that the current display panel 10 is difficult to realize low-cost detection of ambient light, the embodiment of the application provides a display panel 10; the display panel 10 comprises a plurality of sub-pixel units, at least one sub-pixel unit comprises a switch transistor T1 and at least one photosensitive sensor S1, the photosensitive sensor S1 comprises a light shielding layer 201, a first insulating layer arranged on the light shielding layer 201, a light absorbing layer 203 arranged on the first insulating layer, and a photosensitive electrode layer arranged on the light absorbing layer 203, wherein the orthographic projection of the light absorbing layer 203 on the light shielding layer 201 is positioned in the light shielding layer 201, the photosensitive electrode layer comprises a first photosensitive electrode 205 and a second photosensitive electrode 206 which are separately arranged, the first photosensitive electrode 205 is electrically connected with a first end of the light absorbing layer 203, and the second photosensitive electrode 206 is electrically connected with a second end of the light absorbing layer 203; the display panel 10 is provided with at least one photosensitive sensor S1 in at least one of the sub-pixel units, the photosensitive sensor S1 includes a light absorbing layer 203 and a photosensitive electrode layer electrically connected to the light absorbing layer 203, and only one amorphous silicon process needs to be added to integrate the photosensitive sensor S1 in the sub-pixel units, so that the low-cost detection of ambient light is realized.
As shown in fig. 4, a flowchart of a method for manufacturing the display panel 10 provided in the first embodiment of the present application specifically includes (taking the display panel 10 in the first embodiment of the present application as an example):
s10, a light-shielding metal pattern, a buffer layer 103, an active layer 104, a gate metal pattern, and an interlayer insulating layer 107 are sequentially formed on a substrate 101.
Specifically, the S10 further includes:
step 1: preparing a metal pattern on a substrate 101, and patterning the metal pattern by exposure etching or the like to form a light-shielding metal layer 102 and a first sub-light-shielding layer 2011;
step 2: sequentially preparing a buffer layer 103 and an amorphous silicon layer on the substrate 101, wherein the amorphous silicon layer is converted into a polycrystalline silicon layer after excimer laser annealing, and an active layer 104 is formed by adopting an exposure etching method;
step 3: carrying out phosphorus ion doping on two ends of the polycrystalline silicon layer to form a source drain electrode doped region of the active layer 104;
step 4: depositing a gate metal pattern on the buffer layer 103 to form a gate metal layer 106 and a second sub-light shielding layer 2012; then, the active layer 104 is shielded by the gate metal layer 106, and the active layer 104 is subjected to N-Ion implantation; the gate metal layer 106 serves as a top gate structure of the switch transistor T1, and the second sub-light-shielding layer 2012 serves as the photosensorA gate trace of S1;
step 5: an interlayer insulating layer 107, which may be a SiNx/SiOx stack, is deposited on the gate insulating layer 105, and then a first via hole 1071, a second via hole 1072, and a fifth via hole 1073 are formed by exposure etching, as shown in fig. 5A.
S20, preparing a source drain metal layer 108, a second metal layer 202, and a third light shading layer 2013 on the interlayer insulating layer 107.
Specifically, the S20 further includes:
step 6: depositing a metal layer, and patterning by adopting an exposure etching method to form a source/drain metal layer 108, a second metal layer 202 and a third light shading sub-layer 2013; the source 1081 of the source/drain metal layer 108 is electrically connected to one end of the active layer 104 through the first via 1071, the drain 1082 of the source/drain metal layer 108 is electrically connected to the other end of the active layer 104 through the second via 1072, and the third sub-light shielding layer 2013 is electrically connected to the second sub-light shielding layer 2012 through the fifth via 1073, as shown in fig. 5B.
S30, preparing a planarization layer 109 on the interlayer insulating layer 107, wherein the region of the planarization layer 109 corresponding to the third light sub-shielding layer 2013 has an opening 1091.
Specifically, the S30 further includes:
step 7: preparing a planarization layer 109 on the interlayer insulating layer 107, wherein an area of the planarization layer 109 corresponding to the third sub-light shielding layer 2013 is provided with an opening 1091; then, an opening process is performed on the planarization layer 109 to form a third via 1121, a fourth via 1122, and a sixth via 1123, as shown in fig. 5C.
S40, sequentially preparing a first passivation layer 110, a light absorbing layer 203 and a heavily phosphorous ion doped amorphous silicon layer on the planarization layer 109, where the light absorbing layer 203 and the heavily phosphorous ion doped amorphous silicon layer are disposed in the opening 1091.
Specifically, the S40 further includes:
step 8: depositing an inorganic insulating layer, which is plated to form the first passivation layer 110, and then depositing an amorphous silicon layer and a heavily phosphorous ion doped amorphous silicon layer on the portion of the first passivation layer 110 corresponding to the opening 1091, and patterning the amorphous silicon layer into the light absorbing layer 203 of the photosensor S1 by exposure etching, the light absorbing layer 203 and the heavily phosphorous ion doped amorphous silicon layer being disposed in the opening 1091, as shown in fig. 5D.
S50, sequentially forming a bottom electrode pattern, a second passivation layer 112 and a top electrode pattern on the first passivation layer 110.
Specifically, the S40 further includes:
step 9: depositing a bottom electrode layer on the first passivation layer 110, the bottom electrode layer being patterned to form the common electrode 111 of the switching transistor T1 and the first sub-electrode of the photosensor S1; then, etching off part of the amorphous silicon layer heavily doped with phosphorus ions by shielding the first sub-electrode to form an ohmic contact layer 204;
step 10: depositing a second passivation layer 112 on the first passivation layer 110, and opening the third via hole 1121, the fourth via hole 1122 and the sixth via hole 1123 (etching away a portion of the first passivation layer 110 in the above contact holes);
step 11: depositing a top electrode layer on the second passivation layer 112, the top electrode layer being patterned to form a pixel electrode 113 of the switching transistor T1 and a second sub-electrode of the photosensor S1; the pixel electrode 113 is in contact with the source 1081 of the source-drain metal layer 108 through the sixth via hole 1123, and the second sub-electrode is electrically connected to the second metal layer 202 through the third via hole 1121 and the fourth via hole 1122, as shown in fig. 5E.
Correspondingly, the embodiment of the present application further provides a mobile terminal, the mobile terminal includes a terminal main body and the display panel 10 as described in any one of the above, and the terminal main body and the display panel 10 are combined into a whole. The mobile terminal may be a mobile phone, a computer, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment.
The embodiment of the application provides a display panel 10 and a mobile terminal; the display panel 10 comprises a plurality of sub-pixel units, at least one of the sub-pixel units comprises a switch transistor T1 and at least one photosensitive sensor S1, the photosensitive sensor S1 comprises a light shielding layer 201, a first insulating layer arranged on the light shielding layer 201, a light absorbing layer 203 arranged on the first insulating layer, and a photosensitive electrode layer arranged on the light absorbing layer 203, wherein an orthographic projection of the light absorbing layer 203 on the light shielding layer 201 is positioned in the light shielding layer 201, the photosensitive electrode layer comprises a first photosensitive electrode 205 and a second photosensitive electrode 206 which are separately arranged, the first photosensitive electrode 205 is electrically connected with a first end of the light absorbing layer 203, and the second photosensitive electrode 206 is electrically connected with a second end of the light absorbing layer 203; according to the display panel 10, at least one photosensitive sensor S1 is arranged in at least one sub-pixel unit, the photosensitive sensor S1 comprises the light absorbing layer 203 and the photosensitive electrode layer electrically connected with the light absorbing layer 203, and only one amorphous silicon process is needed to integrate the photosensitive sensor S1 into the sub-pixel unit, so that the low-cost detection of ambient light is realized.
The display panel 10 and the mobile terminal provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel is characterized by comprising a plurality of sub-pixel units, wherein at least one sub-pixel unit comprises a switch transistor and at least one photosensitive sensor; wherein, the photosensitive sensor includes:
a light-shielding layer;
a first insulating layer disposed on the light-shielding layer;
the light absorption layer is arranged on the first insulating layer, and the orthographic projection of the light absorption layer on the light shielding layer is positioned in the light shielding layer; and
the sensitization electrode layer, set up in on the light-absorbing layer, the sensitization electrode layer is including separating first sensitization electrode and the second sensitization electrode that sets up, first sensitization electrode with the first end electricity on light-absorbing layer is connected, the second sensitization electrode with the second end electricity on light-absorbing layer is connected.
2. The display panel according to claim 1, wherein the photosensor further comprises a second metal layer, the second metal layer is in the same layer as a source/drain metal layer in the switching transistor and is arranged in an insulating manner, and the second metal layer comprises a first metal block and a second metal block arranged in an insulating manner with respect to the first metal block;
the first photosensitive electrode is electrically connected with a driving chip of the display panel through the first metal block, and the second photosensitive electrode is electrically connected with the driving chip through the second metal block.
3. The display panel according to claim 2, wherein the light-shielding layer includes at least two of a first sub light-shielding layer, a second sub light-shielding layer, and a third sub light-shielding layer;
the first sub-shading layer and the shading metal layer in the switch transistor are arranged on the same layer in an insulating mode, the second sub-shading layer and the grid metal layer in the switch transistor are arranged on the same layer in an insulating mode, and the third sub-shading layer and the second metal layer are arranged on the same layer in an insulating mode.
4. The display panel of claim 2, wherein the light-sensitive sensor further comprises an ohmic contact layer disposed on the light absorbing layer, the ohmic contact layer comprising a first sub-ohmic contact layer and a second sub-ohmic contact layer disposed insulated from the first sub-ohmic contact layer;
the first photosensitive electrode is electrically connected with the light absorption layer through the first sub-ohmic contact layer, and the second photosensitive electrode is electrically connected with the light absorption layer through the second sub-ohmic contact layer.
5. The display panel according to claim 4, wherein the material of the ohmic contact layer is an amorphous silicon layer heavily doped with phosphorus ions, and the material of the light absorbing layer is an amorphous silicon layer.
6. The display panel according to claim 4, wherein the first photosensitive electrode layer and the second photosensitive electrode layer each comprise a first sub-electrode and a second sub-electrode disposed on the first sub-electrode, the first sub-electrode is electrically connected to the light absorbing layer through the ohmic contact layer, and the second sub-electrode is electrically connected to the second metal layer;
the first sub-electrode and the common electrode in the switch transistor are arranged on the same layer and in an insulating mode, and the second sub-electrode and the pixel electrode in the switch transistor are arranged on the same layer and in an insulating mode.
7. The display panel according to claim 4, wherein the first photosensitive electrode layer and the second photosensitive electrode layer each comprise a third sub-electrode, one end of the third sub-electrode is directly electrically connected to the light-absorbing layer, and the other end of the third sub-electrode is electrically connected to the second metal layer;
the third sub-electrode and the pixel electrode in the switch transistor are in the same layer and are arranged in an insulating mode.
8. The display panel according to claim 6, wherein the switching transistor further comprises:
a planarization layer;
a first passivation layer disposed on the planarization layer;
the common electrode is arranged on the first passivation layer;
a second passivation layer disposed on the first passivation layer and covering the common electrode; and
the pixel electrode is arranged on the second passivation layer;
wherein the first insulating layer includes the first passivation layer or a stack of the planarization layer and the first passivation layer.
9. The display panel according to claim 8, wherein a portion of the planarization layer corresponding to the photosensor has an opening, and a portion of the first passivation layer is disposed in the opening;
wherein the light absorbing layer is disposed on the first passivation layer and within the opening.
10. A mobile terminal characterized by comprising a terminal body and the display panel according to any one of claims 1 to 9, the terminal body being integrated with the display panel.
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