CN114594917A

CN114594917A - Interface module, chip reading and writing method and device

Info

Publication number: CN114594917A
Application number: CN202210205753.0A
Authority: CN
Inventors: 曹天航; 祁美超
Original assignee: Apex Microelectronics Co Ltd
Current assignee: Apex Microelectronics Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2022-06-07

Abstract

An interface module, a chip read-write method and a device provided by the embodiment of the application, the interface module includes: the probe matrix comprises at least two probe groups, each probe group corresponds to one signal transmission channel, each probe group comprises at least two probes, and the adjacent probes of any one probe comprise the probes of at least one other probe group. The technical scheme provided by the embodiment of the application has the following advantages: 1. the interface module is a universal interface, can be suitable for different types of chips, and is convenient to use; 2. the probes in the probe matrix are divided into a plurality of probe groups, so that a control circuit is simpler; 3. the probe matrix comprises a probe dense area and a probe sparse area, and compatibility of chips with different contact sizes is achieved.

Description

Interface module, chip reading and writing method and device

Technical Field

The present application relates to the field of electronic technologies, and in particular, to an interface module, a chip read-write method, and an apparatus.

Background

With the development of image forming technology, printing apparatuses such as laser printing apparatuses and inkjet printing apparatuses have been widely used. In the imaging process, the printing device needs the assistance of the imaging auxiliary information of the consumable cartridge to complete the imaging process. The imaging auxiliary information of the printing apparatus is recorded on the consumable chip in addition to the printing apparatus. The consumable chip mainly plays a role in identifying and providing the use condition of the consumable. After the consumptive material use amount recorded in the consumptive material chip reaches a certain value, the printing equipment prompts that the consumptive material box needs to be replaced, and a user needs to purchase a new consumptive material box to replace the used consumptive material box. Because the consumption of the consumable recorded in the consumable chip reaches a certain value, the used imaging box cannot be used even if the ink or the powder is filled, and great waste is caused.

To above-mentioned problem, can realize the used repeatedly of consumptive material box through reseing to the consumptive material chip. Since the contact positions or the number of contacts of different types of consumable chips are different, different communication interfaces need to be configured for different types of consumable chips. When the chip is used, the corresponding communication interface is selected according to the type of the chip, the probe of the communication interface is aligned to the contact of the chip, and the read-write operation is carried out on the chip.

However, the variety of the communication interfaces is large, so that the user needs to select the communication interface when using the communication interface, the use is inconvenient, and the efficiency is low. In addition, the communication interfaces are more in types and difficult to maintain, and cost is increased.

Disclosure of Invention

The application provides an interface module, a chip reading and writing method and a chip reading and writing device, which are beneficial to solving the problems that in the prior art, a plurality of types of communication interfaces are provided, so that a user needs to select the communication interfaces when using the communication interfaces, the use is inconvenient, and the efficiency is low.

In a first aspect, an embodiment of the present application provides an interface module, including:

the probe matrix comprises at least two probe groups, each probe group corresponds to one signal transmission channel, each probe group comprises at least two probes, and the adjacent probe of any one probe comprises the probe of at least one other probe group.

In a possible implementation manner, the probes in the same probe group are arranged at intervals in the horizontal direction and/or the vertical direction of the probe matrix.

In a possible implementation manner, the probes in the same probe group are arranged in series in the oblique direction of the probe matrix.

In one possible implementation manner, the probe matrix includes a probe dense region and a probe sparse region, and the probe arrangement density of the probe dense region is greater than the probe arrangement density of the probe sparse region.

In a second aspect, an embodiment of the present application provides a chip read-write method, which is applied to the interface module in any one of the first aspect, where the method includes:

covering a probe matrix on a contact of a chip to realize the electrical connection between the contact of the chip and a probe of the probe matrix;

identifying an electrical connection probe corresponding to each contact, wherein the electrical connection probe is a probe electrically connected with the contact, and each contact at least corresponds to one electrical connection probe;

determining a signal transmission probe corresponding to each contact point in the electric connection probes according to the signal transmission channels corresponding to the electric connection probes, wherein the signal transmission channels of the signal transmission probes corresponding to any two contact points are different;

selecting signaling probes in each of said probe sets to be in communication such that said signaling probes can transmit signals;

identifying a definition of each of the contacts;

selecting a signal transmission type of each signal transmission probe according to the definition of each contact, wherein the definition of the contact is matched with the signal transmission type of the corresponding signal transmission probe;

and reading and writing the chip through the signal transmission probe.

In one possible implementation, the identifying the electrically connected probe corresponding to each of the contacts includes traversing the probes in the probe matrix by:

selecting a target probe;

sequentially carrying out short circuit on the target probe and each adjacent probe, and determining whether the target probe and the adjacent probes are short-circuited or not;

and taking all the probes which are adjacent and mutually short-circuited as an electrical connection probe corresponding to the contact.

In a possible implementation manner, the sequentially short-circuiting the target probe and each adjacent probe, and determining whether the target probe and the adjacent probe are short-circuited, includes: sequentially carrying out positive and negative short circuit on the target probe and each adjacent probe respectively, and determining whether the target probe and the adjacent probes are short-circuited in both positive and negative short circuits;

all the probes which are adjacent and mutually short-circuited are used as an electric connection probe corresponding to the contact, and the electric connection probe comprises: and taking all adjacent probes which are in short circuit in both positive and negative directions as an electric connection probe corresponding to the contact.

In one possible implementation, the identifying the definition of each of the contacts includes:

and identifying the definition of each contact according to the control relation and/or the position relation among the contacts.

In a possible implementation manner, the identifying the definition of each contact point according to the control relationship and/or the position relationship between the contact points includes:

identifying the definition of at least one contact point according to the control relation among the contact points;

and identifying the definition of each contact in the rest contacts according to the definition of the at least one contact and the position relation between the rest contacts and the at least one contact.

and traversing the communication results of the residual contacts and the residual contact definitions and the chip under different permutation and combination relations, and determining the definition of each contact in the residual contacts.

In a possible implementation manner, the traversing the remaining contact points and the remaining contact point definitions in different permutation and combination relationships with the communication result of the chip, and determining the definition of each of the remaining contact points includes:

selecting a target arrangement combination relation defined by the residual contacts and the residual contacts;

sending test information to the chip according to the definition of the residual contacts corresponding to the target permutation and combination relation;

and if the response information fed back by the chip is received, determining the definition of the residual contact corresponding to the target permutation and combination relationship as the definition of the residual contact.

In a possible implementation manner, the chip includes 4 contacts, which are a high-level signal contact, a data signal contact, a clock signal contact and a ground signal contact, respectively, the high-level signal contact is electrically connected to the data signal contact, the clock signal contact and the ground signal contact through a first diode, a second diode and a third diode, respectively, and cathodes of the first diode, the second diode and the third diode are connected to the high-level signal contact;

the identifying the definition of at least one contact point according to the control relation among the contact points comprises the following steps: detecting the direction of a diode between any two of the 4 contacts; the high level signal contact is determined among the 4 contacts according to the direction of the diode.

In a possible implementation manner, the chip includes 4 contacts, which are a high-level signal contact, a data signal contact, a clock signal contact and a ground signal contact, respectively, the high-level signal contact is electrically connected to the data signal contact, the clock signal contact and the ground signal contact through a first diode, a second diode and a third diode, respectively, and cathodes of the first diode, the second diode and the third diode are connected to the high-level signal contact; the grounding signal contact is electrically connected with the data signal contact and the clock signal contact through a fourth diode and a fifth diode respectively, and the anodes of the fourth diode and the fifth diode are connected with the grounding signal contact;

the identifying the definition of at least one contact point according to the control relation among the contact points comprises: detecting the direction of a diode between any two of the 4 contacts; the high-level signal contact and the ground signal contact are determined among the 4 contacts according to the direction of the diode.

In a third aspect, an embodiment of the present application provides a chip reading and writing apparatus, including:

the interface module of any of the first aspect;

the control module is used for identifying an electric connection probe corresponding to each contact after a probe matrix covers the contact of the chip, the electric connection probe is electrically connected with the contact, and each contact at least corresponds to one electric connection probe; determining a signal transmission probe corresponding to each contact point in the electric connection probes according to the signal transmission channels corresponding to the electric connection probes, wherein the signal transmission channels of the signal transmission probes corresponding to any two contact points are different;

a first switching module for selectively communicating the signal transmission probes in each of the probe sets so that the signal transmission probes can transmit signals;

the control module is further used for identifying the definition of each contact;

the second switch module is used for selecting the signal transmission type of each signal transmission probe according to the definition of each contact, and the definition of the contact is matched with the signal transmission type of the corresponding signal transmission probe;

the control module is also used for reading and writing the chip through the signal transmission probe.

The technical scheme provided by the embodiment of the application has the following advantages:

1. the interface module is a universal interface, can be suitable for different types of chips, and is convenient to use;

2. the probes in the probe matrix are divided into a plurality of probe groups, so that a control circuit is simpler;

3. the probe matrix comprises a probe dense area and a probe sparse area, and compatibility of chips with different contact sizes is achieved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of an interface module according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram illustrating a connection state between an interface module and a chip according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram illustrating a connection state between an interface module and a chip according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating a connection state between an interface module and a chip according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the probe matrix shown in FIG. 1 provided in an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating an arrangement of probe sets in a probe matrix according to an embodiment of the present disclosure;

fig. 7 is a block diagram of a chip read/write apparatus according to an embodiment of the present disclosure;

fig. 8 is a schematic flowchart of a chip read-write method according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram illustrating an identification process of an electrical connection probe according to an embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of a chip according to an embodiment of the present disclosure;

fig. 11 is a schematic circuit structure diagram of another chip according to an embodiment of the present disclosure.

Detailed Description

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the prior art, different communication interfaces are required to be configured for different types of chips, so that the types of the communication interfaces are more, a user needs to select the communication interfaces when using the communication interfaces, and the communication interfaces are inconvenient to use and have lower efficiency. To solve the problem, the embodiment of the present application provides a universal interface module, that is, the universal interface module can be in communication connection with chips of various types, so as to implement reading and writing of the chips. The different types of chips related to the embodiments of the present application mean that the number, types (definition of contacts) or arrangement of contacts of the chips are different, and the contacts mean communication connection points. The number, type or arrangement of contacts is generally related to the communication protocol, for example, in an IIC chip (a chip based on the IIC communication protocol), a high level signal VCC contact, a data signal SDA contact, a clock signal CLK contact and a ground signal GND contact are generally included. Of course, the technical solution provided in the embodiment of the present application may also be applied to other types of chips, and the embodiment of the present application does not specifically limit this.

Referring to fig. 1, a schematic structural diagram of an interface module provided in an embodiment of the present application is shown. As shown in fig. 1, the interface module includes a probe matrix of 40 probes. Of course, those skilled in the art can arrange other numbers of probes in the probe matrix according to actual needs, and the embodiment of the present application is not particularly limited thereto. When the chip needs to be read and written, the chip can be coupled with the probe matrix, so that the contact is electrically connected with the probe, and further, the signal transmission can be carried out through the probe electrically connected with the contact.

Specifically, the above-mentioned "the contact is electrically connected to the probe" means that the contact is electrically connected to a part of the probes in the probe matrix. For convenience of explanation, the 40 probes are numbered 1 to 40 in fig. 1. Referring to fig. 2, a schematic diagram of a connection state between an interface module and a chip according to an embodiment of the present disclosure is shown. In the chip shown in fig. 2, 4 contacts (the shape and size of the contacts are shown by the bold line boxes in fig. 2) are included, respectively contact 1, contact 2, contact 3 and contact 4. Wherein, the contact 1 is electrically connected with the probe 19, the probe 35, the probe 37 and the probe 14; contact 2 is electrically connected to probe 12 and probe 30; contact 3 is electrically connected to probe 28, probe 5, probe 7 and probe 25; the contact 4 is electrically connected to the probe 23 and the probe 4.

It can be understood that the probe matrix provided by the embodiment of the present application can be applied to chips with different numbers or arrangements of contacts, that is, the probe matrix has versatility. For example, in the connected state shown in fig. 3, the chip includes 2 contacts (the shape and size of the contacts are shown by the thick line boxes in fig. 3), respectively contact 1 and contact 2. Wherein, the contact 1 is electrically connected with the probe 33 and the probe 12; contact 2 is electrically connected to probe 10, probe 26, probe 28 and probe 5. As another example, in the connected state shown in fig. 4, the chip includes 4 contacts (the shape and size of the contacts are shown by the thick-line frame in fig. 4), and the relative positional relationship of the 4 contacts is different from the relative positional relationship of the 4 contacts in fig. 2. Wherein, the contact 1 is electrically connected with the probe 19, the probe 35, the probe 37 and the probe 14; contact 2 is electrically connected to probe 33 and probe 12; contact 3 is electrically connected to probe 10, probe 26, probe 28 and probe 5; the contact 4 is electrically connected to the probe 23 and the probe 4.

After the physical connection of the probe to the chip is completed, communication with the chip may be achieved through the probe electrically connected to the contact. Typically, different contacts of a chip have different definitions to enable the transmission of different signals. Also taking fig. 2 as an example, suppose that the contact 1, the contact 2, the contact 3 and the contact 4 are respectively used for transmitting a high-level signal VCC, a data signal SDA, a clock signal CLK and a ground signal GND. Accordingly, during communication, a high level signal VCC may be transmitted through the probe 19, the probe 35, the probe 37, or the probe 14 electrically connected to the contact 1; transmitting the data signal SDA through the probe 12 or the probe 30 electrically connected to the contact 1; transmitting a clock signal CLK through probe 28, probe 5, probe 7 or probe 25 electrically connected to contact 3; the ground signal GND is transmitted through the probe 23 or the probe 4 electrically connected to the contact 4.

That is, the signal transmission type of the probe can be controlled. In one possible implementation, each probe may be controlled by a switching circuit to enable transmission of any type of signal. For example, for 40 probes in fig. 1, any one probe may be controlled to implement transmission of the high-level signal VCC, the data signal SDA, the clock signal CLK, or the ground signal GND. However, this control method results in a complicated control circuit.

In view of the above problem, in the embodiments of the present application, the probes in the probe matrix are divided into a plurality of probe groups, where each probe group corresponds to one signal transmission channel, and a control circuit controls one probe in the probe group to perform signal transmission.

Referring to fig. 5, a schematic diagram of the probe matrix shown in fig. 1 is provided for an embodiment of the present application. In FIG. 5, T11_0 to T11_7 are a probe set, which corresponds to

probes

1, 3, 5, 7, 9, 11, 13, and 15. By analogy, 40 probes were divided into 5 probe sets. An 8-to-1 analog switch is configured for each probe group, so that the selection of the probes for communication in the probe group is realized, namely, the function of controlling 40 paths by 5 paths is realized. Of course, in addition to configuring the analog switch of 1-out-of-8, it is also possible to configure an analog switch of more-out-of-8, that is, to simultaneously select a plurality of probes for communication, and this is not particularly limited in the embodiments of the present application. It should be noted that, since one probe group corresponds to one signal transmission channel, when a plurality of probes for communication are selected, the plurality of probes for communication correspond to the same type of transmission signal.

In addition, each probe can output any type of signal, so that an analog switch is added to each probe set to select the type of signal to be transmitted. For example, the types of signals include a high level signal VCC, a data signal SDA, a clock signal CLK, a ground signal GND, and a TEST signal TEST/low level signal VDD. In this implementation, a 1-from-5 analog switch may be added to implement the selection of the types of the 5 signals. It is understood that in the above implementation, any one probe can be controlled by 10 analog switches to realize any type of signal transmission. On the contrary, if the probes are not grouped and each probe is controlled separately, 40 analog switches are required, resulting in a complicated control circuit.

According to the arrangement of the probe sets, one probe set corresponds to one signal transmission channel, and one signal transmission channel is used for transmitting one type of signal at the same time. In order to facilitate flexible configuration of transmission signals, probes of the same probe group should be arranged at intervals in the probe matrix as much as possible, so as to avoid that more than two contacts only cover the corresponding range of the same probe group. Specifically, the adjacent probe of any one probe includes the probe of at least one other probe set.

Referring to fig. 6, a schematic diagram of an arrangement of probe sets in a probe matrix is provided in the embodiments of the present application. As shown in fig. 6, in the embodiment of the present application, the probes in the probe group are obliquely arranged in the probe matrix, and by this arrangement, the probes in the same probe group are arranged at intervals in the horizontal direction and the vertical direction of the probe matrix, so that it is avoided that more than two contacts only cover the corresponding range of the same probe group. Specifically, in the present embodiment, contact 1 covers the range corresponding to probe set 2, probe set 3, and probe set 4; the contact 2 covers the corresponding range of the probe group 4 and the probe group 5; the contact 3 covers the corresponding ranges of the probe group 5, the probe group 1 and the probe group 2; the contact 4 covers the range corresponding to probe

sets

2 and 3. The flexible configuration of the transmission signals can be facilitated by the correspondence of the contact and the probe set. In contrast, if the

probes

19, 35, 37, 14, 12, and 30 belong to the same probe group, i.e., belong to one signal transmission channel, only one or several of the

probes

19, 35, 37, 14, 12, and 30 can be selected to transmit the same type of signal. While

contacts

1 and 2 obviously need to transmit different types of signals, resulting in no communication with the chip.

It should be noted that fig. 6 is only one possible arrangement of probe sets listed in the examples of the present application, and those skilled in the art can make adjustments according to actual needs. For example, probes of the same probe set are spaced only in the horizontal direction; alternatively, the probes of the same probe group may be spaced only in the vertical direction, and the like, which is not particularly limited in the embodiments of the present application.

In a particular application scenario, the size of the contacts of the chip may vary. In order to adapt to the contacts with different sizes, the probe matrix provided by the embodiment of the application comprises probe dense regions and probe sparse regions, as shown in fig. 1 to 4. Wherein the probe arrangement density of the probe dense region is greater than that of the probe sparse region. When the contact of the chip is large, the contact of the chip can be covered by the probe sparse area of the probe matrix, and the probe in the probe sparse area is communicated with the chip; when the contact of the chip is small, the contact of the chip can be covered by the probe dense area of the probe matrix, and the probe in the probe dense area is communicated with the chip, so that the compatibility of the chips with different contact sizes is realized.

Based on the interface module, the embodiment of the application also provides a chip reading and writing device.

Fig. 7 is a block diagram of a chip read/write apparatus according to an embodiment of the present disclosure. As shown in fig. 7, the chip reading/writing device includes a control module, a first switch module, a second switch module, and the interface module according to the above embodiment. The control module is used for realizing a control function in the chip reading and writing process, and is described in detail in combination with the method embodiment below; the first switch module is used for selectively communicating the signal transmission probes in each probe group, namely communicating the signal transmission probes with the control module, so that the signal transmission probes can transmit signals; the second switch module is used for selecting the signal transmission type of each signal transmission probe, namely determining which type of signal transmission probe each signal transmission probe is, so as to correspond to the corresponding contact; the interface module may refer to the description of the above embodiments, and is not described herein for brevity.

Fig. 8 is a schematic flow chart of a chip read-write method according to an embodiment of the present disclosure. The method is based on the interface module in the above embodiment, as shown in fig. 8, and mainly includes the following steps.

Step S801: and covering the contact points of the chip with the probe matrix to realize the electrical connection between the contact points of the chip and the probes of the probe matrix.

Specifically, when communication with the chip is required (e.g., burning or resetting the chip), the probe matrix may be overlaid on the contacts of the chip such that the contacts of the chip are electrically connected with the probes of the probe matrix. It is understood that the contact electrically connected to the probe means that the contact is electrically connected to a portion of the probes in the probe matrix.

Step S802: and identifying an electric connection probe corresponding to each contact, wherein the electric connection probe is a probe electrically connected with the contact, and each contact at least corresponds to one electric connection probe.

After the probe matrix is covered on the contacts of the chip, the corresponding relationship between the contacts and the probes needs to be determined, that is, the electrically connected probes corresponding to each contact are identified. The identification process is explained in detail below.

In a specific implementation, the number of contacts and the electrically connected probes corresponding to each contact can be determined by detecting whether there is a short circuit between adjacent probes.

Referring to fig. 9, a schematic diagram of an identification process of an electrical connection probe according to an embodiment of the present application is provided. As shown in fig. 9, it mainly includes the following steps.

Step S8021: a target probe is selected.

In particular, the target probe may be any one of a probe matrix. In one possible implementation, probing may be started from one corner of the probe matrix. For example, in the probe matrix shown in fig. 2, probe 1 is taken as the first probe point.

Step S8022: and sequentially carrying out short circuit on the target probe and each adjacent probe, and determining whether the target probe and the adjacent probes are short-circuited.

It can be appreciated that when two probes connected to the same contact are shorted, the two probes will be shorted. Based on this principle, the number of contacts and the electrical connection probes corresponding to the contacts can be determined by the probes where the short circuit occurs.

Also, taking FIG. 2 as an example, probe 1 was set as the target probe. First, the probe 1 is short-circuited with the probe 17 on the right side thereof, and it is determined whether or not the probe 1 and the probe 17 are short-circuited. Since probe 1 and probe 17 are not connected to the same contact, probe 1 and probe 17 are not short-circuited, and the correspondence between probe 1 and probe 17 does not need to be recorded. Then, the probe 1 and the probe 19 on the lower side are short-circuited, and it is determined whether the probe 1 and the probe 19 are short-circuited. Since the probe 1 and the probe 19 are not connected to the same contact, the probe 1 and the probe 19 are not short-circuited, and the correspondence between the probe 1 and the probe 19 does not need to be recorded.

Further, the probe 19 may be used as a target probe. First, the probe 19 is short-circuited to the probe 35 on the right side thereof, and it is determined whether or not the probe 19 and the probe 35 are short-circuited. Since both the probe 19 and the probe 35 are connected to the contact 1, the probe 19 and the probe 35 are short-circuited, and the correspondence between the probe 19 and the probe 35 is recorded. Then, the probe 19 is short-circuited with the probe 37 on the lower side thereof, and it is determined whether or not the probe 19 and the probe 37 are short-circuited. Since both the probe 19 and the probe 37 are connected to the contact 1, the probe 19 and the probe 37 are short-circuited, and the correspondence between the probe 19 and the probe 37 is recorded.

Further, the probe 35 may be used as a target probe. First, the probe 35 is short-circuited to the probe 12 on the right side thereof, and it is determined whether the probe 35 and the probe 12 are short-circuited. Since the

probes

35 and 12 are connected to different contacts, the

probes

35 and 12 are not short-circuited, and the corresponding relationship between the

probes

35 and 12 does not need to be recorded.

Further, the probe 37 may be used as a target probe. Since the probe 37 is located at the lowermost side of the probe matrix, downward probing is not required and only rightward probing is required. Similarly, for the rightmost probe, the right probe is not needed, and only the downward probe is needed. Specifically, the probe 37 is short-circuited to the probe 14 on the right side thereof, and it is determined whether the probe 37 and the probe 14 are short-circuited. Since the probe 37 and the probe 14 are both connected to the contact 1, the probe 37 and the probe 14 are short-circuited, and the corresponding relationship between the probe 37 and the probe 14 is recorded.

And repeating the steps to finish the detection of all the probes.

It should be noted that in the embodiment of the present application, since the probe in the upper left corner of the probe matrix is used as the target probe to start probing, when performing the short-circuit test, only the probes probing the right side and the lower side of the target probe need to be subjected to the short-circuit test (the probe on the upper side or the left side of the target probe has completed the short-circuit probing in the previous round). Of course, those skilled in the art may also perform probe detection according to other sequences, for example, the probe in the lower right corner of the probe matrix is used as the target probe to start detection, and when performing the short-circuit test, only the probes on the left side and the upper side of the target probe need to be subjected to the short-circuit test, which is not limited in the embodiment of the present application. In addition, when the probe matrix includes a probe-dense region and a probe-sparse region, it may not be perfectly aligned for adjacent probes at the boundary of the probe-dense region and the probe-sparse region. In this case, the detection relationship of the probe at the boundary of the probe-dense region and the probe-sparse region may be preset. For example, in the probe matrix shown in FIG. 2, probe 39 probes probe 27 and probe 16, probe 16 probes probe 8, probe 36 and probe 38, and probe 38 probes probe 15. Of course, other detection relationships can be set by those skilled in the art, and the embodiment of the present application is not limited to this.

In some application scenarios, a diode may be connected inside the chip between two contacts of the chip. Thus, there is still a certain probability of a short circuit occurring when probes connected to different contacts are shorted.

To this problem, in a possible implementation manner, the method of sequentially short-circuiting the target probe and each adjacent probe, and determining whether the target probe and the adjacent probe are short-circuited includes: sequentially carrying out positive and negative short circuit on the target probe and each adjacent probe respectively, and determining whether the target probe and the adjacent probes are short-circuited in both positive and negative short circuits; the electric connection probe which takes all the adjacent probes which are short-circuited with each other as a contact point comprises: and taking all adjacent probes which are in short circuit in both positive and negative directions as an electric connection probe corresponding to a contact.

Step S8023: and taking all the probes which are adjacent and short-circuited with each other as the electric connection probes corresponding to one contact.

Specifically, after the detection of all the probes is completed, all the probes adjacent to each other and short-circuited with each other are used as an electrical connection probe corresponding to one contact. For example, in the connection state shown in fig. 2, the probe 19, the probe 35, the probe 37, and the probe 14 are electrical connection probes corresponding to one contact; the probe 12 and the probe 30 are electrically connected probes corresponding to one contact point; probe 28, probe 5, probe 7 and probe 25 are electrically connected probes corresponding to one contact; the probe 23 and the probe 4 are electrically connected probes corresponding to one contact. Thus, the number of contacts in the chip and the correspondence of the contacts to the electrical connection probes can be determined.

Step S803: and determining the signal transmission probe corresponding to each contact in the electric connection probes according to the signal transmission channels corresponding to the electric connection probes, wherein the signal transmission channels of the signal transmission probes corresponding to any two contacts are different.

The number of contacts and the corresponding relationship between the contacts and the electrical connection probes are determined in the above steps. Thereafter, it is necessary to determine the probe to be used among the electrical connection probes. For convenience of explanation, the probe to be used is referred to as a "signal transmission probe".

In general, there are many permutations where each contact can correspond to at least two electrical connection probes, and a single signal transmission probe needs to be selected for each contact. However, since different contacts are used to transmit different signals, the signal transmission probe should satisfy the condition: the signal transmission channels of the signal transmission probes corresponding to any two contacts are different. In other words, the signal transmission channel corresponding to the selected signal transmission probe should not be repeated. It will be appreciated that the number of signal transmission channels in the probe matrix should be greater than or equal to the number of contacts of the chip.

Referring to fig. 6, in fig. 6, the electrically connecting probes of the contact 1 are a probe 19, a probe 35, a probe 37 and a probe 14, which correspond to the signal transmission channel 2, the signal transmission channel 3 and the signal transmission channel 4. That is, the contact 1 can select one of the

signal transmission channels

2, 3, and 4. Similarly, the contact 2 can select one of the signal transmission path 4 and the signal transmission path 5. The contact 3 can select one of the signal transmission channel 5, the signal transmission channel 1, and the signal transmission channel 2. The contact 4 can select one of the

signal transmission channels

2 and 3. For the 4 contacts, a combination of signal transmission channels is selected, wherein the signal transmission channels cannot be reused in different contacts. It will be appreciated that the selection of the signal transmission channel is the selection of the signal transmission probe. For example, if the signal transmission channel 2 is selected for the contact 1, i.e. the selection probe 19 is the signal transmission probe of the contact 1, the signal transmission probes of other contacts can be analogized, and the description thereof is omitted here.

In one possible implementation, the signal transmission path 3, the signal transmission path 5, the signal transmission path 1, and the signal transmission path 2 may be selected for the contact 1, the contact 2, the contact 3, and the contact 4, respectively. Of course, this configuration is only one possible implementation manner, and the embodiment of the present application does not limit this. The following describes how to find the permutation and combination of the signal transmission channels that satisfy the requirements.

Specifically, the number of contact points corresponding to each data transmission channel is enumerated first, and then one contact point corresponding to the data transmission channel is selected from the data transmission channel with the smallest number of contact points (not 0). Then, the data transmission channel and the contact are removed, and next round screening is carried out.

The contact relationship between the signal transmission channel and the contact shown in fig. 6 is shown in table one. In the first table, data "-" in the table corresponding to the contact and the signal transmission channel represents that the corresponding contact and the signal transmission channel do not have a corresponding relationship and cannot be bound; data "1" in the table corresponding to the contact and the signal transmission channel represents that the corresponding contact and the signal transmission channel have a corresponding relationship and can be bound. For example, if the data in the table corresponding to "contact 1" and "signal transmission channel 1" is "-", the "contact 1" and "signal transmission channel 1" may not be bound; if the data in the table corresponding to "contact 1" and "signal transmission channel 2" is "1", the "contact 1" and "signal transmission channel 2" cannot be bound.

In the specific implementation, the number of the contacts contacted by the signal transmission channel 1 is the least, and the contacts 3 can be bound firstly to use the signal transmission channel 1; then, deleting the signal transmission channel 1 and the contact 3 in the first table, refreshing the first table, and determining the signal transmission channel corresponding to each contact. Specifically, the contact 2 is bound with the signal transmission channel 5, the contact 1 is bound with the signal transmission channel 4, and the contact 4 can be selectively bound with the signal transmission channel 2 or the signal transmission channel 3.

Further, after the corresponding relationship between the contact points and the signal transmission channels is determined, the signal transmission probe corresponding to each contact point can be determined. Referring to fig. 6, since the contact 1 is bound with the signal transmission channel 4, and in the electrical connection probe of the contact 1, the probe corresponding to the signal transmission channel 4 is the probe 14, and therefore the probe 14 is the signal transmission probe corresponding to the contact 1. By analogy, the signal transmission probes corresponding to the contact 2, the contact 3 and the contact 4 are respectively a probe 30, a probe 5/probe 7 and a probe 23/probe 4.

Table one:

step S804: the signaling probes in each probe set are selected to be in communication such that the signaling probes can transmit signals.

Specifically, after the signal transmission probe corresponding to each contact is determined, the signal transmission probe in the connected probe group may be selected by the analog switch so that signal transmission may be performed by the signal transmission probe.

For example, in the implementation shown in fig. 6, after the probe 14 is determined to be a signal transmission probe corresponding to the contact 1, the 8-to-1 analog switch selects to communicate the probe 14 in the signal transmission channel 4; by analogy, the probe 30 is communicated with the signal transmission channel 5; the signal transmission channel 1 is communicated with a probe 5/a probe 7; the probe 23 is communicated in the signal transmission channel 2 or the probe 4 is communicated in the signal transmission channel 3.

Step S805: the definition of each contact is identified.

It will be appreciated that in the above steps only the number of contacts is determined and the definition of the contacts is not known, i.e. it is not known what type of signal is transmitted for each contact. In order to achieve proper communication with the chip, it is necessary to further identify the definition of each contact. For example, for an IIC chip, it is necessary to identify which of a high-level signal VCC contact, a data signal SDA contact, a clock signal CLK contact, and a ground signal GND contact corresponds to each contact, respectively.

In one possible implementation, the definition of the contacts may be determined based on the communication characteristics of the chip. Specifically, the definition of each of the contacts may be identified based on the control relationship and/or positional relationship between the contacts.

Referring to fig. 10, a schematic circuit structure of a chip according to an embodiment of the present disclosure is shown. As shown in fig. 10, the chip includes a high level signal VCC contact, a data signal SDA contact, a clock signal CLK contact, and a ground signal GND contact. In order to prevent the chip from being burnt out due to the reverse connection of the high-level signal VCC contact and the grounding signal GND contact when the chip is used, a reverse diode protection is arranged between the high-level signal VCC contact and the grounding signal GND contact of the chip. For convenience of explanation, this diode is referred to as a third diode D3, and specifically, the anode of the third diode D3 is connected to the ground signal GND contact, and the cathode thereof is connected to the high-level signal VCC contact.

For the same reason, the high level signal VCC contact is connected to the data signal SDA contact and the clock signal CLK contact through the first diode D1 and the second diode D2, respectively.

Referring to fig. 11, a schematic diagram of a circuit structure of another chip provided in the embodiment of the present application is shown. It is different from the chip shown in fig. 10 in that the ground signal GND contact is also electrically connected to the data signal SDA contact and the clock signal CLK contact through a fourth diode D4 and a fifth diode D5, respectively, wherein anodes of the fourth diode D4 and the fifth diode D5 are both connected to the ground signal GND contact.

For the chips shown in fig. 10 and 11, there is a third diode D3 reversely connected between the high-level signal VCC contact and the ground signal GND contact. In the probing mode, due to the existence of the third diode D3, when the high-level signal VCC contact is used for output, the waveform of the ground signal GND contact can be controlled, that is, the waveforms of the ground signal GND contact and the high-level signal VCC contact are kept consistent; on the contrary, when the ground signal GND contact is used for output, the waveform of the high level signal VCC contact cannot be controlled. This is also the reason why "the target probe and each adjacent probe are respectively short-circuited in the positive and negative directions, and whether the target probe and the adjacent probe are short-circuited in the positive and negative directions" is required in the above embodiments. The following is a description of the specific working principle thereof.

In a possible application scenario, the high level signal VCC contact and the ground signal GND contact connected to the chip are IO ports of the single chip, and the software needs to configure an IO port pull-up. When the high-level signal VCC contact is output high level and the grounding signal GND contact is input, because the grounding signal GND contact of the chip is not really grounded, the grounding signal GND contact is presented with high level due to pull-up; when the high level signal VCC contact is at the output low level and the ground signal GND contact is at the input, the third diode D3 is turned on, the ground signal GND contact is pulled low by the high level, and the waveform of the ground signal GND contact can be controlled when the waveform shows that the high level signal VCC contact is at the output. On the contrary, when the grounding signal GND contact is at output high level and the high-level signal VCC contact is at input, the high-level signal VCC contact is at high level because of pull-up; when the ground signal GND contact is at the output low level and the high-level signal VCC contact is at the input, the third diode D3 is turned off, and the high-level signal VCC contact is still at the high level, which shows that the waveform of the ground signal GND contact cannot be controlled when the ground signal GND contact is at the output.

Based on the above principle, the definition of the contacts can be determined by determining the orientation of the diode between the contacts within the chip. For example, in the chip shown in fig. 11, the contact controlled the most frequently is the ground signal GND contact, and the other contacts controlled the most frequently is the high-level signal VCC contact. The remaining data signal SDA and clock signal CLK contacts may then be subjected to a trial and error. If the remaining one contact is the data signal SDA contact, the other contact is the clock signal CLK contact. Communicating with the chip (sending test information to the chip) according to the definition, and if corresponding information fed back by the chip is received, determining that the hypothesis is correct; otherwise, the other case. For the chip shown in fig. 10, the other contacts are controlled to be, at most, the high-level signal VCC contact. Then, the definition of each of the remaining contacts is determined by traversing the communication results of the remaining contacts and the remaining contact definitions (data signal SDA contact, clock signal CLK contact, and ground signal GND contact) with the chip under different permutation and combination relationships (there are 6 possibilities in total). Specifically, one permutation and combination relationship, i.e., a target permutation and combination relationship, may be selected from the 6 possible permutation and combination relationships; then sending test information to the chip according to the definition of the residual contacts corresponding to the target permutation and combination relation; if response information fed back by the chip is received, determining that the definition of the residual contact corresponding to the target permutation and combination relation is the correct definition of the residual contact; otherwise, the next permutation-combination relation is tried until the correct permutation-combination relation is found.

That is, in the embodiment of the present application, the definition of at least one contact may be first identified according to the control relationship between the contacts; and then, traversing the communication results of the residual contacts and the residual contact definitions with the chip under different permutation and combination relations, and determining the definition of each contact in the residual contacts, namely completing the identification of the definition of each contact.

In addition, since the relative positional relationship of each contact in most chips is fixed and known, after the definition of at least one contact is identified based on the control relationship between the contacts, the definition of each of the remaining contacts can also be identified based on the positional relationship between the remaining contacts and the at least one contact. For example, with the chip shown in fig. 11, after the ground signal GND contact and the high-level signal VCC contact are determined, which of the remaining 2 contacts is the data signal SDA contact and which is the clock signal CLK contact may be determined according to the relative positional relationship between the data signal SDA contact and the clock signal CLK contact and the ground signal GND contact and the high-level signal VCC contact.

Step S806: the signal transmission type of each signal transmission probe is selected according to the definition of each contact, and the definition of the contact is matched with the signal transmission type of the corresponding signal transmission probe.

As in the previous embodiment, each signal transmission probe corresponds to a signal transmission channel. In order to enable normal communication with the chip, the signal transmission type corresponding to the signal transmission channel should match the definition of the contact, i.e. the signal transmission type of the signal transmission probe matches the definition of the contact. For example, a signal transmission probe corresponding to a data signal SDA contact should be used to transmit the data signal SDA; the signal transmission probe corresponding to the clock signal CLK contact should be used to transmit the clock signal CLK. Therefore, the signal transmission type corresponding to each signal transmission probe needs to be selected according to the definition of each contact.

For example, the types of signals include a high level signal VCC, a data signal SDA, a clock signal CLK, a ground signal GND, and a TEST signal TEST/low level signal VDD. In this implementation, the selection of the 5 signal types can be achieved through a 5-to-1 analog switch. For example, for a signal transmission channel corresponding to a data signal SDA contact, the signal transmission channel is communicated to the data signal SDA through a 1-out-of-5 analog switch; for a signal transmission channel corresponding to a clock signal CLK contact, communicating the signal transmission channel to a clock signal CLK through a 1-out-of-5 analog switch; and so on.

Step S807: and reading and writing the chip through the signal transmission probe.

After the selection of the signal transmission type of each signal transmission probe is completed, the chip read-write device can perform normal read-write with the chip, for example, perform burning or resetting on the chip.

In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, and may mean that a exists alone, a and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of electronic hardware and computer software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided by the present invention, any function, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only an embodiment of the present invention, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An interface module, comprising:

2. The interface module according to claim 1, wherein the probes in the same probe group are spaced apart in the horizontal and/or vertical direction of the probe matrix.

3. The interface module according to claim 2, wherein the probes in the same probe group are arranged consecutively in an oblique direction of the probe matrix.

4. The interface module of claim 1, wherein the probe matrix comprises a probe dense region and a probe sparse region, and wherein a probe arrangement density of the probe dense region is greater than a probe arrangement density of the probe sparse region.

5. A method for reading and writing a chip, which is applied to the interface module according to any one of claims 1 to 4, wherein the method comprises:

identifying a definition of each of the contacts;

and reading and writing the chip through the signal transmission probe.

6. The method of claim 5, wherein said identifying electrical connection probes corresponding to each of said contacts comprises traversing probes in said probe matrix by:

selecting a target probe;

and taking all the probes which are adjacent and mutually short-circuited as an electric connection probe corresponding to the contact.

7. The method of claim 6,

the short circuit is carried out to target probe and every adjacent probe in proper order, confirms target probe with whether the short circuit takes place for adjacent probe, include: sequentially carrying out positive and negative short circuit on the target probe and each adjacent probe respectively, and determining whether the target probe and the adjacent probes are short-circuited in both positive and negative short circuits;

8. The method of claim 5, wherein said identifying a definition for each of said contacts comprises:

9. The method of claim 8, wherein identifying the definition of each of the contacts based on the control relationship and/or the positional relationship between the contacts comprises:

identifying a definition of at least one contact point according to a control relation between the contact points;

10. The method according to claim 8, wherein the identifying the definition of each of the contact points according to the control relationship and/or the position relationship between the contact points comprises:

11. The method of claim 10, wherein traversing the remaining contact definitions from the communication results with the chip under different permutation and combination relationships to determine the definition of each of the remaining contacts comprises:

12. The method according to any one of claims 9-11, wherein the chip comprises 4 contacts, namely a high-level signal contact, a data signal contact, a clock signal contact and a ground signal contact, the high-level signal contact is electrically connected with the data signal contact, the clock signal contact and the ground signal contact through a first diode, a second diode and a third diode, respectively, and cathodes of the first diode, the second diode and the third diode are connected with the high-level signal contact;

the identifying the definition of at least one contact point according to the control relation among the contact points comprises: detecting the direction of a diode between any two of the 4 contacts; the high level signal contact is determined among the 4 contacts according to the direction of the diode.

13. The method according to any one of claims 9-11, wherein the chip comprises 4 contacts, namely a high-level signal contact, a data signal contact, a clock signal contact and a ground signal contact, the high-level signal contact is electrically connected with the data signal contact, the clock signal contact and the ground signal contact through a first diode, a second diode and a third diode, respectively, and cathodes of the first diode, the second diode and the third diode are connected with the high-level signal contact; the grounding signal contact is electrically connected with the data signal contact and the clock signal contact through a fourth diode and a fifth diode respectively, and the anodes of the fourth diode and the fifth diode are connected with the grounding signal contact;

14. A chip read/write apparatus, comprising:

the interface module of any one of claims 1-4;